Display panel and display device

Abstract

A display panel and a display device, the display panel comprising: a display area comprising: M first display areas arranged in sequence along a first direction, the first display area comprising: a plurality of first signal lines arranged in sequence along the first direction and extending along a second direction, the second direction intersecting the first direction; a non-display area comprising: M first array substrate gate drive (GOA) circuits and M clock signal line groups, the clock signal line group comprising: a plurality of clock signal lines, the signals of at least two clock signal lines in at least two clock signal line groups being the same, the first GOA circuit comprising: a plurality of first GOA units, the plurality of first GOA units in the mth first GOA circuit being connected with at least one clock signal line in the mth clock signal line group, and the plurality of first GOA units in the mth first GOA circuit being connected with the plurality of first signal lines in the mth first display area in a one-to-one correspondence.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display panel and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost.

[0003] With the continuous development of display technology, display devices that use OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] On one hand, this disclosure provides a display panel, including: a display area and a non-display area at least partially surrounding the display area; wherein, the display area includes: M first display zones sequentially arranged along a first direction, each first display zone including: a plurality of first signal lines sequentially arranged along the first direction and extending along a second direction, the second direction intersecting the first direction; the non-display area includes: M first array substrate gate driving circuits and M clock signal line groups, each clock signal line group including: a plurality of clock signal lines, wherein at least two clock signal lines in all the clock signal lines of the M clock signal line groups have the same signal. The at least two clock signal lines are respectively located in at least two of the M clock signal line groups; the first array substrate gate driving circuit includes: a plurality of first array substrate gate driving units, the plurality of first array substrate gate driving units in the m-th first array substrate gate driving circuit are connected to at least one of the plurality of clock signal lines in the m-th clock signal line group, and the plurality of first array substrate gate driving units in the m-th first array substrate gate driving circuit are connected one-to-one with the plurality of first signal lines in the m-th first display area, where M is a positive integer greater than or equal to 2, and m is a positive integer less than or equal to M.

[0006] On the other hand, this disclosure also provides a display device, including: the display panel described in the above embodiments.

[0007] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings.

[0008] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0009] The accompanying drawings are provided to illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure, but do not constitute a limitation on the technical solutions of this disclosure. The shape and size of each component in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0010] Figure 1 This is a schematic diagram of the structure of a display panel;

[0011] Figure 2 This is a schematic diagram of a first structure of a display panel in an exemplary embodiment of the present disclosure;

[0012] Figure 3 This is a schematic diagram of a second structure of the display panel in an exemplary embodiment of the present disclosure;

[0013] Figure 4 This is a schematic diagram of a third structure of the display panel in an exemplary embodiment of this disclosure;

[0014] Figure 5 This is a schematic diagram of a fourth structure of the display panel in an exemplary embodiment of this disclosure;

[0015] Figure 6 This is a schematic diagram of a fifth structure of a display panel in an exemplary embodiment of this disclosure;

[0016] Figure 7 This is a schematic diagram of a sixth structure of a display panel in an exemplary embodiment of this disclosure;

[0017] Figure 8 This is a schematic diagram of the structure of the display device in an embodiment of this disclosure. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0019] The scale of the figures in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, etc., can be adjusted according to actual needs. For example, in the figures, sometimes for clarity, the size of each component, the thickness of the layer, or the area is exaggerated. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shape and size of each component in the figures do not reflect the true scale. Furthermore, the figures schematically show ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0020] In the exemplary embodiments disclosed herein, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion of constituent elements, rather than to limit in terms of quantity.

[0021] In the exemplary embodiments of this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," indicating orientation or positional relationship, are used to describe the positional relationship of constituent elements with reference to the accompanying drawings. This is solely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to has a specific orientation, or is constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationship of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0022] In the exemplary embodiments disclosed herein, unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of the above terms in this disclosure as appropriate.

[0023] In exemplary embodiments of this disclosure, "electrical connection" includes the case where constituent elements are connected together by an element having some electrical function. There are no particular limitations on the "electrical function" as long as it enables the transmission and reception of electrical signals between the connected constituent elements. The "electrical function" can be, for example, an electrode or wiring, a switching element such as a transistor, or other functional elements such as a resistor, inductor, or capacitor.

[0024] In exemplary embodiments of this disclosure, a transistor is a device that includes at least three terminals: a gate electrode (gate or control electrode), a drain electrode (drain electrode terminal, drain region, or drain electrode), and a source electrode (source electrode terminal, source region, or source electrode). The transistor has a channel region between the drain electrode and the source electrode, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0025] In exemplary embodiments of this disclosure, to distinguish the two terminals of a transistor other than the gate electrode (gate or control electrode), one terminal is directly described as the first terminal and the other as the second terminal. The first terminal can be the drain electrode and the second terminal can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" can sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0026] The transistors used in the embodiments of this disclosure can all be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. For example, the thin-film transistors used in the embodiments of this disclosure may include, but are not limited to, oxide TFTs or low-temperature poly-silicon TFTs (LTPS TFTs). Here, the embodiments of this disclosure do not limit the scope of the application.

[0027] In the exemplary embodiments of this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes a state in which the angle is greater than or equal to -5° and less than 5°. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes a state in which the angle is greater than or equal to 85° and less than 95°.

[0028] In exemplary embodiments of this disclosure, "about" means a value that is not strictly limited and allows for process and measurement errors.

[0029] To facilitate a better understanding of the technical solutions of this disclosure by those skilled in the art, the technical terms that may be involved in the exemplary embodiments of this disclosure are briefly introduced below.

[0030] OLED driving methods can be divided into two types: passive matrix (PM) driving and active matrix (AM) driving. Compared with passive matrix driving, active matrix driving has the advantages of larger display information capacity, lower power consumption, longer device lifespan, and higher screen contrast.

[0031] Gate Driver on Array (GOA) technology refers to the integration of the driving circuitry controlling the gate of a thin-film transistor (TFT) onto the array substrate of a display panel using TFT technology. This reduces the cost of the gate driving circuitry in the panel and enables narrower bezels. For example, a gate driver circuit (GOA) controls the gate and can include multiple cascaded GOA units, which can be configured as shift registers. Based on their function, GOA units can include gate GOA units, emission (EM) GOA units, or reset (RS) GOA units. The gate GOA unit is configured to provide scan signals to the pixel driving circuit in a sub-pixel, the EM GOA unit is configured to provide emission control signals, and the reset GOA unit is configured to provide reset control signals. Correspondingly, the gate signals provided by the GOA units can include scan signals, emission control signals, or reset control signals. For example, depending on the type of transistor, the Gate GOA unit may include either a Gate GOA N (GN) unit or a Gate GOA P (GP) unit. The GN unit is configured to provide a scan signal to the N-type transistor in the pixel driving circuit of the sub-pixel, and the GP unit is configured to provide a scan signal to the P-type transistor in the pixel driving circuit of the sub-pixel.

[0032] Pulse width refers to the pulse width (time) of a pulse signal. Rise time (Tr) refers to the time it takes for a pulse signal to change from a low level to a high level, and fall time (Tf) refers to the time it takes for a pulse signal to change from a high level to a low level. The unit is nanoseconds (ns).

[0033] With the development of OLED technology, the requirements for display effects are becoming increasingly stringent. The image uniformity of OLED display devices is closely related to the pulse width of the gate signal provided by the gate drive circuit (GOA). Currently, in some OLED display technologies, the entire display screen uses the same clock signal line (CLOCK) to provide the clock signal (e.g., first clock signal line GCK / second clock signal line GCB). During panel driving, due to the increased wiring load of the clock signal line CLOCK, the Tr / Tf of the gate signal at different positions on the display panel becomes inconsistent, resulting in a display unevenness (Mura) phenomenon.

[0034] For example, Figure 1 This is a schematic diagram of the structure of a display panel, such as... Figure 1 As shown, in a plane parallel to the display panel, the display panel may include: a display area 100, a bonding area 200 located on one side of the display area 100 in the first direction DR1, and a border area 300 located on other sides of the display area 100. The bonding area 200 may include: an integrated circuit (IC) 40. The display area 100 may include: a first position A near the driver IC, a third position C away from the driver IC, and a second position B located between the first position A and the third position C. In some technologies, a scheme is typically used where the same set of clock signal lines CLOCK (e.g., first clock signal line GCK / second clock signal line GCB) provides clock signals to all GOA units in the entire display panel. As shown in Table 1, the Tr / Tf of the clock signal line CLOCK at the first position A is approximately 275 / 312, the Tr / Tf of the clock signal line CLOCK at the second position B increases to approximately 363 / 412, and the Tr / Tf of the clock signal line CLOCK at the third position C increases to approximately 402 / 455. It is evident that during the display panel driving process, the clock signal line CLOCK has a greater trace load and a greater delay due to its distance from the driver IC. This leads to inconsistencies in the Tr / Tf of the clock signal line CLOCK at different locations on the display panel, which in turn causes inconsistencies in the Tr / Tf of the Gate signal output by the GOA circuit, resulting in a reduction in display quality.

[0035] In addition, to ensure the consistency of Tr / Tf of the Gate signal, some technologies use a double-layer routing method with a first source-drain metal layer (SD1) and a second source-drain metal layer (SD2) for the clock signal line CLOCK (e.g., the first clock signal line GCK / the second clock signal line GCB) to reduce the loading of the clock signal line. However, this increases the mask process of the SD2 film, making the fabrication process more complex, increasing the production cost, and hindering the application and promotion of the product.

[0036] Table 1 Figure 1 The Tr / Tf values ​​at different locations on the display panel are shown.

[0037] Tr (unit: ns) Tf (unit: ns) First position A 274.7 319.9 Second position B 363.4 412.8 Third position C 401.7 454.5

[0038] In the exemplary embodiments of this disclosure, the first direction DR1 can refer to a vertical direction or the extension direction of a data signal line, the second direction DR2 can refer to a horizontal direction or the extension direction of a scan signal line, and the third direction DR3 can refer to the thickness direction of the display panel or a direction perpendicular to the plane of the display panel, etc. The first direction DR1 intersects with the second direction DR2, and the first direction DR1 intersects with the third direction DR3. For example, the first direction DR1 and the second direction DR2 can be perpendicular to each other, and the first direction DR1 and the third direction DR3 can be perpendicular to each other.

[0039] This disclosure provides a display panel, which may include: a display area and a non-display area that at least partially surrounds the display area; wherein, the display area may include: M first display areas sequentially arranged along a first direction DR1, and the first display area may include: a plurality of first signal lines sequentially arranged along the first direction DR1 and extending along a second direction DR2, the second direction DR2 intersecting the first direction DR1; the non-display area may include: M first GOA circuits and M clock signal line groups, the clock signal line groups may include: a plurality of clock signal lines, all clock signal lines of the M clock signal line groups. The signals of at least two clock signal lines are identical, and the at least two clock signal lines are respectively located in at least two of the M clock signal line groups; the first GOA circuit may include: a plurality of first GOA units, the plurality of first GOA units in the m-th first GOA circuit are connected to at least one of the multiple clock signal lines in the m-th clock signal line group, and the plurality of first GOA units in the m-th first GOA circuit are connected one-to-one with the multiple first signal lines in the m-th first display area, where M is a positive integer greater than or equal to 2, and m is a positive integer less than or equal to M. Thus, the display panel provided by the exemplary embodiment of this disclosure, by dividing the display panel into at least M first display areas and dividing the GOA circuit of the display panel into M first GOA circuits corresponding to the M first display areas, such that the first GOA circuit is connected to the multiple first signal lines in the corresponding first display area, can thus realize the driving of multiple first signal lines in the corresponding first display area through the same first GOA circuit. Then, by increasing the number of clock signal groups on the display panel from 1 to M, the M clock signal line groups correspond to the M first display areas and the M first GOA circuits, and the M clock signal line groups are connected to the M first GOA circuits. This avoids providing clock signals to all GOA units in the entire display panel from a single clock signal line group. Consequently, the Tr / Tf difference of the clock signal in each clock signal line group can be reduced, the Tr / Tf difference of the first signal lines in the first display areas can be reduced, and the brightness difference at different locations on the display panel can be reduced. Therefore, compared to some technologies that use a single clock signal line group to provide clock signals to all GOA units in the entire display panel, the display panel provided in this exemplary embodiment, by adding an additional M-1 clock signal line groups and adjusting the design of the clock signals of the GOA circuits, changes the driving mode of the GOA circuits, which can improve the macroscopic display unevenness (Mura) caused by the inconsistency of Tr / Tf of the gate signals at different locations on the display panel, thereby improving the display quality.

[0040] Furthermore, compared with some technologies that use double-layer routing for clock signal lines, the display panel provided by the exemplary embodiments of this disclosure requires minimal improvement to the existing process. It does not increase the number of patterning processes or structural film layers, does not require adding a mask, has a simple manufacturing process, low production cost, is easy to implement, and is conducive to the promotion and application of the product.

[0041] In one exemplary embodiment, "at least two clock signal lines in all clock signal lines of the M clock signal line groups have the same signal, and the at least two clock signal lines are respectively located in at least two clock signal line groups in the M clock signal line groups" can mean that in at least two clock signal line groups in the M clock signal line groups, at least one clock signal line in one clock signal line group is the same as at least one clock signal line in other clock signal line groups. For example, taking at least two clock signal line groups in M ​​clock signal line groups as an example, including a first clock signal line group and a second clock signal line group, where the first clock signal line group may include a first clock signal line CK1 and a second clock signal line CK2, and the second clock signal line group may include a third clock signal line CK3 and a fourth clock signal line CK4, then "at least two clock signal lines have the same signal" could mean that the first clock signal line CK1 in the first clock signal line group has the same signal as at least one of the third clock signal line CK3 and the fourth clock signal line CK4 in the second clock signal line group; or, "at least two clock signal lines have the same signal" could mean that the first clock signal line CK1 in the first clock signal line group has the same signal as at least one of the third clock signal line CK3 and the fourth clock signal line CK4 in the second clock signal line group; The second clock signal line CK2 has the same signal as at least one of the third clock signal line CK3 and the fourth clock signal line CK4 in the second clock signal line group; or, "the signals of at least two clock signal lines are the same" can mean that one of the first clock signal line CK1 and the second clock signal line CK2 in the first clock signal line group has the same signal as one of the third clock signal line CK3 and the fourth clock signal line CK4 in the second clock signal line group, and the other of the first clock signal line CK1 and the second clock signal line CK2 in the first clock signal line group has the same signal as the other of the third clock signal line CK3 and the fourth clock signal line CK4 in the second clock signal line group.

[0042] In one exemplary embodiment, "the signals of at least two clock signal lines are the same" can mean that the signal types transmitted by the at least two clock signal lines are the same. For example, taking the example that the signals of the first clock signal line CK1 and the third clock signal line CK3 are the same, the first clock signal line CK1 and the third clock signal line CK3 can both refer to the clock signal line GCK of the GOA circuit, or the first clock signal line CK1 and the third clock signal line CK3 can both refer to the clock signal line GCB of the GOA circuit, etc. Here, this disclosure embodiment does not limit this.

[0043] In one exemplary embodiment, the multiple clock signal lines in the m-th clock signal line group can be the input signal lines of the first GOA unit in the m-th first GOA circuit. The first GOA unit in the m-th first GOA circuit can utilize clock signals received from the multiple clock signal lines in the m-th clock signal line group to generate a signal, such as a gate signal, to be provided to the first signal line connected to the first GOA unit.

[0044] In one exemplary embodiment, M clock signal line groups are disposed on the side of the M first GOA circuits away from the display area.

[0045] In one exemplary embodiment, M clock signal line groups are arranged sequentially along the direction closest to the display area.

[0046] In one exemplary embodiment, multiple clock signal lines in the clock signal line group are arranged sequentially at preset intervals along the direction close to the display area.

[0047] In one exemplary embodiment, the non-display area may include two, three, or four clock signal line groups. Of course, other numbers are also possible, and this disclosure does not limit this to any particular number.

[0048] In one exemplary embodiment, the line widths of the multiple clock signal lines in each group of clock signal lines are equal. Here, the line width of the clock signal line can refer to the dimension of the clock signal line along the second direction DR2.

[0049] In one exemplary embodiment, multiple first GOA units in the first GOA circuit are cascaded, and multiple clock signal lines in the m-th clock signal line group can be alternately output during the step-by-step transmission process of the multiple first GOA units in the m-th first GOA circuit.

[0050] In one exemplary embodiment, the first signal line can be an output signal line of the first GOA unit in the first GOA circuit, or it can be an input signal line of the gate of the thin-film transistor. The signal on the first signal line can refer to the gate signal output by the first GOA unit in the first GOA circuit to the gate of the thin-film transistor.

[0051] In one exemplary embodiment, the first signal line may include any one of a scan signal line, a light emission control signal line, and a reset control signal line. This disclosure does not limit the scope of the embodiment.

[0052] In one exemplary embodiment, the signal of the first signal line may include any one of a scan signal, a light emission control signal, and a reset control signal. This disclosure does not limit the scope of the embodiment.

[0053] In one exemplary embodiment, the number of first signal lines in the M first display areas is the same, or the number of first signal lines in at least two of the M first display areas is different. This disclosure does not limit the scope of the embodiments.

[0054] In one exemplary embodiment, the first GOA unit may include any one of a Gate GOA unit, an EM GOA unit, and a Reset GOA unit. This disclosure does not limit the scope of the embodiment.

[0055] In one exemplary embodiment, the total number of first GOA units in the M first GOA circuits may be the same or different. This disclosure does not limit this aspect.

[0056] In one exemplary embodiment, M can be a positive integer such as 2, 3, 4, 5, or 6. For example, the display panel may include two first display areas, and correspondingly, the display panel may also include two first GOA circuits corresponding one-to-one with the two first display areas, and two clock signal line groups corresponding one-to-one with the two first display areas. As another example, the display panel may include three first display areas, and correspondingly, the display panel may also include three first GOA circuits corresponding one-to-one with the three first display areas, and three clock signal line groups corresponding one-to-one with the three first display areas. Of course, other quantities are also possible, and this embodiment of the present disclosure does not limit this.

[0057] In one exemplary embodiment, the M display areas can be divided uniformly or non-uniformly. This disclosure does not limit the scope of the embodiments.

[0058] In one exemplary embodiment, the number of first display areas included in the display panel can be divided using a uniform or non-uniform division method, based on the number of pixel rows or scan signal lines included in the display panel. For example, when using a uniform division method, the number of pixel rows included in multiple first display areas can be equal; or, when using a non-uniform division method, the number of pixel rows included in at least two of the multiple display areas can be unequal. Here, the embodiments of this disclosure do not limit this.

[0059] For example, taking a Full High Definition (FHD) display panel as an example, if the number of pixel rows included in the display panel can be 1080, then when the display area of ​​the display panel is divided evenly according to the number of pixel rows included in the display panel, the display area of ​​the display panel can be divided into 2 first display areas. At this time, the number of pixel rows included in each first display area can be 540. Alternatively, the display area of ​​the display panel can be divided into 3 first display areas. At this time, the number of pixel rows included in each first display area can be 360. For example, taking an Ultra High Definition (UHD) display panel as an example, if the number of pixel rows included in the display panel is 4320, then when the display area of ​​the display panel is divided evenly according to the number of pixel rows included in the display panel, the display area of ​​the display panel can be divided into 2 first display areas, in which case the number of pixel rows included in each first display area can be 2160; or, the display area of ​​the display panel can be divided into 3 first display areas, in which case the number of pixel rows included in each first display area can be 1440; or, the display area of ​​the display panel can be divided into 4 first display areas, in which case the number of pixel rows included in each first display area can be 1080.

[0060] In one exemplary embodiment, the display area may further include a second display area located between two adjacent first display areas. The second display area may include multiple second signal lines alternately arranged along a first direction DR1 and extending along a second direction DR2. The non-display area may further include a second GOA circuit corresponding to the second display area. The second GOA circuit may include multiple second GOA units. An odd number of second GOA units are connected to at least one clock signal line in a group of clock signal lines connected to one of the two adjacent first display areas. An even number of second GOA units are connected to at least one clock signal line in a group of clock signal lines connected to the other of the two adjacent first display areas. The multiple second GOA units are connected to the multiple second signal lines in a one-to-one correspondence.

[0061] In one exemplary embodiment, multiple clock signal lines in the clock signal line group connected to one of the two adjacent first display areas can be input signal lines for an odd number of second GOA units in the second GOA circuit, and multiple clock signal lines in the clock signal line group connected to the other of the two adjacent first display areas can be input signal lines for an even number of second GOA units in the second GOA circuit. The second GOA unit can use clock signals received from the multiple clock signal lines to generate a signal, such as a gate signal, to be provided to the second signal line connected to that second GOA unit.

[0062] In one exemplary embodiment, an odd number of second GOA units are cascaded in the second GOA circuit, and multiple clock signal lines in the clock signal line group connected to one of the two adjacent first display areas can be output alternately during the step-by-step transmission process of the odd number of second GOA units in the second GOA circuit. An even number of second GOA units are cascaded in the second GOA circuit, and multiple clock signal lines in the clock signal line group connected to the other of the two adjacent first display areas can be output alternately during the step-by-step transmission process of the even number of second GOA units in the second GOA circuit.

[0063] In one exemplary embodiment, the second signal line can be an output signal line of the second GOA unit in the second GOA circuit, or it can be an input signal line of the gate of the thin-film transistor. The signal on the second signal line can refer to the gate signal output by the second GOA unit in the second GOA circuit to the gate of the thin-film transistor.

[0064] In one exemplary embodiment, the type of the second GOA unit may be the same as the type of the first GOA unit. In one exemplary embodiment, both the first GOA unit and the second GOA unit may include any one of the following: a Gate GOA unit, an EMGOA unit, and a Reset GOA unit.

[0065] In one exemplary embodiment, the type of the second signal line may be the same as the type of the first signal line. In one exemplary embodiment, both the first and second signal lines may include any one of a scan signal line, a light emission control signal line, and a reset control signal line. This embodiment does not limit the scope of the embodiments described herein. In one exemplary embodiment, the signals of both the first and second signal lines may include any one of a scan signal, a light emission control signal, and a reset control signal. This embodiment does not limit the scope of the embodiments described herein.

[0066] Thus, the display panel provided in this exemplary embodiment, in addition to setting M first display areas and their corresponding M first GOA circuits, also sets a second display area located between two adjacent first display areas, and sets a corresponding second GOA circuit for the second display area, so that the second GOA circuit is connected to multiple second signal lines in the corresponding second display area. In this way, multiple first signal lines in the corresponding first display area can be driven by the first GOA circuit, and multiple second signal lines in the corresponding second display area can be driven by the second GOA circuit. Then, clock signals are alternately provided to the second GOA circuit by two clock signal line groups corresponding to two adjacent first display areas. In this way, the screen splitting problem caused by the Tr / Tf jump between the two clock signal line groups corresponding to two adjacent first display areas can be avoided by reducing the Tr / Tf operating range of the clock signal of each clock signal line group. Therefore, compared with some technologies that use a single clock signal line group to provide clock signals to all GOA units in the entire display panel, the display panel provided by the exemplary embodiments of this disclosure, by adding a clock signal line group and adjusting the design of the clock signal of the GOA circuit, changes the driving mode of the GOA circuit. This can improve the macroscopic display unevenness (Mura) caused by the inconsistency of Tr / Tf of the gate signals at different positions of the display panel, and also avoid the screen splitting problem caused by the Tr / Tf jump between the two clock signal line groups corresponding to two adjacent first display areas, thus achieving a more effective improvement in display quality.

[0067] In one exemplary embodiment, the number of second display areas is less than the number of first display areas. When the number of first display areas is M, the number of second display areas can be a positive integer less than or equal to M-1. For example, if the number of first display areas is 2, then M equals 2, and correspondingly, the number of second display areas can be 1. Or, if the number of first display areas is 3, then M equals 3, and correspondingly, the number of second display areas can be 1 or 2. Or, if the number of first display areas is 4, then M equals 4, and correspondingly, the number of second display areas can be 1, 2, or 3, etc. Here, the number of second display areas can be set by those skilled in the art, and this embodiment does not limit this.

[0068] In one exemplary embodiment, when the number of first display areas is M and the number of second display areas can be M-1, the nth second display area can be located between the nth and (n+1)th first display areas, where n can be a positive integer less than or equal to M-1. For example, taking the example that the number of first display areas can be 3 and the number of second display areas can be 2, the display area can include: a first, a second, and a third display area arranged sequentially along a first direction. The display area can also include: a first and a second display area arranged sequentially along a first direction, wherein the first second display area is located between the first and second first display areas, and the first second display area is located between the first and second first display areas. Here, this embodiment of the disclosure does not limit this.

[0069] In one exemplary embodiment, the display panel may include a first display area and a second display area. The first and second display areas may be uniformly divided, or they may be non-uniformly divided. For example, depending on the number of first display areas, a second display area may be provided between each pair of adjacent first display areas, or no second display area may be provided between some adjacent first display areas. Another example is that a second display area may be provided only between adjacent first display areas that meet preset conditions, wherein the preset conditions may include, but are not limited to, a large difference in the Tr / Tf ratio of the gate signals between adjacent first display areas. This disclosure does not limit the scope of the embodiments.

[0070] In one exemplary embodiment, the number of first display areas and the number of second display areas that the display panel may include can be divided according to the number of pixel rows or the number of scan signal lines that the display panel may include, using a uniform division method, a non-uniform division method, or a combination of both. For example, when using a uniform division method, the number of pixel rows that multiple first display areas may include can be equal, or the number of pixel rows that multiple second display areas may include can be equal, or a second display area may be provided between each pair of adjacent first display areas. As another example, when using a non-uniform division method, the number of pixel rows that at least two of the multiple first display areas may include can be unequal, or a second display area may be provided between some adjacent pairs of first display areas, while a second display area may not be provided between some adjacent pairs of first display areas. Here, the embodiments of this disclosure do not limit this.

[0071] In one exemplary embodiment, the number of second signal lines is less than the number of first signal lines.

[0072] In one exemplary embodiment, the number of second signal lines can be an even number greater than or equal to 4. This disclosure does not limit this to any particular number.

[0073] In one exemplary embodiment, the number of second GOA units in the second GOA circuit is less than the number of first GOA units in the first GOA circuit.

[0074] In one exemplary embodiment, the number of second GOA units in each second GOA circuit can be an even number greater than or equal to 4. For example, the number of second GOA units in the second GOA circuit can be 4, 6, 8, 10, or 12, etc. Here, the number of GOA units in the second GOA circuit can be appropriately set by those skilled in the art based on simulation results, and this disclosure does not limit this.

[0075] In one exemplary embodiment, the number of second GOA units in a plurality of second GOA circuits may be the same or different.

[0076] In one exemplary embodiment, the non-display area may include: a bonding area located on one side of the first direction of the display area and a border area located on other sides of the display area. The bonding area may include: an integrated circuit configured to output clock signals to the M clock signal line groups. The M first array substrate gate driving circuits and the M clock signal line groups are located in the border area. Thus, by increasing the number of clock signal lines in the display panel from 1 to M, it avoids one clock signal line group providing clock signals to all GOA units in the entire display panel. This improves the macroscopic display unevenness (Mura) caused by the increased trace loading of the clock signal line CLOCK further away from the driver IC, the increased delay of the clock signal line CLOCK further away from the driver IC, and the macroscopic display unevenness (Mura) caused by the inconsistency of Tr / Tf of the gate signals at different positions on the display panel, thereby improving display quality.

[0077] In one exemplary embodiment, the non-display area may include a bonding area located on one side of the display area in a first direction. The bonding area may include an integrated circuit (IC) configured to output clock signals to M clock signal line groups, wherein the rise time of the clock signal of the k-th clock signal line group is less than the rise time of the clock signal of the (k+1)-th clock signal line group, and the fall time of the clock signal of the k-th clock signal line group is less than the fall time of the clock signal of the (k+1)-th clock signal line group, where k is a positive integer less than or equal to M-1. This reduces the Tr / Tf operating range of the clock signal of each clock signal line group, more effectively reduces the Tr / Tf difference of the signals of the first signal lines in the first display area, and reduces the brightness difference at different locations in the display panel. Therefore, it improves the macroscopic display inhomogeneity (Mura) caused by the inconsistency of Tr / Tf of the gate signals at different locations in the display panel, thereby improving display quality.

[0078] In one exemplary embodiment, taking the border area as an example, it can include two clock signal line groups, and each clock signal line group can include two clock signal lines. The two clock signal line groups can include a first clock signal line group corresponding to the first first display area and a second clock signal line group corresponding to the second first display area. The first clock signal line group can include a first clock signal line CK1 and a second clock signal line CK2. The second clock signal line group can include a third clock signal line CK3 and a fourth clock signal line CK4. Then, the Tr / Tf of the clock signal output by the IC to the clock signal line group satisfies the following relationship: Tr of CK1 / CK2 < Tr of CK3 / CK4, and Tf of CK1 / CK2 < Tf of CK3 / CK4. For example, taking the border area as including three clock signal line groups, and each clock signal line group including two clock signal lines as an example, the three clock signal line groups can include: the first clock signal line group corresponding to the first first display area, the second clock signal line group corresponding to the second first display area, and the third clock signal line group corresponding to the third first display area. The first clock signal line group can include: the first clock signal line CK1 and the second clock signal line CK2. The second clock signal line group can include: the third clock signal line CK3 and the fourth clock signal line CK4. The third clock signal line group can include: the fifth clock signal line CK5 and the sixth clock signal line CK6. Then, the Tr / Tf of the clock signal output by the IC to the clock signal line group satisfies the following relationship: Tr of CK1 / CK2 < Tr of CK3 / CK4 < Tr of CK5 / CK6, and Tf of CK1 / CK2 < Tf of CK3 / CK4 < Tf of CK5 / CK6. Of course, the number of clock signal line groups can be other than the number of first display areas, and so on. Here, the embodiments disclosed herein do not limit this.

[0079] In one exemplary embodiment, the integrated circuit can be a driver IC chip.

[0080] In one exemplary embodiment, the integrated circuit can be bonded to a driver chip region within the bonding region. For example, the integrated circuit can be bonded to the driver chip region via an anisotropic conductive film or other means. The size of the integrated circuit in the second direction DR2 can be smaller than the width of the driver chip region in the second direction DR2, where the second direction DR2 intersects with the first direction DR1.

[0081] In one exemplary embodiment, the multiple clock signal lines in each clock signal line group can be output signal lines of an integrated circuit, or input signal lines of a first GOA circuit or a second GOA circuit.

[0082] In one exemplary embodiment, the kth clock signal line group is located on the side of the (k+1)th clock signal line group away from the display area.

[0083] In one exemplary embodiment, the display panel may be an Active Matrix Organic Light Emitting Diode (AMOLED) display panel.

[0084] The structure of the display panel in the embodiments of this disclosure will be described below with reference to the accompanying drawings. The traces, display areas, pixel rows, or GOA units shown in the drawings are merely illustrative examples; the number of traces, display areas, pixel rows, or GOA units does not represent the actual number, and the type of GOA unit does not represent the actual type.

[0085] Figure 2 This is a schematic diagram of a first structure of a display panel in an exemplary embodiment of this disclosure. Figure 3 This is a schematic diagram of a second structure of a display panel in an exemplary embodiment of the present disclosure, wherein, in Figure 2 and Figure 3 The example shown is based on a display panel comprising two first display areas, 3000 pixel rows, two clock signal line groups, and each clock signal line group comprising two clock signal lines.

[0086] In one exemplary embodiment, such as Figure 2 As shown, in a plane parallel to the display panel, the display panel may include: a display area 100 and a non-display area that at least partially surrounds the display area 100. The non-display area may include: a bonding area 200 located on one side of the display area 100 and a border area 300 located on other sides of the display area 100. For example, the bonding area 200 may be located on one side (below) of the display area 100 in a first direction DR1. For example, the border area 300 may include M first GOA circuits and M clock signal line groups, and the bonding area 200 may include: an integrated circuit (not shown) configured to output clock signals to the M clock signal line groups.

[0087] In one exemplary embodiment, such as Figure 2 As shown, the display area 100 may include a first display area (upper display area) 11 and a second display area (lower display area) 12 arranged sequentially along the first direction DR1, wherein the first display area (upper display area) 11 serves as the first first display area and the second display area (lower display area) 12 serves as the second first display area.

[0088] In one exemplary embodiment, such as Figure 2As shown, taking a display panel comprising 3000 pixel rows as an example, the display panel may include 3000 scan signal lines (S1 to S3000) sequentially arranged along a first direction DR1 and extending along a second direction DR2. The first display area 11 may include the first scan signal line S1 to the 1500th scan signal line S1500, and the second display area 12 may include the 1501st scan signal line S1501 to the 3000th scan signal line S3000. Here, the first scan signal line S1 to the 1500th scan signal line S1500 can serve as a first signal line, and the 1501st scan signal line S1501 to the 3000th scan signal line S3000 can also serve as first signal lines.

[0089] In one exemplary embodiment, such as Figure 2 As shown, the border area 300 may include two clock signal line groups, which may include a first clock signal line group and a second clock signal line group. Each of the first and second clock signal line groups may include multiple clock signal lines. For example, each clock signal line group includes two clock signal lines. The first clock signal line group may include a first clock signal line CK1 and a second clock signal line CK2, and the second clock signal line group may include a third clock signal line CK3 and a fourth clock signal line CK4. For example, clock signal lines CK1 to CK4 are all located on the side of the first GOA circuit furthest from the display area 100. For example, clock signal lines CK1 to CK4 are sequentially spaced along the direction closest to the display area 100. For example, the line widths of clock signal lines CK1, CK2, CK3, and CK4 are equal. For example, the signals of the first clock signal line CK1 and the third clock signal line CK3 are the same. Similarly, the signals of the second clock signal line CK2 and the fourth clock signal line CK4 are the same.

[0090] In one exemplary embodiment, such as Figure 2 As shown, the border area 300 may further include: a first GOA circuit 21 corresponding to the first display area 11 and a second GOA circuit 22 corresponding to the second display area 12. The first GOA circuit 21 serves as the first first GOA circuit corresponding to the first first display area, and the second GOA circuit 22 serves as the second first GOA circuit corresponding to the second first display area.

[0091] In one exemplary embodiment, such as Figure 2As shown, taking all GOA units as Gate GOA P(GP) units and the display panel as having 3000 GOA units (GP1 to GP3000) as an example, the first GOA circuit 21 may include: the first-level GOA unit GP1 to the 1500th-level GOA unit GP1500. The first-level GOA unit GP1 to the 1500th-level GOA unit GP1500 are all connected to the first clock signal line CK1 and the second clock signal line CK2 in the first clock signal line group. The first-level GOA unit GP1 to the 1500th-level GOA unit GP1500 are respectively connected to the first scan signal line S1 to the 1500th scan signal line S1500. The second GOA circuit 22 may include: GOA units GP1501 (level 1501) to GP3000 (level 3000), each connected to the third clock signal line CK3 and the fourth clock signal line CK4 in the second clock signal line group. Furthermore, each GOA unit GP1501 to GP3000 is connected to the 1501st scan signal line S1501 to the 3000th scan signal line S3000 in a one-to-one correspondence. Here, GOA units GP1 (level 1) to GP3000 (level 3000) can serve as the first GOA unit. Thus, in the upper half of the display panel, the first clock signal line CK1 and the second clock signal line CK2 from the first clock signal line group are connected to the first first GOA circuit. In the lower half of the display panel, the third clock signal line CK3 and the fourth clock signal line CK4 from the second clock signal line group are connected to the second first GOA circuit. This avoids providing clock signals from a single clock signal line group to all GOA units in the entire display panel. Consequently, the Tr / Tf difference of the clock signal in each clock signal line group can be reduced, the Tr / Tf difference of the signal in the first signal line in the first display area can be reduced, and the brightness difference at different locations in the display panel can be reduced. Therefore, compared with some technologies that use a single clock signal line group to provide clock signals to all GOA units in the entire display panel, the display panel provided by the exemplary embodiments of this disclosure, by adding a clock signal line group and adjusting the design of the clock signal of the GOA circuit, changes the driving mode of the GOA circuit, which can improve the macroscopic display unevenness (Mura) caused by the inconsistency of Tr / Tf of the gate signals at different positions of the display panel, and thus improve the display quality.

[0092] In one exemplary embodiment, taking a display panel comprising 3000 GOA units (GP1 to GP3000) as an example, where all GOA units are Gate GOA P(GP) units, the first-level GOA unit GP1 to the 1500th-level GOA unit GP1500 can be cascaded. The first GOA circuit 21 can be configured to generate scan signals for the scan signal lines (first scan signal line S1 to 1500th scan signal line S1500) provided to the first display area 11 by using a clock signal received from the first clock signal line group, thereby enabling line-by-line scanning of the scan signal lines of the first display area 11. For example, the first GOA circuit 21 can be configured to sequentially provide scan signals with conduction level pulses to the scan signal lines S1, S2, ... and S1500 of the first display area 11. The 1501st level GOA unit GP1501 to the 3000th level GOA unit GP3000 can be cascaded. The second GOA circuit 22 can be configured to generate scan signals to be provided to the scan signal lines (1501st scan signal line S1501 to 3000th scan signal line S3000) of the second display area 12 by using clock signals received from the second clock signal line group, so as to realize line-by-line scanning of the scan signal lines of the second display area 12. For example, the second GOA circuit 22 can be configured to sequentially provide scan signals with conduction level pulses to the scan signal lines S1501, S1502, ... and S3000 of the second display area 12.

[0093] In one exemplary embodiment, such as Figure 2 As shown, the display panel can adopt a single-sided driving method. In this case, multiple first GOA units in the first GOA circuit can be arranged on one side of the first direction DR1 of the display area; or, as shown... Figure 3 As shown, the display panel can adopt a dual-side driving method. In this case, multiple first GOA units in the first GOA circuit can be arranged on both sides of the first direction DR1 of the display area. Here, the embodiments of this disclosure do not limit this.

[0094] The inventors of this disclosure can obtain, through simulation experiments, the following results. Figure 2 The image shows Tr / Tf at different locations on the display panel. For example... Figure 2As shown, the display area 100 may include: a first position A near the driver IC, a third position C away from the driver IC, and a second position B located between the first position A and the third position C. As shown in Table 2, the Tr / Tf of the clock signals of the first clock signal line CK1 and the second clock signal line CK2 at the first position A are approximately 275 / 320, respectively; the Tr / Tf of the clock signals of the first clock signal line CK1 and the second clock signal line CK2 at the second position B are approximately 363 / 413, respectively; and the Tr / Tf of the clock signals of the first clock signal line CK1 and the second clock signal line CK2 at the third position C are approximately 402 / 455, respectively. The Tr / Tf of the clock signals of the third clock signal line CK3 and the fourth clock signal line CK4 at the first position A are approximately 360 / 411, respectively. The Tr / Tf of the clock signals of the third clock signal line CK3 and the fourth clock signal line CK4 at the second position B are approximately 405 / 454, respectively. The Tr / Tf of the clock signals of the third clock signal line CK3 and the fourth clock signal line CK4 at the third position C are approximately 440 / 500, respectively.

[0095] Table 2 Figure 2 The Tr / Tf values ​​at different locations on the display panel are shown.

[0096]

[0097] Since the first first display area 11 (upper display area) uses the portions of the first clock signal line CK1 and the second clock signal line CK2 located at the second position B to the third position C to connect to the corresponding first first GOA circuit 21 (first level first GOA unit GP1 to 1500th level first GOA unit GP1500), during the display panel driving process, the Tr range of the clock signal of the clock signal line corresponding to the first first display area 11 (upper display area) can be approximately 363 to 402, and the Tf range of the clock signal of the clock signal line corresponding to the first first display area 11 (upper display area) can be approximately 413 to 455. Because in the second first display area 12 (lower display area), portions of the third clock signal line CK3 and the fourth clock signal line CK4 located at positions A to B are connected to the corresponding second first GOA circuit 22 (first GOA unit GP1501 of level 1501 to first GOA unit GP3000 of level 3000), during the display panel driving process, the Tr range of the clock signal of the clock signal line corresponding to the second first display area 12 (lower display area) can be approximately 360 to 405, and the Tf range of the clock signal of the clock signal line corresponding to the second first display area 12 (lower display area) can be approximately 411 to 454. Therefore, the Tr operating range of the clock signal of the corresponding clock signal line of the entire display panel can be approximately 360 to 405, making the Tr operating range of the clock signal of the corresponding clock signal line of the entire display panel approximately 411 to 455.

[0098] It can be seen that, with Figure 1 Compared to the display panel solution shown, the display panel provided in the exemplary embodiment of this disclosure, by adding a clock signal line group and adjusting the design of the clock signal of the GOA circuit, changes the driving mode of the GOA circuit. The Tr working range of the clock signal of the corresponding clock signal line of the entire display panel can be reduced from the original 275 to 402 to 360 to 405, and the Tf working range of the clock signal of the corresponding clock signal line of the entire display panel can be reduced from the original 320 to 454 to 411 to 454. In this way, the Tr / Tf difference of the clock signal of the clock signal line is reduced, thereby reducing the Tr / Tf difference of the gate signal in the display panel, reducing the brightness difference at different positions of the display panel, improving the macroscopic display non-uniformity (Mura) phenomenon, and improving the display quality.

[0099] Figure 4 This is a schematic diagram of a third structure of the display panel in an exemplary embodiment of this disclosure. Figure 5 This is a schematic diagram of a fourth structure of a display panel in an exemplary embodiment of this disclosure. Wherein, Figures 4 to 5The illustration uses a display panel consisting of two first display areas and one second display area as an example. Figures 4 to 5 The example shown uses a display panel with 3000 pixels. Figures 4 to 5 The example shown is a display panel that includes two clock signal line groups, with each clock signal line group including two clock signal lines.

[0100] In one exemplary embodiment, such as Figure 4 As shown, in a plane parallel to the display panel, the display panel may include: a display area 100 and a non-display area that at least partially surrounds the display area 100. The non-display area may include: a bonding area 200 located on one side of the display area 100 and a border area 300 located on other sides of the display area 100. For example, the bonding area 200 may be located on one side (below) of the display area 100 in a first direction DR1. For example, the border area 300 may include M first GOA circuits and M clock signal line groups, and the bonding area 200 may include: an integrated circuit (not shown) configured to output clock signals to the M clock signal line groups.

[0101] In one exemplary embodiment, such as Figure 4 As shown, the display area 100 may include a first display area (upper display area) 11, a second display area (middle display area) 12 and a third display area (lower display area) 13 arranged sequentially along the first direction DR1, wherein the first display area (upper display area) 11 serves as the first first display area, the second display area (middle display area) 12 serves as the first second display area, and the third display area (lower display area) 13 serves as the second first display area, that is, the second display area is disposed between two adjacent first display areas.

[0102] In one exemplary embodiment, such as Figure 4As shown, taking a display panel comprising 3000 pixel rows as an example, the display panel may include 3000 scan signal lines (S1 to S3000) arranged sequentially along a first direction DR1 and extending along a second direction DR2. The first display area 11 may include the first scan signal line S1 to the 1498th scan signal line S1498, the second display area 12 may include the 1499th scan signal line S1499 to the 1502nd scan signal line S1502, and the third display area 13 may include the 1503rd scan signal line S1503 to the 3000th scan signal line S3000. Here, the first scan signal line S1 to the 1498th scan signal line S1498 can be used as the first signal line, the 1499th scan signal line S1499 to the 1502nd scan signal line S1502 can be used as the second signal line, and the 1503rd scan signal line S1503 to the 3000th scan signal line S3000 can be used as the first signal line.

[0103] In one exemplary embodiment, such as Figure 4 As shown, the border area 300 may include two clock signal line groups, which may include a first clock signal line group and a second clock signal line group. Each of the first and second clock signal line groups may include multiple clock signal lines. For example, each clock signal line group includes two clock signal lines. The first clock signal line group may include a first clock signal line CK1 and a second clock signal line CK2, and the second clock signal line group may include a third clock signal line CK3 and a fourth clock signal line CK4. For example, clock signal lines CK1 to CK4 are all located on the side of the first GOA circuit furthest from the display area 100. For example, clock signal lines CK1 to CK4 are sequentially spaced along the direction closest to the display area 100. For example, the line widths of clock signal lines CK1, CK2, CK3, and CK4 are equal. For example, the signals of the first clock signal line CK1 and the third clock signal line CK3 are the same. Similarly, the signals of the second clock signal line CK2 and the fourth clock signal line CK4 are the same.

[0104] In one exemplary embodiment, such as Figure 4As shown, the border area 300 may further include: a first GOA circuit 21 corresponding to the first display area 11, a second GOA circuit 22 corresponding to the second display area 12, and a third GOA circuit 23 corresponding to the third display area 13. The first GOA circuit 21 serves as the first first GOA circuit corresponding to the first first display area, the second GOA circuit 22 serves as the first second GOA circuit corresponding to the first second display area, and the third GOA circuit 23 serves as the second first GOA circuit corresponding to the second first display area.

[0105] In one exemplary embodiment, such as Figure 4As shown, taking all GOA units as Gate GOA P(GP) units and the display panel as having 3000 GOA circuits (GP1 to GP3000) as an example, the first GOA circuit 21 may include: the first-level GOA unit GP1 to the 1498th-level GOA unit GP1498. The first-level GOA unit GP1 to the 1498th-level GOA unit GP1498 are all connected to the first clock signal line group, and the first-level GOA unit GP1 to the 1498th-level GOA unit GP1498 are respectively connected to the first scan signal line S1 to the 1498th scan signal line S1498. The third GOA circuit 23 may include: GOA units GP1503 (level 1503) to GP3000 (level 3000), all of which are connected to the second clock signal line group, and each of the GOA units GP1503 to GP3000 is connected to the 1503rd scan signal line S1503 to the 3000th scan signal line S3000 in a one-to-one correspondence. Here, GOA units GP1 to GP1498 (level 1) can be used as the first GOA unit, GOA units GP1499 (level 1499) to GP1502 (level 1502) can be used as the second GOA unit, and GOA units GP1503 (level 1503) to GP3000 (level 3000) can be used as the first GOA unit. Thus, in the upper half of the display panel, the first clock signal line CK1 and the second clock signal line CK2 from the first clock signal line group are connected to the first first GOA circuit, and in the lower half of the display panel, the third clock signal line CK3 and the fourth clock signal line CK4 from the second clock signal line group are connected to the second first GOA circuit. This avoids having a single clock signal line group provide clock signals to all GOA units in the entire display panel. Therefore, the Tr / Tf difference of the clock signal in each clock signal line group can be reduced, the Tr / Tf difference of the signal in the first signal line in the first display area can be reduced, and the brightness difference in different positions of the display panel can be reduced. Thus, compared to some technologies that use a single clock signal line group to provide clock signals to all GOA units in the entire display panel, the display panel provided by the exemplary embodiments of this disclosure, by adding a clock signal line group and adjusting the design of the clock signal of the GOA circuit, changes the driving mode of the GOA circuit, which can improve the macroscopic display unevenness (Mura) caused by the inconsistency of Tr / Tf of the gate signals in different positions of the display panel, thereby improving the display quality.

[0106] In one exemplary embodiment, such as Figure 4 and Figure 5As shown, the second GOA circuit 22 may include: GOA units GP1499 (level 1499) to GP1502 (level 1502), which are alternately connected to the first clock signal line group and the second clock signal line group. For example, as... Figure 4 As shown, the 1499th level GOA unit GP1499 is connected to the first clock signal line group and corresponds to the 1499th scan signal line S1499; the 1500th level GOA unit GP1500 is connected to the second clock signal line group and corresponds to the 1500th scan signal line S1500; the 1501st level GOA unit GP1501 is connected to the first clock signal line group and corresponds to the 1501st scan signal line S1501; and the 1502nd level GOA unit GP1502 is connected to the second clock signal line group and corresponds to the 1502nd scan signal line S1502. Alternatively, for example, as... Figure 5 As shown, the 1499th level GOA unit GP1499 can be connected to the second clock signal line group and correspondingly connected to the 1499th scan signal line S1499. The 1500th level GOA unit GP1500 is connected to the first clock signal line group and correspondingly connected to the 1500th scan signal line S1500. The 1501st level GOA unit GP1501 is connected to the second clock signal line group and correspondingly connected to the 1501st scan signal line S1501. The 1502nd level GOA unit GP1502 is connected to the first clock signal line group and correspondingly connected to the 1502nd scan signal line S1502. Thus, in the middle transition section of the display panel, the first and second clock signal line groups are alternately connected to the second GOA circuit. In this way, the screen splitting problem caused by Tr / Tf jumps between the two clock signal line groups corresponding to the two adjacent first display areas can be avoided by reducing the Tr / Tf operating range of the clock signal of each clock signal line group.

[0107] Figure 6 This is a schematic diagram of a fifth structure of a display panel in an exemplary embodiment of the present disclosure, wherein, in Figure 6 The example shown is based on a display panel that includes three first display areas, 3000 pixel rows, three clock signal line groups, and each clock signal line group including two clock signal lines.

[0108] In one exemplary embodiment, such as Figure 6As shown, in a plane parallel to the display panel, the display panel may include: a display area 100 and a non-display area that at least partially surrounds the display area 100. The non-display area may include: a bonding area 200 located on one side of the display area 100 and a border area 300 located on other sides of the display area 100. For example, the bonding area 200 may be located on one side (below) of the display area 100 in a first direction DR1. For example, the border area 300 may include M first GOA circuits and M clock signal line groups, and the bonding area 200 may include: an integrated circuit (not shown) configured to output clock signals to the M clock signal line groups.

[0109] In one exemplary embodiment, such as Figure 6 As shown, the display area 100 may include a first display area (upper display area) 11, a second display area (middle display area) 12 and a third display area (lower display area) 13 arranged sequentially along the first direction DR1, wherein the first display area (upper display area) 11 serves as the first first display area, the second display area (middle display area) 12 serves as the second first display area, and the third display area (lower display area) 13 serves as the third first display area.

[0110] In one exemplary embodiment, such as Figure 6 As shown, taking a display panel comprising 3000 pixel rows as an example, the display panel may include 3000 scan signal lines (S1 to S3000) sequentially arranged along a first direction DR1 and extending along a second direction DR2. The first display area 11 may include the first scan signal line S1 to the 1000th scan signal line S1000, the second display area 12 may include the 1001st scan signal line S1001 to the 2000th scan signal line S2000, and the third display area 13 may include the 2001st scan signal line S2001 to the 3000th scan signal line S3000. Here, all 3000 scan signal lines (S1 to S3000) can serve as first signal lines.

[0111] In one exemplary embodiment, such as Figure 6As shown, the border area 300 may include three clock signal line groups, which may include a first clock signal line group, a second clock signal line group, and a third clock signal line group. Each of the first, second, and third clock signal line groups may include multiple clock signal lines. For example, each clock signal line group may include two clock signal lines. Specifically, the first clock signal line group may include a first clock signal line CK1 and a second clock signal line CK2; the second clock signal line group may include a third clock signal line CK3 and a fourth clock signal line CK4; and the third clock signal line group may include a fifth clock signal line CK5 and a sixth clock signal line CK6. For example, clock signal lines CK1 to CK6 are all located on the side of the first GOA circuit away from the display area 100. For example, clock signal lines CK1 to CK4 are sequentially spaced along the direction closest to the display area 100. For example, the line widths of clock signal lines CK1, CK2, CK3, CK4, CK5, and CK6 are equal. For example, the signals of clock signal lines CK1, CK3, and CK5 are identical. For example, the signals of clock signal lines CK2, CK4, and CK6 are identical.

[0112] In one exemplary embodiment, such as Figure 6 As shown, the border area 300 may further include: a first GOA circuit 21 corresponding to the first display area 11, a second GOA circuit 22 corresponding to the second display area 12, and a third GOA circuit 23 corresponding to the third display area 13. Specifically, the first GOA circuit 21 serves as the first first GOA circuit corresponding to the first first display area, the second GOA circuit 22 serves as the second first GOA circuit corresponding to the second first display area, and the third GOA circuit 23 serves as the third first GOA circuit corresponding to the third first display area.

[0113] In one exemplary embodiment, such as Figure 6As shown, taking all GOA units as Gate GOA P(GP) units and the display panel as having 3000 GOA units (GP1 to GP3000) as an example, the first GOA circuit 21 may include: first-level GOA units GP1 to 1000-level GOA units GP1000. The first-level GOA units GP1 to 1000-level GOA units GP1000 are all connected to the first clock signal line CK1 and the second clock signal line CK2 in the first clock signal line group. The first-level GOA units GP1 to 1000-level GOA units GP1000 are respectively connected to the first scan signal line S1 to the 1000 scan signal line S1000. The second GOA circuit 22 may include: GOA units GP1001 (level 1001) to GP2000 (level 2000), each of which is connected to the third clock signal line CK3 and the fourth clock signal line CK4 in the second clock signal line group. Furthermore, GOA units GP1001 to GP2000 are connected to the 1001st scan signal line S1001 to the 2000th scan signal line S2000 in a one-to-one correspondence. The third GOA circuit 23 may include: GOA units GP2001 (level 2001) to GP3000 (level 3000). Each of these GOA units is connected to the fifth clock signal line CK5 and the sixth clock signal line CK6 in the third clock signal line group. Furthermore, each of these GOA units is connected to a corresponding scan signal line S2001 to S3000. Here, GOA units GP1 (level 1) to GP3000 (level 3000) can serve as the first GOA unit. Thus, in the upper part of the display panel, the first clock signal line CK1 and the second clock signal line CK2 from the first clock signal line group are connected to the first first GOA circuit. In the middle part of the display panel, the third clock signal line CK3 and the fourth clock signal line CK4 from the second clock signal line group are connected to the second first GOA circuit. In the lower part of the display panel, the fifth clock signal line CK5 and the sixth clock signal line CK6 from the third clock signal line group are connected to the third first GOA circuit. This avoids providing clock signals from a single clock signal line group to all GOA units in the entire display panel. Consequently, the Tr / Tf difference of the clock signal in each clock signal line group can be reduced, the Tr / Tf difference of the signal in the first signal line in the first display area can be reduced, and the brightness difference at different locations in the display panel can be reduced.Therefore, compared with some technologies that use a single clock signal line group to provide clock signals to all GOA units in the entire display panel, the display panel provided by the exemplary embodiments of this disclosure, by adding a clock signal line group and adjusting the design of the clock signal of the GOA circuit, changes the driving mode of the GOA circuit, which can improve the macroscopic display unevenness (Mura) caused by the inconsistency of Tr / Tf of the gate signals at different positions of the display panel, and thus improve the display quality.

[0114] In one exemplary embodiment, taking all GOA units as Gate GOA P(GP) units and the display panel as having 3000 GOA units (GP1 to GP3000) as an example, the first-level GOA units GP1 to the 1000th-level GOA units GP1000 can be cascaded. The first GOA circuit 21 can be configured to generate scan signals to be provided to the scan signal lines (first scan signal line S1 to 1000th scan signal line S1000) of the first display area 11 by using clock signals received from the first clock signal line group, etc., so as to realize line-by-line scanning of the scan signal lines of the first display area 11. For example, the first GOA circuit 21 can be configured to sequentially provide scan signals with conduction level pulses to the scan signal lines S1, S2, ... and S1000 of the first display area 11. The 1001st level GOA unit GP1001 to the 2000th level GOA unit GP2000 can be cascaded. The second GOA circuit 22 can be configured to generate scan signals to be provided to the scan signal lines (1001st scan signal line S1001 to 2000th scan signal line S2000) of the second display area 12 by using clock signals received from the second clock signal line group, so as to realize line-by-line scanning of the scan signal lines of the second display area 12. For example, the second GOA circuit 22 can be configured to sequentially provide scan signals with conduction level pulses to the scan signal lines S1001, S1002, ... and S2000 of the second display area 12. The 2001st level GOA unit GP2001 to the 3000th level GOA unit GP3000 can be cascaded. The third GOA circuit 23 can be configured to generate scan signals to be provided to the scan signal lines (such as the 2001st scan signal line S2001 to the 3000th scan signal line S3000) of the third display area 13 by using clock signals received from the third clock signal line group (such as the 5th clock signal line CK5 and the 6th clock signal line CK6), so as to realize line-by-line scanning of the scan signal lines of the third display area 13. For example, the third GOA circuit 23 can be configured to sequentially provide scan signals with conduction level pulses to the scan signal lines S2001, S2002, ... and S3000 of the third display area 13.

[0115] Figure 7 This is a schematic diagram of a fifth structure of a display panel in an exemplary embodiment of the present disclosure, wherein, in Figure 7 The example shown is a display panel comprising three first display areas, two second display areas, 3000 pixel rows, three clock signal line groups, and each clock signal line group comprising two clock signal lines.

[0116] In one exemplary embodiment, such as Figure 7 As shown, in a plane parallel to the display panel, the display panel may include: a display area 100 and a non-display area that at least partially surrounds the display area 100. The non-display area may include: a bonding area 200 located on one side of the display area 100 and a border area 300 located on other sides of the display area 100. For example, the bonding area 200 may be located on one side (below) of the display area 100 in a first direction DR1. For example, the border area 300 may include M first GOA circuits and M clock signal line groups, and the bonding area 200 may include: an integrated circuit (not shown) configured to output clock signals to the M clock signal line groups.

[0117] In one exemplary embodiment, such as Figure 7 As shown, the display area 100 may include a first display area 11, a second display area 12, a third display area 13, a fourth display area 14, and a fifth display area 15 arranged sequentially along the first direction DR1. The first display area (upper display area) 11 serves as the first first display area, the third display area serves as the second first display area, the fifth display area 15 serves as the third first display area, the second display area 12 serves as the first second display area, and the fourth display area 14 serves as the second second display area. That is, the second display area is located between two adjacent first display areas.

[0118] In one exemplary embodiment, such as Figure 7As shown, taking a display panel comprising 3000 pixel rows as an example, the display panel may include 3000 scan signal lines (S1 to S3000) arranged sequentially along a first direction DR1 and extending along a second direction DR2. The first display area 11 may include the first scan signal line S1 to the 1998th scan signal line S998, the second display area 12 may include the 999th scan signal line S999 to the 1002nd scan signal line S1002, the third display area 13 may include the 1003rd scan signal line S1003 to the 1998th scan signal line S1998, the fourth display area 14 may include the 1999th scan signal line S1999 to the 2002nd scan signal line S2002, and the fifth display area 15 may include the 2003rd scan signal line S2003 to the 3000th scan signal line S3000. Here, the first scan signal lines S1 to S998, the 1003rd scan signal lines S1003 to S1998, and the 2003rd scan signal lines S2003 to S3000 can all be used as first signal lines. The 999th scan signal lines S999 to S1002, and the 1999th scan signal lines S1999 to S2002 can all be used as second signal lines.

[0119] In one exemplary embodiment, such as Figure 7As shown, the border area 300 may include three clock signal line groups, which may include a first clock signal line group, a second clock signal line group, and a third clock signal line group. Each of the first, second, and third clock signal line groups may include multiple clock signal lines. For example, each clock signal line group may include two clock signal lines. Specifically, the first clock signal line group may include a first clock signal line CK1 and a second clock signal line CK2; the second clock signal line group may include a third clock signal line CK3 and a fourth clock signal line CK4; and the third clock signal line group may include a fifth clock signal line CK5 and a sixth clock signal line CK6. For example, clock signal lines CK1 to CK6 are all located on the side of the first GOA circuit away from the display area 100. For example, clock signal lines CK1 to CK4 are sequentially spaced along the direction closest to the display area 100. For example, the line widths of clock signal lines CK1, CK2, CK3, CK4, CK5, and CK6 are equal. For example, the signals of clock signal lines CK1, CK3, and CK5 are identical. For example, the signals of clock signal lines CK2, CK4, and CK6 are identical.

[0120] In one exemplary embodiment, such as Figure 7 As shown, the border area 300 may further include: a first GOA circuit 21 corresponding to the first display area 11, a second GOA circuit 22 corresponding to the second display area 12, a third GOA circuit 23 corresponding to the third display area 13, a fourth GOA circuit 24 corresponding to the fourth display area 14, and a fifth GOA circuit 25 corresponding to the fifth display area 15. Specifically, the first GOA circuit 21 serves as the first first GOA circuit corresponding to the first first display area, the third GOA circuit 23 serves as the second first GOA circuit corresponding to the second first display area, and the fifth GOA circuit 25 serves as the third first GOA circuit corresponding to the third first display area. The second GOA circuit 22 serves as the first second GOA circuit corresponding to the first second display area, and the fourth GOA circuit 24 serves as the second second GOA circuit corresponding to the second second display area.

[0121] In one exemplary embodiment, such as Figure 7As shown, taking all GOA units as Gate GOA P(GP) units and the display panel as having 3000 GOA units (GP1 to GP3000) as an example, the first GOA circuit 21 may include: the first-level GOA unit GP1 to the 998th-level GOA unit GP998. The first-level GOA unit GP1 to the 998th-level GOA unit GP998 are all connected to the first clock signal line CK1 and the second clock signal line CK2 in the first clock signal line group. The first-level GOA unit GP1 to the 998th-level GOA unit GP998 are respectively connected to the first scan signal line S1 to the 1000th scan signal line S998. The third GOA circuit 23 may include: GOA units GP1003 to GP1998 at level 1003. GOA units GP1003 to GP1998 at level 1998 are all connected to the third clock signal line CK3 and the fourth clock signal line CK4 in the second clock signal line group. GOA units GP1001 to GP1998 at level 1003 are connected to the 1003 scan signal line S1003 to the 1998 scan signal line S1998 in a one-to-one correspondence. The fifth GOA circuit 25 may include: GOA units GP2003 to GP3000 at level 2003, each connected to the fifth clock signal line CK5 and the sixth clock signal line CK6 in the third clock signal line group, and each GOA unit GP2003 to GP3000 at level 3000 is connected to the second scan signal line S2003 to the third scan signal line S3000 in a one-to-one correspondence. Here, GOA units GP1 to GP998 (level 1), GP1003 to GP1998 (level 1003), and GP2003 to GP3000 (level 2003) can be used as the first GOA unit. Thus, in the upper part of the display panel, the first clock signal line CK1 and the second clock signal line CK2 from the first clock signal line group are connected to the first first GOA circuit; in the middle part of the display panel, the third clock signal line CK3 and the fourth clock signal line CK4 from the second clock signal line group are connected to the second first GOA circuit; and in the lower part of the display panel, the fifth clock signal line CK5 and the sixth clock signal line CK6 from the third clock signal line group are connected to the third first GOA circuit. This avoids having a single clock signal line group provide clock signals to all GOA units in the entire display panel.Therefore, the Tr / Tf difference of the clock signal in each clock signal line group can be reduced, the Tr / Tf difference of the signal in the first signal line in the first display area can be reduced, and the brightness difference in different positions of the display panel can be reduced. Thus, compared to some technologies that use a single clock signal line group to provide clock signals to all GOA units in the entire display panel, the display panel provided by the exemplary embodiments of this disclosure, by adding a clock signal line group and adjusting the design of the clock signal of the GOA circuit, changes the driving mode of the GOA circuit, which can improve the macroscopic display unevenness (Mura) caused by the inconsistency of Tr / Tf of the gate signals in different positions of the display panel, thereby improving the display quality.

[0122] In one exemplary embodiment, such as Figure 7 As shown, the second GOA circuit 22 may include: GOA units GP999 (level 999) to GP1002 (level 1002), which are alternately connected to the first clock signal line group and the second clock signal line group. The fourth GOA circuit 24 may include: GOA units GP1999 (level 1999) to GP2002 (level 2002), which are alternately connected to the second clock signal line group and the third clock signal line group. Thus, a transition section is set between the first and second first display areas of the display panel, using the first and second clock signal line groups alternately connected to the second GOA circuit. Similarly, a transition section is set between the second and third first display areas of the display panel, using the second and third clock signal line groups alternately connected to the second GOA circuit. This avoids screen splitting issues caused by Tr / Tf transitions between the two clock signal line groups corresponding to adjacent first display areas, while reducing the Tr / Tf operating range of the clock signal in each clock signal line group.

[0123] For example, such as Figure 7As shown, the 999th level GOA unit GP999 is connected to the first clock signal line group and is correspondingly connected to the 999th scan signal line S999; the 1000th level GOA unit GP1000 is connected to the second clock signal line group and is correspondingly connected to the 1000th scan signal line S1000; the 1001st level GOA unit GP1001 is connected to the first clock signal line group and is correspondingly connected to the 1001st scan signal line S1001; and the 1002nd level GOA unit GP1002 is connected to the second clock signal line group and is correspondingly connected to the 1002nd scan signal line S1002. The 1999th level GOA unit GP1999 is connected to the second clock signal line group and corresponds to the 1999th scan signal line S1999. The 2000th level GOA unit GP2000 is connected to the third clock signal line group and corresponds to the 2000th scan signal line S2000. The 2001st level GOA unit GP2001 is connected to the second clock signal line group and corresponds to the 2001st scan signal line S2001. The 2002nd level GOA unit GP2002 is connected to the third clock signal line group and corresponds to the 2002nd scan signal line S2002.

[0124] Alternatively, the 999th level GOA unit GP999 can be connected to the second clock signal line group and correspondingly connected to the 999th scan signal line S999; the 1000th level GOA unit GP1000 can be connected to the first clock signal line group and correspondingly connected to the 1000th scan signal line S1000; the 1001st level GOA unit GP1001 can be connected to the second clock signal line group and correspondingly connected to the 1001st scan signal line S1001; and the 1002nd level GOA unit GP1002 can be connected to the first clock signal line group and correspondingly connected to the 1002nd scan signal line S1002. The 1999th level GOA unit GP1999 is connected to the 3rd clock signal line group and corresponds to the 1999th scan signal line S1999. The 2000th level GOA unit GP2000 is connected to the 2nd clock signal line group and corresponds to the 2000th scan signal line S2000. The 2001st level GOA unit GP2001 is connected to the 3rd clock signal line group and corresponds to the 2001st scan signal line S2001. The 2002nd level GOA unit GP2002 is connected to the 2nd clock signal line group and corresponds to the 2002nd scan signal line S2002.

[0125] In one exemplary embodiment, taking all GOA units as Gate GOA P(GP) units and the display panel as having 3000 GOA units (GP1 to GP3000) as an example, the first-level GOA units GP1 to the 1000th-level GOA units GP1000 can be cascaded. The first GOA circuit 21 can be configured to generate scan signals to be provided to the scan signal lines (first scan signal line S1 to 1000th scan signal line S1000) of the first display area 11 by using clock signals received from the first clock signal line group, etc., so as to realize line-by-line scanning of the scan signal lines of the first display area 11. For example, the first GOA circuit 21 can be configured to sequentially provide scan signals with conduction level pulses to the scan signal lines S1, S2, ... and S1000 of the first display area 11. The 1001st level GOA unit GP1001 to the 2000th level GOA unit GP2000 can be cascaded. The second GOA circuit 22 can be configured to generate scan signals (1001st scan signal line S1001 to 2000th scan signal line S2000) to be provided to the scan signal lines of the third display area 13 by using clock signals received from the second clock signal line group, so as to realize line-by-line scanning of the scan signal lines of the third display area 13. For example, the second GOA circuit 22 can be configured to sequentially provide scan signals with conduction level pulses to the scan signal lines S1001, S1002, ... and S2000 of the third display area 13. The 2001st level GOA unit GP2001 to the 3000th level GOA unit GP3000 can be cascaded. The third GOA circuit 23 can be configured to generate scan signals to be provided to the scan signal lines (such as the 2001st scan signal line S2001 to the 3000th scan signal line S3000) of the fifth display area 15 by using clock signals received from the third clock signal line group (such as the 5th clock signal line CK5 and the 6th clock signal line CK6), so as to realize line-by-line scanning of the scan signal lines of the fifth display area 15. For example, the third GOA circuit 23 can be configured to sequentially provide scan signals with conduction level pulses to the scan signal lines S2001, S2002, ... and S3000 of the fifth display area 15.

[0126] This disclosure also provides a display device. The display device may include the display panel described in one or more of the exemplary embodiments above.

[0127] In one exemplary embodiment, the display device may include, but is not limited to, an LCD display device, such as an in-vehicle display device. This disclosure does not limit the scope of the embodiment.

[0128] In one exemplary embodiment, taking an in-vehicle display device as an example, when the size of the in-vehicle display device is less than 15 inches, a display panel with two clock signal lines per clock signal line can be used to achieve GOA dual-sided driving; or, when the size of the in-vehicle display device is greater than 15 inches, a display panel with four clock signal lines per clock signal line can be used to achieve GOA dual-sided driving.

[0129] Figure 8 This is a schematic diagram of the structure of the display device in an embodiment of this disclosure. Figure 8 As shown, the display panel may include: a timing control circuit, a data driving circuit, a Gate GOA circuit, an EM GOA circuit, and a pixel array. The timing control circuit is connected to the data driving circuit, the Gate GOA circuit, and the EM GOA circuit. The data driving circuit is connected to multiple data signal lines (D1 to Dn), the Gate GOA circuit is connected to multiple scan signal lines (S1 to Sm), and the EM GOA circuit is connected to multiple light emission signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emission device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light emission signal lines, and the data signal lines.

[0130] In one exemplary embodiment, the timing control circuit can provide grayscale values ​​and control signals of specifications suitable for the data driving circuit to the data driving circuit, provide clock signals, scan start signals, etc. of specifications suitable for the Gate GOA circuit to the Gate GOA circuit, and provide clock signals, light-emitting stop signals, etc. of specifications suitable for the EM GOA circuit to the EM GOA circuit. For example, the timing control circuit can be provided in the driver IC.

[0131] In one exemplary embodiment, the data driving circuit may use grayscale values ​​and control signals received from the timing control circuit to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driving circuit may use a clock signal to sample the grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-row basis, where n can be a natural number.

[0132] In one exemplary embodiment, the Gate GOA circuit can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from a timing control circuit. For example, the Gate GOA circuit can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the Gate GOA circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number.

[0133] In one exemplary embodiment, the EM GOA circuit can generate transmit signals to be provided to the light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, light-emitting stop signals, etc., from a timing control circuit. For example, the EM GOA circuit can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the EM GOA circuit can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0134] In one exemplary embodiment, the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. For example, the pixel driving circuit may be a circuit structure such as 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C. Here, the embodiments of this disclosure do not limit this.

[0135] In one exemplary embodiment, the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel. For example, the light-emitting device may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), etc. Here, the embodiments of this disclosure do not limit the scope of the application.

[0136] In one exemplary embodiment, the scan signal line, the light emission control signal line, and the reset control signal line RS (reset) can extend horizontally, and the data signal line can extend vertically.

[0137] In one exemplary embodiment, the display device may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P may include: a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the three sub-pixels may include: a thin-film transistor, a pixel electrode, and a common electrode. For example, the first sub-pixel P1 may be a red sub-pixel emitting red (R) light, the second sub-pixel P2 may be a green sub-pixel emitting green (G) light, and the third sub-pixel P3 may be a blue sub-pixel emitting blue (B) light. For example, a pixel unit may include four sub-pixels; however, this embodiment of the present disclosure does not limit this to four sub-pixels.

[0138] In one exemplary embodiment, the multiple sub-pixels in a pixel unit can be arranged in a horizontal, vertical, X-shaped, cross-shaped, or triangular pattern. For example, if a pixel unit includes three sub-pixels, the three sub-pixels can be arranged in a horizontal, vertical, or triangular pattern. For example, if a pixel unit includes four sub-pixels, the four sub-pixels can be arranged in a horizontal, vertical, or square pattern. This disclosure does not limit the scope of the embodiments.

[0139] In one exemplary embodiment, the shape of a sub-pixel in a pixel unit can be any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, and other polygons. This disclosure does not limit the shape of the sub-pixel.

[0140] In one exemplary embodiment, the display device may include, but is not limited to, any product or component with display functionality such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. This disclosure does not limit the scope of the embodiment.

[0141] The description of the above display device embodiments is similar to that of the above display panel embodiments, and has similar beneficial effects. For technical details not disclosed in the display device embodiments of this disclosure, those skilled in the art should refer to the description in the display panel embodiments of this disclosure for understanding, and will not repeat them here.

[0142] While the embodiments disclosed herein are as described above, the above content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein, but the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display panel, comprising: A display area and a non-display area that at least partially surrounds the display area; wherein... The display area includes: M first display areas arranged sequentially along a first direction, each first display area including: a plurality of first signal lines arranged sequentially along the first direction and extending along a second direction, the second direction intersecting the first direction; The non-display area includes: M first array substrate gate driving GOA circuits and M clock signal line groups. The clock signal line groups include: multiple clock signal lines, and at least two clock signal lines are respectively located in at least two of the M clock signal line groups. The first array substrate gate driving circuit includes: multiple first array substrate gate driving units. The multiple first array substrate gate driving units in the m-th first array substrate gate driving circuit are connected to at least one of the multiple clock signal lines in the m-th clock signal line group. The multiple first array substrate gate driving units in the m-th first array substrate gate driving circuit are connected one-to-one with the multiple first signal lines in the m-th first display area. M is a positive integer greater than or equal to 2, and m is a positive integer less than or equal to M. The M clock signal line groups correspond to the M first display areas and the M first array substrate gate drive GOA circuits; The M clock signal line groups include a first clock signal line group, a second clock signal line group, and a third clock signal line group. The first clock signal line group includes a first clock signal line and a second clock signal line. The second clock signal line group includes a third clock signal line and a fourth clock signal line. The third clock signal line group includes a fifth clock signal line and a sixth clock signal line. The non-display area includes a first first GOA circuit, a second first GOA circuit, and a third first GOA circuit; The clock signal lines connected to the first first GOA circuit include only the first clock signal line and the second clock signal line; The clock signal lines connected to the second first GOA circuit include only the third clock signal line and the fourth clock signal line; The clock signal lines connected to the third first GOA circuit include only the fifth clock signal line and the sixth clock signal line.

2. The display panel according to claim 1, wherein, The non-display area includes: a bonding area located on one side of the first direction of the display area and a border area located on other sides of the display area. The bonding area includes: an integrated circuit configured to output clock signals to the M clock signal line groups. The M first array substrate gate driving circuits and the M clock signal line groups are located in the border area.

3. The display panel according to claim 2, wherein, The rise time of the clock signal in the k-th clock signal line group is less than the rise time of the clock signal in the (k+1)-th clock signal line group, and the fall time of the clock signal in the k-th clock signal line group is less than the fall time of the clock signal in the (k+1)-th clock signal line group, where k is a positive integer less than or equal to M-1.

4. The display panel according to claim 3, wherein, The k-th clock signal line group is located on the side of the (k+1)-th clock signal line group that is furthest from the display area.

5. The display panel according to any one of claims 1 to 4, wherein, The display area further includes a second display area located between two adjacent first display areas, the second display area including a plurality of second signal lines alternately arranged along the first direction and extending along the second direction; The non-display area further includes: a second array substrate gate driving circuit corresponding to the second display area, the second array substrate gate driving circuit including: a plurality of second array substrate gate driving units; An odd number of second array substrate gate driving units are connected to at least one of the multiple clock signal lines of the clock signal line group connected to one of the two adjacent first display areas, and an even number of second array substrate gate driving units are connected to at least one of the multiple clock signal lines of the clock signal line group connected to the other of the two adjacent first display areas, and the multiple second array substrate gate driving units are connected to multiple second signal lines in a one-to-one correspondence.

6. The display panel according to claim 5, wherein, The number of the second display areas is M-1. The nth second display area is located between the nth first display area and the (n+1)th first display area, where n is a positive integer less than or equal to M-1.

7. The display panel according to claim 5, wherein, The number of gate driving units of the second array substrate is less than the number of gate driving units of the first array substrate.

8. The display panel according to claim 5, wherein, In each second array substrate gate driving circuit, the number of second array substrate gate driving units is an even number greater than or equal to 4.

9. The display panel according to claim 5, wherein, Both the first array substrate gate driving unit and the second array substrate gate driving unit include any one of the following: a gate array substrate gate driving unit, a light-emitting array substrate gate driving unit, and a reset array substrate gate driving unit.

10. The display panel according to claim 5, wherein, Both the first signal line and the second signal line include any one of the following: a scan signal line, a light emission control signal line, and a reset control signal line.

11. The display panel according to any one of claims 1 to 4, wherein, The non-display area includes: two clock signal line groups, three clock signal line groups, or four clock signal line groups.

12. The display panel according to any one of claims 1 to 4, wherein, Each clock signal line group includes either two clock signal lines or four clock signal lines.

13. The display panel according to any one of claims 1 to 4, wherein, The number of first signal lines in the M first display areas is the same, or the number of first signal lines in at least two of the M first display areas is different.

14. The display panel according to any one of claims 1 to 4, wherein, M clock signal line groups are disposed on the side of the M first array substrate gate driving circuits away from the display area.

15. A display device, comprising: The display panel as described in any one of claims 1 to 14.

Images