Array substrate and display panel

Abstract

The embodiments of the present application disclose an array substrate and a display panel. In the array substrate, a second line segment includes a connecting portion and a routing portion, and a second signal line includes a third line segment. The third line segment is disposed on the same layer as the second line segment and adjacent to the first insulating layer. The third line segment is connected to a gate drive circuit unit, the connecting portion is connected to the first line segment, and the routing portion is connected to the connecting portion and the gate drive circuit unit. The second insulating layer covers the first insulating layer, the third line segment, and the second line segment. A retaining wall is disposed on a side of the second insulating layer away from the substrate. In an orthographic projection pattern of the array substrate, the boundary of the retaining wall does not simultaneously cover the connecting portion and the third line segment. The display panel of the present application employs a retaining wall whose boundary does not correspond to and cover the connecting portion and the third line segment, thereby reducing the risk of the second insulating layer cracking in the area between the connecting portion and the third line segment, thereby reducing the risk of shorting the second signal line and the first signal line.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] During the reliability test of the liquid crystal display panel, when the liquid crystal display panel appears black, one of the reasons is that an electric field is generated between the clock signal (CK) line and the low-frequency clock signal (LC) line in the gate drive circuit unit (GOA) integrated on the array substrate. Under the action of this electric field, copper ions in the two signal lines are precipitated and diffused in the horizontal direction, resulting in a short circuit between the clock signal line and the low-frequency clock signal line set on the same layer. Summary of the Invention

[0003] The embodiments of the present application provide an array substrate and a display panel, which can reduce the risk of short circuit between the second signal line and the first signal line.

[0004] An embodiment of the present application provides an array substrate, including a gate driving circuit unit, wherein the array substrate includes:

[0005] substrate;

[0006] a first signal line, the first signal line comprising a first line segment and a second line segment, the first line segment being arranged on the substrate, and the second line segment comprising a connecting portion and a routing portion;

[0007] a first insulating layer, the first insulating layer covering the substrate and the first line segment, and having at least one first via hole provided on the first insulating layer;

[0008] a second signal line, the second signal line including a third line segment, the third line segment being disposed on the same layer as the second line segment and adjacent to the first insulating layer, the third line segment being connected to the gate driving circuit unit, the connecting portion being connected to the first line segment through the first via and overlapping with the first line segment, one end of the routing portion being connected to the connecting portion, and the other end of the routing portion being connected to the gate driving circuit unit;

[0009] a second insulating layer, the second insulating layer covering the first insulating layer, the third line segment, and the second line segment; and

[0010] a retaining wall, the retaining wall being arranged on a side of the second insulating layer away from the substrate, the retaining wall being arranged to intersect the third line segment;

[0011] In the orthographic projection pattern of the array substrate, the boundary of the retaining wall does not cover the connecting portion and the third line segment at the same time.

[0012] Optionally, in some embodiments of the present application, in the orthographic projection pattern of the array substrate, the retaining wall is located on the periphery of the second line segment.

[0013] Optionally, in some embodiments of the present application, in the orthographic projection pattern of the array substrate, the retaining wall is located outside the first line segment away from the second line segment.

[0014] Optionally, in some embodiments of the present application, the array substrate includes a gate driving circuit unit, the first signal line is a low-frequency clock signal line, the second signal line is a clock signal line, the third line segment is connected to the gate driving circuit unit, and the routing portion is connected to the gate driving circuit unit;

[0015] The second signal line further includes a fourth line segment, the fourth line segment and the first line segment are in the same layer and spaced apart on the substrate, and the first insulating layer also covers the fourth line segment;

[0016] The fourth line segment is located on a side of the first line segment away from the gate driving circuit unit, the first insulating layer is provided with at least one second via hole, the second via hole exposes the fourth line segment, and the third line segment is connected to the fourth line segment through the second via hole;

[0017] In the orthographic projection pattern of the array substrate, the blocking wall is located between the first line segment and the fourth line segment.

[0018] Optionally, in some embodiments of the present application, the distance from the routing portion to the third line segment is greater than the distance from the connecting portion to the third line segment.

[0019] Optionally, in some embodiments of the present application, in the orthographic projection pattern of the array substrate, the retaining wall completely covers the second line segment.

[0020] Optionally, in some embodiments of the present application, the distance from the routing portion to the third line segment is greater than the distance from the connecting portion to the third line segment, wherein, in the orthographic projection pattern of the array substrate, the retaining wall at least completely covers the connecting portion.

[0021] Optionally, in some embodiments of the present application, in the orthographic projection pattern of the array substrate, the retaining wall also fully covers the first line segment.

[0022] Optionally, in some embodiments of the present application, the array substrate includes a gate driving circuit unit, the first signal line is a low-frequency clock signal line, the second signal line is a clock signal line, the third line segment is connected to the gate driving circuit unit, and the routing portion is connected to the gate driving circuit unit.

[0023] Optionally, in some embodiments of the present application, a hollow opening is formed on the first line segment, wherein, in the orthographic projection pattern of the array substrate, at least a portion of the hollow opening is located between the second line segment and the third line segment;

[0024] The first insulating layer covers the hollow opening to form a recessed groove, and at least a portion of the recessed groove is disposed between the second line segment and the third line segment.

[0025] Optionally, in some embodiments of the present application, there are multiple hollow openings, each of which extends along the short axis direction of the third line segment, and the multiple hollow openings are arranged at intervals along the long axis direction of the third line segment.

[0026] Optionally, in some embodiments of the present application, the hollow opening extends along the long axis direction of the third line segment.

[0027] Optionally, in some embodiments of the present application, the at least one first via hole is located on a side of the first line segment close to the gate driving circuit unit.

[0028] Optionally, in some embodiments of the present application, the distance between the second line segment and the third line segment is greater than or equal to 20.4 microns.

[0029] Optionally, in some embodiments of the present application, the thickness of the second insulating layer is greater than or equal to 1000 angstroms.

[0030] Optionally, in some embodiments of the present application, the array substrate further includes a planar layer, the material of the planar layer is an organic material, the planar layer covers the second insulating layer, and the retaining wall is arranged on a side of the planar layer away from the substrate.

[0031] Optionally, in some embodiments of the present application, the thermal expansion coefficient of the flat layer is smaller than the thermal expansion coefficient of the retaining wall, and larger than the thermal expansion coefficient of the second insulating layer.

[0032] An embodiment of the present application further provides a display panel, which includes an opposing substrate, a liquid crystal layer, and the array substrate as described in any one of the above embodiments, wherein the liquid crystal layer is arranged between the opposing substrate and the array substrate.

[0033] The array substrate of an embodiment of the present application includes a substrate, a first signal line, a first insulating layer, a second signal line, a second insulating layer and a retaining wall, the first signal line includes a first line segment and a second line segment, the first line segment is arranged on the substrate, and the second line segment includes a connecting portion and a routing portion; the first insulating layer covers the substrate and the first line segment, and at least one first via is provided on the first insulating layer; the second signal line includes a third line segment, the third line segment is on the same layer as the second line segment and is adjacently arranged on the first insulating layer, the third line segment is connected to the gate driving circuit unit, the connecting portion is connected to the first line segment through the first via and overlaps with the first line segment, one end of the routing portion is connected to the connecting portion, and the other end of the routing portion is connected to the gate driving circuit unit; the second insulating layer covers the first insulating layer, the third line segment and the second line segment; the retaining wall is arranged on a side of the second insulating layer away from the substrate, and the retaining wall is arranged to intersect with the third line segment; in the orthographic projection pattern of the array substrate, the boundary of the retaining wall does not cover the connecting portion and the third line segment at the same time.

[0034] The array substrate of the present application adopts a retaining wall whose boundary does not correspond to the covering connection part and the third line segment, that is, in the positive projection pattern of the array substrate, the boundary of the retaining wall does not divide the connection part and the third line segment into two parts respectively. That is to say, either the retaining wall avoids the area between the connection part and the third line segment, so that the thermal expansion stress of the retaining wall does not affect the second insulating layer in the area between the connection part and the third line segment, thereby reducing the risk of rupture of the second insulating layer in the area between the connection part and the third line segment, thereby reducing the risk of short circuit between the second signal line and the first signal line; or the retaining wall fully covers the area between the connection part and the third line segment, so that the thermal expansion stress of the retaining wall tends to be consistent in its influence on the second insulating layer in this area, thereby reducing the risk of rupture of the second insulating layer in this area, thereby reducing the risk of short circuit between the second signal line and the first signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 1 is a schematic diagram of a top view of the array substrate provided in Example 1 of the present application;

[0036] Figure 2 yes Figure 1 Enlarged view of part A;

[0037] Figure 3 yes Figure 1 Schematic diagram of the cross section along the CC line;

[0038] Figure 4 yes Figure 1 Another enlarged view of part A;

[0039] Figure 5 1 is a schematic diagram of a top view of the array substrate provided in Example 3 of the present application;

[0040] Figure 6 yes Figure 5Enlarged view of part A;

[0041] Figure 7 yes Figure 5 Schematic diagram of the cross section along the CC line. DETAILED DESCRIPTION

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as labels and do not impose numerical requirements or establish an order.

[0043] The embodiments of the present application provide an array substrate and a display panel, which are described in detail below. It should be noted that the order of description of the following embodiments does not limit the preferred order of the embodiments.

[0044] It should be noted that in the relevant technologies of the array substrate, the gate driving circuit unit needs to be connected to the clock signal and the low-frequency clock signal, and the clock signal and the low-frequency clock signal have a voltage difference, and an electric field will be generated between the clock signal line and the low-frequency clock signal line.

[0045] The clock signal line and the low-frequency clock signal are arranged on the same layer, and a thin inorganic insulating layer covers them. In addition, to prevent overflow of the alignment layer on the array substrate, a retaining wall is usually set above the low-frequency clock signal line. The boundary of the retaining wall divides the low-frequency clock signal line and the clock signal line into two parts, resulting in the inorganic insulating layer in the area between the low-frequency clock signal line and the clock signal line being divided into two areas.

[0046] Because the thermal expansion coefficient of the retaining wall is much greater than that of the inorganic insulating layer, the thermal expansion stresses experienced by the area with the retaining wall and the area without the retaining wall on the inorganic insulating layer differ under thermal stress, causing rupture at the junction of the two areas. The rupture of the inorganic insulating layer causes metal ions, such as copper ions, to precipitate from the clock signal line and the low-frequency clock signal line. These ions migrate and diffuse under the influence of the electric field, ultimately shorting the clock signal line and the low-frequency clock signal line.

[0047] Specifically, the low-frequency clock signal line includes a first line segment and a second line segment arranged in different layers and connected by vias. The clock signal line and the second line segment are arranged in the same layer and spaced apart. The inorganic insulating layer covers the second line segment and the clock signal line. On the inorganic insulating layer, an organic retaining wall is provided in the area corresponding to the second line segment and the clock signal line. The side boundary of the organic retaining wall passes through both the second line segment and the clock signal line, dividing the second line segment and the clock signal line into two parts. Due to the different thermal expansion coefficients of the organic retaining wall and the inorganic insulating layer, at a certain temperature, the portion of the second line segment and the clock signal line not covered by the retaining wall will be affected by thermal expansion stress, while the portion not covered by the retaining wall is not affected by the thermal expansion force of the retaining wall. This results in a difference in stress between the two corresponding areas of the inorganic insulating layer, which in turn leads to rupture at the junction of the two areas. Furthermore, under the action of a continuous electric field, copper ions diffuse horizontally and diffuse thermally in all directions, causing the second line segment of the clock signal line and the first signal line on the same layer to short-circuit.

[0048] The array substrate of the present application adopts a retaining wall whose boundary does not correspond to the covering connection part and the third line segment, that is, in the positive projection pattern of the array substrate, the boundary of the retaining wall does not divide the connection part and the third line segment into two parts respectively. That is to say, either the retaining wall avoids the area between the connection part and the third line segment, so that the thermal expansion stress of the retaining wall does not affect the second insulating layer in the area between the connection part and the third line segment, thereby reducing the risk of rupture of the second insulating layer in the area between the connection part and the third line segment, thereby reducing the risk of short circuit between the second signal line and the first signal line; or the retaining wall fully covers the area between the connection part and the third line segment, so that the thermal expansion stress of the retaining wall tends to be consistent in its influence on the second insulating layer in this area, thereby reducing the risk of rupture of the second insulating layer in this area, thereby reducing the risk of short circuit between the second signal line and the first signal line.

[0049] Example 1

[0050] Please refer to Figure 1-3 , an embodiment of the present application provides an array substrate 100.

[0051] The array substrate 100 includes a substrate 11 , a first signal line 12 , a first insulating layer 13 , a second signal line 14 , a second insulating layer 15 and a barrier rib 16 .

[0052] The first signal line 12 includes a first line segment 121 and a second line segment 122. The first line segment 121 is disposed on the substrate 11. The second line segment 122 includes a connecting portion 12a and a routing portion 12b.

[0053] The first insulating layer 13 covers the substrate 11 and the first line segment 121. At least one first via hole 131 is provided in the first insulating layer 13.

[0054] The second signal line 14 includes a third line segment 141, which is disposed adjacent to and in the same layer as the second line segment 122 on the first insulating layer 13. The connecting portion 12a is connected to the first line segment 121 through a first via 131 and overlaps with the first line segment 121. The routing portion 12b is connected to the connecting portion 12a.

[0055] The second insulating layer 15 covers the first insulating layer 13, the third line segment 141 and the second line segment 122. The retaining wall 16 is arranged on the side of the second insulating layer 15 away from the substrate 11. The retaining wall 16 is arranged to intersect with the third line segment 141. Figure 1 ), the boundary of the retaining wall 16 does not cover the connecting portion 12a and the third line segment 141 at the same time.

[0056] In the array substrate 100 of the first embodiment of the present application, the boundaries of the retaining wall 16 do not simultaneously cover the connecting portion 12a and the third line segment 141. The retaining wall 16 avoids the area between the connecting portion 12a and the third line segment 141, so that the thermal expansion stress of the retaining wall 16 does not affect the second insulating layer 15 in the area between the connecting portion 12a and the third line segment 141. This reduces the risk of the second insulating layer 15 in the area between the connecting portion 12a and the third line segment 141 breaking and cracking, thereby reducing the risk of shorting the second signal line 14 and the first signal line 12.

[0057] It should be noted that in the embodiment of the present application, the first signal line is a low-frequency clock signal and the second signal line is a clock signal line as an example, but it is not limited to this; as long as the first signal line and the second signal line meet the above-mentioned position and structure.

[0058] The array substrate 100 includes a gate driving circuit unit GOA. The third line segment 141 is connected to the gate driving circuit unit GOA. The other end of the wiring portion 12b is connected to the gate driving circuit unit GOA.

[0059] Optionally, the second line segment 122 and the third line segment 141 may be formed by the same photomask process, and the materials of the two may be the same.

[0060] Optionally, the material of the barrier rib 16 may be a transparent photoresist material. The material of the first insulating layer 13 and the second insulating layer 15 may each be one including but not limited to silicon oxide, silicon nitride and silicon oxynitride.

[0061] Optionally, the extending direction of the first line segment 121 intersects with the extending direction of the second line segment 122. For example, the extending direction of the first line segment 121 is perpendicular to the extending direction of the second line segment 122.

[0062] Optionally, in the orthographic projection pattern of the array substrate 100 , the barrier wall 16 is located on the periphery of the second line segment 122 .

[0063] Since the retaining wall 16 is located at the periphery of the second line segment 122 , the second line segment 122 is completely covered by the second insulating layer 15 on all sides, which can prevent the metal ions in the second line segment 122 from diffusing outward and thereby reduce the risk of short circuit between the first signal line 12 and the second signal line 14 .

[0064] Optionally, in the orthographic projection pattern of the array substrate 100 , the blocking wall 16 is located outside the first line segment 121 away from the second line segment 122 .

[0065] The retaining wall 16 is set on the outside of the first line segment 121 away from the second line segment 122. On the one hand, it can avoid the influence of the thermal expansion stress of the retaining wall 16 on the gate driving circuit unit GOA, thereby ensuring the stability and effectiveness of the gate driving circuit unit GOA; on the other hand, the retaining wall 16 is further away from the second line segment 122, thereby further reducing the risk of short circuit between the first signal line 12 and the second signal line 14.

[0066] Optionally, the second signal line 14 further includes a fourth line segment 142. The fourth line segment 142 is provided on the same layer as the first line segment 121 and is spaced apart from the first line segment 121 on the substrate 11. The first insulating layer 13 also covers the fourth line segment 142.

[0067] The fourth line segment 142 is located on a side of the first line segment 121 away from the gate driver circuit unit GOA. The first insulating layer 13 is provided with at least one second via 132, which exposes the fourth line segment 142. The third line segment 141 is connected to the fourth line segment 142 through the second via 132.

[0068] In the orthographic projection pattern of the array substrate 100 , the barrier wall 16 is located between the first line segment 121 and the fourth line segment 142 .

[0069] It is understandable that, since there is a voltage difference between the voltage connected to the second signal line 14 and the voltage connected to the first signal line 12 , a parasitic capacitance will be generated between the two.

[0070] The retaining wall 16 is disposed between the first line segment 121 and the fourth line segment 142 to increase the distance therebetween, thereby achieving the effect of reducing lateral parasitic capacitance.

[0071] Optionally, the first line segment 121 and the fourth line segment 142 may be formed by the same photomask process, and the materials of the two may be the same.

[0072] Optionally, the extending direction of the third line segment 141 intersects with the extending direction of the fourth line segment 142. For example, the extending direction of the third line segment 141 is perpendicular to the extending direction of the fourth line segment 142.

[0073] Optionally, the array substrate 100 includes a plurality of second signal lines 14 and at least one first signal line 12. This embodiment is described by taking four second signal lines 14 and two first signal lines as an example.

[0074] The plurality of fourth line segments 142 and the first line segments 121 are arranged along the extending direction of the third line segment 141. The third line segments 141 and the second line segments 122 are arranged alternately along the extending direction of the fourth line segment 142.

[0075] All the second signal lines 14 are located on a side of the first signal line 12 away from the gate driving circuit unit GOA.

[0076] Optionally, the extending direction of the fourth line segment 142 is parallel to the extending direction of the first line segment 121 .

[0077] Optionally, the thickness of the second insulating layer 15 is greater than or equal to 1000 angstroms, for example, it can be 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, 1500 angstroms, 1600 angstroms, 1700 angstroms, 1800 angstroms, 1900 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms or 4000 angstroms, etc.

[0078] The embodiment of the present application increases the thickness of the second insulating layer 15, thereby increasing the ability of the second insulating layer 15 to resist the thermal expansion stress of the retaining wall 16, reducing the risk of the second insulating layer 15 breaking, and improving the ability of the second insulating layer 15 to block the diffusion and migration of metal ions.

[0079] It should be noted that, compared with the array substrate of the related art, when other conditions remain constant and only the thickness of the second insulating layer 15 is thickened to 1000 angstroms, during the panel display test, the panel display is normal and the second signal line 14 and the first signal line 12 are not short-circuited.

[0080] Optionally, the distance between the second line segment 122 and the third line segment 141 is greater than or equal to 20.4 microns, for example, it can be 20.4 microns, 20.5 microns, 20.6 microns, 20.7 microns, 20.8 microns, 20.9 microns, 21 microns, 22 microns, 23 microns, 24 microns, 25 microns, 26 microns, 27 microns, 28 microns, 29 microns or 30 microns, etc.

[0081] Compared with the related art, setting the distance between the second line segment 122 and the third line segment 141 to be greater than or equal to 20.4 microns prolongs the diffusion and migration path of metal ions and further reduces the risk of short circuit between the second line segment 122 and the third line segment 141 .

[0082] It should be noted that, compared with the array substrate of the related technology, when other conditions remain constant and only the distance between the third line segment 141 and the second line segment 122 is extended to 20.4 microns, when performing a panel display test, the panel display is normal and the second signal line 14 and the first signal line 12 are not short-circuited.

[0083] Optionally, a distance d1 from the routing portion 12 b to the third line segment 141 is greater than a distance d2 from the connecting portion 12 a to the third line segment 141 .

[0084] Setting the distance d1 to be greater than the distance d2 increases the distance between the routing portion 12b and the third line segment 141, thereby increasing the path for metal ion diffusion and increasing the area of ​​the second insulating layer 15 that blocks metal ion diffusion, thereby further reducing the risk of short circuit between the second signal line 14 and the first signal line 12.

[0085] Optionally, the width of the end of the routing portion 12b connected to the connecting portion 12a is gradually decreasing. The width of the end of the routing portion 12b connected to the connecting portion 12a gradually decreases from the connecting portion 12a toward the gate driver circuit unit GOA. This can increase the distance between the routing portion 12b and the third line segment 141 while reducing the risk of breakage between the routing portion 12b and the connecting portion 12a.

[0086] Optionally, the array substrate 100 further includes a planar layer 17 , which is made of an organic material. The planar layer 17 covers the second insulating layer 15 . The retaining wall 16 is disposed on a side of the planar layer 17 away from the substrate 11 .

[0087] A flat layer 17 is used to cover the second insulating layer 15 to provide a flat base surface for the retaining wall 16, which facilitates the formation of a retaining wall 16 with uniform height; in addition, the flat layer 17 is an organic material, which can absorb a certain amount of stress, alleviate the impact of the thermal expansion stress of the retaining wall 16 on the second insulating layer 15, and reduce the risk of the second insulating layer 15 breaking.

[0088] Optionally, the thermal expansion coefficient of the flat layer 17 is smaller than the thermal expansion coefficient of the retaining wall 16 , and larger than the thermal expansion coefficient of the second insulating layer 15 .

[0089] Among them, the thermal expansion coefficient of the flat layer 17 is between the thermal expansion coefficients of the retaining wall 16 and the second insulating layer 15, so that the stress of the retaining wall 16 on the second insulating layer 15 is buffered, reducing the impact of the thermal expansion stress of the retaining wall 16 on the second insulating layer 15, thereby reducing the risk of short circuit between the second signal line 14 and the first signal line 12.

[0090] Optionally, the material of the planar layer 17 may be, but is not limited to, transparent photoresist.

[0091] Optionally, at least one first via hole 131 is located on a side of the first line segment 121 close to the gate driving circuit unit GOA.

[0092] Optionally, the plurality of first vias 131 are all located on the side of the first line segment 121 close to the gate driver circuit unit GOA. In the extension direction of the first line segment 121, the overlapping area of ​​the second line segment 122 and the third line segment 141 can be reduced, thereby reducing the risk of short circuit between the two.

[0093] Optional, please refer to Figure 2 and Figure 3 A hollow opening 12c is formed on the first line segment 121, wherein, in the orthographic projection pattern of the array substrate 100, at least a portion of the hollow opening 12c is located between the second line segment 122 and the third line segment 141;

[0094] The first insulating layer 13 covers the hollow opening 12 c to form a recessed groove 13 a . At least a portion of the recessed groove 13 a is disposed between the second line segment 122 and the third line segment 141 .

[0095] In the embodiment of the present application, a hollow opening 12c is opened in the first line segment 121, and at least a part of the area of ​​the hollow opening 12c is blocked between the second line segment 122 and the third line segment 141, so that the first insulating layer 13 covers the hollow opening 12c to form a recessed groove 13a, thereby extending the diffusion path of the metal ions; in addition, in the area of ​​the hollow opening 12c, the third line segment 141 and the second line segment 122 have a height difference, and the first insulating layer 13 covers the side wall of the hollow opening 12c to form a boss, which can block the metal ions in the third line segment 141 from diffusing to the second line segment 122; the second insulating layer 15 covers the recessed groove 13a, thereby increasing the area of ​​the second insulating layer 15 that blocks the diffusion of metal ions.

[0096] In addition, the hollow opening 12c is provided to facilitate light transmission, thereby accelerating the curing of the sealant.

[0097] Optionally, there are multiple hollow openings 12c, and the hollow openings 12c extend along the short axis direction of the third line segment 141. The multiple hollow openings 12c are arranged at intervals along the long axis direction of the third line segment 141.

[0098] The provision of the plurality of hollow openings 12 c increases the light transmittance while enlarging the effective area for intercepting the diffusion of metal ions, thereby reducing the risk of short circuit between the third line segment 141 and the second line segment 122 .

[0099] The third line segment 141 extends and covers the plurality of hollow openings 12 c , so that the portion of the third line segment 141 on the first line segment 121 forms a concave-convex structure, thereby improving the performance of the third line segment 141 in resisting thermal expansion stress.

[0100] Implementation II

[0101] like Figure 4 As shown, the difference between the second embodiment and the first embodiment is that the hollow opening 12c extends along the long axis direction of the third line segment 141 and is arranged between the third line segment 141 and the second line segment 122 .

[0102] Compared with the solution of using multiple vertical hollow openings 12c in embodiment 1, a long strip of hollow opening 12c is used between the third line segment 141 and the second line segment 122, which has a larger effective area for intercepting the diffusion of metal ions, thereby reducing the risk of short circuit between the third line segment 141 and the second line segment 122.

[0103] In the extending direction of the first line segment 121 , the third line segment 141 is arranged between two adjacent hollow openings 12 c.

[0104] It should be noted that, except for the shape and position of the hollow opening 12c, the structure of the second embodiment is similar or identical to that of the first embodiment.

[0105] Example 3:

[0106] Please refer to Figure 5-Figure 7 The difference between this embodiment and the first and second embodiments is that the position of the retaining wall 16 is different.

[0107] Specifically, the distance d1 from the routing portion 12b to the third line segment 141 is greater than the distance d2 from the connecting portion 12a to the third line segment 141 , wherein in the orthographic projection pattern of the array substrate 100 , the retaining wall 16 at least fully covers the connecting portion 12a .

[0108] In the array substrate 100 of the third embodiment, the boundaries of the retaining wall 16 do not correspond to the covering connection portion 12a and the third line segment 141. The retaining wall 16 fully covers the connection portion 12a and the portion of the third line segment 141 along the extension direction of the first line segment 121. The retaining wall 16 covers the area between the connection portion 12a and the third line segment 141. This ensures that the thermal expansion stress of the retaining wall 16 has a uniform effect on the second insulating layer 15 in this area, reducing the risk of cracking the second insulating layer 15 in this area due to uneven stress, thereby reducing the risk of shorting the second signal line 14 and the first signal line 12.

[0109] Optionally, in the orthographic projection pattern of the array substrate 100 , the retaining wall 16 also completely covers the first line segment 121 .

[0110] The retaining wall 16 completely covers the first line segment 121 to expand the contact area between the retaining wall 16 and the flat layer 17 and improve stability.

[0111] Secondly, since the first line segment 121 forms a capacitor with the common electrode on the color filter substrate, the retaining wall 16 fully covers the first line segment 121, which can improve the uniformity and stability of the capacitor.

[0112] In another structure of this embodiment, in the orthographic projection pattern of the array substrate 100 , the retaining wall 16 completely covers the second line segment 122 .

[0113] It should be noted that, except for the position of the retaining wall 16 , the other structures of the third embodiment are similar or identical to those of the first and second embodiments.

[0114] Example 4:

[0115] An embodiment of the present application further provides a display panel, which includes an opposing substrate, a liquid crystal layer, and an array substrate 100 as described in any one of the above embodiments, wherein the liquid crystal layer is disposed between the opposing substrate and the array substrate 100 .

[0116] The array substrate of the display panel of the embodiment of the present application includes a substrate, a first signal line, a first insulating layer, a second signal line, a second insulating layer and a retaining wall, the first signal line includes a first line segment and a second line segment, the first line segment is arranged on the substrate, and the second line segment includes a connecting portion and a routing portion; the first insulating layer covers the substrate and the first line segment, and at least one first via is provided on the first insulating layer; the second signal line includes a third line segment, the third line segment is on the same layer as the second line segment and is adjacently arranged on the first insulating layer, the third line segment is connected to the gate driving circuit unit, the connecting portion is connected to the first line segment through the first via and overlaps with the first line segment, one end of the routing portion is connected to the connecting portion, and the other end of the routing portion is connected to the gate driving circuit unit; the second insulating layer covers the first insulating layer, the third line segment and the second line segment; the retaining wall is arranged on a side of the second insulating layer away from the substrate, and the retaining wall is arranged to intersect with the third line segment; in the orthographic projection pattern of the array substrate, the boundary of the retaining wall does not cover the connecting portion and the third line segment at the same time.

[0117] The display panel of the present application adopts a retaining wall whose boundary does not correspond to the covering connection part and the third line segment, that is, in the positive projection pattern of the array substrate, the boundary of the retaining wall does not divide the connection part and the third line segment into two parts respectively. That is to say, either the retaining wall avoids the area between the connection part and the third line segment, so that the thermal expansion stress of the retaining wall does not affect the second insulating layer in the area between the connection part and the third line segment, thereby reducing the risk of rupture of the second insulating layer in the area between the connection part and the third line segment, thereby reducing the risk of short circuit between the second signal line and the first signal line; or the retaining wall fully covers the area between the connection part and the third line segment, so that the thermal expansion stress of the retaining wall tends to be consistent in its influence on the second insulating layer in this area, thereby reducing the risk of rupture of the second insulating layer in this area, thereby reducing the risk of short circuit between the second signal line and the first signal line.

[0118] It should be noted that the structure of the array substrate of the display panel in the embodiment of the present application is similar to or identical to the structure of the array substrate 100 in any one of Embodiments 1-3.

[0119] The above is a detailed introduction to an array substrate and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: The array substrate includes: substrate; a first signal line, the first signal line comprising a first line segment and a second line segment, the first line segment being arranged on the substrate, and the second line segment comprising a connecting portion and a routing portion; a first insulating layer, the first insulating layer covering the substrate and the first line segment, and having at least one first via hole provided on the first insulating layer; a second signal line, the second signal line including a third line segment, the third line segment being disposed on the same layer as the second line segment and adjacent to the first insulating layer, the connecting portion being connected to the first line segment through the first via and overlapping with the first line segment, and the routing portion being connected to the connecting portion; a second insulating layer, the second insulating layer covering the first insulating layer, the third line segment, and the second line segment; and a retaining wall, the retaining wall being arranged on a side of the second insulating layer away from the substrate, the retaining wall being arranged to intersect the third line segment; In the orthographic projection pattern of the array substrate, the boundary of the retaining wall does not cover the connecting portion and the third line segment at the same time.

2. The array substrate according to claim 1, wherein: In the orthographic projection pattern of the array substrate, the retaining wall is located on the periphery of the second line segment.

3. The array substrate according to claim 2, wherein: In the orthographic projection pattern of the array substrate, the blocking wall is located outside the first line segment away from the second line segment.

4. The array substrate according to claim 3, wherein: The array substrate includes a gate driving circuit unit, the first signal line is a low-frequency clock signal line, the second signal line is a clock signal line, the third line segment is connected to the gate driving circuit unit, and the routing portion is connected to the gate driving circuit unit; The second signal line further includes a fourth line segment, the fourth line segment and the first line segment are in the same layer and spaced apart on the substrate, and the first insulating layer also covers the fourth line segment; The fourth line segment is located on a side of the first line segment away from the gate driving circuit unit, the first insulating layer is provided with at least one second via hole, the second via hole exposes the fourth line segment, and the third line segment is connected to the fourth line segment through the second via hole; In the orthographic projection pattern of the array substrate, the blocking wall is located between the first line segment and the fourth line segment.

5. The array substrate according to claim 2, wherein: The distance from the routing portion to the third line segment is greater than the distance from the connecting portion to the third line segment.

6. The array substrate according to claim 1, wherein: The distance from the routing portion to the third line segment is greater than the distance from the connecting portion to the third line segment, wherein, in the orthographic projection pattern of the array substrate, the retaining wall at least completely covers the connecting portion.

7. The array substrate according to claim 6, wherein: In the orthographic projection pattern of the array substrate, the retaining wall also completely covers the first line segment.

8. The array substrate according to claim 7, wherein: The array substrate includes a gate driving circuit unit, the first signal line is a low-frequency clock signal line, the second signal line is a clock signal line, the third line segment is connected to the gate driving circuit unit, and the routing portion is connected to the gate driving circuit unit.

9. The array substrate according to any one of claims 1 to 8, wherein: A hollow opening is formed on the first line segment, wherein, in the orthographic projection pattern of the array substrate, at least a portion of the hollow opening is located between the second line segment and the third line segment; The first insulating layer covers the hollow opening to form a recessed groove, and at least a portion of the recessed groove is disposed between the second line segment and the third line segment.

10. The array substrate according to claim 9, wherein: There are multiple hollow openings, each of which extends along the short axis direction of the third line segment, and the multiple hollow openings are arranged at intervals along the long axis direction of the third line segment.

11. The array substrate according to claim 9, wherein: The hollow opening extends along the long axis direction of the third line segment.

12. The array substrate according to claim 8, wherein: The at least one first via hole is located on a side of the first line segment close to the gate driving circuit unit.

13. The array substrate according to any one of claims 1 to 8, characterized in that: A distance between the second line segment and the third line segment is greater than or equal to 20.4 micrometers.

14. The array substrate according to any one of claims 1 to 8, wherein: The thickness of the second insulating layer is greater than or equal to 1000 angstroms.

15. The array substrate according to any one of claims 1 to 8, characterized in that: The array substrate further includes a planar layer made of an organic material. The planar layer covers the second insulating layer. The retaining wall is arranged on a side of the planar layer away from the substrate.

16. A display panel, characterized in that: The invention comprises an opposing substrate, a liquid crystal layer and the array substrate according to any one of claims 1 to 15, wherein the liquid crystal layer is arranged between the opposing substrate and the array substrate.

Images