A method for embedding PDK with map dependency effect

Abstract

A method for embedding layout dependency effects into a PDK (Programmable Module Kids) includes the following steps: extracting the PDK specification definition table of simulation effects from the component model of the Spice circuit simulation; defining the component description format parameters of the parameterized cells; defining the callback functions corresponding to the component description format parameters according to the specification; defining the netlist functions corresponding to the layout dependency effects in the simulation information definition interface of the parameterized cells; drawing the layout according to the component description format parameter definition of the layout dependency effects; and compiling and creating multiple cells in the parameterized cell library, including: symbol cells, simulation cells, and layout cells. This invention embeds layout dependency effects into the PDK within the parameterized cells, enabling better, faster, and more accurate simulation of device performance, improving circuit design accuracy, and thus ensuring that the PDK can be stably and efficiently applied to practical engineering projects.

Description

Technical Field

[0001] This invention relates to the field of semiconductor design and manufacturing technology, and in particular to a method for embedding PDK with layout-dependent effects. Background Technology

[0002] As CMOS process dimensions continue to shrink, the characteristics of nanoscale transistors indeed depend not only on gate width and gate length, but also on layout geometry parameters and surrounding devices. This is known as layout-dependent effect, which mainly includes LOD (length of oxide diffusion), WPE (well proximity effect), OSE (active area spacing effect), and PSE (poly space spacing effect). These effects have a significant impact on device performance and have become essential factors to consider in nanoscale process design kit (PDK) development. A process design kit (PDK) is a complete set of process documents. Embedding layout-dependent effect calculations within the PDK can help IC circuit designers fully consider the LOD / WPE impact of the called devices in the overall circuit, thereby ensuring that the final chip's quality and performance meet requirements. How to embed layout-dependent effects into the PDK has become a problem that needs to be solved in this field. Summary of the Invention

[0003] To address the shortcomings of existing technologies, the present invention aims to provide a method for embedding layout dependency effects into a PDK, involving the implementation of PDK parameterized units. This method is a design approach for realizing the layout dependency relationships of parameterized units. By developing a PDK that embeds layout dependency effects (LOD / WPE / OSE / PSE, etc.) into parameterized units, device performance can be simulated better, faster, and more accurately, improving circuit design precision and ensuring that the PDK can be stably and efficiently applied to practical engineering projects.

[0004] To achieve the above objectives, the present invention provides a method for embedding layout dependency effects into a PDK, comprising the following steps:

[0005] Extract the PDK specification definition table of simulation effects from the component model of Spice circuit simulation;

[0006] Define the component description format parameters for the parameterized unit;

[0007] The callback function corresponding to the component description format parameters is defined according to the specification.

[0008] Define the netlist function corresponding to the layout dependency effect in the simulation information definition interface of the parameterized unit;

[0009] Draw the layout according to the component description format parameter definition of the layout dependency effect;

[0010] The compilation creates multiple cells in the parameterized cell library, including symbol cells, simulation cells, and layout cells.

[0011] Furthermore, the layout-dependent effects include: oxide channel effect, well proximity effect, active region spacing effect, and gate spacing effect.

[0012] Furthermore, the layout influence parameters of the oxide channel effect include: gate length, gate width, and number of gates;

[0013] The simulation parameters corresponding to the component models of the Spice circuit simulation include: the distance of the active region extension, the gate spacing, the source area parameter, the drain area parameter, the source perimeter parameter, and the drain perimeter parameter.

[0014] Furthermore, the layout influence parameters of the well proximity effect include: the distance between the gate and the periphery of the channel;

[0015] The simulation parameters corresponding to the component models in Spice circuit simulation include: the first-order integral of the ion distribution scattered on the MOSFET channel, the second-order integral of the ion distribution scattered on the MOSFET channel, and the third-order integral of the ion distribution scattered on the MOSFET channel.

[0016] Furthermore, the layout influence parameters of the active area spacing effect include: gate width;

[0017] The simulation parameters corresponding to the component models in Spice circuit simulation include: shallow trench spacing and the number of vias connecting the source and drain in the MOS gate width direction.

[0018] Furthermore, the layout influence parameters of the gate spacing effect include: the number of polysilicon filler bars and the polysilicon spacing; the simulation parameters corresponding to the component model in the Spice circuit simulation include: the polysilicon filler spacing parameters.

[0019] Furthermore, the PDK specification definition table includes: device parameters and formula definitions.

[0020] Furthermore, the step of defining the callback function corresponding to the component description format parameter according to the specification further includes: checking whether the input value of the parameter conforms to the specification; and calculating and setting other related parameter values ​​based on the input value of the parameter.

[0021] To achieve the above objectives, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to execute the computer program stored in the memory to implement the layout dependency effect embedding PDK method as described above.

[0022] To achieve the above objectives, the present invention also provides a computer-readable storage medium storing at least one instruction, which is loaded and executed by a processor to implement the layout dependency effect embedding PDK method as described above.

[0023] The method for embedding layout dependency effects into PDK provided by this invention has the following advantages compared with the prior art:

[0024] Embedding layout-dependent effects (including LOD, WPE, OSE, and PSE effects) into the parameterized cell PDK allows circuit designers to fully consider the impact of process layout effects when selecting parameterized cell devices in the PDK from the schematic drawing stage. This reflects layout effects such as LOD in the pre-simulation results, thereby improving the simulation accuracy of the circuit and reducing the development and verification iteration cycle from schematic to layout.

[0025] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0027] Figure 1 This is a flowchart of a method for embedding PDK with layout dependency effect according to an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram illustrating the influence parameters of the LOD effect in the layout according to an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of the influence parameters of the WPE effect in the layout according to an embodiment of the present invention;

[0030] Figure 4 This is a schematic diagram illustrating the influence parameters of the OSE effect in the layout according to an embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of the influence parameters of the PSE effect in the layout according to an embodiment of the present invention;

[0032] Figure 6This is a schematic diagram of an electronic device structure according to an embodiment of the present invention. Detailed Implementation

[0033] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0034] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings. Although some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the accompanying drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0035] The LOD effect described in this article is caused by the difference in MOS current due to the different diffusion region lengths. The WPE effect refers to the uneven ion implantation concentration at the edge of the ion implantation well in semiconductor processing, which varies with the distance from the MOS to the well edge, thus affecting the electrical performance of the MOS transistor. The OSE effect is the effect on device performance caused by the different distances from the shallow trench isolation region (STI) to different gates. The PSE effect is the effect of different gate positions and spacings on the performance of a multi-gate MOS transistor.

[0036] The parameterized cells (PCells) of the PDK described in this article generally include schematic symbols, CDF parameters (Component Description Format, which is the parameter format defined for the parameterized cell), callback functions, simulation cells, and layout cells. The layout dependency effect of a PCell is directly related to its layout size. This can be addressed by embedding CDF definitions related to layout dependency effects and implementing the calculation process for each CDF parameter in the callback function.

[0037] Figure 1 The following is a flowchart of a method for embedding PDK with layout dependency effect according to an embodiment of the present invention, with reference to... Figure 1 The method of embedding the layout dependency effect into the PDK according to the present invention will be further explained.

[0038] In step 101, the PDKSpec table (PDK specification definition table, used for specification indicators and parameter alignment before PDK development) that affects the simulation is extracted from the Spice Model (component model for Spice circuit simulation). This table includes the device parameters and formula definitions.

[0039] In step 102, define the CDF parameters of PCell, including: CDF name, data type, default value, editable, display, and callback properties.

[0040] In step 103, the callback corresponding to the CDF parameter is defined according to the specification. This step includes: checking whether the input value of the parameter conforms to the specification; and calculating and setting another related parameter value based on the input value of one parameter.

[0041] In step 104, the netlist function corresponding to the layout dependency effect is defined in the SimInfo interface of PCell.

[0042] In step 105, draw the layout according to the PCell CDF definition.

[0043] In step 106, the compilation creates multiple cells in the PCell library, including the creation of the PCell symbol view, simulation view (including Spectre View and Hspice View), layout view, and aucdl view (a cell used for LVS (layout schematic comparison)).

[0044] In this embodiment, reference Figure 2 LOD effect, layout impact parameters: Gate Width, Gate Length, Fingers.

[0045] The simulation parameters corresponding to the Spice Model are: the distances of the active region extension (SA, SB), the gate spacing (SD), the source area (AS), the drain area (AD), the source perimeter (PS), and the drain perimeter (PD).

[0046] AS(Area of ​​Source)=SA*W+(Fingers / 2-1)*SD*W,

[0047] AD(Area of ​​Drain)=SB*W+(Fingers / 2)*SD*W,

[0048] PS(Perimeter of Source)=(SA+W)*2+(Fingers / 2-1)*(SD+W)*2,

[0049] PD(Perimeter of Drain)=(SB+W)*2+(Fingers / 2)*(SD+W)*2,

[0050] Where W represents the MOS channel length.

[0051] refer to Figure 3 WPE effect, layout-related parameters: distances SC1, SC2, SC3, SC4 between the Gate and the surrounding Well.

[0052] Simulation parameters corresponding to the Spice Model: SCA, SCB, SCC

[0053]

[0054]

[0055]

[0056] Where SCA is the first-order integral of the scattered ion distribution on the MOSFET channel, SCB is the second-order integral of the scattered ion distribution on the MOSFET channel, SCC is the third-order integral of the scattered ion distribution on the MOSFET channel, W represents the MOSFET channel length, and L represents the MOSFET channel width.

[0057] refer to Figure 4 OSE effect, layout influence parameter: Gate Width;

[0058] The simulation parameters corresponding to the Spice Model are: DSTS (STI Spacing, shallow trench spacing) and DCN (Number of Source / Drain Contact in W Dicrection, the number of vias connecting the source and drain in the MOS gate width direction).

[0059] refer to Figure 5PSE effect, layout-related parameters: Dummy Poly Number (number of polysilicon strips), PolySpacing (polysilicon spacing);

[0060] The simulation parameters corresponding to the Spice Model are: DPS (Dummy Poly Spacing, the spacing parameter for filling polysilicon).

[0061] The layout dependency effect embedding method of the present invention embeds the layout dependency effect into the parameter unit of the PDK. This allows circuit designers to fully consider the influence of process layout effects when selecting parameterized unit devices in the PDK from the schematic drawing stage. The layout effects such as LOD / WPE are reflected in the pre-simulation results, which improves the simulation accuracy of the circuit and reduces the development and verification iteration cycle from schematic to layout.

[0062] In embodiments of the present invention, an electronic device is also provided. Figure 6 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention, such as... Figure 6 As shown, the electronic device of the present invention includes a processor 601 and a memory 602, wherein,

[0063] The memory 602 stores a computer program, which, when read and executed by the processor 601, performs the steps described above in the method embodiment for embedding the layout dependency effect into the PDK.

[0064] In embodiments of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored in the computer program, wherein the computer program is configured to execute the steps in the method embodiment of the layout dependency effect embedding PDK as described above when running.

[0065] In this embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0066] It should be noted that the term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the following description.

[0067] The terms "one" and "a plurality of" used in this invention are illustrative and not restrictive. Those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "A plurality of" should be understood as two or more.

[0068] It will be understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for embedding layout dependency effects into a PDK, comprising the following steps: Extract the PDK specification definition table of simulation effects from the component model of Spice circuit simulation; Define the component description format parameters for the parameterized unit; The callback function corresponding to the component description format parameters is defined according to the specification. Define the netlist function corresponding to the layout dependency effect in the simulation information definition interface of the parameterized unit; Draw the layout according to the component description format parameter definition of the layout dependency effect; The compilation creates multiple cells in the parameterized cell library, including symbol cells, simulation cells, and layout cells; The layout-dependent effects include: oxide channel effect, well proximity effect, active region spacing effect, and gate spacing effect; The PDK specification definition table includes: device parameters and formula definitions; The step of defining the callback function corresponding to the component description format parameter according to the specification further includes: checking whether the input value of the parameter conforms to the specification; and calculating and setting other related parameter values ​​according to the input value of the parameter.

2. The method for embedding PDK with layout dependency effect according to claim 1, characterized in that, The layout-affecting parameters of the oxide channel effect include: gate length, gate width, and number of gates; The simulation parameters corresponding to the component models of the Spice circuit simulation include: the distance of the active region extension, the gate spacing, the source area parameter, the drain area parameter, the source perimeter parameter, and the drain perimeter parameter.

3. The method for embedding PDK with layout dependency effect according to claim 1, characterized in that, The well proximity effect Its layout-affected parameters include: the distance between the gate and the periphery of the channel; The simulation parameters corresponding to the component models in Spice circuit simulation include: the first-order integral of the ion distribution scattered on the MOSFET channel, the second-order integral of the ion distribution scattered on the MOSFET channel, and the third-order integral of the ion distribution scattered on the MOSFET channel.

4. The method for embedding PDK with layout dependency effect according to claim 1, characterized in that, The layout influence parameters of the active area spacing effect include: gate width; The simulation parameters corresponding to the component models in Spice circuit simulation include: shallow trench spacing and the number of vias connecting the source and drain in the MOS gate width direction.

5. The method for embedding PDK with layout dependency effect according to claim 1, characterized in that, The gate spacing effect, its layout influence parameters include: the number of polysilicon filler bars, the polysilicon spacing; the simulation parameters corresponding to the component model in the Spice circuit simulation include: the polysilicon filler spacing parameters.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor is configured to execute the computer program stored in the memory to implement the layout dependency effect embedding PDK method according to any one of claims 1 to 5.

7. A computer-readable storage medium, characterized in that, The storage medium stores at least one instruction, which is loaded and executed by a processor to implement the layout dependency effect embedding PDK method according to any one of claims 1 to 5.

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