standalone mode

Abstract

Devices and techniques for implementing an independent mode are described. The independent mode refers to a mode in which a die designed to operate as one of a plurality of interconnected dies can operate independently of another of the plurality of dies. The die can perform independent read operations and / or independent write operations in accordance with the independent mode prior to connecting the die to the other die. In this way, testing or debugging can be performed during an early stage in a manufacturing process prior to integrating the die into an interconnected die architecture. For example, this type of testing can be performed at a wafer level or at a single-die package (SDP) level. In general, the independent mode can be performed independent of whether the die is connected to the other die.

Description

Technical Field

[0001] Embodiments of this application relate to memory devices and technologies, and more particularly, to devices and technologies for implementing stand-alone modes. Background Technology

[0002] The processor executes code based on data to run applications and provide features to the user. The processor obtains code and data from memory that can store information. Therefore, like the processor's speed or the number of cores, the characteristics of memory can affect the performance of an electronic device. Different types of memory have different characteristics. Memory types include volatile memory and non-volatile memory, such as random access memory (RAM) and flash memory. RAM can include static RAM (SRAM) and dynamic RAM (DRAM).

[0003] The demand for different types of memory continues to evolve and grow. For example, processors, designed to execute code faster, benefit from faster memory access. Applications also operate on increasingly larger datasets using ever-growing amounts of memory. Energy constraints on memory systems are becoming more prevalent due to battery-powered electronics and power-hungry data centers. Furthermore, as the form factor of portable electronic devices continues to shrink, manufacturers may seek smaller memory. Therefore, meeting these diverse needs is complex due to the different advantages and capabilities of different types of memory. Summary of the Invention

[0004] According to one embodiment of this disclosure, an apparatus is provided. The apparatus includes a die. The die includes: data pins; connection data pins configured to float; and a memory array. The die is configured to operate according to an independent mode based on the floating connection data pins, the independent mode utilizing the data pins and the memory array.

[0005] According to one embodiment of this disclosure, a method is provided. The method includes the following steps: receiving a request to perform an independent write operation on a die; accepting a write data burst at a data pin of the die based on the independent write operation, the write data burst including a first block and a second block; and writing the first block of the write data burst to a memory array of the die based on the independent write operation.

[0006] According to an embodiment of this disclosure, a method is provided. The method includes the following steps: receiving a request to perform an independent read operation via a die; reading a first block of a read data burst from a memory array of the die based on the independent read operation; generating a second block of the read data burst based on the independent read operation; and transmitting the first block and the second block of the read data burst to a data pin of the die based on the independent read operation.

[0007] According to one embodiment of this disclosure, an apparatus is provided. The apparatus includes a die. The die includes a connection data pin configured to either float or be coupled to another connection data pin of another die among a plurality of dies. The die is configured to selectively perform an independent read operation or an independent write operation based on the connection data pin being floated; and to perform a read operation or a write operation jointly with the other die among the plurality of dies based on the other connection data pin coupled to the other die. Attached Figure Description

[0008] Refer to the following diagrams to describe the equipment and technologies used to implement the stand-alone mode. The same numbers are used throughout the diagrams to refer to similar features and components:

[0009] Figure 1 Describe the operating environment of an instance of a device that includes aspects that can implement standalone modes;

[0010] Figure 2 Describe an example computing system that can implement independent modes;

[0011] Figure 3 This describes the instance memory device that can implement independent mode;

[0012] Figure 4 Examples of systems comprising host devices and memory devices coupled together via interconnects are provided, wherein an independent mode can be implemented within the memory devices;

[0013] Figure 5 This describes an instance package with interconnect dies capable of operating in independent modes;

[0014] Figure 6 This describes the instance connections between the memory controller and multiple interconnect dies;

[0015] Figure 7 This describes instance components of a bare die that can operate according to the independent mode;

[0016] Figure 8-1 This describes the instance interface bare die for the aspect that performs write operations according to the interconnect mode;

[0017] Figure 8-2 This describes an instance linking the die to an aspect that performs a write operation based on the interconnect mode;

[0018] Figure 9-1 This describes the instance interface bare die of the aspect that performs read operations according to the interconnect mode;

[0019] Figure 9-2 This describes an instance linking the bare die that performs a read operation based on the interconnect mode;

[0020] Figure 10 This describes the instance die that performs independent write operations according to the independent mode;

[0021] Figure 11 This describes the instance die that performs independent read operations according to the independent mode;

[0022] Figure 12 This describes an instance-based independent read data generator used to support independent read mode;

[0023] Figure 13 This describes another instance of a data tracking signal loopback circuit used to support independent read mode;

[0024] Figure 14 Describe the instance methods used to implement the standalone pattern;

[0025] Figure 15 This describes the instance methods for performing independent write operations in independent mode; and

[0026] Figure 16 This describes the instance methods that perform independent read operations based on the independent mode. Detailed Implementation

[0027] Overview

[0028] Computers, smartphones, and other electronic devices use processors and memory to run a wide variety of programs and applications, ranging from low-power operating systems and background utilities to computationally intensive applications for high-resolution graphics, computer simulations, artificial intelligence (AI), and more. The execution speed associated with these programs and applications is typically related to the performance of the electronic device's memory, which in turn depends on any latency associated with memory transfers.

[0029] Memory devices may have an interconnect die architecture (e.g., a stacked or linked die architecture). This architecture uses at least one set of interconnect dies (or at least one set of interconnect dies), such as at least one interface die connected to at least one linked die within a combined package. The interface die can directly send data to or receive data from the memory controller. In contrast, the linked die indirectly sends data to or receives data from the memory controller via the interface die. Alternatively, the interface die acts as an interface and passes data between the linked die and the memory controller. The interface die and the linked die can share joint access to the address bus. Compared to other architectures with multiple dies, the interconnect die architecture can have relatively lower cost and / or a smaller footprint.

[0030] Interface dies and link dies are designed to operate together. While interface dies and link dies can be tested and debugged once connected, identifying problems at this stage can be costly. It would be beneficial to be able to test and debug interface dies and link dies individually at an earlier stage of the manufacturing process (e.g., before integration into the interconnect die architecture).

[0031] To address this and other issues regarding interconnect die architecture, this document describes several aspects of independent modes. Independent mode refers to a die designed to operate as one of a plurality of dies in an interconnect, capable of operating independently of the other dies. Before being connected to another die, the die can perform independent read and / or write operations according to independent mode. In this way, testing (or debugging) can be performed early in the manufacturing process before the die is integrated into the interconnect die architecture. For example, this type of testing can be performed at the wafer level or at the single die package (SDP) level. Generally, independent mode can be performed independently of whether the die is connected to another die.

[0032] In some cases, the devices and methods described herein may be suitable for designing memories for lower-power operation or for energy-efficient applications. Therefore, the described principles can be incorporated into low-power memory devices or memory controllers communicating with such low-power memory devices. An example of a memory standard relevant to low-power applications is the Low Power Double Data Rate (LPDDR) standard for Synchronous DRAM (SDRAM) issued by the Joint Electronics Equipment and Materials Engineering Committee (JEDEC) Solid State Technology Association. For clarity, some terms in this document may be derived from one or more of these standards or their versions, such as the LPDDR5 standard. However, the described principles are also applicable to memories that conform to other standards that include other LPDDR standards (e.g., earlier or future versions, such as LPDDR6) and memories that do not conform to common standards.

[0033] The density of memory devices is constantly increasing to maximize available memory and circuit area because improved communication protocols allow for higher data transfer rates between the processor and memory devices. An example of this improved protocol is the computing fast link. TM (CXL TM A protocol or standard (hereinafter referred to as the "CXL protocol" or "CXL standard"). It can be implemented via, for example, PCIe. ® The CXL protocol is implemented at the physical layer managed by the (Fast Interconnect for Peripheral Components) protocol. The CXL protocol is designed for processor and memory device (e.g., accelerators, memory expanders) intensive workloads, where efficient and consistent memory access or interaction between the processor and memory is advantageous.

[0034] The CXL protocol addresses some limitations of PCIe links by providing an interface to electronic devices, such as the PCIe 5.0 physical layer, while offering a lower-latency path for memory access and consistent caching between processors and memory devices. It provides high-bandwidth, low-latency connectivity between host devices (e.g., processors, CPUs, SoCs) and memory devices (e.g., accelerators, memory expanders, memory buffers, intelligent input / output (I / O) devices). The CXL protocol also addresses the growing high-performance computing workloads by supporting heterogeneous processing and memory systems with potential applications in artificial intelligence, machine learning, communication systems, and other high-performance computing.

[0035] A standalone mode can be used in the CXL implementation. Example implementations may include, for example, a memory device having multiple memory controllers and / or one or more sets of interconnect dies. Each set of interconnect dies includes at least one interface die connected via interconnects to at least one link die. The interface die can directly send data to or receive data from the memory controller. In contrast, the link die indirectly sends data to or receives data from the memory controller via the interface die and interconnects. Alternatively, the interface die acts as an interface and transfers data between the link die and the memory controller.

[0036] In several aspects, such as in the case of using high-density memory in the CXL implementation, a standalone mode can be used to test the interface die or the interconnect die. However, a standalone mode can be implemented in various other types of memory devices with interconnect dies to facilitate testing prior to integration.

[0037] Instance operating environment

[0038] Figure 1Typically, the example operating environment of device 102, which can implement a standalone mode, is described using the designation 100. Device 102 may include various types of electronic devices, including Internet of Things (IoT) devices 102-1, tablet devices 102-2, smartphones 102-3, laptop computers 102-4, passenger vehicles 102-5, server computers 102-6, and server clusters 102-7, or portions thereof (e.g., PCBs), which may be part of cloud computing infrastructure or data centers. Other examples of device 102 include wearable devices (e.g., smartwatches or smart glasses), entertainment devices (e.g., set-top boxes, video dongles, smart TVs, gaming devices), desktop computers, motherboards, server blades, home appliances, vehicles, drones, industrial equipment, security devices, sensors, or electronic components thereof. Each type of device may include one or more components for providing computing functionality or features.

[0039] In an example implementation, device 102 may include at least one host device 104, at least one interconnect 106, and at least one memory device 108. Host device 104 may include at least one processor 110, at least one cache memory 112, and a memory controller 114. Memory device 108, which may also be implemented as a memory module, may include, for example, dynamic random access memory (DRAM) dies or modules (e.g., low-power double data rate synchronous DRAM (LPDDRSDRAM)). DRAM dies or modules may include three-dimensional (3D) stacked DRAM devices, which may be high-bandwidth memory (HBM) devices or hybrid memory cube (HMC) devices. Memory device 108 may operate as the main memory of device 102. Although not specified, device 102 may also include storage memory. Storage memory may include, for example, storage-type memory devices (e.g., flash memory, hard disk drives, solid-state drives, phase-change memory (PCM), or memory employing 3D XPoint™).

[0040] Processor 110 is operatively coupled to cache memory 112, which is operatively coupled to memory controller 114. Processor 110 is also directly or indirectly coupled to memory controller 114. Host device 104 may include other components for forming, for example, a system-on-a-chip (SoC). Processor 110 may include a general-purpose processor, central processing unit (CPU), graphics processing unit (GPU), neural network engine or accelerator, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) integrated circuit (IC), or communication processor (e.g., modem or baseband processor).

[0041] In operation, memory controller 114 may provide a high-level or logical interface between processor 110 and at least one memory (e.g., external memory). Memory controller 114 may be implemented using any of a variety of memory controllers suitable for handling requests for data stored on memory device 108. Although not shown, host device 104 may include a physical interface (PHY) that transfers data between memory controller 114 and memory device 108 via interconnect 106. For example, the physical interface may be an interface compatible with the DDR PHY Interface (DFI) group interface protocol. Memory controller 114 may, for example, receive memory requests from processor 110 and provide the memory requests to external memory with appropriate formatting, timing, and reordering. Memory controller 114 may also forward responses to memory requests received from external memory to processor 110.

[0042] Host device 104 is operatively coupled to memory device 108 via interconnect 106. In some instances, memory device 108 is connected to host device 104 via interconnect 106 having an intermediary buffer or cache. Memory device 108 is operatively coupled to storage memory (not shown). Host device 104 may also be directly or indirectly coupled to memory device 108 and storage memory via interconnect 106. Interconnect 106 and other interconnects ( Figure 1 (Not specified) Data can be transferred between two or more components of device 102. Examples of interconnect 106 include a bus, a switching structure, or one or more wires carrying voltage or current signals.

[0043] In some implementations, interconnect 106 may include at least one command and address bus 116 (CA bus 116) and at least one data bus 118 (DQ bus 118). Each bus may be unidirectional or bidirectional. CA bus 116 and DQ bus 118 may be coupled to the CA and DQ pins of memory device 108, respectively. Interconnect 106 may also include, for example, one or more CS pins of memory device 108, chip select (CS) I / O or line-select I / O that may be coupled to one or more CS pins of memory device 108. Figure 1 (Not specified in the text). Interconnector 106 may further include a clock bus (CK bus—) that is part of or separate from the CA bus 122. Figure 1 (Not specified in the text).

[0044] In other implementations, interconnect 106 may be implemented as a CXL link. In other words, interconnect 106 may conform to at least one CXL standard or protocol. A CXL link can provide an interface over the physical layer and electrical devices of the PCIe 5.0 physical layer. A CXL link allows requests to memory device 108 and responses from memory device 108 to be encapsulated as flits. Regarding Figure 4 An example implementation of device 102 with a CXL link is discussed in more detail. In other implementations, interconnect 106 may be another type of link, including a PCIe 5.0 link. In this document, for clarity, some terms may be taken from one or more of these standards or versions thereof, such as the CXL standard. However, the principles described also apply to memories and systems with interconnects conforming to other standards and types.

[0045] The components described in device 102 represent an example architecture with a hierarchical memory system. A hierarchical memory system may contain memory at different tiers, each tier having memory with a different speed or capacity. As illustrated, cache memory 112 logically couples processor 110 to memory device 108. In the illustrated embodiment, cache memory 112 is at a higher tier than memory device 108. Storage memory may, in turn, be at a lower tier than main memory (e.g., memory device 108). Memory at a lower tier may have a reduced speed but increased capacity compared to memory at a higher tier.

[0046] Device 102 can be implemented in various ways with more, fewer, or different components. For example, host device 104 may include multiple cache memories (e.g., cache memories with multiple tiers) or no cache memory. In other embodiments, host device 104 may omit processor 110 or memory controller 114. Memory (e.g., memory device 108) may have “internal” or “local” cache memory. As another example, device 102 may include cache memory between interconnect 106 and memory device 108. Computer engineers may also include any of the components described in a distributed or shared memory system.

[0047] Computer engineers can implement host device 104 and various types of memory in a variety of ways. In some cases, host device 104 and memory device 108 may be mounted on a PCB (e.g., a rigid or flexible motherboard) or physically supported by a PCB. Host device 104 and memory device 108 may additionally be integrated together on an IC or fabricated on a separate IC and packaged together. Memory device 108 may also be coupled to multiple host devices 104 via one or more interconnects 106 and be responsive to memory requests from two or more host devices 104. Each host device 104 may include a corresponding memory controller 114, or multiple host devices 104 may share a memory controller 114. This document references... Figure 2 An instance computing system architecture is described, having at least one host device 104 coupled to a memory device 108.

[0048] Two or more memory components (e.g., modules, dies, memory banks, or groups of memory banks) may share the electrical path or coupling of interconnect 106. In some embodiments, CA bus 116 transmits addresses and commands from memory controller 114 of host device 104 to memory device 108, which excludes data propagation. DQ bus 118 can propagate data between memory controller 114 and memory device 108. Memory device 108 may also be implemented as any suitable memory, including but not limited to DRAM, SDRAM, three-dimensional (3D) stacked DRAM, DDR memory, or LPDDR memory (e.g., LPDDR DRAM or LPDDRSDRAM).

[0049] Memory device 108 may form at least a portion of the main memory of device 102. However, memory device 108 may also form at least a portion of cache memory, storage memory, or SoC of device 102. In some embodiments, and as per [reference to...] Figure 3 In more detail, at least a portion of the memory device 108 has an interconnect die architecture (e.g., a stacked die architecture or a linked die architecture) with at least two interconnect dies 120. The interconnect die architecture enables the memory device 108 to perform single write or read accesses along a shared data path using two or more interconnect dies 120, the shared data path being controllable or managed by the dies of the interconnect dies 120.

[0050] Interconnect dies 120 operate in conjunction to handle write and read requests issued by memory controller 114 or another memory controller within memory device 108, depending on the implementation. Each interconnect die 120 can also handle independent write and / or read requests issued via a mode register or test mode. Regarding Figure 5 and 6 Further description of interconnect die 120. About Figure 2The memory device 108 is further described.

[0051] Figure 2 Example computing system 200 is described, which can implement standalone mode aspects. In some embodiments, computing system 200 includes at least one memory device 108, at least one interconnect 106, and at least one processor 202.

[0052] Memory device 108 may include at least one memory array 204, at least one interface 206, and a control circuitry system 208 operatively coupled to or associated with the memory array 204. Memory device 108 may correspond to Figure 1 The device 102 comprises one or more of a cache memory, main memory, or storage memory. Therefore, the memory array 204 may include an array of memory cells, including, but not limited to, memory cells of DRAM, SDRAM, 3D stacked DRAM, DDR memory, low-power DRAM, or LPDDRSDRAM. For example, the memory array 204 may include memory cells of SDRAM configured as memory modules with a single channel containing 16 or 8 data (DQ) signals, double data rate input / output (I / O) signaling, and supporting a supply voltage of 0.3 to 0.5 V. The density of the memory device 108 may range, for example, from 2 Gb to 32 Gb.

[0053] The memory array 204 and control circuitry system 208 can be a single semiconductor die or a component on a single semiconductor die. The memory array 204 or control circuitry system 208 can also be distributed across multiple dies, for example, interconnect dies 120. Although... Figure 2 Although not explicitly shown, control circuitry 208 may include circuitry enabling one interconnect die to communicate with another interconnect die. This control circuitry can manage traffic on a bus that is separate from interconnect 106.

[0054] Control circuitry system 208 may include various components that memory device 108 can use to perform various operations. These operations may include communicating with other devices, managing memory performance, performing refresh operations (e.g., self-refresh or automatic refresh), and performing memory read or write operations. For example, control circuitry system 208 may include one or more registers 210, at least one example of array control logic 212, and clock circuitry system 214. Registers 210 may be implemented, for example, as one or more registers that can store information to be used by control circuitry system 208 or another part of memory device 108. At least one of registers 210 may include a mode register. Array control logic 212 may include circuitry providing command decoding, address decoding, input / output functions, amplification circuitry, power supply management, power control modes, and other functions. Clock circuitry system 214 may use one or more external clock signals provided via interconnect 106 to synchronize various memory components, said clock signals including command / address clocks or data clocks. Clock circuitry system 214 may also use internal clock signals to synchronize memory components and provide timer functionality.

[0055] Interface 206 can directly or indirectly couple the control circuitry 208 or the memory array 204 to the interconnect 106. For example... Figure 2 As shown, register 210, array control logic 212, and clock circuitry 214 may be part of a single component (e.g., control circuitry 208). In other embodiments, one or more of register 210, array control logic 212, or clock circuitry 214 may be separate components on a single semiconductor die or separate components distributed across multiple semiconductor dies. These components may be individually or jointly coupled to interconnect 106 via interface 206.

[0056] Interconnect 106 may use one or more of various interconnects that communicatively couple various components together and enable commands, addresses, or other information and data to be transferred between two or more components (e.g., between memory device 108 and processor 202). Although interconnect 106 is in Figure 2 While illustrated using a single line, interconnect 106 may include at least one bus, at least one switching structure, one or more wires or traces carrying voltage or current signals, at least one switch, one or more buffers, etc. Furthermore, interconnect 106 may be divided into at least a CA bus 116 and a DQ bus 118 (e.g., Figure 1 (As explained above). Figure 1 As discussed, interconnect 106 may include a CXL link or conform to at least one CXL standard. The CXL link may provide an interface or overlay on top of the physical layer and electrical devices of the PCIe 5.0 physical layer.

[0057] In some aspects, memory device 108 may be relative to ( Figure 1 The memory device 108 is a "separate" component of either the host device 104 or the processor 202. This separate component may include a PCB, memory card, memory stick, or memory module (e.g., a single in-line memory module (SIMM) or a dual in-line memory module (DIMM)). Therefore, the separate physical components may be located together within the same housing of the electronic device or may be distributed across server racks, data centers, etc. Alternatively, the memory device 108 may be integrated with other physical components (including the host device 104 or the processor 202) by being combined on a PCB or in a single package or SoC.

[0058] like Figure 2 As shown, processor 202 may include a computer processor 202-1, a baseband processor 202-2, and an application processor 202-3 coupled to memory device 108 via interconnect 106. Processor 202 may include or form part of a CPU, GPU, SoC, ASIC, or FPGA. In some cases, a single processor may include multiple processing resources, each dedicated to a different function (e.g., modem management, application, graphics, central processing). In some embodiments, baseband processor 202-2 may include or be coupled to a modem (…). Figure 2 (Not specified in the text) and is referred to as a modem processor. The modem or baseband processor 202-2 can, for example, be connected via cellular, Wi-Fi... ® ,Bluetooth ® Near-field or another technology or protocol used for wireless communication is wirelessly coupled to the network.

[0059] In some embodiments, processor 202 may be directly connected to memory device 108 (e.g., via interconnect 106). In other embodiments, one or more of processors 202 may be indirectly connected to memory device 108 (e.g., via a network connection or through one or more other devices). Furthermore, processor 202 may be implemented as a processor capable of communicating via a CXL-compatible interconnect. Therefore, a corresponding processor 202 may include or be associated with a corresponding link controller, such as... Figure 4 The link controller 402 described herein. Alternatively, two or more processors 202 may use a shared link controller 402 to access the memory device 108. In some such cases, the memory device 108 may be implemented as a CXL-compatible memory device (e.g., implemented as a CXL 3 type memory expander) or another memory device compatible with the CXL protocol may or alternatively be coupled to the interconnect 106.

[0060] Example technologies and hardware

[0061] Figure 3The instance memory device 108, which can implement an independent mode, is described. Instance memory module 302 includes a plurality of dies 304. As described, memory module 302 includes a first die 304-1, a second die 304-2, a third die 304-3, and a D-th die 304-D, where "D" represents a positive integer. Two or more dies 304-1 to 304-D may be implemented as interconnect dies 120. For example, dies 304-1 and 304-2 may be interconnect dies 120. In some cases, memory module 302 includes multiple sets of interconnect dies 120, such as multiple pairs of interconnect dies, or a set of interconnect dies 120 having four or more dies.

[0062] As examples, memory module 302 may be a SIMM or a DIMM. As another example, memory module 302 may interface with other components via a bus interconnect (e.g., a Peripheral Component Interconnect Fast (PCIe®) bus). Figure 1 and 2 The memory device 108 described herein may correspond, for example, to a plurality of dies (dies or discs) 304-1 to 304-D or a memory module 302 having two or more dies 304. As shown, the memory module 302 may include one or more electrical contacts 306 (e.g., pins) for connecting the memory module 302 to other components.

[0063] The memory module 302 can be implemented in various ways. For example, the memory module 302 may include a PCB, and multiple dies 304-1 to 304-D may be mounted or otherwise attached to the PCB. The dies 304 (e.g., memory dies) may be arranged in rows or along two or more dimensions (e.g., forming a grid or array). The dies 304 may have similar sizes or may have different sizes. Each die 304 may be similar to another die 304 or differ in size, shape, data capacity, or control circuitry. The dies 304 may also be located on a single side or multiple sides of the memory module 302. In some cases, the memory module 302 may be part of a CXL memory system or module.

[0064] Each die 304 within interconnect die 120 can selectively operate according to interconnect mode 308 (e.g., normal operation mode or task mode) and independent mode 310 (e.g., isolation test mode). During interconnect mode 308, die 304 can operate in conjunction with other dies to perform write operation 312 and / or read operation 314. During write operation 312, two dies 304 write different blocks (or portions) of the write data burst, such as regarding... Figure 8-1 and 8-2Further description. During read operation 314, the two dies 304 read different blocks (or portions) of the read data burst, as described above. Figure 9-1 and 9-2 Further description. For interconnect mode 308, die 304 is configured as an interface die or a link die, which is related to... Figure 5 Further description. Generally, once die 304 is integrated into the interconnect die architecture (e.g., when die 304 is connected to another die of interconnect die 120), die 304 can execute interconnect mode 308.

[0065] During standby mode 310, die 304 can perform standby write operation 316 and / or standby read operation 318 (e.g., mode register read (MRR) operation) independently of another die operation within interconnect die 120. For standby mode 310, die 304 is configured as an interface die, regardless of whether die 304 is intended to operate as a link die or interface die within a link die architecture (e.g., for interconnect mode 308). Standby write operation 316 is similar to write operation 312, except that data used for linking the die is discarded or ignored. For example, during standby write operation 316, die 304 writes a first block of the write data burst to its memory array 204 and discards a second block of the write data burst. Regarding... Figure 10 Further description of independent write operation 316.

[0066] Independent read operation 318 is similar to read operation 314, except that die 304 generates alternative data to represent the data that would otherwise be provided by the linked die. For example, during independent read operation 318, die 304 reads the first block of the read data burst and generates the second block of the read data burst. About Figure 11 The standalone read operation 318 is further described. Standalone mode 310 supports testing of die 304 before integration into interconnect die 120. However, generally, die 304 can perform standalone mode 310 regardless of whether die 304 is connected to another die of interconnect die 120.

[0067] Figure 4 This describes an example of a system 400 comprising a host device 104 and a memory device 108 coupled together via interconnect 106. The system 400 can be configured as follows: Figure 1The device 102 shown in the diagram represents at least a portion of the device. As illustrated, the host device 104 includes a processor 110 and a link controller 402, which can be implemented using at least one initiator 404. Therefore, the initiator 404 can be coupled to either the processor 110 or the interconnect 106 (including coupling to both the processor 110 and the interconnect 106), and the initiator 404 can be coupled between the processor 110 and the interconnect 106. Examples of initiators 404 may include bootstraps, master devices, master controllers, master components, etc.

[0068] In the illustrated example system 400, memory device 108 includes a link controller 406, which may be implemented using at least one target 408. Target 408 may be coupled to interconnect 106. Thus, target 408 and initiator 404 may be coupled to each other via interconnect 106. Example target 408 may include a follower, auxiliary device, slave device, response component, etc. Memory device 108 also includes memory, which may be implemented using at least one memory module 302 or other components (e.g., DRAM 410), as further described below.

[0069] In an example implementation, initiator 404 includes link controller 402, and target 408 includes link controller 406. Link controller 402 or link controller 406 can initiate, coordinate, cause, or otherwise control signaling across a physical or logical link implemented via interconnect 106 according to one or more protocols. Link controller 402 may be coupled to interconnect 106. Link controller 406 may also be coupled to interconnect 106. Thus, link controller 402 may be coupled to link controller 406 via interconnect 106. Each link controller 402 or 406 can, for example, control communication via interconnect 106 at a link layer of a given protocol or at one or more other layers. Communication signaling may include, for example, a request 412 (e.g., a write request or read request), a response 414 (e.g., a write response or read response), and so on.

[0070] The memory device 108 may further include at least one interconnect 416 and at least one memory controller 418 (e.g., MC 418-1 and MC 418-2). Within the memory device 108, and relative to target 408, the interconnect 416, memory controller 418, and / or DRAM 410 (or other memory components) may be referred to as “back-end” components of the memory device 108. In some cases, the interconnect 416 is internal to the memory device 108 and may operate in the same or different manner as the interconnect 106.

[0071] As shown, memory device 108 may include multiple memory controllers 418-1 and 418-2 and / or multiple DRAMs 410-1 and 410-2. Although two of each are shown, memory device 108 may include one or more memory controllers 418 and / or one or more DRAMs 410. For example, memory device 108 may include four memory controllers 418 and 16 DRAMs 410, such as each memory controller 418 having four DRAMs 410. The memory components of memory device 108 are depicted as DRAMs 410 only as examples, as one or more of the memory components may be implemented as another type of memory. For example, the memory components may include non-volatile memory, such as flash or PCM. Alternatively, the memory components may include other types of volatile memory, such as static random access memory (SRAM). Memory device 108 may also include any combination of memory types. In an example implementation, DRAMs 410-1 and / or DRAMs 410-2 include interconnect dies 120.

[0072] In some cases, the memory device 108 may contain the target 408, interconnect 416, at least one memory controller 418, and at least one DRAM 410 within a single housing or other enclosure. However, the housing may be omitted or may be integrated with the host device 104, system 400, or ( Figure 1 The housing of device 102 is integrated. Interconnect 416 may be mounted on a PCB. Each of target 408, memory controller 418, and DRAM 410 may be manufactured on at least one IC and packaged together or separately. The packaged IC may be fixed to the PCB or otherwise supported by the PCB and may be directly or indirectly coupled to interconnect 416. In other cases, target 408, interconnect 416, and one or more memory controllers 418 may be integrated together into a single IC. In some such cases, this IC may be coupled to the PCB, and one or more modules for memory components (e.g., for DRAM 410) may also be coupled to the same PCB, which may form a CXL type memory device 108. This memory device 108 may be enclosed in a housing or may contain such a housing. However, the components of memory device 108 may be manufactured, packaged, combined, and / or housed in other ways.

[0073] like Figure 4As illustrated, target 408, including its link controller 406, can be coupled to interconnect 416. Each memory controller 418 of the plurality of memory controllers 418-1 and 418-2 can also be coupled to interconnect 416. Therefore, target 408 and each memory controller 418 of the plurality of memory controllers 418-1 and 418-2 can communicate with each other via interconnect 416. Each memory controller 418 is coupled to at least one DRAM 410. As shown, each corresponding memory controller 418 of the plurality of memory controllers 418-1 and 418-2 is coupled to at least one corresponding DRAM 410 of the plurality of DRAMs 410-1 and 410-2. However, each memory controller 418 of the plurality of memory controllers 418-1 and 418-2 can be coupled to a corresponding set of a plurality of DRAMs 410 (e.g., five DRAMs 410) or other memory components.

[0074] Each memory controller 418 may implement one or more memory access protocols to facilitate access to at least one DRAM 410 by reading or writing data based on at least one memory address. The memory controller 418 may increase the bandwidth for memory access or reduce its latency based on the memory type or organization of the memory component, such as DRAM 410. Multiple memory controllers 418-1 and 418-2 and multiple DRAMs 410-1 and 410-2 can be organized in many different ways. For example, each memory controller 418 may implement one or more memory channels for accessing DRAM 410. Furthermore, DRAM 410 may be manufactured to include one or more sides, such as single-sided or double-sided memory modules. Each DRAM 410 (e.g., at least one DRAM IC chip) may also include multiple memory banks, such as 8 or 16 memory banks.

[0075] This document now describes an example of host device 104 accessing memory device 108. The example is described in accordance with general access that may include memory read access (e.g., a retrieval operation) or memory write access (e.g., a storage operation). Processor 110 may provide memory access request 420 to initiator 404. Memory access request 420 may be propagated via a bus or other interconnects within host device 104. This memory access request 420 may be or may include a read request or a write request. Initiator 404 (e.g., its link controller 402) may reformulate memory access request 420 in a format suitable for interconnect 106. This reformulation may be performed based on a physical protocol or logical protocol (including both) suitable for interconnect 106. Examples of such protocols are described below.

[0076] Initiator 404 can thus prepare request 412 and transmit request 412 to target 408 via interconnect 106. Target 408 receives request 412 from initiator 404 via interconnect 106. Target 408, including its link controller 406, can process request 412 to determine (e.g., extract or decode) memory access request 420. Based on the determined memory access request 420, target 408 can forward memory request 422 to memory controller 418 via interconnect 416, in this example, memory controller 418 is the first memory controller 418-1. For other memory accesses, target data can be accessed to the second DRAM 410-2 via the second memory controller 418-2.

[0077] The first memory controller 418-1 can prepare a memory command 424 based on a memory request 422. The first memory controller 418-1 can provide the memory command 424 to the first DRAM 410-1 via an interface or interconnect suitable for the type of DRAM or other memory component. The first DRAM 410-1 receives the memory command 424 from the first memory controller 418-1 and can perform the corresponding memory operation. The memory command 424 and the corresponding memory operation may involve a read operation, a write operation, a refresh operation, etc. Based on the result of the memory operation, the first DRAM 410-1 can generate a memory response 426. If the memory request 422 is for a read operation, then the memory response 426 may contain the requested data. If the memory request 422 is for a write operation, then the memory response 426 may contain confirmation of successful execution of the write operation. The first DRAM 410-1 can send the memory response 426 back to the first memory controller 418-1.

[0078] The first memory controller 418-1 receives a memory response 426 from the first DRAM 410-1. Based on the memory response 426, the first memory controller 418-1 can prepare a memory response 428 and transmit the memory response 428 to the target 408 via interconnect 416. The target 408 receives the memory response 428 from the first memory controller 418-1 via interconnect 416. Based on this memory response 428, and in response to the corresponding request 412, the target 408 can express a response 430 for the requested memory operation. The response 430 may include a read data or write acknowledgment and is expressed according to one or more protocols of interconnect 106.

[0079] In response to request 412 from host device 104, target 408 may transmit response 430 to initiator 404 via interconnect 106. Initiator 404 then receives response 430 from target 408 via interconnect 106. Initiator 404 can thus respond to the “raw” memory access request 420 from processor 110 in this instance. To this end, initiator 404 prepares memory access response 432 using information from response 430 and provides memory access response 432 to processor 110. In this way, host device 104 can obtain memory access services from memory device 108 using interconnect 106. Next, an example of interconnect 106 will be described.

[0080] Interconnect 106 can be implemented in various ways to enable memory-related communication between initiator 404 and target 408. Typically, interconnect 106 can carry memory-related information, such as data or memory addresses, between initiator 404 and target 408. In some cases, initiator 404 or target 408 (including both) may prepare memory-related information for communication across interconnect 106 by encapsulating such information. Memory-related information may be encapsulated into, for example, at least one packet (e.g., a slice). One or more packets may contain headers with information indicating or describing the contents of each packet.

[0081] In example implementations, interconnect 106 may support, enforce, or implement memory coherence for shared memory systems, cache memories, combinations thereof, etc. Additionally or alternatively, interconnect 106 may operate based on a credit allocation system. Having credit enables an entity, such as initiator 404, to transmit another memory request 412 to target 408. Target 408 may return credit to "refill" the credit balance at initiator 404. Credit-based communication schemes across interconnect 106 may be implemented by credit logic of target 408 or by credit logic of initiator 404 (including through both working together).

[0082] System 400, the initiator 404 of host device 104, or the target 408 of memory device 108 can operate or interface with interconnect 106 according to one or more physical or logical protocols. For example, interconnect 106 can be constructed according to the Peripheral Component Interconnect Fast (PCIe or PCI-e) standard. Applicable versions of the PCIe standard may include 1.x, 2.x, 3.x, 4.0, 5.0, 6.0, and future or alternative versions. In some cases, at least one other standard is layered via a physical-oriented PCIe standard. For example, initiator 404 or target 408 can communicate via interconnect 106 according to the Compute Fast Link (CXL) standard. Applicable versions of the CXL standard may include 1.x, 2.0, and future or alternative versions. The CXL standard can operate based on credits (e.g., read credits and write credits). In such embodiments, link controller 402 and link controller 406 may be CXL controllers.

[0083] Examples of the standalone mode 310 are described herein with reference to at least one memory controller 114 or 418 and at least one memory device 108 (e.g., having a memory array 204, a memory module 302, and / or DRAM 410) including its interconnect die 120. Regarding Figure 5 and 6 Further description of interconnect die 120.

[0084] Figure 5 This illustration describes an example package 500 having interconnect dies 120 that can operate individually according to independent mode 310. Although not shown, package 500 may also include other components, such as one or more other components of memory device 108 and / or one or more components of host device 104. In the depicted configuration, package 500 includes a substrate 502. Interconnect dies 120 are disposed on or embedded in substrate 502. Interconnect die 120 includes at least one interface die 504 and at least one link die 506. In this example, package 500 is shown as including interface dies 504-1 to 504-N and link dies 506-1 to 506-N, where N represents a positive integer. Each link die 506 is coupled to the interface die 504 via an interconnect 508. Figure 5 In the process, the link dies 506-1 to 506-N are coupled to the interface dies 504-1 to 504-N via interconnects 508-1 to 508-N respectively.

[0085] Although not explicitly shown, interface die 504 is operatively coupled to (e.g., Figure 1The memory controller 114 or 418 (or 4) acts as an interface between the link die 506 and the memory controller 114 or 418 for at least data transfer or exchange. Although the interface die 504 and the link die 506 may not behave differently, they may optionally be manufactured as dies of the same type containing the same circuit components. Once the package 500 is assembled, each of the dies can be programmed to function as either the interface die 504 or the link die 506. As an example, the interconnect die 120 can be programmed by providing at least one corresponding fuse in each die 304.

[0086] In an example, a set of interconnect dies 510 may refer to an interface die 504 and a link die 506. However, other configurations are also possible, in which the interface die 504 is operatively coupled to two or more link dies 506. Generally, the set of interconnect dies 510 refers to a group of interconnect dies 120 operatively coupled together. For example, the link die 506 within the set of interconnect dies 510 is operatively coupled to the interface die 504 within the set of interconnect dies 510 via interconnect 508. Furthermore, the interface die 504 within the set of interconnect dies 510 is operatively coupled to one or more link dies 506 within the set of interconnect dies 510 via interconnect 508. Figure 5 In the diagram, interface die 504-1 and link die 506-1 can represent the first group of interconnect dies 510, and interface die 504-N and link die 506-N can represent the Nth group of interconnect dies 510.

[0087] Interconnects 508-1 to 508-N can respectively transfer data between corresponding interface dies 504-1 to 504-N and link dies 506-1 to 506-N. For example, interconnect 508-1 can transfer data between interface die 504-1 and link die 506-1. Similarly, interconnect 508-N can transfer data between interface die 504-N and link die 506-N. In an example implementation, interconnect 508 supports 128-bit (e.g., 16-byte) transfers per access. Although interconnects 508-1 to 508-N... Figure 5 Individual lines are used to illustrate this, but each interconnect 508 may include at least one bus, at least one switching structure, one or more wires or traces carrying voltage or current signals, at least one switch, one or more buffers, etc.

[0088] Interface die 504 and / or link die 506 may each include at least one memory array 204, at least one interface 206, and a control circuitry 208. Interface 206 can directly or indirectly couple the control circuitry 208 or the memory array 204 to interconnect 508. Interface 206 may also include a data bus. (About...) Figure 6 The example pins of interface die 504 and link die 506 are further described.

[0089] Figure 6 This describes an example connection between the memory controller 114 or 418 of memory device 108 and a plurality of interconnect dies 120. In the case of memory controller 114, interconnect 106 may provide multiple electrical communication lines between memory controller 114 and each die in interconnect die 120. Alternatively, in the case of memory controller 418, interconnect 602 may provide multiple electrical communication lines between memory controller 418 and each die in interconnect die 120. The lines of interconnect 106 or 602 may correspond to clock (CK) lines, write clock (WCK) lines, write mask lines, command / address (CA) lines, or other memory communication lines. Using interconnect 106 or 602, interface die 504 and link die 506 can receive commands from a common command and address bus.

[0090] Interface die 504 and link die 506 each include a data pin 604, a connection data pin 606 (CQ 606), and a data trace signal (DTS) pin 608 (DTS 608). The data pin 604 may represent multiple pins that implement the transfer of multiple bits per access. For example, the data pin 604 may represent eight pins. The data pin 604 may be at least partially LPDDR5 compliant, compliant with another standard, or not compliant with a common standard. The difference between interface die 504 and link die 506 is that the data pin 604 of interface die 504 is actively and operatively coupled to memory controller 114 or 418. In this way, interface die 504 can "directly" transfer data to or receive data from memory controller 114 or 418 without using another die as an intermediary for sending or receiving data to or from memory controller 114 or 418. In contrast, the data pin 604 of the link die 506 is inactive and non-operationally coupled to the memory controller 114 or 418. To explain further, the data pin 604 is floating, so that no current flows through it. Therefore, the link die 506 cannot communicate directly with the memory controller 114 or 418. Specifically, the link die 506 cannot directly transfer data to or receive data from the memory controller 114 or 418. Instead, the link die 506 can communicate "indirectly" with the memory controller 114 or 418 via at least one other die (the interface die 504 described below).

[0091] Interface die 504 and link die 506 each include a connection data pin 606 and a data trace signal pin 608 (DTS pin 608). The connection data pin 606 and the data trace signal pin 608 can each represent multiple pins that transfer multiple bits per access. For example, the connection data pin 606 can represent 32 pins and the data trace signal pin 608 can represent 2 pins. Interconnect 508 operatively couples link die 506 to interface die 504 via the connection data pin 606 of each die and via the data trace signal pin 608 of each die. Using interconnect 508, the connection data pin 606, and the data trace signal pin 608, link die 506 can transfer data to or receive data from interface die 504 during interconnect mode 308. Specifically, interface die 504 can transfer data from memory controller 114 or 418 to link die 506 during write operation 312. Furthermore, the interface die 504 can transfer data from the link die 506 to the memory controller 114 or 418 during read operation 314. In this way, the link die 506 can indirectly transfer data to or receive data from the memory controller 114 or 418 via the interface die 504. Alternatively, the interface die 504 acts as an interface to the link die 506 and transfers data between the link die 506 and the memory controller 114 or 418 according to interconnection mode 308.

[0092] Figure 6 The interconnect die architecture described herein can reduce costs and save space within device 102. For example, fewer electrical communication lines can be used to implement interconnects 106 or 602 because fewer pins on link die 506 are active relative to interface die 504.

[0093] Before being integrated into the interconnect die architecture, the interface die 504 or link die 506 is not operatively coupled together via the data connection pin 606 and the data trace signal pin 608. In this case, the interface die 504 or link die 506 can be on a die or a single die package. Therefore, the data connection pin 606 and the data trace signal pin 608 can be floating, so that current does not flow through these pins.

[0094] To perform testing or debugging prior to integration, interface die 504 or link die 506 may receive a stand-alone mode request 610 from an external source (e.g., a test engine) or an internal source (e.g., the mode register of register 210). The stand-alone mode request 610 instructs interface die 504 or link die 506 to operate according to stand-alone mode 310. Specifically, the stand-alone mode request 610 causes interface die 504 or link die 506 to perform a stand-alone write operation 316 and / or a stand-alone read operation 318. (About...) Figure 7 Further describe the instance components of interface die 504 and / or link die 506.

[0095] Figure 7 This describes an example component of die 304 capable of operating in standalone mode 310. In an example implementation, once integrated as part of an interconnect die architecture, die 304 can be configured as interface die 504 or link die 506. Die 304 includes at least one write circuit 702, at least one read circuit 704, interface 206, and memory array 204. Die 304 also includes at least one data path 706 and at least one data tracking signal path 708. The write circuit 702 and / or read circuit 704 can be implemented as part of control circuitry system 208 or interface 206.

[0096] If die 304 is configured to interface die 504 during write operation 312, then write circuitry 702 enables data to be written to memory array 204 of die 304 and memory array 204 of another die interconnecting die 120. If die 304 is configured to link die 506 during write operation 312, then write circuitry 702 can be disabled. Write circuitry 702 also enables data to be written to memory array 204 of die 304 during independent write operation 316. Write circuitry 702 can be disabled during independent read operation 318.

[0097] The write circuit 702 includes a deserializer 710 and a data trace signal generator 712. The deserializer 710 provides serial-to-parallel data conversion and separates data blocks during write operation 312 and during independent write operation 316. The data trace signal generator 712 generates a data trace signal during write operation 312 and during independent write operation 316. The data trace signal contains information about the location of the data stored in memory array 204 and the timing associated with the data.

[0098] If die 304 is configured to interface die 504 during read operation 314, then read circuitry 704 enables data to be read from memory array 204 of die 304 and memory array 204 of another die interconnecting die 120. If die 304 is configured to link die 506 during read operation 314, then read circuitry 704 can be disabled. Read circuitry 704 also enables data to be read from memory array 204 of die 304 during standby read operation 318. Read circuitry 704 can be disabled during standby write operation 316.

[0099] The read circuit 704 includes at least one first-in-first-out (FIFO) circuit 714 and at least one serializer 716. Generally, the FIFO circuit 714 operates in a pipelined manner. The serializer 716 provides parallel-to-serial data conversion and combines read data blocks from the interface die 504 and the link die 506 during read operation 314. During independent read operation 318, the serializer 716 also provides parallel-to-serial data conversion and combines data blocks from the die under test 304 with another data block generated by die 304.

[0100] Data path 706 propagates data between data pin 604, memory array 204, and the connection data pin 606. Data trace signal path 708 propagates a data trace signal between data trace signal generator 712, memory array 204, read circuitry 704, and data trace signal pin 608. Data path 706 and data trace signal path 708 may include one or more buffers 718. Buffers 718 can be used to drive data and data trace signals according to the current mode (e.g., according to interconnect mode 308 or standalone mode 310). In some cases, different combinations of buffers 718 may be enabled according to write operation 312, read operation 314, standalone write operation 316, and / or standalone read operation 318.

[0101] To implement the standalone mode 310, die 304 also includes a standalone read data generator 720 and a data tracking signal loopback circuit 722 (DTS loopback circuit 722). Generally, the standalone read data generator 720 generates read data blocks during standalone read operation 318 and transmits these read data blocks to read circuit 704 via data path 706. This read data block has a pre-positioned mode, serving as an alternative to read data blocks otherwise provided by link die 506 during read operation 314.

[0102] The data trace signal loopback circuit 722 generates another data trace signal during standalone read operation 318. This other data trace signal serves as an alternative to the data trace signal otherwise provided by the link die 506 during read operation 314. The data trace signal loopback circuit 722 transmits the data trace signal to the read circuit 704 via data trace signal path 708. Using the standalone read data generator 720 and the data trace signal loopback circuit 722, die 304 can perform standalone read operation 318 without being integrated into the interconnect die architecture (e.g., without being connected to another die 304 connected to interconnect die 120). Regarding Figures 8-1 to 11 Further description of the operation of bare die 304.

[0103] Figure 8-1This illustration describes an example of an interface die 504 performing a write operation 312 according to interconnect mode 308. In the depicted configuration, write circuitry 702 is coupled to interface 206 and memory array 204. Read circuitry 704 is also coupled to memory array 204 and interface 206. Interface die 504 includes a data path indicated by solid lines and a data trace signal path 708 indicated by dashed lines. Although not explicitly shown, interface die 504 is integrated within the interconnect die architecture such that connection data pin 606 and data trace signal pin 608 are coupled to corresponding pins on the link die 506, which... Figure 8-2 It is displayed in the middle.

[0104] Some components of the interface die 504 may be optionally disabled during write operation 312. These components are indicated using dashed lines. For example, the read circuitry 704 may be optionally disabled during write operation 312.

[0105] During write operation 312, interface die 504 receives one or more write data bursts 802 from memory controller 114 or 418 at data pin 604 of interface 206. Each write data burst 802 comprises multiple blocks 804. For example, write data burst 802 comprises a first block 804-1 and a second block 804-2. Depending on the configuration of memory device 108, each write data burst 802 may contain, for example, 32 bytes. In an example implementation, the first block 804-1 may correspond to the lower 16 bytes, and the second block 804-2 may correspond to the higher 16 bytes. In other words, the first block 804-1 may contain the least significant byte, and the second block 804-2 may contain the most significant byte. In general, the first block 804-1 and the second block 804-2 represent 32 bytes of write data burst 802. However, write data burst 802 may have a different length, such as 16 bytes. In this case, each block 804 can represent 8 bytes of data written to burst 802.

[0106] Upon receiving each segment 804, the interface die 504 passes the segment 804 through the deserializer 710 of the write circuit 702. Generally, when the next segment 804 is received at the data pin 604 of the interface die 504, the deserializer 710 operates in a pipelined manner on the previously received segment 804. For example, when the interface die 504 receives the second segment 804-2 from the memory controller 114 or 418, the deserializer 710 operates on the first segment 804-1.

[0107] After deserialization, interface die 504 uses data path 706 to transfer (e.g., propagate or pass) one of the blocks 804 (e.g., block 804-1) from write circuit 702 to connection data pin 606. Interface die 504 also uses data path 706 to transfer another of the blocks 804 (e.g., block 804-2) from write circuit 702 to memory array 204. As an example, interface die 504 transfers odd-numbered blocks 804 to link die 506 (when counting from 1) and writes even-numbered blocks 804 to its memory array 204 (when counting from 1). As another example, interface die 504 writes odd-numbered blocks 804 to its memory array 204 (when counting from 1) and transfers even-numbered blocks 804 to link die 506 (when counting from 1).

[0108] Interface die 504 also generates a first data trace signal 806-1 (DTS 806-1) associated with block 804-1 and a second data trace signal 806-2 (DTS 806-2) associated with block 804-2. Using data trace signal path 708, interface die 504 transmits data trace signal 806-1 from write circuit 702 to data trace signal pin 608. Interface die 504 also uses data trace signal path 708 to transmit data trace signal 806-2 to memory array 204. Link die 506 receives block 804-1 and data trace signal 806-1, as per [reference to...]. Figure 8-2 Further description.

[0109] Figure 8-2 Example link die 506 is illustrated for an aspect of performing write operation 312 according to interconnect mode 308. In the depicted configuration, interface 206 is coupled to memory array 204. Some components of link die 506 may be optionally disabled during write operation 312. These components are indicated using dashed lines. In this example, write circuitry 702 and read circuitry 704 may be optionally disabled during write operation 312. Although not explicitly shown, read circuitry 704 and / or write circuitry 702 may be coupled to memory array 204 and interface 206 via data path 706 and data trace signal path 708, as shown in interface die 504.

[0110] During write operation 312, link die 506 uses data path 706 and data trace signal path 708 to transfer block 804-1 and data trace signal 806-1 to memory array 204, respectively. Specifically, link die 506 uses data path 706 to transfer block 804-1 from connection data pin 606 to memory array 204. Furthermore, link die 506 uses data trace signal path 708 to transfer data trace signal 806-1 from data trace signal pin 608 to memory array 204. Link die 506 writes block 804-1 to memory array 204. Regarding... Figure 9-1 and 9-2 Further description of read operation 314.

[0111] Figure 9-1 This describes an example of an interface die 504 that performs a read operation 314 according to interconnect mode 308. Although not explicitly shown, interface die 504 is integrated within the interconnect die architecture, such that the connection data pin 606 and the data tracking signal pin 608 are coupled to corresponding pins on the connection die 506. Figure 9-2 It is displayed in the middle.

[0112] Some components of the interface die 504 can be optionally disabled during read operation 314. These components are indicated using dashed lines. For example, write circuitry 702 can be optionally disabled during read operation 314.

[0113] During read operation 314, interface die 504 transmits read data burst 902 to memory controller 114 or 418. Read data burst 902 comprises a first block 904-1 and a second block 904-2. Depending on the configuration of memory device 108, read data burst 902 may contain, for example, 32 bytes. In an example implementation, the first block 904-1 may correspond to the high 16 bytes, and the second block 904-2 may correspond to the low 16 bytes. In other words, the first block 904-1 may contain the most significant byte, and the second block 904-2 may contain the least significant byte. In general, the first block 904-1 and the second block 904-2 represent 32 bytes. However, read data burst 902 may have a different length, for example, 16 bytes. In this case, each block 904 may represent 8 bytes of read data burst 902.

[0114] To transmit the read data burst 902 to memory controllers 114 or 418, interface die 504 can read one of blocks 904 (e.g., block 904-1) from its memory array 204 and receive another of blocks 904 (e.g., block 904-2) from link die 506 via data trace signal pin 608. Using data path 706 and data trace signal path 708, interface die 504 transmits block 904-1 and its corresponding data trace signal 906-1 from memory array 204 to read circuit 704. Interface die 504 also transmits block 904-2 and its corresponding data trace signal 906-2 from interface 206 to read circuit 704. The first-in-first-out circuit 714 and serializer 716 of read circuit 704 generate read data burst 902 based on blocks 904-1 and 904-2.

[0115] In one example implementation, interface die 504 reads odd-numbered blocks 904 from its memory array 204 (starting from 1) and receives even-numbered blocks 904 from link die 506 (starting from 1). As another example, interface die 504 receives odd-numbered blocks 904 from link die 506 (starting from 1) and reads even-numbered blocks 904 from its memory array 204 (starting from 1). Link die 506 transmits blocks 904-2 and data tracking signals 906-2 to interface die 504, as per [reference to...]. Figure 9-2 Further description.

[0116] Figure 9-2 Example linking die 506 illustrates aspects of performing read operation 314 according to interconnect mode 308. In the depicted configuration, interface 206 is coupled to memory array 204. Although not explicitly shown, read circuitry 704 and / or write circuitry 702 may be coupled to memory array 204 and interface 206 via data path 706 and data tracking signal path 708, as shown in interface die 504.

[0117] Some components linking die 506 can be optionally disabled during read operation 314. These components are indicated using dashed lines. In this example, write circuitry 702 and read circuitry 704 can be optionally disabled during read operation 314.

[0118] During read operation 314, link die 506 reads block 904-2 from memory array 204. Link die 506 uses data path 706 to transfer block 904-2 from memory array 204 to connection data pin 606. Furthermore, link die 506 uses data trace signal path 708 to transfer data trace signal 906-2 from memory array 204 to data trace signal pin 608.

[0119] Although for the sake of simplicity Figures 8-1 to 9-2 It was not explicitly shown in the text, but Figures 8-1 to 9-2 Dies 504 and 506 may also include an independent read data generator 720 and a data tracking signal loopback circuit 722, which are related to Figure 11 Further description: The independent read data generator 720 and the data tracking signal loopback circuit 722 can be disabled during interconnect mode 308.

[0120] The technology used to implement standalone mode 310 enables interface die 504 and / or link die 506 to perform alternative forms of write operation 312 and read operation 314 for testing and debugging before integration into the link die architecture. About Figure 10 and 11 Further description of aspects of standalone mode 310.

[0121] Figure 10 This describes an example die 304 that performs an independent write operation 316 according to independent mode 310. Die 304 can be configured as an interface die 504 or a link die 506 within an interconnect die architecture. Before integration into the interconnect die architecture, the connection data pin 606 and data trace signal pin 608 of die 304 are not connected to corresponding pins on another die. Therefore, the connection data pin 606 and data trace signal pin 608 are floating 1002 (e.g., not connected to corresponding pins on link die 506).

[0122] The die 304 receives a standalone mode request 610 to perform a standalone write operation 316. The standalone write operation 316 may be similar to the write operation 312 performed by the interface die 504, such as... Figure 8-1 As shown in the figure. However, instead of transmitting one of the blocks 804 of the write data burst 802 to one of the interconnect dies 120 according to the write operation 312, the die 304 discards (e.g., ignores or disregards) the block 804 during the independent write operation 316.

[0123] During a standalone write operation 316, die 304 receives a write data burst 802 at data pin 604. The write data burst 802 includes a first block 804-1 and a second block 804-2. Die 304 writes one of the blocks 804 of the write data burst 802 (e.g., 804-2) to its memory array 204. Die 304 also discards another block 804 of the write data burst 802 (e.g., block 804-1). In one example implementation, die 304 transmits block 804-1 and a data trace signal 806-1 from write circuitry 702 to the connection pins 606 and 608, respectively. However, because the connection between data pin 606 and data tracking signal pin 608 is floating 1002, block 804-1 and data tracking signal 806-1 are effectively discarded. The die 304 can also perform independent read operations 318, such as regarding... Figure 11 Further description.

[0124] Figure 11 This describes an example die 304 that performs an independent read operation 318 according to independent mode 310. Die 304 can be configured as an interface die 504 or a link die 506 within an interconnect die architecture. Before integration into the interconnect die architecture, the connection data pin 606 and data trace signal pin 608 of die 304 are not connected to corresponding pins on another die. Therefore, the connection data pin 606 and data trace signal pin 608 are floating 1002.

[0125] The bare die 304 receives a standalone mode request 610 to perform a standalone read operation 318. The standalone read operation 318 may be similar to the read operation 314 performed by the interface bare die 504, such as... Figure 9-1 As shown in the diagram. However, instead of receiving one of the blocks 904 and one of the data tracking signals 906 from the link die 506, the die 304 generates alternative blocks 904 and alternative data tracking signals 906 during the independent read operation 318.

[0126] During independent read operation 318, die 304 reads block 904-1 from memory array 204 and transmits the first block 904-1 and the corresponding data tracking signal 906-1 from memory array 204 to read circuit 704. Die 304 also uses independent read data generator 720 to generate a second block 904-2. The second block 904-2 represents predetermined data with a specific positioning mode (e.g., previously known data). In some cases, independent read data generator 720 can select the specific positioning mode from at least two available bit modes. (Regarding...) Figure 12 An example implementation of the independent read data generator 720 is further described.

[0127] Using a data trace signal loopback circuit 722, die 304 generates a second data trace signal 906-2 based on a first data trace signal 906-1. In some embodiments, the data trace signal loopback circuit 722 routes the data trace signal 906-1 to a readout circuit 704, such that the readout circuit 704 associates the routed data trace signal 906-1 (e.g., data trace signal 906-2) with block 904-2. Regarding Figure 13 An example implementation of the data tracking signal loopback circuit 722 is further described.

[0128] Figure 12 This describes the instance of the independent read data generator 720, which supports independent read mode 318. Figure 12 In the diagram, a portion of die 304 is shown as including an independent read data generator 720, a data path 706, and connection data pins 606-1 to 606-N, where N represents a positive integer. Figure 12 Each of the connection data pins 606-1 to 606-N is associated with an individual bit of block 804 or 904. For example, connection data pin 606-1 is associated with the first bit of block 804 or 904 (when counting from 1), and connection data pin 606-N is associated with the last bit of block 804 or 904.

[0129] Data path 706 includes buffers 718-1, 718-2…718-(2N-1) and 718-(2N). Generally, each connection data pin 606 is connected to the output of the buffer 718 associated with transmission (e.g., buffers 718-1 and 718-(2N-1)) and the input of the buffer 718 associated with reception (e.g., buffers 718-2 and 718-(2N)). The input of the buffer 718 associated with transmission is coupled to a separate read data generator 720. Although not explicitly shown, the output of the buffer 718 associated with reception is coupled to read circuitry 704.

[0130] The independent read data generator 720 includes one or more inverters 1202 and multiplexers 1204-1 to 1204-N. The inverters 1202 enable the independent read data generator 720 to generate specific positioning patterns. Although not explicitly shown, one of the inputs of each of the multiplexers 1204-1 to 1204-N is coupled to the write circuit 702. Assuming die 304 represents interface die 504, the multiplexers 1204-1 to 1204-N enable the transmission of blocks 804-1 of the write data burst 802 to the link die 506 during write operation 312. The multiplexers 1204-1 to 1204-N also enable the transmission of blocks 904-2 generated by the independent read data generator 720 to the read circuit 704 during independent read operation 318.

[0131] To perform the independent read operation 318, the independent read data generator 720 receives the independent mode enable signal 1206 based on the independent mode request 610. The independent mode enable signal 1206 causes multiplexers 1204-1 to 1204-N to pass block 904-2 to the read circuit 704. Specifically, individual bits of block 904-2 are propagated to the read circuit 704 via buffers 718-1 and 718-(2N-1), connection data pins 606-1 to 606-N, and buffers 718-2 and 718-(2N), respectively.

[0132] During independent read operation 318, buffers 718-2 and 718-(2N) are enabled by receive enable signal 1210. Furthermore, buffers 718-1 and 718-(2N-1) are enabled by transmit enable signal 1212. By enabling the buffers 718 associated with transmit (e.g., buffers 718-1 and 718-(2N-1)) and the buffers 718 associated with receive (e.g., buffers 718-2 and 718-(2N)), block 904-2 can propagate from independent read data generator 720 to read circuit 704 via connection data pins 606-1 and 606-N. Although not explicitly shown, receive enable signal 1210 and transmit enable signal 1212 can be set based on independent mode enable signal 1206.

[0133] In the depicted configuration, the independent read data generator 720 generates blocks 904-2 based on the test data signal 1208. In this example, the independent read data generator 720 may generate two different bit patterns based on the test data signal 1208 representing a high voltage (e.g., "1") or a low voltage (e.g., "0").

[0134] In other embodiments, die 304 can perform independent read operation 318 without test data signal 1208. In this case, independent read data generator 720 can generate block 804-2 based on independent mode enable signal 1206 to provide a known bit pattern. Alternatively, independent read data generator 720 can generate block 904-2 based on data retained on the data bus. In this case, the bit pattern may be unknown. Further embodiments of independent read data generator 720 can generate user-defined bit patterns.

[0135] Figure 13 This describes the instance data tracking signal loopback circuit 722 that supports independent read mode 318. Figure 13 In the diagram, a portion of die 304 is shown as including a data trace signal loopback circuit 722, a data trace signal path 708, a logic "OR" gate 1302, and data trace signal pins 608-1 to 608-M, where M represents a positive integer. The data trace signal path 708 includes buffers 718-1, 718-2…718-(2M-1) and 718-(2M). Generally, each data trace signal pin 608 is connected to the output of a buffer 718 associated with transmission (e.g., buffers 718-1 and 718-(2M-1)) and the input of a buffer 718 associated with reception (e.g., buffers 718-2 and 718-(2M)). The input of the buffer 718 associated with transmission is coupled to the data trace signal loopback circuit 722. Although not explicitly shown, the output of the buffer 718 associated with reception is coupled to the readout circuit 704.

[0136] In the depicted configuration, the data tracking signal loopback circuit 722 includes multiplexers 1304-1 to 1304-M, which can be similar to... Figure 12 Multiplexers 1204-1 to 1204-N are used. Multiplexers 1304-1 to 1304-M are designed to pass the data track signal 906-1 to the read circuit 704 during an independent read operation 318. In this case, multiplexers 1304-1 to 1304-M pass the data track signal 906-1 regardless of the operation being performed. In other embodiments, the data track signal loopback circuit 722 does not have multiplexers 1304-1 to 1304-M.

[0137] During independent read operation 318, buffers 718-2 and 718-(2M) are enabled by receiving enable signal 1210 or independent mode enable signal 1206. In other words, the state of buffers 718-2 and 718-(2M) is controlled by the output of logic "OR" gate 1302. Furthermore, buffers 718-1 and 718-(2M-1) are enabled by transmission enable signal 1212. By enabling the buffers 718 associated with transmission (e.g., buffers 718-1 and 718-(2M-1)) and the buffers 718 associated with receiving (e.g., buffers 718-2 and 718-(2M)), data tracking signal 906-1 can propagate from data tracking signal loopback circuit 722 to read circuit 704 via data tracking signal pins 608-1 and 608-M. Although not explicitly shown, transmission enable signal 1212 can be set based on independent mode enable signal 1206.

[0138] Other implementations of the independent read data generator 720 and the data tracking signal loopback circuit 722 are also possible. For example, another implementation of the independent read data generator 720 may inject block 904-2 within the data path 706 instead of passing block 804-1 through the data connection pin 606. As another example, another implementation of the data tracking signal loopback circuit 722 may generate a data tracking signal 906-2 instead of passing a data tracking signal 906-1 through the data tracking signal pin 608.

[0139] While the description of independent mode 310 regarding the connection data pin 606 and data trace signal pin 608 as floating 1002 is helpful, die 304 can also operate according to independent mode 310 in other cases. For example, consider the case where die 304 is integrated within an interconnect die architecture. In this case, connection data pin 606 and data trace signal pin 608 can be connected to a high impedance (e.g., via a switch) based on independent mode request 610 to simulate that die 304 is independent (e.g., isolated from another interconnect die 120). With pins 606 and 608 set to high impedance, die 304 can operate according to independent mode 310 and perform independent write operation 316 and / or independent read operation 318.

[0140] Instance methods

[0141] This chapter references Figure 14 , 15 The flowcharts and flow diagrams in section 16 describe instance methods for implementing the standalone pattern. These descriptions may also be used as examples only. Figures 1 to 13 The components, entities, and other aspects described herein. The methods described are not necessarily limited to being performed by one or more entities operating on a device.

[0142] Figure 14 The flowchart 1400 illustrates operations 1402 through 1406. These operations can be performed by die 304 to implement aspects of standalone mode 310. At 1402, die 304 performs a standalone write operation 316 or a standalone read operation 318 before its connection data pin 606 is coupled to another connection data pin of another die. In other words, die 304 operates according to standalone mode 310 before being integrated into the interconnect die architecture. In this case, connection data pin 606 can be considered floating 1002. Standalone write operation 316 and standalone read operation 318 enable testing independent of whether die 304 is connected to another of the interconnect dies 120. In this case, die 304 can be implemented on a wafer or a single die package.

[0143] In die 1404, the connection data pin 606 of die 304 is coupled to another connection data pin of another die. For example, die 304 is integrated within an interconnect die architecture and is packaged with one or more other interconnect dies 120.

[0144] At 1406, die 304 performs a write operation 312 or a read operation 314 in conjunction with another die based on a connection data pin coupled to another connection data pin of another die. In other words, die 304 operates according to interconnect mode 308. Die 304 can be configured as an interface die 504 or a link die 506.

[0145] Figure 15 Flowchart 1500 illustrates operations 1502 through 1506. These operations can be performed by die 304 to generally implement aspects of standalone mode 310 and, more specifically, standalone write operation 316. At 1502, die 304 receives a request to perform standalone write operation 316 (e.g., standalone mode request 610). For example, die 304 receives standalone mode request 610 from a mode register or an external test engine.

[0146] At 1504, die 304 receives a write data burst 802 at its data pin 604 based on an independent write operation 316. The write data burst 802 includes a first block 804-1 and a second block 804-2. In some embodiments, the first block 804-1 contains the most significant byte, and the second block 804-2 contains the least significant byte. In other embodiments, the first block 804-1 contains the least significant byte, and the second block 804-2 contains the most significant byte.

[0147] At 1506, die 304 writes the first block 804-1 of the write data burst 802 to the memory array 204 of die 304 based on independent write operation 316. Die 304 may also discard (e.g., ignore or disregard) the second block 804-2 of the write data burst 802 according to independent write operation 316. In some embodiments, die 304 transmits the second block 804-2 of the write data burst 802 to connection data pin 606. When connection data pin 606 is floating 1002, the second block 804-2 of the write data burst 802 is discarded.

[0148] Figure 16 The flowchart 1600 illustrates operations 1602 through 1608. These operations can be performed by die 304 to generally implement aspects of independent mode 310 and, specifically, independent read operation 318. At 1602, die 304 receives independent mode request 610 to perform independent read operation 318. For example, die 304 receives independent mode request 610 from a mode register or an external text engine.

[0149] At 1604, die 304 reads a first block 904-1 of read data burst 902 from memory array 204 based on independent read operation 318. At 1606, die 304 generates a second block 904-2 of read data burst 902 based on independent read operation 318. The second block 904-2 of read data burst 902 may contain data with a pre-defined bit pattern selected according to independent mode request 610.

[0150] At 1608, the die 304 transmits the first block 904-1 and the second block 904-2 of the read data burst 902 to the die's data pin 604 based on the independent read operation 318.

[0151] The order in which the operations are shown and / or described in the flowcharts and flow diagrams described above is not intended to be restrictive. Any number or combination of the described process operations can be combined or rearranged in any order to implement the given method or alternative methods. Operations can also be omitted from or added to the described method. Furthermore, the described operations can be implemented in a completely or partially overlapping manner.

[0152] These methods or operations can be implemented, for example, in hardware (e.g., a fixed logic circuit system or a processor combined with memory), firmware, or a combination thereof. Figures 1 to 6The diagrams illustrate one or more of the devices, systems, or components used to implement methods, and these components may be further divided, combined, rearranged, etc. The devices, systems, and components in these diagrams generally represent: firmware, such as executable code or its actions; hardware, such as electronic devices, packaged modules, IC chips, or circuits; software, such as processor-executable instructions; or combinations thereof. The components of the illustrated devices 102 and 200 include, for example, a memory controller 114, interconnect 106, and a memory device 108. Figures 1 to 6 This describes some of the many possible systems or devices capable of implementing the described method.

[0153] Computer-readable media includes non-transitory computer storage media and communication media, including any media that facilitates the transfer of computer programs (e.g., applications) or data from one entity to another. Non-transitory computer storage media can be any available media that can be accessed by a computer, such as RAM, ROM, flash memory, EEPROM, optical media, and magnetic media.

[0154] Unless the context otherwise requires, the use of the word “or” herein may be interpreted as the use of “includes or”, or a term that allows inclusion or application of one or more items linked by the word “or” (e.g., the phrase “A or B” may be interpreted as allowing only “A”, only “B”, or both “A” and “B”). Furthermore, as used herein, the phrase “at least one of” in a list of items refers to any combination of those items containing a single member. For example, “at least one of a, b, or c” may cover a, b, c, ab, ac, bc, and abc, as well as any combination having multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c). Additionally, items represented in the figures and terminology discussed herein may indicate one or more items or terms, and therefore the singular or plural forms of items and terms in this written description may be used interchangeably.

[0155] Summarize

[0156] Although aspects of implementing the independent mode have been described in language specific to certain features and / or methods, the subject matter of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as various exemplary embodiments of implementing the independent mode.

Claims

1. A memory device comprising: The die is configured as one of a plurality of dies, the die comprising: Data pins; Connect the data pin, which is configured as follows: Floating, causing the connection data pin to be electrically disconnected from another die of the plurality of dies; or Another connection data pin coupled to the other die; and Memory array, The die is configured to operate in an independent mode based on the floating connection data pin, the independent mode including the die being configured to transfer data between the data pin and the memory array.

2. The memory device of claim 1, wherein the die is configured to: Perform independent write operations according to the independent mode; Based on the independent write operation, a write data burst is received at the data pin, the write data burst comprising a first block and a second block; and The first block of the write data burst is written to the memory array based on the independent write operation.

3. The memory device of claim 2, wherein the die is configured to discard the second block of the write data burst based on the independent write operation.

4. The memory device of claim 3, wherein the die is configured to transfer the second block of the write data burst from the data pin to the connected data pin based on the independent write operation.

5. The memory device of claim 1, wherein the die is configured to: Perform independent read operations according to the independent mode; Based on the independent read operation, the first block of the read data burst is read from the memory array; The second block of the read data burst is generated based on the independent read operation; and Based on the independent read operation, the first block of the read data burst and the second block of the read data burst are transmitted to the data pin.

6. The memory device according to claim 5, wherein: The bare wafer includes: Reading circuit; and A data path is provided, which connects the data connection pin to the read circuit; and The die is configured such that the second block of the read data burst propagates through at least a portion of the data path.

7. The memory device according to claim 6, wherein: The bare die is configured to: A first data tracking signal is propagated from the memory array to the read circuit, the first data tracking signal being associated with the first block of the read data burst; and A second data tracking signal is generated based on the first data tracking signal; and The read circuit is configured to: The first block of the read data burst is processed based on the first data tracking signal; and The second block of the read data burst is processed based on the second data tracking signal.

8. The memory device according to claim 7, wherein: The die includes a data tracking signal pin; and The die is configured to generate the second data tracking signal by propagating the first data tracking signal from the memory array to the data tracking signal pin and from the data tracking signal pin to the read circuit.

9. The memory device according to claim 5, wherein: The second block includes a pre-positioning pattern; and The die is configured to select the pre-defined bit mode from at least two available bit modes.

10. The memory device according to claim 1, wherein: The plurality of dies are configured to interconnect via the connection data pins; and The bare die is configured as follows: When the connection data pin floats, it operates according to the independent mode, or is coupled to the other connection data pin of the other die.

11. The memory device according to claim 10, wherein: The connection data pin is coupled to another connection data pin of another die among the plurality of dies; The data pins are configured to couple to the memory controller; and The die is configured to communicate data with the memory controller during a read or write operation, without the data propagating through the other die.

12. The memory device according to claim 10, wherein: The connection data pin is coupled to another connection data pin of another die among the plurality of dies; The data pin is configured to be inactive during read or write operations; and The die is configured to communicate data with the memory controller via another die among the plurality of dies during the read operation or the write operation.

13. The memory device of claim 10, further comprising: A memory controller coupled to the die.

14. The memory device according to claim 13, wherein: The memory device includes a fast computing link. ® CXL ® Device; and The memory controller is coupled to the die via interconnects within the CXL device.

15. A memory device comprising: Nude films, including: Connect the data pin, which is configured as follows: Float; or Another connection data pin of another die coupled to multiple dies. The bare die is configured to selectively: Based on the floating nature of the connection data pin, independent read or write operations are performed; and Based on the connection data pin coupled to the other die, a read operation or write operation is jointly performed with the other die among the plurality of dies.

16. The memory device of claim 15, wherein the die is configured to: Perform the independent write operation; Based on the independent write operation, a write data burst is received at the data pin, the write data burst comprising a first block and a second block; and The first block of the write data burst is written to the memory array of the die based on the independent write operation.

17. The memory device of claim 15, wherein the die is configured to: Perform the independent read operation; The first block of the read data burst is read from the memory array of the die based on the independent read operation; The second block of the read data burst is generated based on the independent read operation; and Based on the independent read operation, the first block of the read data burst and the second block of the read data burst are transmitted to the data pin.

18. The memory device of claim 15, wherein the die is configured to: Perform the read operation or the write operation; and During the read or write operation, data is communicated to the memory controller, but the data is not propagated through the other die.

19. The memory device of claim 15, wherein the die is configured to: Perform the read operation or the write operation; and The die is configured to transmit data to the memory controller via the other die.

20. A method for a memory device, comprising: Requests to perform independent write operations are received via the bare die; Based on the independent write operation, a write data burst is received at the data pin of the bare die, and the write data burst includes a first block and a second block; and The first block of the write data burst is written to the memory array of the die based on the independent write operation.

21. The method of claim 20, further comprising discarding the second block of the write data burst based on the independent write operation.

22. The method of claim 21, further comprising: Based on the independent write operation, the second block of the write data burst is transferred from the data pin to the connection data pin of the die. The connection data pins are floating.

23. The method of claim 20, wherein the receipt of the request, the acceptance of the write data burst, and the write of the first block of the write data burst are independent of the connection data pin of the die, which is either floating or coupled to another connection data pin of another die.

24. The method of claim 20, further comprising: The die receives another request to perform an independent read operation; Based on the independent read operation, the first block of the read data burst is read from the memory array; The second block of the read data burst is generated based on the independent read operation; and Based on the independent read operation, the first block of the read data burst and the second block of the read data burst are transmitted to the data pin.

25. A method for a memory device, comprising: Requests to perform independent read operations are received via the bare die; The first block of the read data burst is read from the memory array of the die based on the independent read operation; The second block of the read data burst is generated based on the independent read operation; and Based on the independent read operation, the first block of the read data burst and the second block of the read data burst are transmitted to the data pin of the die.

26. The method of claim 25, wherein the receipt of the request, the reading of the first block of the read data burst, the generation of the second block of the read data burst, and the transmission of the first block of the read data burst and the second block of the read data burst are independent of the connection data pin of the die, which is either floating or coupled to another connection data pin of another die.

27. The method of claim 25, further comprising: The die receives another request to perform an independent write operation; Based on the independent write operation, a write data burst is accepted at the data pin, the write data burst including a first block and a second block; and The first block of the write data burst is written to the memory array based on the independent write operation.

28. The method of claim 27, further comprising discarding the second block of the write data burst based on the independent write operation.

29. The method of claim 28, further comprising: Based on the independent write operation, the second block of the write data burst is transferred from the data pin to the connection data pin of the die. The connection data pins are floating.

30. A method for a memory device, comprising: Perform an independent write or read operation before the connection data pin of a die is coupled to another connection data pin of another die; Couple the connection data pin of the bare die to the other connection data pin of the other bare die; and Write or read operations can be performed in conjunction with the other die based on the other connection data pin coupled to the other die.

31. The method of claim 30, wherein performing the independent write operation or the independent read operation comprises: The request to perform the independent write operation is received via the die; Based on the independent write operation, a write data burst is received at the data pin of the bare die, and the write data burst includes a first block and a second block; and The first block of the write data burst is written to the memory array of the die based on the independent write operation.

32. The method of claim 31, further comprising discarding the second block of the write data burst based on the independent write operation.

33. The method of claim 30, wherein performing the independent write operation or the independent read operation comprises: The request to perform the independent read operation is received via the bare die; The first block of the read data burst is read from the memory array of the die based on the independent read operation; The second block of the read data burst is generated based on the independent read operation; and Based on the independent read operation, the first block of the read data burst and the second block of the read data burst are transmitted to the data pin of the die.

34. The method of claim 30, wherein performing the write operation or the read operation comprises communicating data with a memory controller, wherein the data is not propagated through the other die.

35. The method of claim 30, wherein performing the write operation or the read operation includes communicating data via the other die and memory controller.

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