Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, including: forming a first type doped layer in a substrate at a side of a device isolation structure and in the substrate at a bottom of the device isolation structure, and a second type doped layer on top of and in contact with the first type doped layer at the side of the device isolation structure, the first type doped layer at the bottom of the device isolation structure being in contact with the device isolation structure, the top of the first type doped layer at the side of the device isolation structure being lower than the bottom of the device isolation structure, and the first type doped layer at the side of the device isolation structure being in communication with the first type doped layer at the bottom of the device isolation structure, the device isolation structure covering a portion of a sidewall of the second doped layer, the first type doped layer and the second type doped layer being of different doping types; forming a source region and a drain region in the substrate at two sides of a gate structure, respectively, the gate structure and the source region and the drain region at the two sides of the gate structure forming a first transistor. The probability of current leakage between the source region or the drain region in the adjacent first transistor is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] Traditional CMOS (Complementary Metal Oxide Semiconductor) devices are subject to Boltzmann limitation, resulting in a minimum subthreshold swing at room temperature. Therefore, as CMOS device sizes continue to shrink, static power consumption increases exponentially with decreasing operating voltage. Consequently, CMOS is generally used in high-performance computing, where dynamic power consumption is dominant.

[0003] Unlike conventional CMOS, TFET (Tunneling Field-effect Transistor) has different doping types in its source and drain regions. TFET replaces the source-channel-drain structure with a PIN structure and uses band-to-band tunneling as the conduction mechanism. This can overcome the subthreshold swing limitation and achieve extremely low static leakage current and lower operating voltage, thereby reducing static power consumption.

[0004] Therefore, TFET devices with excellent subthreshold characteristics can be hybridized with traditional CMOS devices to reduce the overall power consumption of the circuit. The high-frequency part of the circuit is completed by conventional CMOS devices, and the low-frequency part is completed by TFET devices. This hybrid integration method has wide applications in the Internet of Things.

[0005] However, the performance of TFET devices still needs to be improved. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby optimizing the performance of semiconductor devices.

[0007] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate, the substrate including a first device region and a second device region; a first transistor, respectively located on the substrate of the first device region and the second device region, the first transistor including a gate structure and source and drain regions respectively located on both sides of the gate structure, wherein the doping types of the source and drain regions corresponding to the same first transistor are different; a device isolation structure, located in the substrate at the boundary between adjacent first and second device regions; and a first-type doped layer, located in the substrate on the side of the device isolation structure and in the substrate at the bottom of the device isolation structure, wherein the doping concentration of the first-type doped layer increases sequentially from bottom to top along the normal direction of the substrate surface. The first type doped layer located at the bottom of the device isolation structure is in contact with the device isolation structure. The top of the first type doped layer located on the side of the device isolation structure is lower than the bottom of the device isolation structure, and the first type doped layer located on the side of the device isolation structure is connected to the first type doped layer located at the bottom of the device isolation structure. The second type doped layer is located in the substrate on top of the first type doped layer. Along the normal direction of the substrate surface, the doping concentration of the second type doped layer decreases from bottom to top. The second type doped layer is in contact with the top of the first type doped layer, and the device isolation structure covers part of the sidewall of the second type doped layer. The first type doped layer and the second type doped layer have different doping types.

[0008] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first device region and a second device region for forming a first transistor, a gate structure being formed on the substrate of the first device region and the second device region, and a device isolation structure being formed in the substrate at the junction of adjacent first device regions and second device regions; forming a first type doped layer and a second type doped layer located on top of and in contact with the top of the first type doped layer in the substrate on the side of the device isolation structure and in the substrate at the bottom of the device isolation structure, wherein the doping concentration of the first type doped layer increases sequentially from bottom to top along the normal direction of the substrate surface, and the doping concentration of the second type doped layer decreases sequentially from bottom to top, and the second type doped layer is located on the substrate at the junction of adjacent first device regions and second device regions; and forming a first type doped layer and a second type doped layer located on top of and in contact with the top of the first type doped layer in the substrate at the junction of the device isolation structure and the second type doped layer. The first type doped layer at the bottom of the structure is in contact with the device isolation structure. The top of the first type doped region layer located on the side of the device isolation structure is lower than the bottom of the device isolation structure, and the first type doped layer located on the side of the device isolation structure is connected to the first type doped layer located at the bottom of the device isolation structure. The device isolation structure covers part of the sidewall of the second doped layer. The first type doped layer and the second type doped layer have different doping types. After the first type doped layer and the second type doped layer are formed, a source region and a drain region are formed in the substrate on both sides of the gate structure in the first device region and the second device region, respectively. The gate structure and the source and drain regions located on both sides of it constitute a first transistor. The drain and source regions corresponding to the same first transistor have different doping types.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] In the semiconductor structure formation method provided by this invention, a first type doped layer and a second type doped layer are formed in the substrate on the side of the device isolation structure and in the substrate at the bottom of the device isolation structure. The first type doped layer is located on top of and in contact with the top of the first type doped layer. The first type doped layer at the bottom of the device isolation structure is in contact with the device isolation structure. The top of the first type doped layer on the side of the device isolation structure is lower than the bottom of the device isolation structure, and the first type doped layer on the side of the device isolation structure is connected to the first type doped layer at the bottom of the device isolation structure. The device isolation structure covers part of the sidewall of the second type doped layer. The first type doped layer and the second type doped layer have different doping types. Accordingly, after the drain and source regions are subsequently formed, because the device isolation structure covers part of the sidewall of the second type doped layer, and the bottom of the second type doped layer is lower than the bottom of the device isolation structure, the second type doped layer isolates the source or drain regions in adjacent first transistors with doping types opposite to those of the second type doped layer, reducing the number of adjacent first transistors with doping types opposite to those of the second type doped layer. The probability of leakage between the source or drain regions of the first transistor through the lower position of the first transistor and the corner of the device isolation structure is reduced. Since the first type doped layer at the bottom of the device isolation structure is in contact with the device isolation structure, and the first type doped layer on the side of the device isolation structure is connected to the first type doped layer at the bottom of the device isolation structure, the first type doped layer isolates the source or drain regions in adjacent first transistors with the opposite doping type to the first type doped layer, reducing the probability of leakage between the source or drain regions in adjacent first transistors with the opposite doping type to the first type doped layer through the lower position of the first transistor and the corner of the device isolation structure. At the same time, since the first type doped layer is in contact with the second type doped layer, a depletion layer can be formed at the interface between the first type doped layer and the second type doped layer. The formation of the depletion layer reduces the probability of leakage channels between the source or drain regions in adjacent first transistors through the lower position of the first transistor and the corner of the isolation structure, that is, it reduces the probability of leakage between the source or drain regions in adjacent first transistors, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0011] Figures 1-2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figure 3 This is a schematic diagram of the corresponding structure in one embodiment of the semiconductor structure of the present invention;

[0013] Figures 4-6 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0014] As the background technology shows, the performance of semiconductor devices still needs improvement. This paper analyzes the reasons why the performance of semiconductor devices still needs improvement, using a semiconductor structure formation method as an example.

[0015] Figures 1-2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0016] refer to Figure 1 A substrate 10 is provided, the substrate 10 including a first device region 10A and a second device region 10B for forming a first transistor. A gate structure 11 is formed on the substrate 10 of the first device region 10A and the second device region 10B. A device isolation structure 12 is formed in the substrate 10 at the junction of adjacent first device region 10A and second device region 10B.

[0017] refer to Figure 2 In the first device region 10A and the second device region 10B, a source region 17 and a drain region 18 are formed in the substrate 10 on both sides of the gate structure 11, respectively. The gate structure 11 and the source region 17 and the drain region 18 located on both sides of it constitute a first transistor. The drain region 18 and the source region 17 corresponding to the same first transistor have different doping types.

[0018] In this configuration, either the first transistor located in the first device region 10A or the second device region 10B is an N-type transistor, and the other first transistor is a P-type transistor. The doped ions in the drain region 18 of the N-type transistor are N-type ions, the doped ions in the source region 17 of the N-type transistor are P-type ions, the doped ions in the drain region 18 of the P-type transistor are P-type ions, and the doped ions in the source region 17 of the P-type transistor are N-type ions.

[0019] Research has revealed that after the formation of source region 17 and drain region 18, the dopant ions in the drain region 18 of the N-type transistor easily diffuse with the dopant ions in the source region 17 of the P-type transistor. Specifically, the dopant ions in the drain region 18 of the N-type transistor easily diffuse with the dopant ions in the source region 17 of the P-type transistor through the substrate 10, forming a leakage channel between the N-type and P-type transistors, thus affecting the performance of the semiconductor structure.

[0020] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first device region and a second device region for forming a first transistor, a gate structure formed on the substrate of the first device region and the second device region, and a device isolation structure formed in the substrate at the boundary between adjacent first device regions and second device regions; forming a first type doped layer and a second type doped layer located on top of and in contact with the top of the first type doped layer in the substrate on the side of the device isolation structure and in the substrate at the bottom of the device isolation structure, wherein the doping concentration of the first type doped layer increases sequentially from bottom to top along the normal direction of the substrate surface, and the doping concentration of the second type doped layer decreases sequentially from bottom to top. The first type doped layer at the bottom of the device isolation structure is in contact with the device isolation structure. The top of the first type doped region layer located on the side of the device isolation structure is lower than the bottom of the device isolation structure, and the first type doped layer located on the side of the device isolation structure is connected to the first type doped layer located at the bottom of the device isolation structure. The device isolation structure covers part of the sidewall of the second doped layer. The first type doped layer and the second type doped layer have different doping types. After the first type doped layer and the second type doped layer are formed, a source region and a drain region are formed in the substrate on both sides of the gate structure in the first device region and the second device region, respectively. The gate structure and the source and drain regions located on both sides of it constitute a first transistor. The drain and source regions corresponding to the same first transistor have different doping types.

[0021] In the semiconductor structure formation method provided by this invention, a first type doped layer and a second type doped layer are formed in the substrate on the side of the device isolation structure and in the substrate at the bottom of the device isolation structure. The first type doped layer is located on top of and in contact with the top of the first type doped layer. The first type doped layer at the bottom of the device isolation structure is in contact with the device isolation structure. The top of the first type doped layer on the side of the device isolation structure is lower than the bottom of the device isolation structure, and the first type doped layer on the side of the device isolation structure is connected to the first type doped layer at the bottom of the device isolation structure. The device isolation structure covers part of the sidewall of the second type doped layer. The first type doped layer and the second type doped layer have different doping types. Accordingly, after the drain and source regions are subsequently formed, because the device isolation structure covers part of the sidewall of the second type doped layer, and the bottom of the second type doped layer is lower than the bottom of the device isolation structure, the second type doped layer isolates the source or drain regions in adjacent first transistors with doping types opposite to those of the second type doped layer, reducing the number of adjacent first transistors with doping types opposite to those of the second type doped layer. The probability of leakage between the source or drain regions of the first transistor through the lower position of the first transistor and the corner of the device isolation structure is reduced. Since the first type doped layer at the bottom of the device isolation structure is in contact with the device isolation structure, and the first type doped layer on the side of the device isolation structure is connected to the first type doped layer at the bottom of the device isolation structure, the first type doped layer isolates the source or drain regions in adjacent first transistors with the opposite doping type to the first type doped layer, reducing the probability of leakage between the source or drain regions in adjacent first transistors with the opposite doping type to the first type doped layer through the lower position of the first transistor and the corner of the device isolation structure. At the same time, since the first type doped layer is in contact with the second type doped layer, a depletion layer can be formed at the interface between the first type doped layer and the second type doped layer. The formation of the depletion layer reduces the probability of leakage channels between the source or drain regions in adjacent first transistors through the lower position of the first transistor and the corner of the isolation structure, that is, it reduces the probability of leakage between the source or drain regions in adjacent first transistors, thereby improving the performance of the semiconductor structure.

[0022] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Figure 3 This is a schematic diagram of the semiconductor structure corresponding to the first embodiment of the present invention.

[0024] The semiconductor structure includes: a substrate 200, which includes a first device region 200A and a second device region 200B; a first transistor, located on the substrate 200 of the first device region 200A and the second device region 200B respectively, the first transistor including a gate structure 201 and a source region 207 and a drain region 208 located on both sides of the gate structure 201 respectively, the source region 207 and the drain region 208 corresponding to the same first transistor having different doping types; a device isolation structure 202, located in the substrate 200 at the junction of adjacent first device regions 200A and second device regions 200B; and a first-type doped layer 206, located in the substrate 200 on the side of the device isolation structure 202 and in the substrate 200 at the bottom of the device isolation structure 202, the doping concentration of the first-type doped layer 206 increasing sequentially from bottom to top along the normal direction of the surface of the substrate 200, and located in the... The first type doped layer 206 at the bottom of the device isolation structure 202 is in contact with the device isolation structure 202. The top of the first type doped layer 206 located on the side of the device isolation structure 202 is lower than the bottom of the device isolation structure 202, and the first type doped layer 206 located on the side of the device isolation structure 202 is connected to the first type doped layer 206 located at the bottom of the device isolation structure 202. The second type doped layer 203 is located in the substrate 200 on top of the first type doped layer 206. Along the normal direction of the surface of the substrate 200, the doping concentration of the second type doped layer 203 decreases from bottom to top. The second type doped layer 203 is in contact with the top of the first type doped layer 206, and the device isolation structure 202 covers part of the sidewall of the second type doped layer 203. The doping types of the first type doped layer 206 and the second type doped layer 203 are different.

[0025] Specifically, by providing a first-type doped layer 206 and a second-type doped layer 203 in the substrate 200 of the first device region 200A and the second device region 200B, since the device isolation structure 202 covers part of the sidewall of the second-type doped layer 203, and the bottom of the second-type doped layer 203 is lower than the bottom of the device isolation structure 202, the second-type doped layer 203 isolates the source region 207 or drain region 208 in the adjacent first transistor with the opposite doping type to the second-type doped layer 203, reducing the probability of leakage between the source region 207 or drain region 208 in the adjacent first transistor with the opposite doping type to the second-type doped layer 203 through the position below the first transistor and the corner of the device isolation structure 202. Since the first-type doped layer 206 located at the bottom of the device isolation structure 202 is in contact with the device isolation structure 202, and the first-type doped layer 206 located on the side of the device isolation structure 202 is in contact with the first-type doped layer 203 located at the bottom of the device isolation structure 202, the first-type doped layer 206 located on the side of the device isolation structure 202 is in contact with the first-type doped layer 203 located at the bottom of the device isolation structure 202. Layers 206 are interconnected. The first type doped layer 206 isolates the source region 207 or drain region 208 in adjacent first transistors that have the opposite doping type to the first type doped layer 206. This reduces the probability of leakage between the source region 207 or drain region 208 in adjacent first transistors that have the opposite doping type to the first type doped layer 206 through the position below the first transistor and the corner of the device isolation structure 202. At the same time, since the first type doped layer 206 is in contact with the second type doped layer 203, a depletion layer can be formed at the interface between the first type doped layer 206 and the second type doped layer 203. The formation of the depletion layer reduces the probability of the source region 207 or drain region 208 in adjacent first transistors forming a leakage path between the first type doped layer 206 and the second type doped layer 203 through the position below the first transistor and the corner of the isolation structure. In other words, it reduces the probability of leakage between the source region 207 or drain region 208 in adjacent first transistors, thereby improving the performance of the semiconductor structure.

[0026] The substrate 200 is used to provide a process platform for subsequent process manufacturing.

[0027] In this embodiment, taking the substrate 200 as an example of forming a planar field-effect transistor, the substrate 200 is a planar substrate. In other embodiments, depending on the type of transistor actually formed, the substrate can also be a three-dimensional substrate. For example, when the substrate is used to form a fin field-effect transistor (FinFET), the substrate includes a substrate and fins protruding from the substrate.

[0028] In this embodiment, the first device region 200A and the second device region 200B are areas where transistors are disposed.

[0029] The first transistor is a variable current switch with a semiconductor structure, which can control the output current based on the input voltage.

[0030] In this embodiment, the first transistor includes a tunneling field-effect transistor (TFET). In other embodiments, depending on the actual type of transistor formed, the first type of transistor may also be a fin field-effect transistor (FinFET).

[0031] The gate structure 201 is used to control the opening and closing of the conductive channel.

[0032] In this embodiment, the gate structure 201 includes a polysilicon gate structure 201.

[0033] In this embodiment, the gate structure 201 includes a gate oxide layer (not shown) and a gate layer (not shown) located on the gate oxide layer. The gate oxide layer is used to isolate the gate layer and the substrate 200. When the device is working, the gate layer is used to control the opening or closing of the conductive channel.

[0034] In this embodiment, the gate layer is made of polysilicon, and the gate oxide layer is made of silicon oxide or silicon oxynitride.

[0035] Specifically, the drain region 208 and the source region 207 are used as the drain and source of the first transistor, respectively.

[0036] The drain region 208 and the source region 207 have different doping types, thus forming a PIN (P-Intrinsic-N) structure, and then using band tunneling as the conduction mechanism.

[0037] In this embodiment, the first transistor located in either the first device region 200A or the second device region 200B is an N-type transistor, and the first transistor in the other is a P-type transistor; wherein, the doped ions in the drain region 208 of the N-type transistor are N-type ions, the doped ions in the source region 207 of the N-type transistor are P-type ions, the doped ions in the drain region 208 of the P-type transistor are P-type ions, and the doped ions in the source region 207 of the P-type transistor are N-type ions.

[0038] Specifically, N-type ions include P ions, As ions, or Sb ions, while P-type ions include B ions, Ga ions, or In ions.

[0039] The device isolation structure 202 is used to achieve isolation between the first device region 200A and the second device region 200B, thereby reducing the risk of mutual leakage between adjacent first device regions 200A and second device regions 200B.

[0040] Therefore, the material of the device isolation structure 202 is an insulating material; as an example, the material of the device isolation structure 202 is silicon oxide.

[0041] In this embodiment, the substrate 200 also includes a third device region (not shown).

[0042] Specifically, the third device area is the area where transistors are located.

[0043] In this embodiment, the semiconductor structure further includes a second transistor located on the substrate 200 of the third device region. The second transistor includes a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0044] Therefore, the first device region 200A and the second device region 200B are used to form a tunneling field-effect transistor (TFET), and the third device region is used to form a metal-oxide-semiconductor (MOS) field-effect transistor. The tunneling field-effect transistor is isolated from the MOS field-effect transistor.

[0045] Specifically, an isolation structure is provided in the substrate 200 at the junction of the second device region 200B and the third device region. The isolation structure is used to achieve isolation between the second device region 200B and the third device region, thereby reducing the risk of mutual leakage between adjacent second device regions 200B and third device regions.

[0046] In this embodiment, the material of the isolation structure includes silicon oxide.

[0047] In the formation process of the first type doped layer 206, by gradually increasing the doping dose of the ion implantation process, the doping concentration of the first type doped layer 206 increases sequentially from bottom to top along the normal direction of the surface of the substrate 200.

[0048] It should be noted that the doping concentration at the top of the first type doped layer 206 is the highest, which allows the first type doped layer to isolate the source or drain regions in the adjacent first transistors that have the opposite doping type to the first type doped layer 206. This reduces the probability of leakage between the source or drain regions in the adjacent first transistors that have the opposite doping type to the first type doped layer 206 through the position below the first transistor and the corner of the device isolation structure.

[0049] In this embodiment, the first type doped layer 206 is located in the substrate 200 on the side of the device isolation structure 202 and in the substrate 200 at the bottom of the device isolation structure 202. The first type doped layer 206 at the bottom of the device isolation structure 202 is in contact with the device isolation structure 202. The top of the first type doped layer 206 on the side of the device isolation structure 202 is lower than the bottom of the device isolation structure 202, and the first type doped layer 206 on the side of the device isolation structure 202 is connected to the first type doped layer 206 at the bottom of the device isolation structure 202.

[0050] Specifically, the first type doped layer 206 located at the bottom of the device isolation structure 202 is in contact with the device isolation structure 202, and the first type doped layer 206 located on the side of the device isolation structure 202 is connected to the first type doped layer 206 located at the bottom of the device isolation structure 202. The first type doped layer 206 isolates the source region 207 or drain region 208 in the adjacent first transistors that have the opposite doping type to the first type doped layer 206, thereby reducing the probability of leakage between the source region 207 or drain region 208 in the adjacent first transistors that have the opposite doping type to the first type doped layer 206 through the position below the first transistor and the corner of the device isolation structure 202.

[0051] It should be noted that the concentration of doped ions in the first type doped layer 206 should not be too high or too low. If the concentration of doped ions in the first type doped layer 206 is too high, it increases the probability of interdiffusion of ions in the source region 207 or drain region 208 of the adjacent first transistor with the same doping type as the first type doped layer 206. If the concentration of doped ions in the first type doped layer 206 is too low, the first type doped layer 206 cannot completely block the diffusion of ions from the source region 207 or drain region 208 of the adjacent first transistor with the opposite doping type to the first type doped layer 206, increasing the probability of leakage between the source region 207 or drain region 208 of the adjacent first transistor with the opposite doping type to the first type doped layer 206, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the concentration of doped ions in the first type doped layer 206 is 1E12 atom / cm³. 3 Up to 1E14atom / cm 3 .

[0052] It should also be noted that the thickness of the first type doped layer 206 along the normal direction of the substrate 200 surface should not be too large or too small. If the thickness of the first type doped layer 206 is too large, the process cost of forming the first type doped layer 206 will increase, and the process efficiency will be reduced. If the thickness of the first type doped layer 206 is too small, the first type doped layer 206 cannot completely block the diffusion of ions from the source region 207 or drain region 208 of the adjacent first transistor with the opposite doping type to the first type doped layer 206, increasing the probability of leakage between the source region 207 or drain region 208 of the adjacent first transistor with the opposite doping type to the first type doped layer 206, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the first type doped layer 206 along the normal direction of the substrate 200 surface is 40 nanometers to 300 nanometers.

[0053] In this embodiment, the ions doped in the first type doped layer 206 are P-type ions.

[0054] Specifically, P-type ions include one or more of B ions, Ga ions, or In ions.

[0055] In other embodiments, the ions doped in the first type doped layer may also be N-type ions.

[0056] In the process of forming the second type doped layer 203, by gradually reducing the doping dose of the ion implantation process, the doping concentration of the second type doped layer 203 decreases sequentially from bottom to top along the normal direction of the surface of the substrate 200.

[0057] Specifically, the bottom of the second type doped layer 203 has the highest doping concentration, which isolates the source or drain regions in the adjacent first transistors that have the opposite doping type to the second type doped layer 203. This reduces the probability of leakage between the source or drain regions in the adjacent first transistors that have the opposite doping type to the second type doped layer 203 through the position below the first transistor and the corner of the device isolation structure 202.

[0058] The topmost doping concentration of the second-type doped layer 203 is the lowest, which reduces the probability of short circuits between the second-type doped layer 203 and the source region 207 or the drain region 208, thereby improving the performance of the semiconductor structure.

[0059] It should be noted that the concentration of doped ions in the second-type doped layer 203 should not be too high or too low. If the concentration of doped ions in the second-type doped layer 203 is too high, the probability of short circuit between the second-type doped layer 203 and the source region 207 or drain region 208 increases, thus affecting the performance of the semiconductor structure. If the concentration of doped ions in the second-type doped layer 203 is too low, the second-type doped layer 203 cannot completely block the diffusion of ions from the source region 207 or drain region 208 in the adjacent first transistor, which has the opposite doping type to the second-type doped layer 203. This increases the probability of leakage between the source region 207 or drain region 208 in the adjacent first transistor, which has the opposite doping type to the second-type doped layer 203, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the concentration of doped ions in the second-type doped layer 203 is 1E12 atom / cm³. 3 Up to 1E14atom / cm 3 .

[0060] It should also be noted that the distance from the top of the second-type doped layer 203 to the bottom of the source region 207 or drain region 208 along the normal direction of the substrate 200 surface should not be too large or too small. If the distance from the top of the second-type doped layer 203 to the bottom of the source region 207 or drain region 208 is too large, it may lead to an insufficiently small formation area for the second-type doped layer 203, even if the doping depth of the first-type doped layer 206 meets the process requirements. Consequently, the second-type doped layer 203 may not be able to completely block the diffusion of ions from the source region 207 or drain region 208 of the adjacent first transistor, which has a doping type opposite to that of the second-type doped layer 203. This increases the probability of leakage between the source region 207 or drain region 208 of the adjacent first transistor, which has a doping type opposite to that of the second-type doped layer 203. If the distance from the top of the second-type doped layer 203 to the top surface of the substrate 200 is too small, it increases the probability of short-circuiting between the second-type doped layer 203 and the source region 207 or drain region 208, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the distance from the top of the second type doped layer 203 to the top surface of the substrate 200 along the normal direction of the surface of the substrate 200 is 150 nanometers to 800 nanometers.

[0061] Specifically, the thickness of the second-type doped layer 203 along the normal direction of the substrate 200 surface should not be too large or too small. If the thickness of the second-type doped layer 203 is too large, the probability of the top of the second-type doped layer 203 short-circuiting with the source region 207 or drain region 208 increases, thereby affecting the performance of the semiconductor structure. If the thickness of the second-type doped layer 203 is too small, it is easy for the second-type doped layer 203 to fail to completely block the diffusion of ions from the source region 207 or drain region 208 in the adjacent first transistor with the opposite doping type to the second-type doped layer 203, increasing the probability of leakage between the source region 207 or drain region 208 in the adjacent first transistor with the opposite doping type to the second-type doped layer 203. Therefore, in this embodiment, the thickness of the second-type doped layer 203 is 150 nanometers to 800 nanometers.

[0062] In this embodiment, the ions doped in the second type doped layer 203 are N-type ions.

[0063] Specifically, N-type ions include one or more of P ions, As ions, or Sb ions.

[0064] In other embodiments, the ions doped in the second type doped layer may also be P-type ions.

[0065] Figures 4-6 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention.

[0066] refer to Figure 4A substrate 100 is provided, the substrate 100 including a first device region 100A and a second device region 100B for forming a first transistor. A gate structure 101 is formed on the substrate 100 of the first device region 100A and the second device region 100B. A device isolation structure 102 is formed in the substrate 100 at the junction of adjacent first device regions 100A and second device regions 100B.

[0067] Substrate 100 is used to provide a process platform for subsequent process manufacturing.

[0068] In this embodiment, taking the substrate 100 as an example of forming a planar field-effect transistor, the substrate 100 is a planar substrate. In other embodiments, depending on the type of transistor actually formed, the substrate can also be a three-dimensional substrate. For example, when the substrate is used to form a fin field-effect transistor (FinFET), the substrate includes a substrate and fins protruding from the substrate.

[0069] In this embodiment, the first device region 100A and the second device region 100B are the transistor formation regions.

[0070] In this embodiment, either the first device region 100A or the second device region 100B is used to form an N-type first transistor, and the other is used to form a P-type first transistor.

[0071] In this embodiment, the first transistor includes a tunneling field-effect transistor (TFET). In other embodiments, depending on the actual type of transistor formed, the first type of transistor may also be a fin field-effect transistor (FinFET).

[0072] The device isolation structure 102 is used to achieve isolation between the first device region 100A and the second device region 100B, thereby reducing the risk of mutual leakage between adjacent first device regions 100A and second device regions 100B.

[0073] Therefore, the material of the device isolation structure 102 is an insulating material; as an example, the material of the device isolation structure 102 is silicon oxide.

[0074] The gate structure 101 is used to control the opening and closing of the conductive channel.

[0075] In this embodiment, the gate structure 101 includes a polysilicon gate structure 101.

[0076] In this embodiment, the gate structure 101 includes a gate oxide layer (not shown) and a gate layer (not shown) located on the gate oxide layer. The gate oxide layer is used to isolate the gate layer and the substrate 100. When the device is working, the gate layer is used to control the opening or closing of the conductive channel.

[0077] In this embodiment, the gate layer is made of polysilicon, and the gate oxide layer is made of silicon oxide or silicon oxynitride.

[0078] In this embodiment, the substrate 100 further includes a third device region (not shown) for forming a second transistor, which includes a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0079] The first device region 100A and the second device region 100B are used to form a tunneling field-effect transistor (TFET), and the third device region is used to form a metal-oxide-semiconductor (MOS) field-effect transistor. The tunneling field-effect transistor is isolated from the MOS field-effect transistor.

[0080] Specifically, an isolation structure (not shown) is formed in the substrate 100 at the junction of the second device region 100B and the third device region. The isolation structure is used to achieve isolation between the second device region 100B and the third device region, and reduce the risk of mutual leakage between adjacent second device regions 100B and third device regions.

[0081] In this embodiment, the material of the isolation structure includes silicon oxide.

[0082] refer to Figure 5 A first type doped layer 106 and a second type doped layer 103 located on top of and in contact with the top of the first type doped layer 106 are formed in the substrate 100 on the side of the device isolation structure 102 and in the substrate 100 at the bottom of the device isolation structure 102. Along the normal direction of the surface of the substrate 100, the doping concentration of the first type doped layer 106 increases sequentially from bottom to top, and the doping concentration of the second type doped layer 103 decreases sequentially from bottom to top. The second type doped layer 103 located at the bottom of the device isolation structure 102... The first type doped layer 106 is in contact with the device isolation structure 102. The top of the first type doped layer 106 located on the side of the device isolation structure 102 is lower than the bottom of the device isolation structure 102. The first type doped layer 106 located on the side of the device isolation structure 102 is connected to the first type doped layer 106 located at the bottom of the device isolation structure 102. The device isolation structure 102 covers part of the sidewall of the second doped layer 103. The first type doped layer 106 and the second type doped layer 103 have different doping types.

[0083] It should be noted that after the drain and source regions are subsequently formed, since the device isolation structure 102 covers part of the sidewall of the second type doped layer 103, and the bottom of the second type doped layer 103 is lower than the bottom of the device isolation structure 102, the second type doped layer 103 isolates the source or drain regions in adjacent first transistors that have the opposite doping type to the second type doped layer 103, reducing the probability of leakage between the source or drain regions in adjacent first transistors that have the opposite doping type to the second type doped layer 103 through the position below the first transistor and the corner of the device isolation structure 102. Since the first type doped layer 106 located at the bottom of the device isolation structure 102 is in contact with the device isolation structure 102, and the first type doped layer 106 located on the side of the device isolation structure 102 is connected to the first type doped layer 106 located at the bottom of the device isolation structure 102, the first... The first doped layer 106 isolates the source or drain regions in adjacent first transistors that have a doping type opposite to that of the first doped layer 106, reducing the probability of leakage between these regions through the lower part of the first transistor and the corner of the device isolation structure 102. Simultaneously, since the first doped layer 106 is in contact with the second doped layer 103, a depletion layer can be formed at the interface between them. This depletion layer reduces the probability of leakage paths between the source or drain regions in adjacent first transistors through the lower part of the first transistor and the corner of the isolation structure, thereby improving the performance of the semiconductor structure.

[0084] In this embodiment, the steps of forming the first type doped layer 106 and the second type doped layer 103 include: forming the first type doped layer 106 in the substrate 100 on the side of the device isolation structure 102 and in the substrate 100 at the bottom of the device isolation structure 102, wherein the top of the first type doped layer 106 on the side of the device isolation structure 102 is lower than the bottom of the device isolation structure 102; after forming the first type doped layer 106, forming the second type doped layer 103 on the top of the first type doped layer 106 on the side of the device isolation structure 102, wherein the device isolation structure 102 covers part of the sidewall of the second type doped layer 103.

[0085] In this embodiment, the process for forming the first type doped layer 106 and the second type doped layer 103 includes an ion implantation process.

[0086] It should be noted that ion implantation process has the characteristics of high controllability, which can precisely control the concentration and depth of doped ions. Accordingly, the formation of the first type doped layer 106 and the second type doped layer 103 by ion implantation process can ensure that the formation regions of the first type doped layer 106 and the second type doped layer 103 meet the process requirements, thereby reducing leakage current between the source or drain regions in adjacent first transistors and thus improving the performance of the semiconductor structure.

[0087] In this embodiment, during the formation of the first type doped layer 106, the doping dose of the ion implantation process is gradually increased, thereby increasing the doping concentration of the first type doped layer 106 from bottom to top along the normal direction of the surface of the substrate 100.

[0088] It should be noted that the doping concentration at the top of the first type doped layer 106 is the highest, which isolates the source or drain regions in the adjacent first transistors that have the opposite doping type to the first type doped layer 106. This reduces the probability of leakage between the source or drain regions in the adjacent first transistors that have the opposite doping type to the first type doped layer 106 through the position below the first transistor and the corner of the device isolation structure 102.

[0089] It should be noted that during the formation of the first type doped layer 106, the doping dose range of the ion implantation process should not be too large or too small. If the doping dose of the ion implantation process is too large, the probability of ions in the source or drain regions of adjacent first transistors with the same doping type as the first type doped layer 106 diffusing into each other increases. If the doping dose of the ion implantation process is too small, after the subsequent formation of the source and drain regions, the first type doped layer 106 cannot completely block the diffusion of ions from the source or drain regions of adjacent first transistors with the opposite doping type to the first type doped layer 106, increasing the probability of leakage between the source or drain regions of adjacent first transistors with the opposite doping type to the first type doped layer 106, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, during the formation of the first type doped layer 106, the doping dose range of the ion implantation process is 1E12 atom / cm. 3 Up to 1E14atom / cm 3 .

[0090] It should also be noted that during the formation of the first type doped layer 106, the implantation energy range of the ion implantation process should not be too large or too small. If the implantation energy is too large, the doping depth of the first type doped layer 106 may be too large, making it unable to effectively block ions diffusing from the source or drain regions of adjacent first transistors with opposite doping types. This increases the probability of leakage between the source or drain regions of adjacent first transistors with opposite doping types, thus affecting the performance of the semiconductor structure. If the implantation energy is too small, the doping depth of the first type doped layer 106 may be too small. Consequently, after the formation of the second type doped layer 103, the probability of short-circuiting between the second type doped layer 103 and the subsequently formed source or drain regions increases, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the implantation energy range of the ion implantation process during the formation of the first type doped layer 106 is 50 keV to 500 keV.

[0091] Specifically, the thickness of the first type doped layer 106 along the normal direction of the substrate 100 surface should not be too large or too small. If the thickness of the first type doped layer 106 is too large, the process cost of forming the first type doped layer 106 will increase, and the process efficiency will be reduced. If the thickness of the first type doped layer 106 is too small, after the subsequent formation of the source and drain regions, the first type doped layer 106 cannot completely block the diffusion of ions from the source or drain regions of adjacent first transistors with doping types opposite to those of the first type doped layer 106, increasing the probability of leakage between the source or drain regions of adjacent first transistors with doping types opposite to those of the first type doped layer 106, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the first type doped layer 106 along the normal direction of the substrate 100 surface is 40 nanometers to 300 nanometers.

[0092] In this embodiment, the ions doped in the first type doped layer 106 are P-type ions.

[0093] Specifically, P-type ions include one or more of B ions, Ga ions, or In ions.

[0094] In other embodiments, the ions doped in the first type doped layer may also be N-type ions.

[0095] During the formation of the second type doped layer 103, the doping concentration of the second type doped layer 103 decreases sequentially from bottom to top along the normal direction of the surface of the substrate 100 by gradually reducing the doping dose of the ion implantation process.

[0096] Specifically, the bottom of the second type doped layer 103 has the highest doping concentration, which isolates the source or drain regions in the adjacent first transistors that have the opposite doping type to the second type doped layer 103. This reduces the probability of leakage between the source or drain regions in the adjacent first transistors that have the opposite doping type to the second type doped layer 103 through the position below the first transistor and the corner of the device isolation structure 102.

[0097] The topmost doping concentration of the second-type doped layer 103 is the lowest, which reduces the probability of short circuits between the second-type doped layer 103 and the source region 107 or the drain region 108, thereby improving the performance of the semiconductor structure.

[0098] It should be noted that during the formation of the second type doped layer 103, the doping dose range of the ion implantation process should not be too large or too small. If the doping dose of the ion implantation process is too large, the probability of short circuit between the second type doped layer 103 and the subsequently formed source or drain regions increases, thereby affecting the performance of the semiconductor structure. If the doping dose of the ion implantation process is too small, after the subsequent formation of the source and drain regions, the second type doped layer 103 cannot completely block the diffusion of ions from the source or drain regions of the adjacent first transistor with the opposite doping type to the second type doped layer 103, increasing the probability of leakage between the source or drain regions of the adjacent first transistor with the opposite doping type to the second type doped layer 103, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the doping dose range of the ion implantation process during the formation of the second type doped layer 103 is 1E12 atom / cm. 3 Up to 1E14atom / cm 3 .

[0099] It should also be noted that during the formation of the second type doped layer 103, the implantation energy range of the ion implantation process should not be too large or too small. If the implantation energy is too large, the ions doped in the second type doped layer 103 can easily be implanted into the first type doped layer 106, causing the second type doped layer 103 to be unable to completely block the diffusion of ions from the source or drain regions of adjacent first transistors with opposite doping types to the second type doped layer 103. This increases the probability of leakage between the source or drain regions of adjacent first transistors with opposite doping types to the second type doped layer 103, thereby affecting the performance of the semiconductor structure. If the implantation energy is too small, the doping depth of the second type doped layer 103 is too small. Consequently, after the subsequent formation of the source and drain regions, the probability of short-circuiting between the second type doped layer 103 and the source or drain regions increases, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the implantation energy range of the ion implantation process during the formation of the second type doped layer 103 is 50 keV to 500 keV.

[0100] Specifically, along the normal direction of the substrate 100 surface, the distance from the top of the second type doped layer 103 to the top surface of the substrate 100 should not be too large or too small. If the distance from the top of the second type doped layer 103 to the top surface of the substrate 100 is too large, it may lead to an excessively small formation area for the second type doped layer 103, even if the doping depth of the first type doped layer 106 meets the process requirements. Consequently, the second type doped layer 103 may not be able to completely block the diffusion of ions from the source or drain regions of adjacent first transistors with doping types opposite to those of the second type doped layer 103, increasing the probability of leakage between the source or drain regions of adjacent first transistors with doping types opposite to those of the second type doped layer 103. If the distance from the top of the second type doped layer 103 to the top surface of the substrate 100 is too small, it increases the probability of short-circuiting between the second type doped layer 103 and the source or drain regions after the subsequent formation of the source and drain regions, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the distance from the top of the second type doped layer 103 to the top surface of the substrate 100 along the normal direction of the surface of the substrate 100 is 150 nanometers to 800 nanometers.

[0101] It should be noted that the thickness of the second-type doped layer 103 along the normal direction of the substrate 100 surface should not be too large or too small. If the thickness of the second-type doped layer 103 is too large, the probability of the top of the second-type doped layer 103 short-circuiting with the subsequently formed source or drain region increases, thereby affecting the performance of the semiconductor structure. If the thickness of the second-type doped layer 103 is too small, it is easy for the second-type doped layer 103 to fail to completely block the diffusion of ions from the source or drain region of the adjacent first transistor with the opposite doping type to the second-type doped layer 103, increasing the probability of leakage between the source or drain regions of the adjacent first transistor with the opposite doping type to the second-type doped layer 103. Therefore, in this embodiment, the thickness of the second-type doped layer 103 along the normal direction of the substrate 100 surface is 150 nanometers to 800 nanometers.

[0102] In this embodiment, the ions doped in the second type doped layer 103 are N-type ions.

[0103] Specifically, N-type ions include one or more of P ions, As ions, or Sb ions.

[0104] In other embodiments, the ions doped in the second type doped layer may also be P-type ions.

[0105] It should be noted that, in this embodiment, before forming the first type doped layer 106, the method further includes: forming a first mask layer (not shown) on top of the substrate 100 of the third device region, the first mask layer exposing the first device region 100A and the second device region 100B.

[0106] Specifically, during the formation of the first type doped layer 106, the first mask layer protects the third device region, reducing the probability of doped ions in the first type doped layer 106 entering the third device region, thereby affecting the performance of the semiconductor structure.

[0107] In this embodiment, the material of the first mask layer includes photoresist.

[0108] In this embodiment, the process of forming the first mask layer includes an adhesive coating process.

[0109] It should be noted that, in this embodiment, during the formation of the first type doped layer 106, the first device region 100A and the second device region 100B exposed by the first mask layer are doped.

[0110] It should be noted that, in this embodiment, before forming the second type doped layer 103, a second mask layer (not shown) is formed on the top of the substrate 100 of the third device region and on the top of the device isolation structure, and the second mask layer exposes the first device region 100A and the second device region 100B.

[0111] During the formation of the second type doped layer 103, the second mask layer protects the third device region, reducing the probability of doped ions in the second type doped layer 103 entering the third device region, thereby affecting the performance of the semiconductor structure. At the same time, the second mask layer is formed on top of the device isolation structure 102, which protects the top of the device isolation structure 102, reducing the impact on the electrical isolation effect of the device isolation structure 102, thereby improving the performance of the semiconductor structure.

[0112] In this embodiment, the material of the second mask layer includes photoresist.

[0113] In this embodiment, the process of forming the second mask layer includes an adhesive coating process.

[0114] In this embodiment, during the formation of the second type doped layer 103, the first device region 100A and the second device region 100B exposed by the second mask layer are doped.

[0115] In this embodiment, the first mask layer and the second mask layer are different mask layers.

[0116] refer to Figure 6After forming the first type doped layer 106 and the second type doped layer 103, in the first device region 100A and the second device region 100B, the source region 107 and the drain region 108 are formed in the substrate 100 on both sides of the gate structure 101, respectively. The gate structure 101 and the source region 107 and the drain region 108 located on both sides of it constitute the first transistor. The drain region 108 and the source region 107 corresponding to the same first transistor have different doping types.

[0117] Specifically, the drain region 108 and the source region 107 are used as the drain and source of the first transistor, respectively.

[0118] The drain region 108 and the source region 107 have different doping types, thus forming a PIN (P-Intrinsic-N) structure, and then using band-to-band tunneling as the conduction mechanism.

[0119] In this embodiment, in the step of forming source region 107 and drain region 108 in the substrate 100 on both sides of gate structure 101, the doped ions of drain region 108 corresponding to N-type first transistor are N-type ions and the doped ions of source region 107 corresponding to it are P-type ions; the doped ions of drain region 108 corresponding to P-type first transistor are P-type ions and the doped ions of source region 107 corresponding to it are N-type ions.

[0120] Specifically, N-type ions include P ions, As ions, or Sb ions, while P-type ions include B ions, Ga ions, or In ions.

[0121] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate comprising a first device region and a second device region; A first transistor is located on the substrate of the first device region and the second device region, respectively. The first transistor includes a gate structure and a source region and a drain region located on both sides of the gate structure, respectively. The doping types of the source region and the drain region corresponding to the same first transistor are different. A device isolation structure is located in the substrate at the junction of the adjacent first device region and second device region; A first type doped layer is located in the substrate on the side of the device isolation structure and in the substrate at the bottom of the device isolation structure. Along the normal direction of the substrate surface, the doping concentration of the first type doped layer increases sequentially from bottom to top. The first type doped layer at the bottom of the device isolation structure is in contact with the device isolation structure. The top of the first type doped layer on the side of the device isolation structure is lower than the bottom of the device isolation structure. The first type doped layer on the side of the device isolation structure is connected to the first type doped layer at the bottom of the device isolation structure. The second type doped layer is located in the substrate on top of the first type doped layer. Along the normal direction of the substrate surface, the doping concentration of the second type doped layer decreases from bottom to top. The second type doped layer is in contact with the top of the first type doped layer, and the device isolation structure covers part of the sidewall of the second type doped layer. The doping types of the first type doped layer and the second type doped layer are different.

2. The semiconductor structure as described in claim 1, characterized in that, The concentration of doped ions in the first type of doped layer is 1E12 atom / cm³. 3 Up to 1E14atom / cm 3 ; The concentration of doped ions in the second type doped layer is 1E12 atom / cm³. 3 Up to 1E14atom / cm 3 .

3. The semiconductor structure as described in claim 1, characterized in that, Along the normal direction of the substrate surface, the distance from the top of the second type doped layer to the bottom of the source or drain region is 150 nanometers to 800 nanometers.

4. The semiconductor structure as described in claim 1, characterized in that, Along the normal direction of the substrate surface, the thickness of the first type doped layer is 40 nanometers to 300 nanometers; Along the normal direction of the substrate surface, the thickness of the second type doped layer is 150 nanometers to 800 nanometers.

5. The semiconductor structure as described in claim 1, characterized in that, The first type of doped layer contains P-type ions; the second type of doped layer contains N-type ions. or, The first type of doped layer contains N-type ions; the second type of doped layer contains P-type ions.

6. The semiconductor structure as described in claim 1, characterized in that, The first transistor located in either the first device region or the second device region is an N-type transistor, and the other first transistor is a P-type transistor; wherein, the doped ions in the drain region of the N-type transistor are N-type ions, the doped ions in the source region of the N-type transistor are P-type ions, the doped ions in the drain region of the P-type transistor are P-type ions, and the doped ions in the source region of the P-type transistor are N-type ions.

7. The semiconductor structure as described in claim 1, characterized in that, The first transistor includes a tunneling field-effect transistor.

8. The semiconductor structure as described in claim 1 or 7, characterized in that, The substrate also includes a third device region; The semiconductor structure further includes a second transistor located on the substrate of the third device region, the second transistor comprising a metal-oxide-semiconductor field-effect transistor.

9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first device region and a second device region for forming a first transistor, a gate structure is formed on the substrate of the first device region and the second device region, and a device isolation structure is formed in the substrate at the junction of adjacent first device regions and second device regions; A first type doped layer and a second type doped layer located on top of and in contact with the top of the first type doped layer are formed in the substrate on the side of the device isolation structure and in the substrate at the bottom of the device isolation structure. Along the normal direction of the substrate surface, the doping concentration of the first type doped layer increases sequentially from bottom to top, and the doping concentration of the second type doped layer decreases sequentially from bottom to top. The first type doped layer located at the bottom of the device isolation structure is in contact with the device isolation structure. The top of the first type doped layer located on the side of the device isolation structure is lower than the bottom of the device isolation structure, and the first type doped layer located on the side of the device isolation structure is connected to the first type doped layer located at the bottom of the device isolation structure. The device isolation structure covers part of the sidewall of the second type doped layer. The first type doped layer and the second type doped layer have different doping types. After forming the first type doped layer and the second type doped layer, a source region and a drain region are formed in the substrate on both sides of the gate structure in the first device region and the second device region, respectively. The gate structure and the source and drain regions located on both sides thereon constitute a first transistor. The doping types of the drain and source regions corresponding to the same first transistor are different.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The steps of forming the first type doped layer and the second type doped layer include: forming a first type doped layer in the substrate on the side of the device isolation structure and in the substrate at the bottom of the device isolation structure, wherein the top of the first type doped layer on the side of the device isolation structure is lower than the bottom of the device isolation structure; after forming the first type doped layer, forming a second type doped layer on top of the first type doped layer on the side of the device isolation structure, wherein the device isolation structure covers a portion of the sidewall of the second type doped layer.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process for forming the first type doped layer and the second type doped layer includes ion implantation.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, During the formation of the first type of doped layer, the parameters of the ion implantation process include: a doping dose range of 1E12 atom / cm². 3 Up to 1E14atom / cm 3 The injection energy range is 50 keV to 500 keV. During the formation of the second type doped layer, the parameters of the ion implantation process include: a doping dose range of 1E12 atom / cm². 3 Up to 1E14atom / cm 3 The injected energy range is 50 keV to 500 keV.

13. The method for forming a semiconductor structure as described in claim 9, characterized in that, Along the normal direction of the substrate surface, the distance from the top of the second type doped layer to the top surface of the substrate is 150 nanometers to 800 nanometers.

14. The method for forming a semiconductor structure as described in claim 9, characterized in that, Along the normal direction of the substrate surface, the thickness of the first type doped layer is 40 nanometers to 300 nanometers; Along the normal direction of the substrate surface, the thickness of the second type doped layer is 150 nanometers to 800 nanometers.

15. The method for forming a semiconductor structure as described in claim 9, characterized in that, The first type of doped layer contains P-type ions; the second type of doped layer contains N-type ions. or, The first type of doped layer contains N-type ions; the second type of doped layer contains P-type ions.

16. The method for forming a semiconductor structure as described in claim 9, characterized in that, Either the first device region or the second device region is used to form an N-type first transistor, and the other is used to form a P-type first transistor; In the step of forming source and drain regions in the substrates on both sides of the gate structure, the doped ions of the drain region corresponding to the N-type first transistor are N-type ions and the doped ions of the source region corresponding to the N-type first transistor are P-type ions; the doped ions of the drain region corresponding to the P-type first transistor are P-type ions and the doped ions of the source region corresponding to the P-type first transistor are N-type ions.

17. The method for forming a semiconductor structure as described in claim 9, characterized in that, The first transistor includes a tunneling field-effect transistor.

18. The method for forming a semiconductor structure as described in claim 9 or 17, characterized in that, In the step of providing a substrate, the substrate further includes a third device region for forming a second transistor, the second transistor including a metal-oxide-semiconductor field-effect transistor; Before forming the first type of doped layer, the method further includes: forming a first mask layer on top of the substrate of the third device region, the first mask layer exposing the first device region and the second device region; During the formation of the first type of doped layer, the first device region and the second device region exposed by the first mask layer are doped. Before forming the second type doped layer, the method further includes: forming a second mask layer on top of the substrate of the third device region and on top of the device isolation structure, wherein the second mask layer exposes the first device region and the second device region; During the formation of the second type doped layer, the first device region and the second device region exposed by the second mask layer are doped.

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