Hemt device structure and method for suppressing current collapse
By epitaxially layering an n++ type heavily doped layer on a P-type semiconductor, avoiding etching and ion implantation, and directly pulling down the 2DEG level, the current collapse problem of HEMT devices is solved, and a high-performance HEMT device structure is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU INST OF NANO TECH & NANO BIONICS CHINESE ACEDEMY OF SCI
- Filing Date
- 2023-12-13
- Publication Date
- 2026-07-24
AI Technical Summary
In the fabrication of p-gate enhancement-mode GaN high electron mobility transistors (HEMTs), the current collapse problem caused by channel etching and high-resistance passivation, including surface damage from etching and ion implantation damage, is difficult to control, leading to a decrease in 2DEG density and deterioration of electrical performance.
By directly epitaxially growing an n++ type heavily doped layer on a P-type semiconductor, the conduction band of the carrier channel is pulled down to below the Fermi level, avoiding etching and ion implantation. Through special gate, source, and drain designs, the source and drain are isolated from the n++ layer, avoiding an increase in surface state density and forming an enhancement-mode HEMT device.
It effectively suppresses current collapse, improves the dynamic characteristics and performance of the device, and enhances the current stability and reliability of HEMT devices.
Smart Images
Figure CN117673139B_ABST
Abstract
Description
Technical Field
[0001] This invention specifically relates to a HEMT device structure and method for suppressing current collapse, belonging to the field of semiconductor device technology. Background Technology
[0002] Currently, the two main techniques for realizing p-gate enhancement-mode GaN high electron mobility transistors (HEMTs) are channel etching and high-resistivity passivation. Etching or passivating the p-type (Al) GaN in the channel region creates a high-resistivity layer, thereby reproducing the two-dimensional electron gas (2DEG). Both techniques lead to a certain degree of current collapse in the device. First, the surface damage caused by etching introduces a large number of defect states. Under drain operating voltage, gate electrons injected into the (Al) GaN are trapped by surface traps, forming a negative charge region and depleting the 2DEG, the so-called virtual gate model. Second, the implantation damage caused by annealing and passivating the p-type GaN in the channel region after ion implantation, the difficulty in controlling the implantation depth, and the diffusion into the 2DEG due to annealing all contribute to current collapse.
[0003] The hole injection structure in CN 115842041 A can be close enough to the gate to allow for more complete surface trap recombination. At the same time, it avoids long-distance surface charge transport, resulting in faster surface charge transfer and improved surface trap recombination efficiency to achieve the best hole injection effect. However, etching damage introduces a large number of surface states, which form a negative charge region during charging and discharging, depleting the underlying 2DEG and causing current collapse. Moreover, the etching rate is difficult to control, and both over-etching and under-etching will lead to a decrease in 2DEG density. Passivation ion implantation damage and ion diffusion into the channel will both lead to the deterioration of 2DEG electrical performance. Summary of the Invention
[0004] The main objective of this invention is to provide a HEMT device structure and method for suppressing current collapse, which achieves 2DEG reproducibility without damaging the channel region, obtains extremely low surface states, improves the dynamic characteristics of the device, and thus overcomes the shortcomings of the prior art.
[0005] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:
[0006] This invention provides a HEMT device structure for suppressing current collapse, characterized in that it comprises:
[0007] The epitaxial structure includes a heterojunction, a P-type semiconductor layer and an n++ type heavily doped layer arranged sequentially along a first direction. The heterojunction has a carrier channel, and the conduction band of the carrier channel is pulled down to below the Fermi level by the n++ type heavily doped layer.
[0008] In addition, there is a source, a drain, and a gate, wherein the source and the drain are electrically connected to the heterojunction, the gate is disposed on the P-type semiconductor layer, and the gate is disposed between the source and the drain along a second direction, wherein the second direction and the first direction are intersected.
[0009] In a more specific implementation, the n++ type heavily doped layer is disposed between the gate and the source, and between the gate and the drain.
[0010] Furthermore, the P-type semiconductor layer includes a first portion, a second portion, and a third portion sequentially disposed between the source and the drain along the second direction, the gate is disposed on the second portion, and the n++ type heavily doped layer is disposed on the first portion and the third portion. In the second direction, the spacing between the first portion and the source and the spacing between the third portion and the drain are equal.
[0011] Furthermore, the gate region of the epitaxial structure has a trench structure, the bottom of the trench structure is located in the P-type semiconductor layer, the opening of the trench structure is located in the n++ type heavily doped layer, and the gate is disposed in the trench structure.
[0012] Furthermore, the n++ type heavily doped layer is isolated from the gate, the source, and the drain by a passivation layer.
[0013] In another more specific embodiment, the n++ type heavily doped layer is disposed between the gate and the source or the gate and the drain.
[0014] Furthermore, the gate is electrically connected to the n++ type heavily doped layer.
[0015] Furthermore, in the second direction, the spacing between the source and the P-type semiconductor layer is different from the spacing between the drain and the P-type semiconductor layer.
[0016] Furthermore, in the second direction, the source and the gate are located on the same side of the n++ type heavily doped layer, and the distance between the source and the P-type semiconductor layer is greater than the distance between the drain and the P-type semiconductor layer.
[0017] Furthermore, the doping concentration of the n++ type heavily doped layer is 5E18 / cm². 3 above.
[0018] Furthermore, the thickness of the n++ type heavily doped layer is adjusted according to the actual doping concentration, and the thickness of the n++ type heavily doped layer is above 70nm.
[0019] Another aspect of the present invention provides a method for suppressing current collapse in HEMT devices, comprising:
[0020] An epitaxial structure for a HEMT device is fabricated, the epitaxial structure comprising a heterojunction, a P-type semiconductor layer and an n++ type heavily doped layer arranged sequentially along a first direction, wherein the heterojunction has a carrier channel, and the conduction band of the carrier channel is pulled down to below the Fermi level by the n++ type heavily doped layer;
[0021] In addition, a source, a drain, and a gate are prepared, and the source and the drain are electrically connected to the heterojunction. The gate is disposed on the P-type semiconductor layer and is disposed between the source and the drain along a second direction, wherein the second direction and the first direction are intersected.
[0022] In a more specific implementation, the method specifically includes: forming a trench structure within the epitaxial structure, such that the bottom of the trench structure is located in the P-type semiconductor layer and the opening of the trench structure is located in the n++ type heavily doped layer, and then fabricating the gate within the trench structure.
[0023] In another more specific embodiment, the method specifically includes: removing a portion of the P-type semiconductor layer located between the gate region and the source region and drain region, removing a portion of the n++ type heavily doped layer and exposing the P-type semiconductor layer, and fabricating the gate on the exposed P-type semiconductor layer, wherein the n++ type heavily doped layer is disposed between the gate and the source or the drain along the second direction.
[0024] Furthermore, in the second direction, the source and the gate are located on the same side of the n++ type heavily doped layer, and the distance between the source and the P-type semiconductor layer is greater than the distance between the drain and the P-type semiconductor layer.
[0025] Furthermore, the doping concentration of the n++ type heavily doped layer is 5E18 / cm². 3 above.
[0026] Furthermore, the thickness of the n++ type heavily doped layer is adjusted according to the actual doping concentration, and the thickness of the n++ type heavily doped layer is above 70nm.
[0027] Compared with the prior art, the advantages of the present invention include:
[0028] This invention directly epitaxially grows an n++ type heavily doped layer on a P-type semiconductor, directly pulling the two-dimensional potential well energy level down to below the Fermi level. The 2DEG can be reproduced without etching the P-type semiconductor in the non-gate region, effectively reducing the surface state density near the gate and improving the dynamic characteristics of the device, thereby obtaining a high-performance HEMT device.
[0029] This invention avoids additional semiconductor manufacturing processes such as etching and ion implantation near the gate, thus avoiding the introduction of a large number of surface states and improving the dynamic characteristics of the device. Attached Figure Description
[0030] Figures 1-7 These are schematic diagrams of the device structure formed in each step of the fabrication process of the HEMT device provided in Embodiment 1 of the present invention;
[0031] Figure 8 and Figure 9 The results are simulation test results of a HEMT device provided in Embodiment 1 of the present invention;
[0032] Figure 10 This is a schematic diagram of the structure of a HEMT device provided in Embodiment 2 of the present invention. Detailed Implementation
[0033] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate the technical solution, its implementation process and principle in conjunction with the accompanying drawings and specific embodiments. Unless otherwise specified, the semiconductor epitaxial growth process and equipment, photolithography and etching process and equipment, metal deposition process and equipment, and self-alignment process used in the embodiments of this invention are all known to those skilled in the art, and are not specifically limited or described here.
[0034] Example 1
[0035] An HEMT device includes an epitaxial structure and a source, drain, and gate that cooperate with the epitaxial structure. The epitaxial structure includes a channel layer, a barrier layer, a P-type semiconductor layer, and an n++ type heavily doped layer sequentially stacked on a substrate along a first direction. A carrier channel (e.g., two-dimensional electron gas, 2EDG) is formed at the interface between the channel layer and the barrier layer. The gate region of the n++ type heavily doped layer has a trench structure, with the bottom of the trench structure located on the P-type semiconductor layer. The source and drain are disposed on the barrier layer and electrically connected via the carrier channel. The gate is disposed within the trench structure and is positioned between the source and the drain along a second direction. The conduction band of the carrier channel is pulled down below the Fermi level by the n++ type heavily doped layer.
[0036] Specifically, the second direction and the first direction are intersected. The first direction can be the longitudinal direction of the HEMT device, and the second direction can be the transverse direction of the HEMT device.
[0037] Specifically, the n++ type heavily doped layer is disposed between the gate and the source, and between the gate and the drain, and the n++ type heavily doped layer is isolated from the gate, the source, and the drain by a passivation layer.
[0038] In this embodiment, a method for fabricating a HEMT device includes the following steps:
[0039] 1) A channel layer, a barrier layer, a P-type semiconductor layer, and an n++ type heavily doped layer are sequentially epitaxially grown on a substrate along a first direction to form the epitaxial structure of a HEMT device, such as... Figure 1 As shown, the channel layer and the barrier layer form a heterojunction, and a carrier channel (e.g., a two-dimensional electron gas, 2DEG) is formed at the interface between the channel layer and the barrier layer.
[0040] Specifically, the substrate can be a Si substrate, a SiC substrate, a sapphire substrate, a GaN substrate, etc.
[0041] Specifically, the channel layer can be a GaN layer, the barrier layer can be an AlGaN layer, the p-type semiconductor layer can be a p-type GaN layer, the n++ type heavily doped layer can be an n++ type GaN layer, and the n-type doping concentration of the n++ type GaN layer is 5E18 / cm³. 3 above.
[0042] 2) Etching removes the n++ type heavily doped layer located in the gate region, thereby forming a trench structure. The bottom of the trench structure is located in the P-type semiconductor layer, such as... Figure 2 As shown, a self-aligned process is used, where a mask is directly deposited on the surface of the epitaxial structure, which also serves as a surface protection layer, followed by full-area etching, such as... Figure 3 As shown, after etching the entire surface, a gate is formed within the trench structure, depleting the underlying 2DEG to create an enhancement mode, as shown. Figure 4 As shown.
[0043] Specifically, a mask can be deposited on the non-gate region of the n++ type heavily doped layer surface to etch the n++ type heavily doped layer exposed in the gate region until the P-type semiconductor layer is exposed.
[0044] Specifically, metal deposition processes can be used to fabricate the gate, but no specific limitations are made here.
[0045] 3) Etching removes the n++ type heavily doped layer and p-type semiconductor layer located in the source and drain regions, such as... Figure 5 As shown, a self-aligned process is then used to form sidewall passivation in the source and drain regions to isolate the source and drain from the n++ type heavily doped layer, as shown. Figure 6 As shown, source and drain electrodes are formed in the source and drain regions respectively, and the source and drain electrodes are electrically connected via 2DEG to form an enhancement-mode HEMT device, as shown. Figure 7 As shown.
[0046] The simulation test results of the HEMT device in this embodiment are as follows: Figure 8 and Figure 9 As shown, from Figure 8 It can be seen that, under the influence of the n++ type heavily doped layer, the conduction band of the non-gate region of the device is pulled back below the Fermi level. Figure 9 As can be seen, the 2DEG in the non-gate region is reproduced, and the 2DEG under the gate is depleted, thus realizing an enhancement-mode HEMT.
[0047] Example 2
[0048] Please see Figure 10 A HEMT device includes an epitaxial structure and a source, drain, and gate that cooperate with the epitaxial structure. The epitaxial structure includes a channel layer, a barrier layer, a P-type semiconductor layer, and an n++ type heavily doped layer sequentially stacked on a substrate along a first direction. A carrier channel (e.g., two-dimensional electron gas, 2EDG) is formed at the interface between the channel layer and the barrier layer. The P-type semiconductor layer is located in the gate region and between the gate region and the drain region. The n++ type heavily doped layer is located between the gate region and the drain region. The source and drain are disposed on the barrier layer, and the gate is disposed on the P-type semiconductor layer and is electrically in contact with the n++ type heavily doped layer. In a second direction, the distance between the source and the P-type semiconductor layer and the n++ type heavily doped layer is greater than the distance between the drain and the P-type semiconductor layer and the n++ type heavily doped layer.
[0049] This invention avoids additional semiconductor manufacturing processes such as etching and ion implantation near the gate, thus avoiding the introduction of a large number of surface states and improving the dynamic characteristics of the device.
[0050] This invention directly epitaxially grows an n++ type heavily doped layer on a P-type semiconductor, directly pulling the two-dimensional well level below the Fermi level. The 2DEG can be reproduced without etching the non-gate region of the P-type semiconductor, effectively reducing the surface state density near the gate and improving the dynamic characteristics of the device, thus obtaining a high-performance HEMT device. The special design of the gate, source, and drain electrodes in this invention isolates the source and drain from direct contact with the n++ layer, preventing leakage current. The insulating dielectric of the gate sidewall effectively prevents gate electron injection from being assisted by defects to form a virtual gate structure, thus preventing current collapse and further improving the dynamic performance of the device.
[0051] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.
Claims
1. A HEMT device structure for suppressing current collapse, characterized in that, include: The epitaxial structure includes a heterojunction, a P-type semiconductor layer and an n++ type heavily doped layer arranged sequentially along a first direction. The heterojunction has a carrier channel, and the conduction band of the carrier channel is pulled down to below the Fermi level by the n++ type heavily doped layer. In addition, there is a source, a drain, and a gate, wherein the source and the drain are electrically connected to the heterojunction, the gate is disposed on the P-type semiconductor layer and in direct contact with the P-type semiconductor layer, and the gate is disposed between the source and the drain along a second direction, wherein the second direction and the first direction are intersected.
2. The HEMT device structure for suppressing current collapse according to claim 1, characterized in that: The n++ type heavily doped layer is disposed between the gate and the source, and between the gate and the drain.
3. The HEMT device structure for suppressing current collapse according to claim 1 or 2, characterized in that: The P-type semiconductor layer includes a first portion, a second portion, and a third portion sequentially disposed between the source and the drain along the second direction. The gate is disposed on the second portion, and the n++ type heavily doped layer is disposed on the first portion and the third portion. In the second direction, the spacing between the first portion and the source and the spacing between the third portion and the drain are equal.
4. The HEMT device structure for suppressing current collapse according to claim 2, characterized in that: The gate region of the epitaxial structure has a trench structure, the bottom of the trench structure is located in the P-type semiconductor layer, the opening of the trench structure is located in the n++ type heavily doped layer, the trench structure is formed by photolithography and ICP etching, and the gate is disposed in the trench structure.
5. The HEMT device structure for suppressing current collapse according to claim 4, characterized in that: The n++ type heavily doped layer is isolated from the gate, the source, and the drain by a passivation layer.
6. The HEMT device structure for suppressing current collapse according to claim 1, characterized in that: The n++ type heavily doped layer is disposed between the gate and the source or between the gate and the drain.
7. The HEMT device structure for suppressing current collapse according to claim 6, characterized in that: The gate is electrically connected to the n++ type heavily doped layer.
8. The HEMT device structure for suppressing current collapse according to claim 6, characterized in that: In the second direction, the spacing between the source and the P-type semiconductor layer is different from the spacing between the drain and the P-type semiconductor layer.
9. The HEMT device structure for suppressing current collapse according to claim 8, characterized in that: In the second direction, the source and the gate are located on the same side of the n++ type heavily doped layer, and the distance between the source and the P-type semiconductor layer is greater than the distance between the drain and the P-type semiconductor layer.
10. The HEMT device structure for suppressing current collapse according to claim 1, characterized in that: The doping concentration of the n++ type heavily doped layer is 5E18 / cm². 3 above.
11. The HEMT device structure for suppressing current collapse according to claim 1, characterized in that: The thickness of the n++ type heavily doped layer is above 70 nm.
12. A method for suppressing current collapse in HEMT devices, characterized in that, include: An epitaxial structure for a HEMT device is fabricated, the epitaxial structure comprising a heterojunction, a P-type semiconductor layer and an n++ type heavily doped layer arranged sequentially along a first direction, wherein the heterojunction has a carrier channel, and the conduction band of the carrier channel is pulled down to below the Fermi level by the n++ type heavily doped layer; In addition, a source, a drain, and a gate are prepared, and the source and the drain are electrically connected to the heterojunction. The gate is disposed on the P-type semiconductor layer and is in direct contact with the P-type semiconductor layer. The gate is disposed between the source and the drain along a second direction, and the second direction and the first direction are intersected.
13. The method according to claim 12, characterized in that, Specifically, it includes: A trench structure is formed within the epitaxial structure, with the bottom of the trench structure located in the P-type semiconductor layer and the opening located in the n++ type heavily doped layer. The gate is then fabricated within the trench structure. Alternatively, a portion of the P-type semiconductor layer located between the gate region and the source and drain regions may be removed, and a portion of the n++ type heavily doped layer may be removed and the P-type semiconductor layer exposed. The gate may then be fabricated on the exposed P-type semiconductor layer, wherein the n++ type heavily doped layer is disposed between the gate and the source or the drain along the second direction.
14. The method according to claim 13, characterized in that: In the second direction, the source and the gate are located on the same side of the n++ type heavily doped layer, and the distance between the source and the P-type semiconductor layer is greater than the distance between the drain and the P-type semiconductor layer.
15. The method according to claim 12, characterized in that: The doping concentration of the n++ type heavily doped layer is 5E18 / cm². 3 above.
16. The method according to claim 12, characterized in that: The thickness of the n++ type heavily doped layer is above 70 nm.