Shift register unit, gate drive circuit, and gate drive method

Abstract

A shift register unit comprises a sensing control circuit (1) connected with a sensing signal input end (INPUT2), a random signal input end (OE), and a sensing control node (H), and configured to write a signal provided by the sensing signal input end (INPUT2) to the sensing control node (H) in response to a control of an effective level signal provided by the random signal input end (OE); a first sensing input circuit (2) connected with a clock control signal input end (CLKA), the sensing control node (H), and a first pull-up node (PU1), and configured to write a signal provided by the clock control signal input end (CLKA) to the first pull-up node (PU1) in response to a control of an effective level signal at the sensing control node (H); and a first driving output circuit (5) connected with the first pull-up node (PU1), a first driving clock signal input end (CLKE), and a first driving signal output end (OUT2), and configured to write a signal provided by the first driving clock signal input end (CLKE) to the first driving signal output end (OUT2) in response to a control of an effective level signal at the first pull-up node (PU1).

Description

Technical Field

[0001] This invention relates to the field of display, and in particular to a shift register unit, a gate driving circuit, and a gate driving method. Background Technology

[0002] The application of Active Matrix Organic Light Emitting Diode (AMOLED) panels is becoming increasingly widespread. The pixel display device of AMOLED is Organic Light-Emitting Diode (OLED). AMOLED emits light by driving thin-film transistors to generate a driving current in a saturated state, which drives the light-emitting device to emit light. Summary of the Invention

[0003] In a first aspect, embodiments of this disclosure provide a shift register unit, wherein:

[0004] A sensing control circuit, connected to a sensing signal input terminal, a random signal input terminal, and a sensing control node, is configured to write the signal provided by the sensing signal input terminal to the sensing control node in response to a valid level signal provided by the random signal input terminal.

[0005] A first sensing input circuit is connected to a clock control signal input terminal, the sensing control node, and a first pull-up node. The first sensing input circuit is configured to write the signal provided by the clock control signal input terminal to the first pull-up node only in response to the control of a valid level signal at the sensing control node.

[0006] The first drive output circuit is connected to the first pull-up node, the first drive clock signal input terminal, and the first drive signal output terminal, and is configured to write the signal provided by the first drive clock signal input terminal to the first drive signal output terminal in response to the control of the effective level signal at the first pull-up node.

[0007] In some embodiments, the first sensing input circuit includes: a second transistor;

[0008] The control electrode of the second transistor is connected to the sensing control node, the first electrode of the second transistor is connected to the clock control signal input terminal, and the second electrode of the second transistor is connected to the first pull-up node.

[0009] In some embodiments, the shift register unit further includes:

[0010] A first display input circuit is connected to a display signal input terminal, a third power supply terminal, and a first pull-up node, and is configured to write the valid level signal provided by the third power supply terminal to the first pull-up node in response to the control of the valid level signal provided by the display signal input terminal.

[0011] The second drive output circuit is connected to the first pull-up node, the second drive clock signal input terminal, and the second drive signal output terminal, and is configured to write the signal provided by the second drive clock signal input terminal to the second drive signal output terminal in response to the control of the effective level signal at the first pull-up node.

[0012] The first cascaded output circuit is connected to the first pull-up node, the first cascaded clock signal input terminal, and the first cascaded signal output terminal, and is configured to write the signal provided by the first cascaded clock signal input terminal to the first cascaded signal output terminal in response to the control of the effective level signal at the first pull-up node.

[0013] In some embodiments, the shift register unit further includes:

[0014] A first voltage control circuit is connected to a third power supply terminal, a first pull-up node, and a first voltage control node. The first voltage control circuit is configured to write the effective level signal provided by the third power supply terminal to the first voltage control node in response to the control of the effective level signal at the first pull-up node.

[0015] The shift register unit further includes: a first sensing input leakage protection circuit, wherein the first sensing input circuit is connected to the clock control signal input terminal through the first sensing input leakage protection circuit, the first sensing input circuit and the first sensing input leakage protection circuit are connected to the first sensing input leakage protection node, and the first sensing input leakage protection node is connected to the first voltage control node;

[0016] The first sensing input leakage protection circuit is connected to the sensing control node. The first sensing input leakage protection circuit is configured to form a path between the first sensing input leakage protection node and the clock control signal input terminal in response to the control of an effective level signal at the sensing control node, and to disconnect the first sensing input leakage protection node from the clock control signal input terminal in response to the control of an ineffective level signal at the sensing control node.

[0017] In some embodiments, the first voltage control circuit includes: a twentieth transistor;

[0018] The control electrode of the twentieth transistor is connected to the first pull-up node, the first electrode of the twentieth transistor is connected to the third power supply terminal, and the second electrode of the twentieth transistor is connected to the first voltage control node.

[0019] The first sensing input leakage protection circuit includes: a third transistor;

[0020] The control electrode of the third transistor is connected to the sensing control node, the first electrode of the third transistor is connected to the clock control signal input terminal, and the second electrode of the third transistor is connected to the first sensing input leakage protection node.

[0021] In some embodiments, the shift register unit further includes: a first sensing input leakage protection circuit, wherein the first sensing input circuit is connected to a clock control signal input terminal through the first sensing input leakage protection circuit, and the first sensing input circuit and the first sensing input leakage protection circuit are connected to a first sensing input leakage protection node;

[0022] The first sensing input leakage protection circuit is connected to a preset input control signal input terminal and a first cascaded signal output terminal. The first sensing input leakage protection circuit is configured to form a path between the first sensing input leakage protection node and the clock control signal input terminal in response to the control of an effective level signal provided by the preset input control signal input terminal, and to disconnect the circuit between the first sensing input leakage protection node and the clock control signal input terminal in response to the control of an ineffective level signal provided by the preset input control signal input terminal. When the circuit between the first sensing input leakage protection node and the clock control signal input terminal is disconnected, the effective level signal is written to the first sensing input leakage protection node in response to the control of an effective level signal provided by the first cascaded signal output terminal.

[0023] In some embodiments, the first sensing input leakage protection circuit includes: a third transistor and a fourth transistor;

[0024] The control electrode of the third transistor is connected to the preset input control signal input terminal, the first electrode of the third transistor is connected to the clock control signal input terminal, and the second electrode of the third transistor is connected to the first sensing input leakage protection node.

[0025] The control electrode and the first electrode of the fourth transistor are both connected to the first cascaded signal output terminal, and the second electrode of the fourth transistor is connected to the first sensing input leakage protection node.

[0026] In some embodiments, the shift register unit further includes:

[0027] A first global reset circuit is connected to a global reset signal input terminal, a second power supply terminal, and a first pull-up node, and is configured to write an invalid level signal provided by the second power supply terminal to the first pull-up node in response to the control of an effective level signal provided by the global reset signal input terminal.

[0028] A first display reset circuit is connected to a display reset signal input terminal, a second power supply terminal, and a first pull-up node, and is configured to write an invalid level signal provided by the second power supply terminal to the first pull-up node in response to the control of an effective level signal provided by the display reset signal input terminal.

[0029] The first pull-down control circuit is connected to the second power supply terminal, the fifth power supply terminal, the first pull-up node, and the first pull-down node, and is configured to write a voltage that is opposite to the voltage at the first pull-up node to the first pull-down node.

[0030] The first pull-up noise reduction circuit is connected to the second power supply terminal, the first pull-up node and the first pull-down node, and is configured to write the ineffective level signal provided by the second power supply terminal to the first pull-up node in response to the control of the effective level signal at the first pull-down node.

[0031] The first cascaded output circuit is also connected to the first pull-down node and the second power supply terminal, and is configured to write the ineffective level signal provided by the second power supply terminal to the first cascaded signal output terminal in response to the control of the effective level signal at the first pull-down node.

[0032] The first drive output circuit is also connected to the first pull-down node and the fourth power supply terminal. The first drive output circuit is also configured to write the inactive level signal provided by the fourth power supply terminal to the first drive signal output terminal in response to the control of the active level signal at the first pull-down node.

[0033] The second drive output circuit is also connected to the first pull-down node and the fourth power supply terminal. The second drive output circuit is also configured to write an invalid level signal provided by the fourth power supply terminal to the second drive signal output terminal in response to the control of an effective level signal at the first pull-down node.

[0034] In some embodiments, the shift register unit further includes:

[0035] A first voltage control circuit is connected to a third power supply terminal, a first pull-up node, and a first voltage control node. The first voltage control circuit is configured to write the effective level signal provided by the third power supply terminal to the first voltage control node in response to the control of the effective level signal at the first pull-up node.

[0036] The shift register unit further includes at least one of a first leakage protection circuit, a second leakage protection circuit, and a third leakage protection circuit;

[0037] The first global reset circuit is connected to the second power supply terminal through the first leakage protection circuit. The first global reset circuit and the first leakage protection circuit are connected to the first leakage protection node. The first leakage protection node is connected to the first voltage control node. The first leakage protection circuit is connected to the global reset signal input terminal. The first leakage protection circuit is configured to form a path between the first leakage protection node and the second power supply terminal in response to the control of the valid level signal provided by the global reset signal input terminal, and to disconnect the circuit between the first leakage protection node and the second power supply terminal in response to the control of the invalid level signal provided by the global reset signal input terminal.

[0038] The first display reset circuit is connected to the second power supply terminal through the second leakage protection circuit. The first display reset circuit and the second leakage protection circuit are connected to the second leakage protection node. The second leakage protection node is connected to the first voltage control node. The second leakage protection circuit is connected to the display reset signal input terminal. The second leakage protection circuit is configured to form a path between the second leakage protection node and the second power supply terminal in response to the control of the valid level signal provided by the display reset signal input terminal, and to disconnect the circuit between the second leakage protection node and the second power supply terminal in response to the control of the invalid level signal provided by the display reset signal input terminal.

[0039] The first pull-up noise reduction circuit is connected to the second power supply terminal through the third leakage protection circuit. The first pull-up noise reduction circuit and the third leakage protection circuit are connected to the third leakage protection node. The third leakage protection node is connected to the first voltage control node. The third leakage protection circuit is connected to the first pull-down node. The third leakage protection circuit is configured to form a path between the third leakage protection node and the second power supply terminal in response to the control of an effective level signal at the first pull-down node, and to disconnect the circuit between the third leakage protection node and the second power supply terminal in response to the control of an ineffective level signal at the first pull-down node.

[0040] In some embodiments, the shift register unit further includes:

[0041] A first sensing reset circuit is connected to a sensing reset signal input terminal, the sensing control node, the first pull-up node, and a second power supply terminal. It is configured to write an invalid level signal provided by the second power supply terminal to the first pull-up node in response to the control of the signal provided by the sensing reset signal input terminal and the valid level signal at the sensing control node.

[0042] In some embodiments, the first sensing reset circuit includes:

[0043] A first sensing reset control circuit is connected to the sensing reset signal input terminal, the first sensing reset control node, the sensing control node, and the second power supply terminal. It is configured to write the valid level signal at the sensing control node to the first sensing reset control node in response to the control of the inactive level signal provided by the sensing reset signal input terminal and the valid level signal at the sensing control node.

[0044] A first switching circuit, connected to the first sensing reset control node, the first pull-up node, and the second power supply terminal, is configured to form a path between the second power supply terminal and the first pull-up node in response to a valid level signal at the first sensing reset control node, and to form an open circuit between the second power supply terminal and the first pull-up node in response to an invalid level signal at the first sensing reset control node.

[0045] In some embodiments, the first sensing reset control circuit includes a seventy-first transistor and a seventy-second transistor, and the first switching circuit includes a seventy-third transistor.

[0046] The control electrode and the first electrode of the seventy-first transistor are both connected to the sensing control node, and the second electrode of the seventy-first transistor is connected to the first sensing reset control node;

[0047] The control electrode of the seventy-second transistor is connected to the sensing reset signal input terminal, the first electrode of the seventy-second transistor is connected to the first sensing reset control node, and the second electrode of the seventy-second transistor is connected to the second power supply terminal.

[0048] The control electrode of the seventy-third transistor is connected to the first sensing reset control node, the first electrode of the seventy-third transistor is connected to the first pull-up node, and the second electrode of the seventy-third transistor is connected to the second power supply terminal.

[0049] In some embodiments, the shift register unit further includes:

[0050] A first voltage control circuit is connected to a third power supply terminal, a first pull-up node, and a first voltage control node. The first voltage control circuit is configured to write the effective level signal provided by the third power supply terminal to the first voltage control node in response to the control of the effective level signal at the first pull-up node.

[0051] The shift register unit further includes: a first sensing reset leakage protection circuit, the first switching circuit being connected to the second power supply terminal through the first sensing reset leakage protection circuit, the first switching circuit and the first sensing reset leakage protection circuit being connected to the first sensing reset leakage protection node, and the first sensing reset leakage protection node being connected to the first voltage control node;

[0052] The first sensing reset leakage protection circuit is connected to the first sensing reset control node. The first sensing reset leakage protection circuit is configured to form a path between the first sensing reset leakage protection node and the second power supply terminal in response to the control of an effective level signal at the first sensing reset control node, and to form an open circuit between the first sensing reset leakage protection node and the second power supply terminal in response to the control of an ineffective level signal at the first sensing reset control node.

[0053] In some embodiments, the first voltage control circuit includes: a twentieth transistor;

[0054] The control electrode of the twentieth transistor is connected to the first pull-up node, the first electrode of the twentieth transistor is connected to the third power supply terminal, and the second electrode of the twentieth transistor is connected to the first voltage control node.

[0055] The first sensing reset leakage protection circuit includes: a seventy-fourth transistor;

[0056] The control electrode of the seventy-fourth transistor is connected to the first sensing reset control node, the first electrode of the seventy-fourth transistor is connected to the first sensing reset leakage protection node, and the second electrode of the seventy-fourth transistor is connected to the second power supply terminal.

[0057] In some embodiments, the first sensing reset circuit includes: a second switching circuit and a third switching circuit connected in series between the first pull-up node and the second power supply terminal, wherein the second switching circuit is located between the third switching circuit and the first pull-up node;

[0058] One of the second switching circuit and the third switching circuit is connected to the sensing reset signal input terminal, and the other is connected to the sensing control node;

[0059] The second and third switching circuits are configured to provide a path between the second power supply terminal and the first pull-up node in response to a valid level signal provided by the sensing reset signal input terminal and a valid level signal at the sensing control node, and to provide an open circuit between the second power supply terminal and the first pull-up node in response to a low level signal provided by at least one of the sensing reset signal input terminal and the sensing control node.

[0060] In some embodiments, the second switching circuit includes a seventy-first transistor, and the third switching circuit includes a seventy-second transistor;

[0061] The control electrode of one of the seventy-first transistors and the seventy-second transistor is connected to the sensing reset signal input terminal, and the control electrode of the other transistor is connected to the sensing control node.

[0062] The first terminal of the seventy-first transistor is connected to the first pull-up node, the second terminal of the seventy-first transistor is connected to the first terminal of the seventy-second transistor, and the second terminal of the seventy-second transistor is connected to the second power supply terminal.

[0063] In some embodiments, the shift register unit further includes:

[0064] A first voltage control circuit is connected to a third power supply terminal, a first pull-up node, and a first voltage control node. The first voltage control circuit is configured to write the effective level signal provided by the third power supply terminal to the first voltage control node in response to the control of the effective level signal at the first pull-up node.

[0065] The shift register unit further includes: a first sensing reset leakage protection circuit;

[0066] The second switching circuit is connected to the sensing reset signal input terminal. The second switching circuit is connected to the third switching circuit through the first sensing reset leakage protection circuit. The second switching circuit and the first sensing reset leakage protection circuit are connected to the first sensing reset leakage protection node. The first sensing reset leakage protection node is connected to the first voltage control node.

[0067] The first sensing reset leakage protection circuit is connected to the sensing reset signal input terminal. The first sensing reset leakage protection circuit is configured to form a path between the first sensing reset leakage protection node and the third switching circuit in response to the control of an effective level signal at the sensing reset signal input terminal, and to form an open circuit between the first sensing reset leakage protection node and the third switching circuit in response to the control of an ineffective level signal at the sensing reset signal input terminal.

[0068] Alternatively, the third switching circuit is connected to the sensing reset signal input terminal, the third switching circuit is connected to the second power supply terminal through the first sensing reset leakage protection circuit, the third switching circuit and the first sensing reset leakage protection circuit are connected to the first sensing reset leakage protection node, and the first sensing reset leakage protection node is connected to the first voltage control node.

[0069] The first sensing reset leakage protection circuit is connected to the sensing reset signal input terminal. The first sensing reset leakage protection circuit is configured to form a path between the first sensing reset leakage protection node and the second power supply terminal in response to the control of an effective level signal at the sensing reset signal input terminal, and to form an open circuit between the first sensing reset leakage protection node and the second power supply terminal in response to the control of an ineffective level signal at the sensing reset signal input terminal.

[0070] In some embodiments, the first voltage control circuit includes: a twentieth transistor;

[0071] The control electrode of the twentieth transistor is connected to the first pull-up node, the first electrode of the twentieth transistor is connected to the third power supply terminal, and the second electrode of the twentieth transistor is connected to the first voltage control node.

[0072] The first sensing reset leakage protection circuit includes: a seventy-fourth transistor, the control electrode of the seventy-fourth transistor is connected to the sensing reset signal input terminal, and the first electrode of the seventy-fourth transistor is connected to the first sensing reset leakage protection node;

[0073] When the second switching circuit is connected to the sensing reset signal input terminal, the second terminal of the seventy-fourth transistor is connected to the third switching circuit;

[0074] When the third switching circuit is connected to the sensing reset signal input terminal, the second terminal of the seventy-fourth transistor is connected to the second power supply terminal.

[0075] In some embodiments, the shift register unit further includes:

[0076] The second sensing input circuit is connected to the clock control signal input terminal, the sensing control node, and the second pull-up node, and is configured to write the signal provided by the clock control signal input terminal to the second pull-up node in response to the control of the effective level signal at the sensing control node.

[0077] The second display input circuit is connected to the display signal input terminal and the second pull-up node, and is configured to write the valid level signal to the second pull-up node in response to the control of the valid level signal provided by the display signal input terminal;

[0078] The third drive output circuit is connected to the second pull-up node, the third drive clock signal input terminal, and the third drive signal output terminal, and is configured to write the signal provided by the third drive clock signal input terminal to the third drive signal output terminal in response to the control of the effective level signal at the second pull-up node.

[0079] The fourth drive output circuit is connected to the second pull-up node, the fourth drive clock signal input terminal, and the fourth drive signal output terminal, and is configured to write the signal provided by the fourth drive clock signal input terminal to the fourth drive signal output terminal in response to the control of the effective level signal at the second pull-up node.

[0080] In some embodiments, the second sensing input circuit includes: a thirty-second transistor;

[0081] The control electrode of the thirty-second transistor is connected to the sensing control node, the first electrode of the thirty-second transistor is connected to the clock control signal input terminal, and the second electrode of the thirty-second transistor is connected to the second pull-up node.

[0082] In some embodiments, when a first sensing input leakage protection circuit is provided in the shift register unit, the second sensing input circuit is connected to the first sensing input leakage protection node, so as to be connected to the clock control signal input terminal through the first sensing input leakage protection node and the first sensing input leakage protection circuit.

[0083] In some embodiments, the shift register unit further includes:

[0084] The second cascaded output circuit is connected to the second pull-up node, the second cascaded clock signal input terminal, and the second cascaded signal output terminal, and is configured to write the signal provided by the second cascaded clock signal input terminal to the second cascaded signal output terminal in response to the control of the effective level signal at the second pull-up node.

[0085] The shift register unit further includes: a second sensing input leakage protection circuit, wherein the second sensing input circuit is connected to the clock control signal input terminal through the second sensing input leakage protection circuit, and the second sensing input circuit and the second sensing input leakage protection circuit are connected to the second sensing input leakage protection node;

[0086] The second sensing input leakage protection circuit is connected to a preset input control signal input terminal and a second cascaded signal output terminal. The second sensing input leakage protection circuit is configured to form a path between the second sensing input leakage protection node and the clock control signal input terminal in response to the control of an effective level signal provided by the preset input control signal input terminal, and to disconnect the second sensing input leakage protection node from the clock control signal input terminal in response to the control of an ineffective level signal provided by the preset input control signal input terminal. When the second sensing input leakage protection node is disconnected from the clock control signal input terminal, it writes an effective level signal to the second sensing input leakage protection node in response to the control of an effective level signal provided by the second cascaded signal output terminal.

[0087] In some embodiments, the second sensing input leakage protection circuit includes: a thirty-third transistor and a thirty-fourth transistor;

[0088] The control electrode of the thirty-third transistor is connected to the preset input control signal input terminal, the first electrode of the thirty-third transistor is connected to the clock control signal input terminal, and the second electrode of the thirty-third transistor is connected to the second sensing input leakage protection node.

[0089] The control electrode and the first electrode of the thirty-fourth transistor are both connected to the second cascaded signal output terminal, and the second electrode of the thirty-fourth transistor is connected to the second sensing input leakage protection node.

[0090] In some embodiments, the shift register unit further includes:

[0091] The second global reset circuit is connected to the global reset signal input terminal, the first inactive level supply terminal, and the second pull-up node, and is configured to write the inactive level signal provided by the first inactive level supply terminal to the second pull-up node in response to the control of the active level signal provided by the global reset signal input terminal.

[0092] The second display reset circuit is connected to the display reset signal input terminal, the first inactive level supply terminal, and the second pull-up node, and is configured to write the inactive level signal provided by the first inactive level supply terminal to the second pull-up node in response to the control of the active level signal provided by the display reset signal input terminal.

[0093] The second pull-down control circuit is connected to the second power supply terminal, the sixth power supply terminal, the second pull-up node, and the second pull-down node, and is configured to write a voltage that is opposite to the voltage at the second pull-up node to the second pull-down node;

[0094] The second pull-up noise reduction circuit is connected to the first inactive level supply terminal, the second pull-up node, and the second pull-down node, and is configured to write the inactive level signal provided by the first inactive level supply terminal to the second pull-up node in response to the control of the active level signal at the second pull-down node.

[0095] The third drive output circuit is also connected to the second pull-down node and the fourth power supply terminal. The third drive output circuit is also configured to write the ineffective level signal provided by the fourth power supply terminal to the third drive signal output terminal in response to the control of the effective level signal at the second pull-down node.

[0096] The fourth drive output circuit is also connected to the second pull-down node and the fourth power supply terminal. The fourth drive output circuit is also configured to write an invalid level signal provided by the fourth power supply terminal to the fourth drive signal output terminal in response to the control of an effective level signal at the second pull-down node.

[0097] In some embodiments, the first inactive level supply terminal is the second power supply terminal;

[0098] Alternatively, the shift register unit includes a first voltage control circuit, and the first non-active level supply terminal is the first voltage control node connected to the first voltage control circuit.

[0099] In some embodiments, the first inactive level supply terminal is the second power supply terminal;

[0100] The shift register unit further includes:

[0101] The second voltage control circuit is connected to the effective level supply terminal, the second pull-up node, and the second voltage control node. The second voltage control circuit is configured to write the effective level signal provided by the effective level supply terminal to the second voltage control node in response to the control of the effective level signal at the second pull-up node.

[0102] The shift register unit further includes at least one of the following: a fourth leakage protection circuit, a fifth leakage protection circuit, and a sixth leakage protection circuit;

[0103] The second global reset circuit is connected to the second power supply terminal through the fourth leakage protection circuit. The second global reset circuit and the fourth leakage protection circuit are connected to the fourth leakage protection node. The fourth leakage protection node is connected to the second voltage control node. The fourth leakage protection circuit is connected to the global reset signal input terminal. The fourth leakage protection circuit is configured to form a path between the fourth leakage protection node and the second power supply terminal in response to the control of an effective level signal provided by the global reset signal input terminal, and to disconnect the fourth leakage protection node from the second power supply terminal in response to the control of an ineffective level signal provided by the global reset signal input terminal.

[0104] The second display reset circuit is connected to the second power supply terminal through the fifth leakage protection circuit. The second display reset circuit and the fifth leakage protection circuit are connected to the fifth leakage protection node. The fifth leakage protection node is connected to the second voltage control node. The fifth leakage protection circuit is connected to the display reset signal input terminal. The fifth leakage protection circuit is configured to form a path between the fifth leakage protection node and the second power supply terminal in response to the control of an effective level signal provided by the display reset signal input terminal, and to disconnect the circuit between the fifth leakage protection node and the second power supply terminal in response to the control of an ineffective level signal provided by the display reset signal input terminal.

[0105] The second pull-up noise reduction circuit is connected to the second power supply terminal through the sixth leakage protection circuit. The second pull-up noise reduction circuit and the sixth leakage protection circuit are connected to the sixth leakage protection node. The sixth leakage protection node is connected to the second voltage control node. The sixth leakage protection circuit is connected to the second pull-down node. The sixth leakage protection circuit is configured to form a path between the sixth leakage protection node and the second power supply terminal in response to the control of an effective level signal at the second pull-down node, and to disconnect the circuit between the sixth leakage protection node and the second power supply terminal in response to the control of an ineffective level signal at the second pull-down node.

[0106] In some embodiments, the shift register unit includes a first sensing reset circuit, and the first sensing reset circuit includes a first sensing reset control circuit and a first switching circuit;

[0107] The shift register unit further includes: a second sensing reset circuit, the second sensing reset circuit comprising:

[0108] The second sensing reset control circuit is connected to the sensing reset signal input terminal, the second sensing reset control node, the second power supply terminal, and the second sensing reset control node. It is configured to write the valid level signal at the sensing reset control node to the second sensing reset control node in response to the control of the inactive level signal provided by the sensing reset signal input terminal and the valid level signal at the sensing control node.

[0109] The fourth switching circuit is connected to the second sensing reset control node, the second pull-up node, and the second inactive level supply terminal. The fourth switching circuit is configured to form a path between the second inactive level supply terminal and the second pull-up node in response to the control of the active level signal at the second sensing reset control node, and to form an open circuit between the second inactive level supply terminal and the second pull-up node in response to the control of the inactive level signal at the second sensing reset control node.

[0110] In some embodiments, the second sensing reset control circuit includes an eighty-first transistor and an eighty-second transistor, and the fourth switching circuit includes an eighty-third transistor;

[0111] The control electrode and the first electrode of the eighty-first transistor are both connected to the sensing control node, and the second electrode of the eighty-first transistor is connected to the second sensing reset control node;

[0112] The control electrode of the 82nd transistor is connected to the sensing reset signal input terminal, the first electrode of the 82nd transistor is connected to the second sensing reset control node, and the second electrode of the 82nd transistor is connected to the second power supply terminal.

[0113] The control electrode of the 83rd transistor is connected to the second sensing reset control node, the first electrode of the 83rd transistor is connected to the second pull-up node, and the second electrode of the 83rd transistor is connected to the second inactive level supply terminal.

[0114] In some embodiments, the second inactive level supply terminal is a second power supply terminal;

[0115] The shift register unit further includes:

[0116] The second voltage control circuit is connected to the third power supply terminal, the second pull-up node, and the second voltage control node. The second voltage control circuit is configured to write the effective level signal provided by the third power supply terminal to the second voltage control node in response to the control of the effective level signal at the second pull-up node.

[0117] The shift register unit further includes: a second sensing reset leakage protection circuit, the fourth switching circuit being connected to the second power supply terminal through the second sensing reset leakage protection circuit, the fourth switching circuit and the second sensing reset leakage protection circuit being connected to the second sensing reset leakage protection node, and the second sensing reset leakage protection node being connected to the second voltage control node;

[0118] The second sensing reset leakage protection circuit is connected to the second sensing reset control node. The second sensing reset leakage protection circuit is configured to form a path between the second sensing reset leakage protection node and the second power supply terminal in response to the control of an effective level signal at the second sensing reset control node, and to form an open circuit between the second sensing reset leakage protection node and the second power supply terminal in response to the control of an ineffective level signal at the second sensing reset control node.

[0119] In some embodiments, the second voltage control circuit includes: a fiftieth transistor;

[0120] The control electrode of the fiftieth transistor is connected to the second pull-up node, the first electrode of the fiftieth transistor is connected to the third power supply terminal, and the second electrode of the fiftieth transistor is connected to the second voltage control node.

[0121] The second sensing reset leakage protection circuit includes: an eighty-fourth transistor;

[0122] The control electrode of the 84th transistor is connected to the second sensing reset control node, the first electrode of the 84th transistor is connected to the second sensing reset leakage protection node, and the second electrode of the 84th transistor is connected to the second power supply terminal.

[0123] In some embodiments, the shift register unit includes a first voltage control circuit, and the second inactive level supply terminal is a first voltage control node connected to the first voltage control circuit.

[0124] In some embodiments, the shift register unit includes a first sensing reset circuit, and the first sensing reset circuit includes a second switching circuit and the third switching circuit;

[0125] The shift register unit further includes: a second sensing reset circuit, the second sensing reset circuit including: a fifth switch circuit and a sixth switch circuit connected in series between the second pull-up node and the second power supply terminal, the fifth switch circuit being located between the sixth switch circuit and the second pull-up node;

[0126] One of the fifth switch circuit and the sixth switch circuit is connected to the sensing reset signal input terminal, and the other is connected to the sensing control node;

[0127] The fifth and sixth switching circuits are configured to, in response to the control of a valid level signal provided by the sensing reset signal input terminal and a valid level signal at the sensing control node, provide a path between the second power supply terminal and the second pull-up node, and in response to the control of a low level signal provided by at least one of the sensing reset signal input terminal and the sensing control node, provide an open circuit between the second power supply terminal and the second pull-up node.

[0128] In some embodiments, the fifth switching circuit includes an eighty-first transistor, and the sixth switching circuit includes an eighty-second transistor;

[0129] The control electrode of one of the eighty-first transistors and the eighty-second transistor is connected to the sensing reset signal input terminal, and the control electrode of the other transistor is connected to the sensing control node.

[0130] The first terminal of the eighty-first transistor is connected to the first pull-up node, the second terminal of the eighty-first transistor is connected to the first terminal of the eighty-second transistor, and the second terminal of the eighty-second transistor is connected to the second power supply terminal.

[0131] In some embodiments, the shift register unit further includes:

[0132] The second voltage control circuit is connected to the third power supply terminal, the second pull-up node, and the second voltage control node. The second voltage control circuit is configured to write the effective level signal provided by the third power supply terminal to the second voltage control node in response to the control of the effective level signal at the second pull-up node.

[0133] The shift register unit further includes: a second sensing reset leakage protection circuit;

[0134] The fifth switching circuit is connected to the sensing reset signal input terminal. The fifth switching circuit is connected to the sixth switching circuit through the second sensing reset leakage protection circuit. The second switching circuit and the second sensing reset leakage protection circuit are connected to the second sensing reset leakage protection node. The second sensing reset leakage protection node is connected to the second voltage control node.

[0135] The second sensing reset leakage protection circuit is connected to the sensing reset signal input terminal. The second sensing reset leakage protection circuit is configured to form a path between the second sensing reset leakage protection node and the sixth switching circuit in response to the control of an effective level signal at the sensing reset signal input terminal, and to form an open circuit between the second sensing reset leakage protection node and the sixth switching circuit in response to the control of an ineffective level signal at the sensing reset signal input terminal.

[0136] Alternatively, the fifth switching circuit is connected to the sensing reset signal input terminal, the sixth switching circuit is connected to the second power supply terminal through the second sensing reset leakage protection circuit, the sixth switching circuit and the second sensing reset leakage protection circuit are connected to the second sensing reset leakage protection node, and the second sensing reset leakage protection node is connected to the second voltage control node;

[0137] The second sensing reset leakage protection circuit is connected to the sensing reset signal input terminal. The second sensing reset leakage protection circuit is configured to form a path between the second sensing reset leakage protection node and the second power supply terminal in response to the control of an effective level signal at the sensing reset signal input terminal, and to form an open circuit between the second sensing reset leakage protection node and the second power supply terminal in response to the control of an ineffective level signal at the sensing reset signal input terminal.

[0138] In some embodiments, the second voltage control circuit includes: a fiftieth transistor;

[0139] The control electrode of the fiftieth transistor is connected to the second pull-up node, the first electrode of the fiftieth transistor is connected to the third power supply terminal, and the second electrode of the fiftieth transistor is connected to the second voltage control node.

[0140] The second sensing reset leakage protection circuit includes: an eighty-fourth transistor, the control electrode of the eighty-fourth transistor is connected to the second sensing reset control node, and the first electrode of the eighty-fourth transistor is connected to the second sensing reset leakage protection node;

[0141] When the fifth switching circuit is connected to the sensing reset signal input terminal, the second terminal of the eighty-fourth transistor is connected to the third switching circuit;

[0142] When the sixth switch circuit is connected to the sensing reset signal input terminal, the second terminal of the eighty-fourth transistor is connected to the second power supply terminal.

[0143] In some embodiments, the shift register unit includes a first sensing reset circuit, and the first sensing reset circuit includes a second switching circuit and the third switching circuit, and the first shift register unit includes a first voltage control circuit.

[0144] The shift register unit further includes: a second sensing reset circuit, the second sensing reset circuit comprising:

[0145] The seventh switch circuit is connected to the second pull-up node, the sensing reset signal input terminal, and the first voltage control node connected to the first voltage control circuit. The seventh switch circuit is configured to form a path between the second pull-up node and the first voltage control node in response to the control of the valid level signal provided by the sensing reset signal input terminal, and to form an open circuit between the second pull-up node and the first voltage control node in response to the control of the control of the invalid level signal provided by the sensing reset signal input terminal.

[0146] In some embodiments, the seventh switching circuit includes: an eighty-fifth transistor;

[0147] The control electrode of the 85th transistor is connected to the sensing reset signal input terminal, the first electrode of the 85th transistor is connected to the second pull-up node, and the second electrode of the 85th transistor is connected to the first control voltage node.

[0148] Secondly, embodiments of this disclosure provide a shift register unit, wherein:

[0149] A sensing control circuit, connected to a sensing signal input terminal, a random signal input terminal, and a sensing control node, is configured to write the signal provided by the sensing signal input terminal to the sensing control node in response to a valid level signal provided by the random signal input terminal.

[0150] A first sensing input circuit is connected to an effective level supply terminal, a clock control signal input terminal, the sensing control node, and a first pull-up node. The first sensing input circuit is controlled by the signal provided at the sensing control node and the signal provided at the clock control signal input terminal. The first sensing input circuit is configured to write the effective level signal provided by the effective level supply terminal to the first pull-up node in response to the control of the effective level signal at the sensing control node and the effective level signal provided at the clock control signal input terminal.

[0151] A first sensing reset circuit is connected to a sensing reset signal input terminal, the sensing control node, the first pull-up node, and the second power supply terminal. It is configured to write an invalid level signal provided by the second power supply terminal to the first pull-up node in response to the control of the signal provided by the sensing reset signal input terminal and the valid level signal at the sensing control node.

[0152] The first drive output circuit is connected to the first pull-up node, the first drive clock signal input terminal, and the first drive signal output terminal, and is configured to write the signal provided by the first drive clock signal input terminal to the first drive signal output terminal in response to the control of the effective level signal at the first pull-up node.

[0153] In some embodiments, the effective level supply terminal is the clock control signal input terminal.

[0154] Thirdly, embodiments of this disclosure provide a gate driving circuit, comprising: a plurality of cascaded shift register units, wherein the shift register units are the shift register units provided in the first aspect above.

[0155] Thirdly, embodiments of this disclosure provide a gate driving method, wherein the gate driving method is based on the shift register unit provided in the first aspect, and the gate driving method includes:

[0156] The sensing control circuit, in response to the effective level signal provided by the random signal input terminal, writes the signal provided by the sensing signal input terminal to the sensing control node;

[0157] The first sensing input circuit, in response to the control of the valid level signal at the sensing control node, writes the signal provided by the clock control signal input terminal to the first pull-up node;

[0158] The first drive output circuit, in response to the control of the effective level signal at the first pull-up node, writes the signal provided by the first drive clock signal input terminal to the first drive signal output terminal.

[0159] In some embodiments, the step of the sensing control circuit writing the signal provided by the sensing signal input terminal to the sensing control node in response to the control of the valid level signal provided by the random signal input terminal includes:

[0160] The sensing control circuit, in response to the control of the valid level signal provided by the random signal input terminal, writes the valid level signal provided by the sensing signal input terminal to the sensing control node;

[0161] The sensing control circuit, in response to the control of the valid level signal provided by the random signal input terminal, writes the invalid level signal provided by the sensing signal input terminal to the sensing control node;

[0162] Before the step of the sensing control circuit writing the valid level signal provided by the sensing signal input terminal to the sensing control node in response to the control of the valid level signal provided by the random signal input terminal, the method further includes:

[0163] The first display input circuit, in response to the control of the valid level signal provided by the display signal input terminal, writes the valid level signal provided by the third power supply terminal to the first pull-up node;

[0164] The second drive output circuit, in response to the control of the effective level signal at the first pull-up node, writes the signal provided by the second drive clock signal input terminal to the second drive signal output terminal; the first cascade output circuit, in response to the control of the effective level signal at the first pull-up node, writes the signal provided by the first cascade clock signal input terminal to the first cascade signal output terminal.

[0165] From the moment the sensing control circuit writes the valid level signal provided by the sensing signal input terminal to the sensing control node in response to the valid level signal provided by the random signal input terminal, until the start of the sensing output phase, the first sensing input circuit writes the invalid signal provided by the clock control signal input terminal to the first pull-up node in response to the valid level signal at the sensing control node.

[0166] During the sensing output phase, the first sensing input circuit, in response to the control of the valid level signal at the sensing control node, writes the valid signal provided by the clock control signal input terminal to the first pull-up node.

[0167] The step of the sensing control circuit writing an invalid level signal provided by the sensing signal input terminal to the sensing control node in response to the control of the valid level signal provided by the random signal input terminal is located in the...

[0168] In some embodiments, after the step of the first drive output circuit writing the signal provided by the first drive clock signal input terminal to the first drive signal output terminal in response to the control of the effective level signal at the first pull-up node, the method further includes:

[0169] The first sensing reset circuit, in response to the signal provided by the sensing reset signal input terminal and the control of the valid level signal at the sensing control node, writes the invalid level signal provided by the second power supply terminal to the first pull-up node. Attached Figure Description

[0170] Figure 1 This is a schematic diagram of the pixel circuitry within an organic light-emitting diode (OLED) display panel.

[0171] Figure 2 for Figure 1 The diagram shows a timing sequence of one type of pixel circuit.

[0172] Figure 3 A schematic diagram of the circuit structure of a shift register unit provided in an embodiment of this disclosure;

[0173] Figure 4 A schematic diagram of another circuit structure for a shift register unit provided in an embodiment of this disclosure;

[0174] Figure 5 for Figure 4 The diagram shows a timing diagram of one type of shift register unit.

[0175] Figure 6 A schematic diagram of another circuit structure for a shift register unit provided in an embodiment of this disclosure;

[0176] Figure 7 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0177] Figure 8 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0178] Figure 9 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0179] Figure 10 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0180] Figure 11 for Figure 10 The diagram shows a timing diagram of one type of shift register unit.

[0181] Figure 12 for Figure 10 Another timing diagram of the shift register unit shown;

[0182] Figure 13 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0183] Figure 14 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0184] Figure 15 for Figure 14 The diagram shows a timing diagram of one type of shift register unit.

[0185] Figure 16 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0186] Figure 17A A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0187] Figure 17B A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0188] Figure 18A A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0189] Figure 18B A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0190] Figure 19 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0191] Figure 20 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0192] Figure 21 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0193] Figure 22 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0194] Figure 23A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0195] Figure 24 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0196] Figure 25 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0197] Figure 26 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0198] Figure 27A A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0199] Figure 27B A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0200] Figure 28A A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0201] Figure 28B A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0202] Figure 29 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0203] Figure 30 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0204] Figure 31 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0205] Figure 32 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0206] Figure 33 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0207] Figure 34 A schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure;

[0208] Figure 35 A schematic diagram of a gate drive circuit provided in an embodiment of this disclosure;

[0209] Figure 36 for Figure 35 The diagram shows a timing sequence of one type of gate drive circuit.

[0210] Figure 37 A flowchart of a gate driving method provided in an embodiment of this disclosure;

[0211] Figure 38 A flowchart of another gate driving method provided in an embodiment of this disclosure;

[0212] Figure 39 A flowchart illustrating yet another gate driving method provided in this disclosure embodiment;

[0213] Figure 40 A flowchart of yet another gate driving method provided in an embodiment of this disclosure. Detailed Implementation

[0214] To enable those skilled in the art to better understand the technical solution of the present invention, a shift register unit, gate driving circuit, display panel, and display device provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0215] The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "coupled" or "connected" are not limited to physical or mechanical coupling, but can include electrical connections, whether direct or indirect.

[0216] The transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other devices with the same characteristics. In this embodiment, the coupling method of the drain and source of each transistor can be interchanged; therefore, the drain and source of each transistor in this disclosure embodiment are actually indistinguishable. Here, one of the two terminals of the transistor, excluding the control terminal (i.e., the gate), is called the drain, and the other is called the source. The thin-film transistors used in the embodiments of this disclosure can be N-type transistors or P-type transistors. In the embodiments of this disclosure, when an N-type thin-film transistor is used, its first terminal can be the source, and its second terminal can be the drain. In the following embodiments, the description uses an N-type thin-film transistor as an example.

[0217] In this disclosure, "effective level signal" refers to a signal that, when input to the gate electrode of a transistor, can control the transistor to conduct, and "ineffective level signal" refers to a signal that, when input to the gate electrode of a transistor, can control the transistor to cut off. For N-type transistors, a high-level signal is an effective level signal, and a low-level signal is an ineffective level signal; for P-type transistors, a low-level signal is an effective level signal, and a high-level signal is an ineffective level signal.

[0218] In the following description, an N-type transistor will be used as an example. In this case, the active level signal refers to a high-level signal, and the inactive level signal refers to a low-level signal. It is conceivable that when using a P-type transistor, the timing of the control signal needs to be adjusted accordingly. Specific details are not elaborated here, but should be within the scope of this disclosure.

[0219] Figure 1 This is a schematic diagram of the pixel circuitry within an organic light-emitting diode (OLED) display panel. Figure 2 for Figure 1 The following is a timing diagram of the pixel circuit: Figure 1 and Figure 2 As shown, for an organic light-emitting diode display panel with external compensation function, a frame can be divided into two stages: the display driving stage and the sensing stage. In the display driving stage, each row of pixel units in the display panel completes the display driving. In the sensing stage, a certain row of pixel units in the display panel completes current extraction (i.e., sensing).

[0220] See Figure 1 As shown, the pixel circuit includes a display switch transistor QTFT (with its control electrode connected to the first gate line G1), a driving transistor DTFT, a sensing switch transistor STFT (with its control electrode connected to the second gate line G2), and a Cst. When external compensation is required for the pixel circuit, the pixel circuit includes at least two stages during operation: a pixel driving stage (including the data voltage writing process) and a pixel sensing stage (including the current reading process).

[0221] During the pixel driving stage, the data voltage Vdata in the data line Data needs to be written to the pixel unit. During the pixel sensing stage, a test voltage Vsence needs to be written to the pixel unit via the data line Data, and the electrical signal at the drain of the driving transistor is read to the signal readout line Sence via the sensing switch transistor STFT. Specifically, during current readout, an effective level voltage needs to be written to the gate of the sensing switch transistor STFT via the corresponding second gate line G2. It should be noted that external compensation is performed on the pixel units in the OLED display panel; the specific compensation process and principle are not detailed here.

[0222] For the second gate line G2 used to control the sensing switching transistor STFT, a corresponding gate driving circuit is configured in the peripheral area of ​​the display panel. This gate driving circuit includes multiple cascaded shift register units. However, the circuit structures of the shift register units involved in current related technologies are relatively complex and contain a large number of transistors. Therefore, how to simplify the circuit structure of the shift register unit is a technical problem that urgently needs to be solved by those skilled in the art.

[0223] To address the aforementioned technical problems, this disclosure provides corresponding solutions, and the embodiments will be described in detail below with reference to the accompanying drawings.

[0224] Figure 3 A circuit structure diagram of a shift register unit provided in an embodiment of this disclosure is shown below. Figure 3 As shown, the shift register unit includes: a sensing control circuit 1, a first sensing input circuit 2, and a first driving output circuit 5.

[0225] The sensing control circuit 1 is connected to the sensing signal input terminal INPUT2, the random signal input terminal OE, and the sensing control node H. The sensing control circuit 1 is configured to write the signal provided by the sensing signal input terminal INPUT2 to the sensing control node H in response to the control of the valid level signal provided by the random signal input terminal OE.

[0226] The first sensing input circuit 2 is connected to the clock control signal input terminal CLKA, the sensing control node H, and the first pull-up node PU1. The first sensing input circuit 2 is configured to write the signal provided by the clock control signal input terminal CLKA to the first pull-up node PU1 only in response to the control of the effective level signal at the sensing control node H.

[0227] The first drive output circuit 5 is connected to the first pull-up node PU1, the first drive clock signal input terminal CLKE, and the first drive signal output terminal OUT2, and is configured to write the signal provided by the first drive clock signal input terminal CLKE to the first drive signal output terminal OUT2 in response to the control of the effective level signal at the first pull-up node PU1.

[0228] In the related technology, the first sensing input circuit 2 is controlled not only by the voltage at the sensing control node H, but also by the signal provided by the clock control signal input terminal. Therefore, the first sensing input circuit 2 in the related technology needs to be configured with at least one transistor whose gate is connected to the sensing control node H, and at least one transistor whose gate is connected to the clock control signal input terminal CLKA. Only when the voltage at the sensing control node H is at an effective level and the signal provided by the clock control signal input terminal CLKA is at an effective level will the first sensing input circuit 2 write the effective level signal (e.g., the effective level signal provided by the clock control signal input terminal CLKA, or the working voltage at an effective level) to the first pull-up node PU1.

[0229] In the technical solution provided in this disclosure, the first sensing input circuit 2 is only controlled by the voltage at the sensing control node H, and is not controlled by the clock control signal input terminal CLKA. That is, the first sensing input circuit 2 provided in this disclosure does not require a transistor whose gate is connected to the clock control signal input terminal CLKA. Therefore, compared with related technologies, the technical solution of this disclosure can effectively reduce the number of transistors in the first sensing input circuit 2; thus, the technical solution of this disclosure can reduce the number of transistors in the shift register unit and simplify the circuit structure of the shift register unit.

[0230] It should be noted that, in the related technology, the first sensing input circuit 2 can only write valid level signals to the first pull-up node PU1, but cannot write invalid level signals to the first pull-up node PU1; while in the disclosed technology, the first sensing input circuit 2 can not only write valid level signals (valid level signals provided by the clock control signal input terminal CLKA) to the first pull-up node PU1, but also write invalid level signals (invalid level signals provided by the clock control signal input terminal CLKA) to the first pull-up node PU1. This will be described in detail below with specific examples.

[0231] Figure 4 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, as shown below. Figure 4 As shown, in some embodiments, the first sensing input circuit 2 includes: a second transistor M2; the control electrode of the second transistor M2 is connected to the sensing control node H, the first electrode of the second transistor M2 is connected to the clock control signal input terminal CLKA, and the second electrode of the second transistor M2 is connected to the first pull-up node PU1.

[0232] To facilitate a clearer understanding of the technical solutions of this disclosure by those skilled in the art, the technical solutions of this disclosure will be described in detail below with reference to specific examples. Specifically, the second power supply terminal provides a non-active level voltage VGL1.

[0233] In some embodiments, the sensing control circuit 1 includes a first transistor M1, the control electrode of the first transistor M1 is connected to the random signal input terminal OE, the first electrode of the first transistor M1 is connected to the sensing signal input terminal INPUT2, and the second electrode of the first transistor M1 is connected to the sensing control node H.

[0234] The first drive output circuit 5 includes a fifth transistor M5. The control electrode of the fifth transistor M5 is connected to the first pull-up node PU1, the first electrode of the fifth transistor M5 is connected to the first drive clock signal input terminal CLKE, and the second electrode of the fifth transistor M5 is connected to the first drive signal output terminal OUT2.

[0235] In some embodiments, a first capacitor C1 is provided at the sensing control node H to stabilize the voltage at the sensing control node H. A second capacitor C2 is provided at the first drive signal output terminal OUT2 to ensure stable output of the first drive signal output terminal OUT2.

[0236] Figure 5 for Figure 4 The following is a timing diagram of one type of shift register unit, as shown: Figure 5 As shown, in some embodiments, the operation of this shift register unit includes the following stages:

[0237] During phase p1, the sensing signal input terminal INPUT2 provides a high-level signal, the random signal input terminal OE provides a high-level signal, and the clock control signal input terminal CLKA provides a low-level signal.

[0238] At this time, the first transistor M1 is turned on, and the high-level signal provided by the sensing signal input terminal INPUT2 is written to the sensing control node H, resulting in a high-level voltage at the sensing control node H. Correspondingly, the second transistor M2 is turned on, and the low-level signal provided by the clock control signal input terminal CLKA is written to the first pull-up node PU1 through the second transistor M2. The first pull-up node PU1 is in a low-level state, and the fifth transistor M5 is turned off.

[0239] The p2 stage (also known as the sensing output stage) includes the p21 stage and the p22 stage.

[0240] It should be noted that there is a time interval between the p1 stage and the p2 stage. In order to ensure that the voltage at the sensing and control node H remains stable during this time interval, the aforementioned first capacitor C1 can be added at the sensing and control node H.

[0241] During phase p21, the sensing signal input terminal INPUT2 provides a low-level signal, the random signal input terminal OE provides a low-level signal, the clock control signal input terminal CLKA provides a high-level signal, and the first drive clock signal input terminal CLKE provides a low-level signal.

[0242] At this time, the first transistor is cut off, the sensing control node H is in a floating state to maintain a high level, the second transistor remains on, the clock control signal input terminal CLKA provides a high level signal to the first pull-up node PU1, the first pull-up node PU1 is in a high level state, the fifth transistor M5 is on, the low level signal provided by the first drive clock signal input terminal CLKE is written to the first drive signal output terminal OUT2 through the fifth transistor M5, the first drive signal output terminal OUT2 outputs a low level signal.

[0243] In stage p22, the sensing signal input terminal INPUT2 provides a low-level signal, the random signal input terminal OE provides a low-level signal, the clock control signal input terminal CLKA provides a high-level signal, and the first drive clock signal input terminal CLKE first provides a high-level signal and then a low-level signal.

[0244] The high-level signal provided by the clock control signal input terminal CLKA is continuously written to the first pull-up node PU1 through the second transistor. When the first pull-up node PU1 is in a high-level state, the fifth transistor M5 is turned on. The signal provided by the first drive clock signal input terminal CLKE is written to the first drive signal output terminal OUT2 through the fifth transistor M5. The first drive signal output terminal OUT2 first outputs a high-level signal and then outputs a low-level signal.

[0245] During the p3 phase, the sensing signal input terminal INPUT2 provides a low-level signal, the random signal input terminal OE provides a low-level signal, and the clock control signal input terminal CLKA provides a low-level signal.

[0246] The low-level signal provided by the clock control signal input terminal CLKA is written to the first pull-up node PU1 through the second transistor. When the first pull-up node PU1 is in a low-level state, the fifth transistor M5 is turned off, and the first drive signal output terminal OUT2 maintains the low-level state of the previous stage.

[0247] During the p4 stage, the sensing signal input terminal INPUT2 provides a low-level signal, the random signal input terminal OE provides a high-level signal, and the clock control signal input terminal CLKA provides a low-level signal.

[0248] At this time, the first transistor M1 is turned on, and the low-level signal provided by the sensing signal input terminal INPUT2 is written to the sensing control node H, and the voltage at the sensing control node H is in a low-level state. Correspondingly, the second transistor M2 is turned off; correspondingly, the first pull-up node PU1 is in a floating state to maintain the low-level state of the previous stage, the fifth transistor M5 is turned off, and the first drive signal output terminal OUT2 maintains the low-level state of the previous stage.

[0249] As can be seen from the above, the first sensing input circuit 2 can not only write the valid level signal (the high level signal provided by the clock control signal input terminal CLKA) to the first pull-up node PU1, but also write the invalid level signal (the low valid level signal provided by the clock control signal input terminal CLKA) to the first pull-up node PU1.

[0250] Figure 6 This is another circuit structure diagram of the shift register unit provided in the embodiments of this disclosure, such as... Figure 6 As shown, in some embodiments, the shift register unit further includes: a first display input circuit 7, a second drive output circuit 9, and a first cascaded output circuit 13.

[0251] The first display input circuit 7 is connected to the display signal input terminal INPUT1, the third power supply terminal, and the first pull-up node PU1. The first display input circuit 7 is configured to write the valid level signal provided by the third power supply terminal to the first pull-up node PU1 in response to the control of the valid level signal provided by the display signal input terminal INPUT1.

[0252] The second drive output circuit 9 is connected to the first pull-up node PU1, the second drive clock signal input terminal CLKD, and the second drive signal output terminal OUT1. The second drive output circuit 9 is configured to write the signal provided by the second drive clock signal input terminal CLKD to the second drive signal output terminal OUT1 in response to the control of the effective level signal at the first pull-up node PU1.

[0253] The first cascaded output circuit 13 is connected to the first pull-up node PU1, the first cascaded clock signal input terminal CLKC, and the first cascaded signal output terminal CR, and is configured to write the signal provided by the first cascaded clock signal input terminal CLKC to the first cascaded signal output terminal CR in response to the control of the effective level signal at the first pull-up node PU1.

[0254] Figure 6 The shift register unit shown not only has a sensing drive function, that is, to Figure 1 The second gate line G2 provides the drive signal and also has a display drive function, that is, to... Figure 1(The first gate line G1 provides the driving signal). In other words, the first gate line G1 and the second gate line G2 in the display panel can be driven by the same gate driving circuit, which can effectively reduce the number of gate driving circuits configured in the display panel and is beneficial for the narrow bezel design of the product.

[0255] Figure 7 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 7 As shown, as a leakage protection design for the first sensing input circuit 2, in some embodiments, the shift register unit further includes: a first voltage control circuit 14 and a first sensing input leakage protection circuit 41.

[0256] The first voltage control circuit 14 is connected to the third power supply terminal, the first pull-up node PU1, and the first voltage control node OFF1. The first voltage control circuit 14 is configured to write the effective level signal provided by the third power supply terminal to the first voltage control node OFF1 in response to the control of the effective level signal at the first pull-up node PU1.

[0257] The first sensing input circuit 2 is connected to the clock control signal input terminal CLKA through the first sensing input leakage protection circuit 41. The first sensing input circuit 2 and the first sensing input leakage protection circuit 41 are connected to the first sensing input leakage protection node IQ1. The first sensing input leakage protection node IQ1 is connected to the first voltage control node OFF1.

[0258] The first sensing input leakage protection circuit 41 is connected to the sensing control node H. The first sensing input leakage protection circuit 41 is configured to form a path between the first sensing input leakage protection node IQ1 and the clock control signal input terminal CLKA in response to the control of an effective level signal at the sensing control node 41, and to disconnect the circuit between the first sensing input leakage protection node IQ1 and the clock control signal input terminal CLKA in response to the control of an ineffective level signal at the sensing control node H.

[0259] In some embodiments, the first voltage control circuit 14 includes: a twentieth transistor M20, the control electrode of the twentieth transistor M20 is connected to the first pull-up node PU1, the first electrode of the twentieth transistor M20 is connected to the third power supply terminal, and the second electrode of the twentieth transistor M20 is connected to the first voltage control node OFF1.

[0260] The first sensing input leakage protection circuit 41 includes: a third transistor M3, the control electrode of the third transistor M3 is connected to the sensing control node H, the first electrode of the third transistor M3 is connected to the clock control signal input terminal, and the second electrode of the third transistor M3 is connected to the first sensing input leakage protection node IQ1.

[0261] Figure 8This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 8 As shown, as another leakage protection design for the first sensing input circuit 2, the shift register unit further includes a first sensing input leakage protection circuit 41. The first sensing input circuit 2 is connected to the clock control signal input terminal CLKA through the first sensing input leakage protection circuit 41, and the first sensing input circuit 2 and the first sensing input leakage protection circuit 41 are connected to the first sensing input leakage protection node IQ1.

[0262] The first sensing input leakage protection circuit 41 is connected to the preset input control signal input terminal CLKB and the first cascaded signal output terminal CR. The first sensing input leakage protection circuit 41 is configured to form a path between the first sensing input leakage protection node IQ1 and the clock control signal input terminal CLKA in response to the control of the valid level signal provided by the preset input control signal input terminal CLKB, and to disconnect the circuit between the first sensing input leakage protection node IQ1 and the clock control signal input terminal CLKA in response to the control of the invalid level signal provided by the preset input control signal input terminal CLKB, and to write the valid level signal to the first sensing input leakage protection node IQ1 in response to the control of the valid level signal provided by the first cascaded signal output terminal CR when the circuit between the first sensing input leakage protection node IQ1 and the clock control signal input terminal CLKA is disconnected.

[0263] In some embodiments, the first sensing input leakage protection circuit 41 includes: a third transistor M3 and a fourth transistor M4; the control electrode of the third transistor M3 is connected to the preset input control signal input terminal CLKB, the first electrode of the third transistor M3 is connected to the clock control signal input terminal CLKA, and the second electrode of the third transistor M3 is connected to the first sensing input leakage protection node IQ1; the control electrode and the first electrode of the fourth transistor M4 are both connected to the first cascaded signal output terminal CR, and the second electrode of the fourth transistor M4 is connected to the first sensing input leakage protection node IQ1.

[0264] Specifically, the preset input control signal input terminal CLKB provides an inactive level signal during the display output stage of the shift register unit, thereby creating an open circuit between the first sensing input leakage protection node IQ1 and the clock control signal input terminal CLKA; and after the display output stage of the shift register unit (i.e., from... Figure 5 The p1 phase (from the beginning of the p1 phase to the end of a frame) provides an effective level signal to enable a path to be formed between the first sensing input leakage protection node IQ1 and the clock control signal input CLKA.

[0265] Figure 9 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 9As shown, in some embodiments, the shift register unit includes not only the first display input circuit 7, the second drive output circuit 9, and the first cascaded output circuit 13 in the previous embodiments, but also the first global reset circuit 6, the first display reset circuit 8, the first pull-down control circuit 11, and the first pull-up noise reduction circuit 12.

[0266] The first global reset circuit 6 is connected to the global reset signal input terminal T-RST, the second power supply terminal, and the first pull-up node PU1. The first global reset circuit 6 is configured to write the ineffective level signal provided by the second power supply terminal to the first pull-up node in response to the control of the effective level signal provided by the global reset signal input terminal T-RST.

[0267] The first display reset circuit 8 is connected to the display reset signal input terminal RST, the second power supply terminal, and the first pull-up node PU1. The first display reset circuit 8 is configured to write the invalid level signal provided by the second power supply terminal to the first pull-up node PU1 in response to the control of the valid level signal provided by the display reset signal input terminal RST.

[0268] The first pull-down control circuit 11 is connected to the second power supply terminal, the fifth power supply terminal, the first pull-up node PU1 and the first pull-down node PD1. The first pull-down control circuit 11 is configured to write a voltage that is opposite to the voltage at the first pull-up node PU1 to the first pull-down node PD1.

[0269] The first pull-up noise reduction circuit 12 is connected to the second power supply terminal, the first pull-up node PU1 and the first pull-down node PD1. The first pull-up noise reduction circuit 12 is configured to write the ineffective level signal provided by the second power supply terminal to the first pull-up node PU1 in response to the control of the effective level signal at the first pull-down node PD1.

[0270] At this time, the first cascaded output circuit 13 is also connected to the first pull-down node PD1 and the second power supply terminal. The first cascade is also configured to write the ineffective level signal provided by the second power supply terminal to the cascaded signal output terminal CR in response to the control of the effective level signal at the first pull-down node PD1.

[0271] The first drive output circuit 5 is also connected to the first pull-down node PD1 and the fourth power supply terminal. The first drive output circuit 5 is also configured to write the ineffective level signal provided by the fourth power supply terminal to the first drive signal output terminal OUT2 in response to the control of the effective level signal at the first pull-down node PD1.

[0272] The second drive output circuit 9 is also connected to the second pull-down node PD2 and the fourth power supply terminal. The second drive output circuit 9 is also configured to write the inactive level signal provided by the fourth power supply terminal to the second drive signal output terminal OUT1 in response to the control of the effective level signal at the second pull-down node PD2.

[0273] Figure 10 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, as shown below. Figure 10 As shown, Figure 10 The shift register unit shown is Figure 9 One specific alternative implementation of the shift register unit shown is as follows: Figure 10 Both the sensing control circuit 1 and the first sensing input preparation circuit 2 within the shift register unit shown can be adopted. Figure 4 As shown in the image.

[0274] In some embodiments, the first global reset circuit 6 includes a seventh transistor M7, the first display input circuit 7 includes a ninth transistor M9, the first display reset circuit 8 includes a tenth transistor M10, the first pull-down control circuit 11 includes a twelfth transistor M12 and a thirteenth transistor M13, the first pull-up noise reduction circuit 12 includes a fourteenth transistor M14, the first drive output circuit 5 includes a fifth transistor M5 and a seventeenth transistor M17, the second drive output circuit 9 includes a fifteenth transistor M15 and an eighteenth transistor M18, and the first cascaded output circuit 13 includes a sixteenth transistor M16 and a nineteenth transistor M19.

[0275] Among them, the control electrode of the seventh transistor M7 is connected to the global reset signal input terminal T-RST, the first electrode of the seventh transistor M7 is connected to the first pull-up node PU1, and the second electrode of the seventh transistor M7 is connected to the second power supply terminal.

[0276] The control electrode of the ninth transistor M9 is connected to the display signal input terminal INPUT1, the first electrode of the ninth transistor M9 is connected to the third power supply terminal, and the second electrode of the ninth transistor M9 is connected to the first pull-up node PU1.

[0277] The control electrode of the tenth transistor M10 is connected to the display reset signal input terminal RST, the first electrode of the tenth transistor M10 is connected to the first pull-up node PU1, and the second electrode of the tenth transistor M10 is connected to the second power supply terminal.

[0278] The control electrode of the twelfth transistor M12 is connected to the fifth power supply terminal, the first electrode of the twelfth transistor M12 is connected to the fifth power supply terminal, and the second electrode of the twelfth transistor M12 is connected to the first pull-down node PD1.

[0279] The control electrode of the thirteenth transistor M13 is connected to the first pull-up node PU1, the first electrode of the thirteenth transistor M13 is connected to the first pull-down node PD1, and the second electrode of the thirteenth transistor M13 is connected to the second power supply terminal.

[0280] The control electrode of the fourteenth transistor M14 is connected to the first pull-down node PD1, the first electrode of the fourteenth transistor M14 is connected to the first pull-up node PU1, and the second electrode of the fourteenth transistor M14 is connected to the second power supply terminal.

[0281] The control electrode of the fifth transistor M5 is connected to the first pull-up node PU1, the first electrode of the fifth transistor M5 is connected to the first drive clock signal input terminal CLKE, and the second electrode of the fifth transistor M5 is connected to the first drive signal output terminal OUT2.

[0282] The control electrode of the seventeenth transistor M17 is connected to the first pull-down node PD1, the first electrode of the seventeenth transistor M17 is connected to the first drive signal output terminal OUT2, and the second electrode of the seventeenth transistor M17 is connected to the fourth power supply terminal.

[0283] The control terminal of the fifteenth transistor M15 is connected to the first pull-up node PU1, the first terminal of the fifteenth transistor M15 is connected to the second drive clock signal input terminal CLKD, and the second terminal of the fifteenth transistor M15 is connected to the second drive signal output terminal OUT1.

[0284] The control electrode of the eighteenth transistor M18 is connected to the first pull-down node PD1, the first electrode of the eighteenth transistor M18 is connected to the second drive signal output terminal OUT1, and the second electrode of the eighteenth transistor M18 is connected to the fourth power supply terminal.

[0285] The control electrode of the sixteenth transistor M16 is connected to the first pull-up node PU1, the first electrode of the sixteenth transistor M16 is connected to the cascade drive clock signal input terminal CLKC, and the second electrode of the sixteenth transistor M16 is connected to the cascade signal output terminal CR.

[0286] The control electrode of the nineteenth transistor M19 is connected to the first pull-down node PD1, the first electrode of the nineteenth transistor M19 is connected to the cascaded signal output terminal CR, and the second electrode of the nineteenth transistor M19 is connected to the fourth power supply terminal.

[0287] In some embodiments, a second capacitor C2 and a third capacitor C3 are respectively configured at the first drive signal output terminal OUT2 and the second drive signal output terminal OUT1.

[0288] Figure 11 for Figure 10 The following is a timing diagram of one type of shift register unit, as shown: Figure 11 As shown, the second power supply terminal provides a low-level voltage VGL1, the third power supply terminal provides a high-level voltage VDD1, the fourth power supply terminal provides a low-level voltage VGL2, and the fifth power supply terminal provides a high-level voltage VDDA; the operation of this shift register unit includes:

[0289] During the global reset phase t0, the display signal input terminal INPUT1 provides a low-level signal, the sensing signal input terminal INPUT2 provides a low-level signal, the random signal input terminal OE provides a high-level signal, the clock control signal input terminal CLKA provides a low-level signal, the display reset signal input terminal RST provides a low-level signal, and the global reset signal input terminal T-RST provides a high-level signal.

[0290] Since the random signal input terminal OE provides a high-level signal, the first transistor M1 is turned on, and the low-level signal provided by the sensing signal input terminal INPUT2 is written to the sensing control node H to perform a global reset of the sensing control node H; since the global reset signal input terminal T-RST provides a high-level signal, the seventh transistor M7 is turned on, and the low-level voltage VGL1 provided by the second power supply terminal is written to the first pull-up node PU1 through the seventh transistor M7 to perform a global reset of the first pull-up node PU1.

[0291] During the display input phase t1, the display signal input terminal INPUT1 provides a high-level signal, the sensing signal input terminal INPUT2 provides a low-level signal, the random signal input terminal OE provides a low-level signal, the clock control signal input terminal CLKA provides a low-level signal, the display reset signal input terminal RST provides a low-level signal, and the global reset signal input terminal T-RST provides a low-level signal.

[0292] Since the display signal input terminal INPUT1 provides a high-level signal, the ninth transistor M9 is turned on. The high-level voltage VDD1 provided by the third power supply terminal is written to the first pull-up node PU1 through the ninth transistor M9. The voltage at the first pull-up node PU1 is in a high-level state. At this time, the thirteenth transistor M13, the fifth transistor M5, the fifteenth transistor M15, and the sixteenth transistor M16 are all turned on. The low-level signal provided by the second power supply terminal is written to the first pull-down node PD1 through the thirteenth transistor M13. The low-level signal provided by the first drive clock signal input terminal CLKE is written to the first drive signal output terminal OUT2 through the fifth transistor M5. The low-level signal provided by the second drive clock signal input terminal CLKD is written to the second drive signal output terminal OUT1 through the fifteenth transistor M15. The low-level signal provided by the first cascade clock signal input terminal CLKC is written to the first cascade signal output terminal CR through the sixteenth transistor M16. That is to say, the first drive signal output terminal OUT2, the second drive signal output terminal OUT1, and the first cascade signal output terminal CR all output low-level signals.

[0293] It should be noted that since the random signal input terminal OE provides a low-level signal, the first transistor is in the off state, and the sensing control node H is in the floating state, that is, maintaining the low-level state of the previous stage. At this time, the second transistor remains in the off state.

[0294] During the display output phase t2, the display signal input terminal INPUT1 provides a low-level signal, the sensing signal input terminal INPUT2 provides a low-level signal, the random signal input terminal OE provides a low-level signal, the clock control signal input terminal CLKA provides a low-level signal, the display reset signal input terminal RST provides a low-level signal, and the sensing reset signal input terminal T-RST provides a low-level signal.

[0295] Since both the display signal input terminal INPUT1 and the sensing signal input terminal INPUT2 provide low-level signals, the ninth transistor M9 and the first transistor M1 are both turned off. At this time, the sensing control node H is also in a low-level state, and the second transistor is in a turned-off state. Therefore, the first pull-up node is in a floating state, that is, it maintains the high-level state of the previous stage.

[0296] Since the first pull-up node PU1 is in a high-level state, the thirteenth transistor M13, the fifth transistor M5, the fifteenth transistor M15, and the sixteenth transistor M16 are all kept on. The first drive clock signal input terminal CLKE continuously writes a signal to the first drive signal output terminal OUT2, the second drive clock signal input terminal CLKD continuously writes a signal to the second drive signal output terminal OUT1, and the first cascade clock signal input terminal CLKC continuously writes a signal to the first cascade signal output terminal CR.

[0297] During this process, the first drive clock signal input terminal CLKE, the second drive clock signal input terminal CLKD, and the first cascade signal input terminal CLKC all input high-level signals first, followed by low-level signals. Therefore, the first drive signal output terminal OUT2, the second drive signal output terminal OUT1, and the first cascade signal output terminal CR output high-level signals first, followed by low-level signals. It should be noted that during the switching from low-level to high-level output signals at the first drive signal output terminal OUT2 and the second drive signal output terminal OUT1, the voltage at the first pull-up node PU1 is pulled up to a higher level under the bootstrap effect of the second capacitor C2 and the third capacitor C3; conversely, during the switching from high-level to low-level output signals at the first drive signal output terminal OUT2 and the second drive signal output terminal OUT1, the voltage at the first pull-up node PU1 is pulled down to the initial high-level state under the bootstrap effect of the second capacitor C2 and the third capacitor C3.

[0298] Display reset phase t3 (corresponding to) Figure 5In the p1 stage, the display signal input terminal INPUT1 provides a low-level signal, the sensing signal input terminal INPUT2 provides a high-level signal, the random signal input terminal OE provides a high-level signal, the clock control signal input terminal CLKA provides a low-level signal, the display reset signal input terminal RST provides a high-level signal, and the global reset signal input terminal T-RST provides a low-level signal.

[0299] Because the reset signal input terminal RST provides a high-level signal, the tenth transistor M10 is turned on. At this time, the low-level signal provided by the second power supply terminal is written to the first pull-up node PU1 through the tenth transistor M10. Simultaneously, because the random signal input terminal OE provides a high-level signal, the first transistor M1 is turned on. The high-level signal provided by the sensing signal input terminal INPUT2 is written to the sensing control node H through the first transistor. The sensing control node is in a high-level state, the second transistor is turned on, and the low-level signal provided by the clock control signal input terminal CLKA is written to the first pull-up node PU1 through the second transistor M2. Because the tenth transistor M10 and the second transistor M2 simultaneously write low-level signals to the first pull-up node PU1, the voltage at the first pull-up node PU1 can quickly drop to a low-level state.

[0300] At this time, the thirteenth transistor M13 is turned off, and the high-level signal provided by the fifth power supply terminal is written to the first pull-down node PD1 through the twelfth transistor M12. The first pull-down node PD1 is in a high-level state, and the fourteenth transistor M14, the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19 are all turned on.

[0301] Specifically, when the fourteenth transistor M14 is turned on, the low-level signal provided by the second power supply is written to the first pull-up node PU1 through the fourteenth transistor M14 to reduce noise in the first pull-up node PU1. When the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19 are all turned on, the low-level signal provided by the second power supply is written to the first drive signal output terminal OUT2 and the second drive signal output terminal OUT1 through the seventeenth transistor M17 and the eighteenth transistor M18, respectively. The low-level signal provided by the fourth power supply is written to the first cascaded signal output terminal CR through the nineteenth transistor M19. That is to say, the first drive signal output terminal OUT2, the second drive signal output terminal OUT1, and the first cascaded signal output terminal CR all output low-level signals.

[0302] During the sensing output stage t4, the display signal input terminal INPUT1 provides a low-level signal, the sensing signal input terminal INPUT2 provides a low-level signal, the random signal input terminal OE provides a low-level signal, the clock control signal input terminal CLKA provides a high-level signal, the display reset signal input terminal RST provides a low-level signal, and the global reset signal input terminal T-RST provides a low-level signal.

[0303] Since the voltage at the sensing control node H remains at the high level of the previous stage, the second transistor M2 remains on. The clock control signal input terminal CLKA provides a high-level signal, which is written to the first pull-up node PU1 through the second transistor M2. Because the first pull-up node PU1 is at a high level, the thirteenth transistor M13, the fifth transistor M5, the fifteenth transistor M15, and the sixteenth transistor M16 are all on. The low-level signal provided by the second power supply terminal is written to the first pull-down node PD1 through the thirteenth transistor M13.

[0304] The sensing output stage t4 can be divided into stage t41 (corresponding to...) Figure 5 (p21 stage) t42 stage (corresponding to) Figure 5 (p22 stage in the middle).

[0305] During stage t41, the first drive clock signal input terminal CLKE, the second drive clock signal input terminal CLKD, and the first cascade clock signal input terminal CLKC all provide low-level signals. At this time, the low-level signal provided by the first drive clock signal input terminal CLKE is written to the first drive signal output terminal OUT2 through the fifth transistor M5, the low-level signal provided by the second drive clock signal input terminal CLKD is written to the second drive signal output terminal OUT1 through the fifteenth transistor M15, and the low-level signal provided by the first cascade clock signal input terminal CLKC is written to the first cascade signal output terminal CR through the sixteenth transistor M16. In other words, the first drive signal output terminal OUT2, the second drive signal output terminal OUT1, and the first cascade signal output terminal CR all output low-level signals.

[0306] During stage t42, the first drive clock signal input terminal CLKE first provides a high-level signal and then a low-level signal, while the second drive clock signal input terminal CLKD and the first cascaded clock signal input terminal CLKC both provide low-level signals.

[0307] At this time, the second drive signal output terminal OUT1 and the first cascaded signal output terminal CR continuously output low-level signals, while the first drive signal output terminal OUT2 first outputs a high-level signal and then a low-level signal. Under the bootstrap effect of the second capacitor C2, the voltage at the first pull-up node PU1 is first pulled up and then pulled down.

[0308] Then it enters the global reset phase t0 of the next frame. In the global reset phase t0 of the next frame (corresponding to...) Figure 5 In the p4 stage, the voltages at the sensing control node H and the first pull-up node are both reset to a low level.

[0309] The thirteenth transistor M13 is turned off, and the high-level signal provided by the fifth power supply terminal is written to the first pull-down node PD1 through the twelfth transistor M12. The first pull-down node PD1 is in a high-level state, and the fourteenth transistor M14, the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19 are all turned on.

[0310] Specifically, when the fourteenth transistor M14 is turned on, the low-level signal provided by the second power supply is written to the first pull-up node PU1 through the fourteenth transistor M14 to reduce noise in the first pull-up node PU1. When the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19 are all turned on, the low-level signal provided by the second power supply is written to the first drive signal output terminal OUT2 and the second drive signal output terminal OUT1 through the seventeenth transistor M17 and the eighteenth transistor M18, respectively. The low-level signal provided by the fourth power supply is written to the first cascaded signal output terminal CR through the nineteenth transistor M19. That is to say, the first drive signal output terminal OUT2, the second drive signal output terminal OUT1, and the first cascaded signal output terminal CR all output low-level signals.

[0311] In this embodiment of the disclosure, the first cascaded clock signal input terminal CLKC and the second drive clock signal input terminal CLKD can input the same clock signal, so they can be the same clock signal input terminal.

[0312] In related technologies, the global reset signal input terminal T-RST is generally connected to the frame start signal input terminal (also known as the STV terminal, used to provide the frame start signal, representing the start of a frame) in the display panel, that is, the frame start signal is used as the global reset signal. In the power-off scenario, after the sensing output stage t4 of the last frame ends, if the effective level signal provided by the global reset signal input terminal T-RST is directly used to control the first global reset circuit to sense and reset the first pull-up node PU1, it will cause the first display input circuit 7 of the first stage or several stages of shift register units (the specific number is preset according to actual needs, and the first stage or several stages of shift register units are generally used as dummy GOA) connected to the frame start signal input terminal in the gate drive circuit to precharge the corresponding first pull-up node. In other words, after power-off, the first pull-up node in the first stage or several stages of the shift register unit will be in an active level state. The transistors whose control electrodes are connected to the first pull-up node (such as the fifth transistor M5, the fifteenth transistor M6, and the sixteenth transistor M7) will be in a high-voltage (stress) state for a long time and the transistor electrical characteristics (such as threshold voltage) will drift, which will reduce the reliability of the shift register unit.

[0313] To address the aforementioned issues, the present disclosure provides a new operating timing for a shift register unit.

[0314] Figure 12 for Figure 10 Another timing diagram of the shift register unit shown is as follows: Figure 12 As shown, Figure 12 The working process shown includes not only Figure 11 The global reset phase t0, display input phase t1, display output phase t2, display reset phase t3, and sensing output phase t4, and also the sensing reset phase t5 (corresponding to) after the sensing output phase t4 and before the global reset phase t0 of the next frame. Figure 5 (P3 stage in the process). The following only describes the sensing reset stage t5 in detail.

[0315] During the sensing reset phase t5 (corresponding to) Figure 5 In the p3 stage, the display signal input terminal INPUT1 provides a low-level signal, the sensing signal input terminal INPUT2 provides a low-level signal, the random signal input terminal OE provides a low-level signal, the clock control signal input terminal CLKA provides a low-level signal, the display reset signal input terminal RST provides a low-level signal, and the global reset signal input terminal T-RST provides a low-level signal.

[0316] Since the second transistor M2 remains on, the low-level signal provided by the clock control signal input terminal CLKA can be written to the first pull-up node PU1 through the second transistor M2.

[0317] and Figure 8 The difference in the working process shown is that, in Figure 12 During the operation shown, the voltage at the first pull-up node PU1 can be reset within the frame by sensing the reset phase t5.

[0318] In the power-off scenario, after the sensing output phase t4 of the last frame ends, a sensing reset phase t5 is performed first to reset the voltage at the first pull-up node PU1 (i.e., to perform a sensing reset on the first pull-up node). Then, the valid level signal provided by the random signal input terminal OE controls the sensing control circuit 1 to write an invalid level signal to the sensing control node H in order to reset the sensing control node H.

[0319] It should be noted that although the technical solution of this disclosure can reset the first pull-up node PU1 after the sensing output stage by setting the above-mentioned "sensing reset stage t5" and relying on the invalid level signal provided by the clock control signal input terminal CLKA, it has high requirements for the circuit structure of the first sensing input circuit 2 (for example, under certain circuit structures, the invalid level signal provided by the clock control signal input terminal CLKA cannot be output to the first pull-up node PU1) and the precise control of the signal provided by the clock control signal input terminal CLKA, which makes the product reliability low.

[0320] To this end, this disclosure provides a new shift register unit. By adding a first sensing reset circuit 3 to the shift register unit, the reliability of the shift register unit in resetting the first pull-up node PU2 during the sensing reset phase t5 can be effectively improved.

[0321] Figure 13 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 13 As shown, Figure 13 The provided shift register unit includes not only the sensing control circuit 1, the first sensing input circuit 2, and the first driving output circuit 5 in the previous embodiments, but also the first sensing reset circuit 3. The first sensing reset circuit 3 will be described in detail below.

[0322] The first sensing reset circuit 3 is connected to the sensing reset signal input terminal S-RST, the sensing control node H, the first pull-up node PU1, and the second power supply terminal. The first sensing reset circuit 3 is configured to write the ineffective level signal provided by the second power supply terminal to the first pull-up node in response to the control of the signal provided by the sensing reset signal input terminal S-RST and the effective level signal at the sensing control node H.

[0323] It should be noted that the first sensing reset circuit 3 in this embodiment operates at... Figure 5 p3 stage and Figure 9 The sensing reset phase t5 in the process.

[0324] Figure 14 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 14 As shown, as a sensing reset scheme, the first sensing reset circuit 3 includes: a first sensing reset control circuit 301 and a first switching circuit 302.

[0325] The first sensing reset control circuit 301 is connected to the sensing reset signal input terminal S-RST, the sensing control node H, the first sensing reset control node RSC1, and the second power supply terminal. The first sensing reset control circuit 301 is configured to write the valid level signal at the sensing control node H to the first sensing reset control node RSC1 in response to the control of the inactive level signal provided by the sensing reset signal input terminal S-RST and the valid level signal at the sensing control node H.

[0326] The first switching circuit 302 is connected to the first sensing reset control node RSC1, the first pull-up node PU1, and the second power supply terminal. The first switching circuit 302 is configured to form a path between the second power supply terminal and the first pull-up node PU1 in response to the control of an effective level signal at the first sensing reset control node RSC1, and to form an open circuit between the second power supply terminal and the first pull-up node PU1 in response to the control of an ineffective level signal at the first sensing reset control node RSC1.

[0327] In other words, Figure 14 In the scheme shown, when the sensing reset signal input terminal S-RST provides an invalid level signal and the sensing control node H provides an valid level signal, the first sensing reset control node RSC1 can provide a valid level signal, the first switch circuit 302 is turned on, and the invalid level signal provided by the second power supply terminal can be written to the first pull-up node PU1 through the first switch circuit 302 to reset the first pull-up node.

[0328] In some embodiments, the first sensing reset control circuit 301 includes a seventy-first transistor M71 and a seventy-second transistor M72, and the first switching circuit 302 includes a seventy-third transistor M73.

[0329] The control electrode and the first electrode of the seventy-first transistor M71 are both connected to the sensing control node H, and the second electrode of the seventy-first transistor M71 is connected to the first sensing reset control node RSC1.

[0330] The control electrode of the 72nd transistor M72 is connected to the sensing reset signal input terminal S-RST, the first electrode of the 72nd transistor M72 is connected to the first sensing reset control node RSC1, and the second electrode of the 72nd transistor M72 is connected to the second power supply terminal.

[0331] The control electrode of the 73rd transistor M73 is connected to the first sensing reset control node RSC1, the first electrode of the 73rd transistor M73 is connected to the first pull-up node PU1, and the second electrode of the 73rd transistor M73 is connected to the second power supply terminal.

[0332] Figure 15 for Figure 14 The following is a timing diagram of one type of shift register unit, as shown: Figure 15 As shown, for a detailed description of the sensing control circuit 1, the first sensing input circuit 2, and the first drive output circuit 5 in stages p1 to p4, please refer to the previous description. Figure 5 The following is a detailed description of the operation of the first sensing reset circuit 3 and the sensing reset signal input terminal S-RST at each stage.

[0333] Specifically, in the p3 stage, the S-RST input terminal of the sensing reset signal provides an inactive level signal (e.g., a low level signal), while in other stages, the S-RST input terminal of the sensing reset signal provides an active level signal (e.g., a high level signal).

[0334] In the p3 stage, since the sensing reset signal input terminal S-RST provides an inactive level signal, the seventy-second transistor M72 is in the off state. At this time, the active level signal at the sensing control node can be provided to the seventy-first transistor M71 to be written to the first sensing reset control node RSC1. Correspondingly, the seventy-third transistor M73 is turned on, and the inactive level signal provided by the second power supply terminal is written to the first pull-up node through the seventy-third transistor M73 to reset the first pull-up node.

[0335] It should be noted that when Figure 14 The shift register unit in the middle adopts Figure 12 In the operating timing shown, the sensing reset signal input terminal S-RST is only used during the sensing reset phase t5 (corresponding to...). Figure 15The p3 stage provides an inactive signal level, while the other stages provide an active signal level.

[0336] Figure 16 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 16 As shown, as Figure 14 The first sensing reset circuit 3 shown in the figure has a leakage protection design. In some embodiments, the shift register unit further includes: a first voltage control circuit 14 and a first sensing reset leakage protection circuit 51.

[0337] The first voltage control circuit 14 is connected to the third power supply terminal, the first pull-up node PU1, and the first voltage control node OFF1. The first voltage control circuit 14 is configured to write the effective level signal provided by the third power supply terminal to the first voltage control node OFF1 in response to the control of the effective level signal at the first pull-up node PU1.

[0338] The first switching circuit 302 is connected to the second power supply terminal through the first sensing reset leakage protection circuit 51. The first switching circuit and the first sensing reset leakage protection circuit 51 are connected to the first sensing reset leakage protection node RQ1. The first sensing reset leakage protection node RQ1 is connected to the first voltage control node OFF1.

[0339] The first sensing reset leakage protection circuit 51 is connected to the first sensing reset control node RSC1. The first sensing reset leakage protection circuit 51 is configured to form a path between the first sensing reset leakage protection node RQ1 and the second power supply terminal in response to the control of the effective level signal at the first sensing reset control node RSC1, and to form an open circuit between the first sensing reset leakage protection node RQ1 and the second power supply terminal in response to the control of the control of the ineffective level signal at the first sensing reset control node RSC1.

[0340] In some embodiments, the first voltage control circuit 14 includes: a twentieth transistor M20; the control electrode of the twentieth transistor M20 is connected to the first pull-up node PU1, the first electrode of the twentieth transistor M20 is connected to the third power supply terminal, and the second electrode of the twentieth transistor M20 is connected to the first voltage control node OFF1.

[0341] The first sensing reset leakage protection circuit 51 includes: a seventy-fourth transistor M74; the control terminal of the seventy-fourth transistor M74 is connected to the first sensing reset control node RSC1, the first terminal of the seventy-fourth transistor M74 is connected to the first sensing reset leakage protection node RQ1, and the second terminal of the seventy-fourth transistor M74 is connected to the second power supply terminal.

[0342] Figure 17A This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure. Figure 17BThis is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 17A Book Figure 17B As shown, as another sensing reset scheme, in some embodiments, the first sensing reset circuit 3 includes: a second switch circuit 303 and a third switch circuit 304 connected in series between the first pull-up node PU1 and the second power supply terminal, wherein the second switch circuit 303 is located between the third switch circuit 304 and the first pull-up node PU1.

[0343] One of the second switching circuit 303 and the third switching circuit 304 is connected to the sensing reset signal input terminal S-RST, and the other is connected to the sensing control node H.

[0344] The second switching circuit 303 and the third switching circuit 304 are configured to, in response to the control of the valid level signal provided by the sensing reset signal input terminal S-RST and the valid level signal at the sensing control node, enable the second power supply terminal to form a path with the first pull-up node PU1, and in response to the control of the control of the low level signal provided by at least one of the sensing reset signal input terminal S-RST and the sensing control node H, enable the second power supply terminal to form an open circuit with the first pull-up node PU1.

[0345] in, Figure 17A The diagram illustrates the connection between the second switch circuit 303 and the sensing reset signal input terminal S-RST, and the connection between the third switch circuit 303 and the sensing control node H. Figure 17B The diagram illustrates the connection between the second switching circuit 303 and the sensing reset signal input terminal S-RST, and the connection between the third switching circuit 304 and the sensing control node H.

[0346] In other words, Figure 17A and Figure 17B In the scheme shown, when the sensing reset signal input terminal S-RST provides a valid level signal and the sensing control node H provides a valid level signal, both the second switch circuit 303 and the third switch circuit 304 are turned on. The invalid level signal provided by the second power supply terminal can be written to the first pull-up node PU1 through the second switch circuit 303 and the third switch circuit 304 to reset the first pull-up node.

[0347] In some embodiments, the second switching circuit 303 includes a seventy-first transistor M71, and the third switching circuit 304 includes a seventy-second transistor M72. The control electrode of one of the seventy-first transistor M71 and the seventy-second transistor M72 is connected to the sensing reset signal input terminal S-RST, and the control electrode of the other is connected to the sensing control node H. The first electrode of the seventy-first transistor M71 is connected to the first pull-up node, the second electrode of the seventy-first transistor M71 is connected to the first electrode of the seventy-second transistor M72, and the second electrode of the seventy-second transistor M72 is connected to the second power supply terminal.

[0348] Figure 18A This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure. Figure 18B This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 18A and Figure 18B As shown, as Figure 17A and Figure 17B The first sensing reset circuit 3 shown in the figure has a leakage protection design. In some embodiments, the shift register unit further includes: a first voltage control circuit 14 and a first sensing reset leakage protection circuit 51.

[0349] The first voltage control circuit 14 is connected to the third power supply terminal, the first pull-up node PU1, and the first voltage control node OFF1. The first voltage control circuit 14 is configured to write the effective level signal provided by the third power supply terminal to the first voltage control node OFF1 in response to the control of the effective level signal at the first pull-up node PU1.

[0350] See Figure 18A As shown, the second switch circuit 303 is connected to the sensing reset signal input terminal S-RST. The second switch circuit 303 is connected to the third switch circuit 304 through the first sensing reset leakage protection circuit 51. The second switch circuit 303 and the first sensing reset leakage protection circuit 51 are connected to the first sensing reset leakage protection node RQ1. The first sensing reset leakage protection node RQ1 is connected to the first voltage control node OFF1.

[0351] The first sensing reset leakage protection circuit 51 is connected to the sensing reset signal input terminal S-RST. The first sensing reset leakage protection circuit 51 is configured to form a path between the first sensing reset leakage protection node RQ1 and the third switch circuit 304 in response to the control of the effective level signal at the sensing reset signal input terminal S-RST, and to form an open circuit between the first sensing reset leakage protection node RQ1 and the third switch circuit 304 in response to the control of the ineffective level signal at the sensing reset signal input terminal S-RST.

[0352] See Figure 18BAs shown, the third switch circuit 304 is connected to the sensing reset signal input terminal S-RST. The third switch circuit 304 is connected to the second power supply terminal through the first sensing reset leakage protection circuit 51. The third switch circuit 304 and the first sensing reset leakage protection circuit 51 are connected to the first sensing reset leakage protection node RQ1. The first sensing reset leakage protection node RQ1 is connected to the first voltage control node OFF1.

[0353] The first sensing reset leakage protection circuit 51 is connected to the sensing reset signal input terminal S-RST. The first sensing reset leakage protection circuit 51 is configured to form a path between the first sensing reset leakage protection node RQ1 and the second power supply terminal in response to the control of the effective level signal at the sensing reset signal input terminal S-RST, and to form an open circuit between the first sensing reset leakage protection node RQ1 and the second power supply terminal in response to the control of the ineffective level signal at the sensing reset signal input terminal S-RST.

[0354] In some embodiments, the first voltage control circuit 14 includes: a twentieth transistor M20, the control electrode of the twentieth transistor M20 is connected to the first pull-up node PU1, the first electrode of the twentieth transistor M20 is connected to the third power supply terminal, and the second electrode of the twentieth transistor M20 is connected to the first voltage control node OFF1.

[0355] The first sensing reset leakage protection circuit 51 includes: a seventy-fourth transistor M74, the control electrode of the seventy-fourth transistor M74 is connected to the sensing reset signal input terminal S-RST, and the first electrode of the seventy-fourth transistor M74 is connected to the first sensing reset leakage protection node RQ1.

[0356] See Figure 18A As shown, when the second switch circuit 303 is connected to the sensing reset signal input terminal S-RST, the second terminal of the seventy-fourth transistor M74 is connected to the third switch circuit 304.

[0357] See Figure 18B As shown, when the third switch circuit 304 is connected to the sensing reset signal input terminal S-RST, the second terminal of the seventy-fourth transistor M74 is connected to the second power supply terminal.

[0358] Figure 19 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 19 As shown, in some embodiments, when the shift register unit includes a first global reset circuit 6, a first display reset circuit 8, and a first pull-up noise reduction circuit 12, leakage protection design can be performed for at least one of the first global reset circuit 6, the first display reset circuit 8, and the first pull-up noise reduction circuit 12.

[0359] In some embodiments, the shift register unit includes a first voltage control circuit 14; the first voltage control circuit 14 is connected to a third power supply terminal, a first pull-up node PU1, and a first voltage control node OFF1, and the first voltage control circuit 14 is configured to write the valid level signal provided by the valid level supply terminal to the first voltage control node OFF1 in response to the control of the valid level signal at the first pull-up node PU1.

[0360] The shift register unit also includes at least one of a first leakage protection circuit 15, a second leakage protection circuit 16, and a third leakage protection circuit 17.

[0361] The first global reset circuit 6 is connected to the second power supply terminal through the first leakage protection circuit 15. The first global reset circuit 6 and the first leakage protection circuit 15 are connected to the first leakage protection node Q1. The first leakage protection node Q1 is connected to the first voltage control node OFF1. The first leakage protection circuit 15 is connected to the global reset signal input terminal T-RST. The first leakage protection circuit 15 is configured to form a path between the first leakage protection node Q1 and the second power supply terminal in response to the control of the valid level signal provided by the global reset signal input terminal T-RST, and to disconnect the circuit between the first leakage protection node Q1 and the second power supply terminal in response to the control of the invalid level signal provided by the global reset signal input terminal T-RST.

[0362] The first display reset circuit 8 is connected to the second power supply terminal through the first leakage protection circuit 16. The first display reset circuit 8 and the first leakage protection circuit 16 are connected to the second leakage protection node Q2. The second leakage protection node Q2 is connected to the first voltage control node OFF1. The first leakage protection circuit 16 is connected to the display reset signal input terminal RST. The first leakage protection circuit 16 is configured to form a path between the second leakage protection node Q2 and the second power supply terminal in response to the control of the valid level signal provided by the display reset signal input terminal RST, and to disconnect the second leakage protection node Q2 and the second power supply terminal in response to the control of the invalid level signal provided by the display reset signal input terminal RST.

[0363] The first pull-up noise reduction circuit 12 is connected to the second power supply terminal through the third leakage protection circuit 17. The first pull-up noise reduction circuit 12 and the third leakage protection circuit 17 are connected to the third leakage protection node Q3. The third leakage protection node Q3 is connected to the first voltage control node OFF1. The third leakage protection circuit 17 is connected to the first pull-down node PD1. The third leakage protection circuit 17 is configured to form a path between the third leakage protection node Q3 and the second power supply terminal in response to the control of the effective level signal at the first pull-down node PD1, and to disconnect the circuit between the third leakage protection node Q3 and the second power supply terminal in response to the control of the ineffective level signal at the first pull-down node PD1.

[0364] The third power supply terminal provides an active level signal; as an example, the third power supply terminal provides a high-level voltage VDD1.

[0365] In some embodiments, the first voltage control circuit 14 includes a twentieth transistor M20, the control electrode of the twentieth transistor M20 is connected to the first pull-up node PU1, the first electrode of the twentieth transistor M20 is connected to the effective level supply terminal, and the second electrode of the twentieth transistor M20 is connected to the first voltage control node OFF1.

[0366] In some embodiments, the first leakage protection circuit 15 includes a twenty-first transistor M21, the control electrode of the twenty-first transistor M21 is connected to the global reset signal input terminal T-RST, the first electrode of the twenty-first transistor M21 is connected to the first leakage protection node Q1, and the second electrode of the twenty-second transistor M22 is connected to the second power supply terminal.

[0367] In some embodiments, the first leakage protection circuit 16 includes a 22nd transistor M22, the control electrode of the 22nd transistor M22 is connected to the display reset signal input terminal RST, the first electrode of the 22nd transistor M22 is connected to the second leakage protection node Q2, and the second electrode of the 22nd transistor M22 is connected to the second power supply terminal.

[0368] In some embodiments, the third leakage protection circuit 17 includes: a twenty-third transistor M23, the control electrode of the twenty-third transistor M23 is connected to the first pull-down node PD1, the first electrode of the twenty-third transistor M23 is connected to the third leakage protection node Q3, and the second electrode of the twenty-third transistor M23 is connected to the second power supply terminal.

[0369] It should be noted that, Figure 19 The example provided illustrates a shift register unit that simultaneously includes a first leakage protection circuit 15, a first leakage protection circuit 16, and a third leakage protection circuit 17. In practical applications, at least one of the first leakage protection circuit 15, the first leakage protection circuit 16, and the third leakage protection circuit 17 can be configured according to actual needs.

[0370] See also Figure 19 As shown, in some embodiments, the shift register unit further includes a first pull-down noise reduction circuit 18 and / or a second pull-down noise reduction circuit 19.

[0371] The first pull-down noise reduction circuit 18 is connected to the first pull-down node PD1, the second power supply terminal, the sensing control node H, and the clock control signal input terminal CLKA. The first pull-down noise reduction circuit 18 is configured to write the ineffective level signal provided by the second power supply terminal to the first pull-down node PD1 in response to the control of the effective level signal at the sensing control node H and the effective level signal provided by the clock control signal input terminal CLKA, so as to perform noise reduction processing on the output voltage of the first pull-down node PD1.

[0372] The second pull-down noise reduction circuit 19 is connected to the first pull-down node PD1, the second power supply terminal, and the sensing signal input terminal INPUT2. The second pull-down noise reduction circuit 19 is configured to write the ineffective level signal provided by the second power supply terminal to the first pull-down node PD1 in response to the control of the effective level signal provided by the sensing signal input terminal INPUT2, so as to perform noise reduction processing on the output voltage of the first pull-down node PD1.

[0373] In some embodiments, the first pull-down noise reduction circuit 18 includes a twenty-ninth transistor M29 and a thirtieth transistor M30, and the second pull-down noise reduction circuit 19 includes a thirty-first transistor M31.

[0374] Among them, the control terminal of the twenty-ninth transistor M29 is connected to the clock control signal input terminal CLKA, the first terminal of the twenty-ninth transistor M29 is connected to the first pull-down node PD1, and the second terminal of the twenty-ninth transistor M29 is connected to the first terminal of the thirtieth transistor M30.

[0375] The control electrode of the thirtieth transistor M30 is connected to the sensing control node H, and the second electrode of the thirtieth transistor M30 is connected to the second power supply terminal.

[0376] The control electrode of the thirty-first transistor M31 is connected to the sensing signal input terminal INPUT2, the first electrode of the thirty-first transistor M31 is connected to the first pull-down node PD1, and the second electrode of the thirty-first transistor M31 is connected to the second power supply terminal.

[0377] Figure 20 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 20 As shown, Figure 20 The shift register unit shown includes not only the first display input circuit 7, the second drive output circuit 9, and the first cascaded output circuit 13 in the previous embodiment, but also: the second sensing input circuit 23, the second display input circuit 27, the third drive output circuit 25, and the fourth drive output circuit 29.

[0378] The second sensing input circuit 23 is connected to the sensing control node H, the clock control signal input terminal CLKA, and the second pull-up node PU2. The second sensing input circuit is configured to write the signal provided by the clock control signal input terminal CLKA to the second pull-up node PU2 in response to the control of the effective level signal at the sensing control node H.

[0379] The second display input circuit 27 is connected to the display signal input terminal INPUT1 and the second pull-up node PU2. The second display input circuit 27 is configured to write the valid level signal to the second pull-up node PU2 in response to the control of the valid level signal provided by the display signal input terminal INPUT1.

[0380] The third drive output circuit 25 is connected to the second pull-up node PU2, the third drive clock signal input terminal CLKE', and the third drive signal output terminal. The third drive output circuit 25 is configured to write the signal provided by the third drive clock signal input terminal CLKE' to the third drive signal output terminal in response to the control of the effective level signal at the second pull-up node PU2.

[0381] The fourth drive output circuit 29 is connected to the second pull-up node PU2, the fourth drive clock signal input terminal CLKD', and the fourth drive signal output terminal. The fourth drive output circuit 29 is configured to write the signal provided by the fourth drive clock signal input terminal CLKD' to the fourth drive signal output terminal in response to the control of the effective level signal at the second pull-up node PU2.

[0382] In this embodiment, the first drive output circuit 5 and the second drive output circuit 9 can respectively provide corresponding drive signals to the two gate lines G2 and G1 configured in a certain row of pixel units in the display panel. Simultaneously, the third drive output circuit 25 and the fourth drive output circuit 29 can respectively provide corresponding drive signals to the two gate lines G2 and G1 configured in another row of pixel units in the display panel. That is, the shift register unit provided in this embodiment can be used to drive four gate lines configured in two rows of pixel units (e.g., two adjacent rows of pixel units). This design effectively reduces the number of stages in the shift register unit within the gate drive circuit, reduces the size occupied by the gate drive circuit, and is beneficial for narrow bezel design of the product.

[0383] Figure 21 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 21 As shown, in some embodiments, the second sensing input circuit 23 includes: a thirty-second transistor M32; the control electrode of the thirty-second transistor M32 is connected to the sensing control node H, the first electrode of the thirty-second transistor M32 is connected to the clock control signal input terminal CLKA, and the second electrode of the thirty-second transistor M32 is connected to the second pull-up node PU2.

[0384] Figure 22 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 22 As shown, as a leakage protection design for the second sensing input circuit 23, in some embodiments, a first sensing input leakage protection circuit 41 is configured in the first sensing input circuit 2 (e.g., using...). Figure 7 In the circuit structure shown, the second sensing input circuit 23 is connected to the first sensing input leakage protection node IQ1, so as to be connected to the clock control signal input terminal CLKA through the first sensing input leakage protection node IQ1 and the first sensing input leakage protection circuit 41.

[0385] In other words, the first sensing input circuit 2 and the second sensing input circuit 23 share the same leakage protection structure, which helps to simplify the circuit structure of the shift register unit.

[0386] Figure 23 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 23 As shown, as another leakage protection design for the second sensing input circuit 23, in some embodiments, the shift register unit includes a second cascaded output circuit 22. The second cascaded output circuit 22 is connected to the second pull-up node PU2, the second cascaded clock signal input terminal CLKC', and the second cascaded signal output terminal CR'. The second cascaded output circuit 22 is configured to write the signal provided by the second cascaded clock signal input terminal CLKC' to the second cascaded signal output terminal CR' in response to the control of the effective level signal at the second pull-up node PU2.

[0387] The shift register unit also includes: a second sensing input leakage protection circuit 42, a second sensing input circuit 23 connected to the clock control signal input terminal CLKA through the second sensing input leakage protection circuit 42, and the second sensing input circuit 23 and the second sensing input leakage protection circuit 42 connected to the second sensing input leakage protection node IQ2.

[0388] The second sensing input leakage protection circuit 42 is connected to the preset input control signal input terminal CLKB and the second cascaded signal output terminal CR'. The second sensing input leakage protection circuit 42 is configured to form a path between the second sensing input leakage protection node IQ2 and the clock control signal input terminal CLKA in response to the control of the valid level signal provided by the preset input control signal input terminal CLKB, and to disconnect the second sensing input leakage protection node IQ2 and the clock control signal input terminal CLKA in response to the control of the invalid level signal provided by the preset input control signal input terminal CLKB, and to write the valid level signal to the second sensing input leakage protection node IQ2 in response to the control of the valid level signal provided by the second cascaded signal output terminal CR' when the second sensing input leakage protection node IQ2 and the clock control signal input terminal CLKA are disconnected.

[0389] In some embodiments, the second sensing input leakage protection circuit 42 includes: a thirty-third transistor M33 and a thirty-fourth transistor M34;

[0390] The control electrode of the 33rd transistor M33 is connected to the preset input control signal input terminal CLKB, the first electrode of the 33rd transistor M33 is connected to the clock control signal input terminal CLKA, and the second electrode of the 33rd transistor M33 is connected to the second sensing input leakage protection node IQ2.

[0391] The control electrode and the first electrode of the thirty-fourth transistor M34 are both connected to the second cascaded signal output terminal CR', and the second electrode of the thirty-fourth transistor M34 is connected to the second sensing input leakage protection node IQ2.

[0392] Similarly, to improve the reliability of the shift register unit in resetting the second pull-up node PU2 during the sensing reset phase t5, the technical solution of this disclosure includes a second sensing reset circuit 4 within the shift register unit.

[0393] Figure 24 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 24 As shown, in some embodiments, the shift register unit further includes a second sensing reset circuit 4, wherein the circuit structure of the second sensing reset circuit needs to correspond to the circuit structure of the first sensing reset circuit.

[0394] See Figure 24 As shown, the first sensing reset circuit 3 includes a first sensing reset control circuit 301 and a first switching circuit 302 (i.e., the first sensing reset circuit 3 adopts...). Figure 14 As shown in the figure, the second sensing reset circuit 4 includes: a second sensing reset control circuit 401 and a fourth switching circuit 402.

[0395] The second sensing reset control circuit 401 is connected to the sensing reset signal input terminal S-RST, the sensing control node H, the second sensing reset control node RSC2, and the second power supply terminal. The second sensing reset control circuit 401 is configured to write the valid level signal at the sensing control node H to the second sensing reset control node RSC2 in response to the control of the inactive level signal provided by the sensing reset signal input terminal S-RST and the valid level signal at the sensing control node H.

[0396] The fourth switching circuit 402 is connected to the second sensing reset control node RSC2, the second pull-up node PU2, and the second inactive level supply terminal. The fourth switching circuit 402 is configured to form a path between the second inactive level supply terminal and the second pull-up node PU2 in response to the control of the active level signal at the second sensing reset control node RSC2, and to form an open circuit between the second inactive level supply terminal and the second pull-up node PU2 in response to the control of the inactive level signal at the second sensing reset control node RSC2.

[0397] In other words, Figure 24 In the scheme shown, when the sensing reset signal input terminal S-RST provides an inactive level signal and the sensing control node H provides an active level signal, the second sensing reset control node RSC2 can provide an active level signal, the fourth switch circuit 402 is turned on, and the inactive level signal of the second inactive level supply terminal can be written to the second pull-up node PU2 through the fourth switch circuit 402 to reset the second pull-up node PU2.

[0398] In some embodiments, the second sensing reset control circuit 401 includes an eighty-first transistor M81 and an eighty-second transistor M82, and the fourth switching circuit 402 includes an eighty-third transistor M83.

[0399] The control electrode and the first electrode of the 81st transistor M81 are both connected to the sensing control node H, and the second electrode of the 81st transistor M81 is connected to the second sensing reset control node RSC2.

[0400] The control electrode of the 82nd transistor M82 is connected to the sensing reset signal input terminal S-RST, the first electrode of the 82nd transistor M82 is connected to the second sensing reset control node RSC2, and the second electrode of the 82nd transistor M82 is connected to the second power supply terminal.

[0401] The control electrode of the 83rd transistor M83 is connected to the second sensing reset control node RSC2, the first electrode of the 83rd transistor M83 is connected to the second pull-up node PU2, and the second electrode of the 83rd transistor M83 is connected to the second inactive level supply terminal.

[0402] Figure 25This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 25 As shown, as Figure 24 The second sensing reset circuit 4 shown in the figure has a leakage protection design. In some embodiments, the shift register unit further includes: a second voltage control circuit 34 and a second sensing reset leakage protection circuit 52.

[0403] At this time, the second inactive level supply terminal is the second power supply terminal, and the second power supply terminal provides an inactive level signal.

[0404] The second voltage control circuit 34 is connected to the third power supply terminal, the second pull-up node PU2, and the second voltage control node OFF2. The second voltage control circuit 34 is configured to write the effective level signal provided by the third power supply terminal to the second voltage control node OFF2 in response to the control of the effective level signal at the second pull-up node PU2.

[0405] The fourth switching circuit 402 is connected to the second power supply terminal through the second sensing reset leakage protection circuit 52. The fourth switching circuit 402 and the second sensing reset leakage protection circuit 52 are connected to the second sensing reset leakage protection node RQ2. The second sensing reset leakage protection node RQ2 is connected to the second voltage control node OFF2.

[0406] The second sensing reset leakage protection circuit 52 is connected to the second sensing reset control node RSC2. The second sensing reset leakage protection circuit 52 is configured to form a path between the second sensing reset leakage protection node RQ2 and the second power supply terminal in response to the control of the effective level signal at the second sensing reset control node RSC2, and to form an open circuit between the second sensing reset leakage protection node RQ2 and the second power supply terminal in response to the control of the control of the ineffective level signal at the second sensing reset control node RSC2.

[0407] In some embodiments, the control electrode of the fiftieth transistor M50 is connected to the second pull-up node PU2, the first electrode of the fiftieth transistor M50 is connected to the third power supply terminal, and the second electrode of the fiftieth transistor M50 is connected to the second control voltage node OFF2.

[0408] The second sensing reset leakage protection circuit 52 includes: an eighty-fourth transistor M84; the control terminal of the eighty-fourth transistor M84 is connected to the second sensing reset control node RSC2, the first terminal of the eighty-fourth transistor M84 is connected to the second sensing reset leakage protection node RQ2, and the second terminal of the eighty-fourth transistor M84 is connected to the second power supply terminal.

[0409] Figure 26 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 26 As shown, as Figure 24Another leakage protection design for the second sensing reset circuit 4 shown in the diagram involves a shift register containing the aforementioned first voltage control circuit 14, with the second inactive level supply terminal being the first voltage control node connected to the first voltage control circuit 14. In other words, the fourth switching circuit 402 can share the leakage protection design with other structures, which simplifies the circuit structure.

[0410] Figure 27A This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure. Figure 27B This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 27A and Figure 27B As shown, the shift register unit includes a first sensing reset circuit 3, and the first sensing reset circuit 3 includes a second switching circuit 303 and a third switching circuit 304 (i.e., the first sensing reset circuit 3 adopts...). Figure 17A and Figure 17B (As shown in the diagram). At this time, the second sensing reset circuit 4 includes a fifth switch circuit 403 and a sixth switch circuit 404 connected in series between the second pull-up node PU2 and the second power supply terminal.

[0411] The fifth switch circuit 403 is located between the sixth switch circuit 404 and the second pull-up node PU2;

[0412] One of the fifth switch circuit 403 and the sixth switch circuit 404 is connected to the sensing reset signal input terminal S-RST, and the other is connected to the sensing control node H;

[0413] The fifth switch circuit 403 and the sixth switch circuit 404 are configured to, in response to the control of the valid level signal provided by the sensing reset signal input terminal S-RST and the valid level signal at the sensing control node H, enable the second power supply terminal to form a path with the second pull-up node PU2, and in response to the control of the control of the low level signal provided by at least one of the sensing reset signal input terminal S-RST and the sensing control node H, enable the second power supply terminal to form an open circuit with the second pull-up node PU2.

[0414] In some embodiments, the fifth switching circuit 403 includes an eighty-first transistor M81, and the sixth switching circuit 404 includes an eighty-second transistor M82; the control electrode of one of the eighty-first transistor M81 and the eighty-second transistor M82 is connected to the sensing reset signal input terminal S-RST, and the control electrode of the other is connected to the sensing control node H; the first electrode of the eighty-first transistor M81 is connected to the second pull-up node PU2, the second electrode of the eighty-first transistor M81 is connected to the first electrode of the eighty-second transistor M82, and the second electrode of the eighty-second transistor M82 is connected to the second power supply terminal.

[0415] Figure 28AThis is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure. Figure 28B This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure. As a leakage protection design for the second sensing reset circuit 4, in some embodiments, the shift register unit further includes: a second voltage control circuit 34 and a second sensing reset leakage protection circuit 52.

[0416] The second voltage control circuit 34 is connected to the third power supply terminal, the second pull-up node PU2, and the second voltage control node OFF2. The second voltage control circuit 34 is configured to write the effective level signal provided by the third power supply terminal to the second voltage control node OFF2 in response to the control of the effective level signal at the second pull-up node PU2.

[0417] As an optional option, see Figure 28A As shown, the fifth switch circuit 403 is connected to the sensing reset signal input terminal S-RST. The fifth switch circuit 403 is connected to the sixth switch circuit 404 through the second sensing reset leakage protection circuit 52. The fifth switch circuit 403 and the second sensing reset leakage protection circuit 52 are connected to the second sensing reset leakage protection node RQ2. The second sensing reset leakage protection node RQ2 is connected to the second voltage control node OFF2.

[0418] The second sensing reset leakage protection circuit 52 is connected to the sensing reset signal input terminal S-RST. The second sensing reset leakage protection circuit 52 is configured to form a path between the second sensing reset leakage protection node RQ2 and the sixth switch circuit 404 in response to the control of the effective level signal at the sensing reset signal input terminal S-RST, and to form an open circuit between the second sensing reset leakage protection node RQ2 and the sixth switch circuit 404 in response to the control of the ineffective level signal at the sensing reset signal input terminal S-RST.

[0419] As another alternative, see Figure 28B As shown, the sixth switch circuit 404 is connected to the sensing reset signal input terminal S-RST. The sixth switch circuit 404 is connected to the second power supply terminal through the second sensing reset leakage protection circuit 52. The sixth switch circuit 404 and the second sensing reset leakage protection circuit 52 are connected to the second sensing reset leakage protection node RQ2. The second sensing reset leakage protection node RQ2 is connected to the second voltage control node OFF2.

[0420] The second sensing reset leakage protection circuit 52 is connected to the sensing reset signal input terminal S-RST. The second sensing reset leakage protection circuit 52 is configured to form a path between the second sensing reset leakage protection node RQ2 and the second power supply terminal in response to the control of the valid level signal of S-RST at the sensing reset signal input terminal, and to form an open circuit between the second sensing reset leakage protection node RQ2 and the second power supply terminal in response to the control of the invalid level signal of S-RST at the sensing reset signal input terminal.

[0421] In some embodiments, the control electrode of the fiftieth transistor M50 is connected to the second pull-up node PU2, the first electrode of the fiftieth transistor M50 is connected to the third power supply terminal, and the second electrode of the fiftieth transistor M50 is connected to the second control voltage node OFF2.

[0422] The second sensing reset leakage protection circuit 52 includes: an eighty-fourth transistor M84; the control electrode of the eighty-fourth transistor M84 is connected to the sensing reset signal input terminal S-RST, and the first electrode of the eighty-fourth transistor M84 is connected to the second sensing reset leakage protection node RQ2.

[0423] See Figure 28A As shown, when the fifth switch circuit 403 is connected to the sensing reset signal input terminal S-RST, the second terminal of the eighty-fourth transistor M84 is connected to the third switch circuit.

[0424] See Figure 28B As shown, when the sixth switch circuit 404 is connected to the sensing reset signal input terminal S-RST, the second terminal of the eighty-fourth transistor M84 is connected to the second power supply terminal.

[0425] Figure 29 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 29 As shown, as another embodiment of the second sensing reset circuit, the shift register unit includes a first sensing reset circuit 3, and the first sensing reset circuit 3 includes a second switching circuit 303 and a third switching circuit 304 (i.e., the first sensing reset circuit 3 adopts...). Figure 17A and Figure 17B As shown in the diagram, the first shift register unit includes the aforementioned first voltage control circuit 14. At this time, the second sensing reset circuit 4 includes a seventh switch circuit 405.

[0426] The seventh switch circuit 405 is connected to the second pull-up node PU2, the sensing reset signal input terminal S-RST, and the first voltage control node OFF1 connected to the first voltage control circuit 4. The seventh switch circuit 405 is configured to form a path between the second pull-up node PU2 and the first voltage control node OFF1 in response to the control of the valid level signal provided by the sensing reset signal input terminal S-RST, and to form an open circuit between the second pull-up node PU2 and the first voltage control node OFF1 in response to the control of the invalid level signal provided by the sensing reset signal input terminal S-RST.

[0427] In some embodiments, the seventh switching circuit 405 includes: an eighty-fifth transistor M85; the control electrode of the eighty-fifth transistor M85 is connected to the sensing reset signal input terminal S-RST, the first electrode of the eighty-fifth transistor M85 is connected to the second pull-up node PU2, and the second electrode of the eighty-fifth transistor M85 is connected to the first control voltage node OFF.

[0428] In some embodiments, the shift register unit includes not only the second sensing input circuit 23, the second display input circuit 27, the third drive output circuit 25, and the fourth drive output circuit 29 in the previous embodiments, but also: a second global reset circuit 26, a second display reset circuit 28, a second pull-down control circuit 31, and a second pull-up noise reduction circuit 32.

[0429] The second global reset circuit 26 is connected to the global reset signal input terminal T-RST, the inactive level supply terminal, and the second pull-up node PU2. The second global reset circuit 26 is configured to write the inactive level signal provided by the inactive level supply terminal to the second pull-up node PU2 in response to the control of the active level signal provided by the global reset signal input terminal T-RST.

[0430] The second display reset circuit 28 is connected to the display reset signal input terminal RST, the inactive level supply terminal, and the second pull-up node PU2. The second display reset circuit 28 is configured to write the inactive level signal provided by the inactive level supply terminal to the second pull-up node PU2 in response to the control of the active level signal provided by the display reset signal input terminal RST.

[0431] The second pull-down control circuit 31 is connected to the second power supply terminal, the sixth power supply terminal, the second pull-up node PU2, and the second pull-down node PD2. The second pull-down control circuit 31 is configured to write a voltage that is inversely phase to the voltage at the second pull-down node PD2. The sixth power supply terminal provides the sixth operating voltage VDDB.

[0432] The second pull-up noise reduction circuit 32 is connected to the inactive level supply terminal, the second pull-up node PU2, and the second pull-down node PD2. The second pull-up noise reduction circuit 32 is configured to write the inactive level signal provided by the inactive level supply terminal to the second pull-up node PU2 in response to the control of the active level signal at the second pull-down node PD2.

[0433] At this time, the third drive output circuit 25 is also connected to the second pull-down node PD2 and the fourth power supply terminal. The third drive output circuit 25 is also configured to write the inactive level signal provided by the fourth power supply terminal to the third drive signal output terminal in response to the control of the effective level signal at the second pull-down node PD2.

[0434] The fourth drive output circuit 29 is also connected to the second pull-down node PD2 and the fourth power supply terminal. The fourth drive output circuit 29 is also configured to write the inactive level signal provided by the fourth power supply terminal to the fourth drive signal output terminal in response to the control of the active level signal at the second pull-down node PD2.

[0435] Figure 30 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 30 As shown, Figure 30 The shift register unit shown is a specific optional implementation based on the shift register unit shown above. For the specific circuit structure of the sensing control circuit 1, the first sensing input circuit 2, the first driving output circuit 5, the first display input circuit 7, the second driving output circuit 9, the first cascaded output circuit 13, the first global reset circuit 6, the first display reset circuit 8, the first pull-down control circuit 11, the first pull-up noise reduction circuit 12, and the second sensing input circuit 23 in this embodiment, please refer to the content in the previous embodiments, and it will not be repeated here.

[0436] In some embodiments, the second display input circuit 27 includes a thirty-ninth transistor M39, the control terminal of the thirty-ninth transistor M39 is connected to the display signal input terminal INPUT1, the first terminal of the thirty-ninth transistor M39 is connected to the third power supply terminal, and the second terminal of the thirty-ninth transistor M39 is connected to the second pull-up node PU2.

[0437] The third drive output circuit 25 includes the thirty-fifth transistor M35 and the forty-seventh transistor M47, and the fourth drive output circuit 29 includes the forty-fifth transistor M45 and the forty-eighth transistor M48.

[0438] Among them, the control terminal of the thirty-fifth transistor M35 is connected to the second pull-up node PU2, the first terminal of the thirty-fifth transistor M35 is connected to the third drive clock signal input terminal CLKE', and the second terminal of the thirty-fifth transistor M35 is connected to the third drive signal output terminal OUT2'.

[0439] The control electrode of the forty-seventh transistor M47 is connected to the second pull-down node PD2, the first electrode of the forty-seventh transistor M47 is connected to the third drive signal output terminal OUT2', and the second electrode of the forty-seventh transistor M47 is connected to the fourth power supply terminal.

[0440] The control terminal of the forty-fifth transistor M45 is connected to the second pull-up node PU2, the first terminal of the forty-fifth transistor M45 is connected to the fourth drive clock signal input terminal CLKD', and the second terminal of the forty-fifth transistor M45 is connected to the fourth drive signal output terminal OUT1'.

[0441] The control electrode of the forty-eighth transistor M48 is connected to the second pull-down node PD2, the first electrode of the forty-eighth transistor M48 is connected to the fourth drive signal output terminal OUT1', and the second electrode of the forty-eighth transistor M48 is connected to the fourth power supply terminal.

[0442] In some embodiments, a fourth capacitor C4 and a fifth capacitor C5 are respectively configured for the third drive signal output terminal OUT2' and the fourth drive signal output terminal OUT1'.

[0443] In some embodiments, the second global reset circuit 26 includes a thirty-seventh transistor M37, the second display reset circuit 28 includes a fortieth transistor M40, the second pull-down control circuit 31 includes a forty-second transistor M42 and a forty-third transistor M43, and the second pull-up noise reduction circuit 32 includes a forty-fourth transistor M44.

[0444] The control electrode of the 37th transistor M37 is connected to the global reset signal input terminal T-RST, the first electrode of the 37th transistor M37 is connected to the second pull-up node PU2, and the second electrode of the 37th transistor M37 is connected to the inactive level supply terminal.

[0445] The control electrode of the 40th transistor M40 is connected to the display reset signal input terminal RST, the first electrode of the 40th transistor M40 is connected to the second pull-up node PU2, and the second electrode of the 40th transistor M40 is connected to the inactive level supply terminal.

[0446] The control terminal of the forty-second transistor M42 is connected to the sixth power supply terminal, the first terminal of the forty-second transistor M42 is connected to the sixth power supply terminal, and the second terminal of the forty-second transistor M42 is connected to the second pull-down node PD2.

[0447] The control electrode of the forty-third transistor M43 is connected to the second pull-up node PU2, the first electrode of the forty-third transistor M43 is connected to the second pull-down node PD2, and the second electrode of the forty-third transistor M43 is connected to the non-active level supply terminal.

[0448] The control electrode of the forty-fourth transistor M44 is connected to the second pull-down node PD2, the first electrode of the forty-fourth transistor M44 is connected to the second pull-up node PU2, and the second electrode of the forty-fourth transistor M44 is connected to the non-active level supply terminal.

[0449] Figure 31 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 31 As shown, as a leakage protection design, in some embodiments the first non-effective level supply terminal is the second power supply terminal.

[0450] The shift register unit also includes a second voltage control circuit 34; the second voltage control circuit 34 is connected to the third power supply terminal, the second pull-up node PU1, and the second voltage control node OFF2, and the second voltage control circuit 34 is configured to write the valid level signal provided by the third power supply terminal to the second voltage control node OFF2 in response to the control of the valid level signal at the second pull-up node PU2.

[0451] The shift register unit also includes at least one of the following: a fourth leakage protection circuit 35, a fifth leakage protection circuit 36, and a sixth leakage protection circuit 37.

[0452] The second global reset circuit 26 is connected to the second power supply terminal through the fourth leakage protection circuit 35. The second global reset circuit 26 and the fourth leakage protection circuit 35 are connected to the fourth leakage protection node Q4. The fourth leakage protection node Q4 is connected to the second voltage control node OFF2. The fourth leakage protection circuit 35 is connected to the sensing reset signal input terminal T-RST. The fourth leakage protection circuit 35 is configured to form a path between the fourth leakage protection node Q4 and the second power supply terminal in response to the control of the valid level signal provided by the sensing reset signal input terminal T-RST, and to disconnect the fourth leakage protection node Q4 and the second power supply terminal in response to the control of the invalid level signal provided by the cascaded reset signal input terminal.

[0453] The second display reset circuit 28 is connected to the second power supply terminal through the fifth leakage protection circuit 36. The second display reset circuit 28 and the fifth leakage protection circuit 36 ​​are connected to the fifth leakage protection node Q5. The fifth leakage protection node Q5 is connected to the second voltage control node OFF2. The fifth leakage protection circuit 36 ​​is connected to the display reset signal input terminal RST. The fifth leakage protection circuit 36 ​​is configured to form a path between the fifth leakage protection node Q5 and the second power supply terminal in response to the control of the valid level signal provided by the display reset signal input terminal RST, and to disconnect the fifth leakage protection node Q5 and the second power supply terminal in response to the control of the invalid level signal provided by the cascade reset signal input terminal.

[0454] The second pull-up noise reduction circuit 32 is connected to the second power supply terminal through the sixth leakage protection circuit 37. The second pull-up noise reduction circuit 32 and the sixth leakage protection circuit 37 are connected to the sixth leakage protection node Q6. The sixth leakage protection node Q6 is connected to the second voltage control node OFF2. The sixth leakage protection circuit 37 is connected to the second pull-down node PD2. The sixth leakage protection circuit 37 is configured to form a path between the sixth leakage protection node Q6 and the second power supply terminal in response to the control of the effective level signal at the second pull-down node PD2, and to disconnect the circuit between the sixth leakage protection node Q6 and the second power supply terminal in response to the control of the ineffective level signal at the second pull-down node PD2.

[0455] Figure 31 The example provided illustrates a shift register unit that simultaneously includes a fourth leakage protection circuit 35, a fifth leakage protection circuit 36, and a sixth leakage protection circuit 37. In practical applications, at least one of the fourth leakage protection circuit 35, the fifth leakage protection circuit 36, and the sixth leakage protection circuit 37 can be configured according to actual needs.

[0456] In some embodiments, the second voltage control circuit 34 includes a fiftieth transistor M50, the control electrode of the fiftieth transistor M50 is connected to the first pull-up node PU1, the first electrode of the fiftieth transistor M50 is connected to the effective level supply terminal, and the second electrode of the fiftieth transistor M50 is connected to the second voltage control node OFF2.

[0457] In some embodiments, the fourth leakage protection circuit 35 includes a fifty-first transistor M51. The control electrode of the fifty-first transistor M51 is connected to the sensing reset signal input terminal T-RST. The first electrode of the fifty-first transistor M51 is connected to the sensing reset circuit and the second voltage control node OFF2. The second electrode of the fifty-second transistor M52 is connected to the second power supply terminal.

[0458] In some embodiments, the fifth leakage protection circuit 36 ​​includes a fifty-second transistor M52. The control electrode of the fifty-second transistor M52 is connected to the display reset signal input terminal RST, the first electrode of the fifty-second transistor M52 is connected to the display reset circuit and the second control voltage node OFF2, and the second electrode of the fifty-second transistor M52 is connected to the second power supply terminal.

[0459] In some embodiments, the sixth leakage protection circuit 37 includes: a fifty-third transistor M53, the control electrode of the fifty-third transistor M53 is connected to the second pull-down node PD2, the first electrode of the fifty-third transistor M53 is connected to the second pull-down control circuit and the second voltage control node OFF2, and the second electrode of the fifty-third transistor M53 is connected to the second power supply terminal.

[0460] Figure 32 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 32As shown, in some embodiments, when the shift register unit includes the first voltage control circuit 14, the non-active level supply terminal is the first voltage control node OFF1.

[0461] At this time, the second global reset circuit 26, the second display reset circuit 28, and the second pull-up noise reduction circuit 32 in the shift register unit can be protected against leakage by the first leakage protection circuit 15, the first leakage protection circuit 16, and / or the third leakage protection circuit 17. Therefore, there is no need to configure the fourth leakage protection circuit 35, the fifth leakage protection circuit 36, and the sixth leakage protection circuit 37 in the shift register unit, which is beneficial to simplifying the circuit structure.

[0462] See Figure 31 and Figure 32 As shown, in some embodiments, the shift register unit further includes a third pull-down noise reduction circuit 38 and / or a fourth pull-down noise reduction circuit 39.

[0463] The third pull-down noise reduction circuit 38 is connected to the second pull-down node PD2, the second power supply terminal, the sensing control node H, and the clock control signal input terminal CLKA. The first pull-down noise reduction circuit 18 is configured to write the ineffective level signal provided by the second power supply terminal to the first pull-down node PD1 in response to the control of the effective level signal at the sensing control node H and the effective level signal provided by the clock control signal input terminal CLKA, so as to perform noise reduction processing on the output voltage of the first pull-down node PD1.

[0464] The fourth pull-down noise reduction circuit 39 is connected to the second pull-down node PD2, the second power supply terminal and the sensing signal input terminal INPUT2. The second pull-down noise reduction circuit 19 is configured to write the ineffective level signal provided by the second power supply terminal to the first pull-down node PD1 in response to the control of the effective level signal provided by the sensing signal input terminal INPUT2, so as to perform noise reduction processing on the output voltage of the first pull-down node PD1.

[0465] In some embodiments, the third pull-down noise reduction circuit 38 includes the fifty-ninth transistor M59 and the sixtieth transistor M60, and the fourth pull-down noise reduction circuit 39 includes the sixty-first transistor M61.

[0466] Among them, the control terminal of the fifty-ninth transistor M59 is connected to the clock control signal input terminal CLKA, the first terminal of the fifty-ninth transistor M59 is connected to the second pull-down node PD2, and the second terminal of the fifty-ninth transistor M59 is connected to the first terminal of the sixtieth transistor M60.

[0467] The control electrode of the 60th transistor M60 is connected to the sensing control node H, and the second electrode of the 60th transistor M60 is connected to the second power supply terminal.

[0468] The control electrode of the sixty-first transistor M61 is connected to the sensing signal input terminal INPUT2, the first electrode of the sixty-first transistor M61 is connected to the second pull-down node PD2, and the second electrode of the sixty-first transistor M61 is connected to the second power supply terminal.

[0469] It should be noted that, in the above embodiments, when the shift register unit includes a second sensing input circuit 23, a second display input circuit 27, a third drive output circuit 25, and a fourth drive output circuit 29, the shift register unit can also be... Figure 11 , Figure 12 , Figure 15 The operation will proceed according to any of the working sequences shown in the diagram.

[0470] Furthermore, by combining some circuit structures from the above embodiments to obtain a new shift register unit circuit structure, the new shift register unit circuit structure obtained by combination should also fall within the protection scope of this disclosure.

[0471] Figure 33 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 33 As shown, the shift register includes: a sensing control circuit 1, a first sensing input circuit 2, a first sensing reset circuit 3, and a first drive output circuit 5.

[0472] The sensing control circuit 1 is connected to the sensing signal input terminal INPUT2, the random signal input terminal OE, and the sensing control node H. The sensing control circuit 1 is configured to write the signal provided by the sensing signal input terminal INPUT2 to the sensing control node H in response to the control of the valid level signal provided by the random signal input terminal OE.

[0473] The first sensing input circuit 2 is connected to the effective level supply terminal, the clock control signal input terminal CLKA, the sensing control node H, and the first pull-up node PU1. The first sensing input circuit 2 is controlled by the signal provided by the signal at the sensing control node H and the signal provided by the clock control signal input terminal CLKA. The first sensing input circuit 2 is configured to write the effective level signal provided by the effective level supply terminal to the first pull-up node PU1 in response to the control of the effective level signal at the sensing control node H and the effective level signal provided by the clock control signal input terminal CLKA.

[0474] The first sensing reset circuit 3 is connected to the sensing reset signal input terminal S-RST, the sensing control node H, the first pull-up node PU, and the second power supply terminal. The first sensing reset circuit 3 is configured to write the ineffective level signal provided by the second power supply terminal to the first pull-up node PU1 in response to the control of the signal provided by the sensing reset signal input terminal S-RST and the effective level signal at the sensing control node H.

[0475] The first drive output circuit 5 is connected to the first pull-up node PU1, the first drive clock signal input terminal CLKE, and the first drive signal output terminal OUT2, and is configured to write the signal provided by the first drive clock signal input terminal CLKE to the first drive signal output terminal OUT2 in response to the control of the effective level signal at the first pull-up node PU1.

[0476] Unlike the previous embodiments, in this embodiment, the first sensing input circuit 2 is not only controlled by the sensing control node H, but also by the clock control signal input terminal CLKA. Furthermore, the first sensing input circuit 2 will only write the valid level signal to the first pull-up node when the sensing control node H provides a valid level signal and the clock control signal input terminal CLKA provides a valid level signal.

[0477] The shift register unit provided in this embodiment is configured with a first sensing reset circuit 3, which can be used to reset the voltage at the first pull-up node after the sensing output phase is completed. For a detailed description of the first sensing reset circuit, please refer to the content in the previous embodiments, which will not be repeated here.

[0478] Figure 34 This is a schematic diagram of another circuit structure of the shift register unit provided in the embodiments of this disclosure, such as... Figure 34 As shown, Figure 34 The shift register unit shown is based on Figure 33 One specific alternative implementation of the shift register unit shown. In some embodiments, the first sensing input circuit 2 includes a second transistor M2 and a sixth transistor M6.

[0479] Among them, the control electrode of the second transistor M2 is connected to the sensing control node H, the first electrode of the second transistor M2 is connected to the effective level supply terminal, and the second electrode of the second transistor M2 is connected to the first electrode of the sixth transistor M6.

[0480] The control electrode of the sixth transistor M6 is connected to the clock control signal input terminal CLKA, and the second electrode of the sixth transistor M6 is connected to the first pull-up node PU1.

[0481] In some embodiments, the effective level supply terminal is the clock control signal input terminal CLKA.

[0482] It should be noted that, in Figure 33 and Figure 34In the illustrated embodiment, some or all of the circuits in the first display input circuit 7, second drive output circuit 9, first cascaded output circuit 13, first global reset circuit 6, first display reset circuit 8, first pull-down control circuit 11, first pull-up noise reduction circuit 12, first pull-down noise reduction circuit 18, first voltage control circuit 14, first leakage protection circuit 15, first leakage protection circuit 16, third leakage protection circuit 17, second pull-down noise reduction circuit 19, second sensing input circuit 23, second display input circuit 27, third drive output circuit 25, fourth drive output circuit 29, second cascaded output circuit 22, second sensing reset circuit 4, second global reset circuit 26, second display reset circuit 28, second pull-down control circuit 31, second pull-up noise reduction circuit 32, second voltage control circuit 35, fourth leakage protection circuit 35, fifth leakage protection circuit 36, sixth leakage protection circuit 37, third pull-down noise reduction circuit 38, and fourth pull-down noise reduction circuit 39 from the aforementioned embodiments may also be included; corresponding figures are not provided for these combinations.

[0483] Based on the same inventive concept, this disclosure also provides a gate driving circuit. Figure 35 This is a schematic diagram of a circuit structure for a gate driving circuit provided in an embodiment of the present disclosure. Figure 36 for Figure 35 The following is a timing diagram of the gate drive circuit: Figure 35 and Figure 36 As shown, the gate drive circuit includes multiple cascaded shift register units SRU1 to SRU3, wherein the shift register units SRU1 to SRU3 can be the shift register units provided in any of the previous embodiments. For a specific description of the shift register unit, please refer to the content in the previous embodiments, which will not be repeated here.

[0484] In some embodiments, when each shift register unit SRU1 to SRU3 is used to drive the gate lines corresponding to two rows of pixel units, that is, the shift register unit includes a first driving output circuit 5, a second driving output circuit 9, a third driving output circuit 25, a fourth driving output circuit 29, and a first cascaded output circuit 13, each shift register unit SRU1 to SRU3 can be regarded as two shift register circuits. For example, shift register unit SRU1 includes shift register circuits SR1 and SR2, shift register unit SRU2 includes shift register circuits SR3 and SR4, and shift register unit SRU3 includes shift register circuits SR5 and SR6.

[0485] As an example, if the display panel has 2N rows of pixel units, then the gate drive circuit can be configured with N shift register units. The N shift register units are cascaded, which can be regarded as 2N shift register circuits cascaded. The shift register circuit SR2n-1 located in the odd position is configured with a sensing signal input terminal INPUT2, a random signal input terminal OE, and a first cascaded signal output terminal CR, while the shift register circuit SR2n located in the even position is not configured with a sensing signal input terminal INPUT2, a random signal input terminal OE, and a first cascaded signal output terminal CR, where 1≤n≤N and n is an integer.

[0486] Figure 35 The illustration only shows the case of 3-stage shift register units SRU1 to SRU3 (6-stage shift register circuits SR1 to SR6), and this case is only for illustrative purposes.

[0487] In some embodiments, the sensing signal input terminal INPUT2 of each shift register unit SRU1 to SRU3 is connected to its own configured first cascaded signal output terminal CR; the clock control signal input terminal CLKA of each shift register unit SRU1 to SRU3 is connected to the clock control signal line CKA; the global reset signal input terminal T-RST of each shift register unit SRU1 to SRU3 is connected to the global reset signal supply terminal TRST'; and the random signal input terminal OE of each shift register unit is connected to the random signal input line OE'.

[0488] The display signal input terminal INPUT1 of the first-stage shift register unit SRU1 is connected to the frame start signal input terminal STV. For any shift register unit other than the first-stage shift register unit SRU1, the display signal input terminal INPUT1 of that shift register unit is connected to the first cascaded signal output terminal CR of the shift register unit preceding it. The global reset signal input terminal T-RST of each shift register unit is connected to the global reset signal supply terminal TRST'. The display reset signal input terminal RST of the shift register unit at stage N and the shift register unit at stage N-1 is connected to the frame end reset signal line. For any shift register unit other than the shift register units at stages N and N-1, the display reset signal input terminal RST of that shift register unit is connected to the first cascaded signal output terminal CR of the shift register units two stages following it.

[0489] Of course, in practical applications, the specific cascading method can be adjusted according to actual needs.

[0490] In some embodiments, the global reset signal supply terminal TRST' and the frame start signal input terminal STV are the same signal terminal, meaning that the global reset signal input terminals T-RST of each shift register unit are all connected to the frame start signal input terminal STV. For details, please refer to the relevant descriptions in the preceding embodiments.

[0491] In some embodiments, the gate drive circuit is configured with six first drive clock signal lines CKE1 to CKE6 and six second drive clock signal lines CKD1 to CKD6.

[0492] The first drive clock signal input terminal CLKE of the 3i+1 stage shift register unit SRU3i+1 is connected to the first drive clock signal line CKE1; the second drive clock signal input terminal CLKD of the 3i+1 stage shift register unit SRU3i+1 is connected to the second drive clock signal line CKD1; the third drive clock signal input terminal CLKE' of the 3i+1 stage shift register unit SRU3i+1 is connected to the second drive clock signal line CKE2; the fourth drive clock signal input terminal CLKD' of the 3i+1 stage shift register unit SRU3i+1 is connected to the second drive clock signal line CKD2; and the cascaded clock signal input terminal of the 3i+1 stage shift register unit SRU3i+1... Figure 35 (Not shown in the image) is connected to the second drive clock signal line CKD2.

[0493] The first drive clock signal input terminal CLKE of the shift register unit SRU3i+2 at stage 3i+2 is connected to the first drive clock signal line CKE3; the second drive clock signal input terminal CLKD of the shift register unit SRU3i+2 at stage 3i+2 is connected to the second drive clock signal line CKD3; the third drive clock signal input terminal CLKE' of the shift register unit SRU3i+2 at stage 3i+2 is connected to the second drive clock signal line CKE4; the fourth drive clock signal input terminal CLKD' of the shift register unit SRU3i+2 at stage 3i+2 is connected to the second drive clock signal line CKD4; and the cascaded clock signal input terminal of the shift register unit SRU3i+2 at stage 3i+2 is... Figure 35 (Not shown in the image) is connected to the second drive clock signal line CKD4.

[0494] The first drive clock signal input terminal CLKE of the 3i+3 level shift register unit SRU3i+3 is connected to the first drive clock signal line CKE5; the second drive clock signal input terminal CLKD of the 3i+3 level shift register unit SRU3i+3 is connected to the second drive clock signal line CKD5; the third drive clock signal input terminal CLKE' of the 3i+3 level shift register unit SRU3i+3 is connected to the second drive clock signal line CKE6; the fourth drive clock signal input terminal CLKD' of the 3i+3 level shift register unit SRU3i+3 is connected to the second drive clock signal line CKD6; and the cascaded clock signal input terminal of the 3i+3 level shift register unit SRU3i+3... Figure 35 (Not shown in the diagram) is connected to the second drive clock signal line CKD6. Where i is a positive integer and 3i+3≤N.

[0495] Of course, other cascading schemes can also be used to achieve cascading between shift register units in this embodiment.

[0496] Based on the same inventive concept, this disclosure also provides a display panel, wherein the display panel includes the gate driving circuit provided in the previous embodiment. For a detailed description of the gate driving circuit, please refer to the content in the previous embodiment, which will not be repeated here.

[0497] In some embodiments, the gate driving circuit is fabricated on the array substrate of the display panel using the GOA method.

[0498] Based on the same inventive concept, this disclosure also provides a display device, which includes the display panel provided in the previous embodiments. For a detailed description of the display panel, please refer to the content in the previous embodiments, which will not be repeated here.

[0499] The display device provided in this disclosure can be any product or component with display function, such as a liquid crystal display screen, wearable device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0500] Based on the same inventive concept, this disclosure also provides a gate driving method. This gate driving method is based on the shift register unit provided in the previous embodiments. For a detailed description of the shift register unit, please refer to the content in the previous embodiments, which will not be repeated here. Figure 37 This is a flowchart of a gate driving method provided in an embodiment of the present disclosure, as follows: Figure 37 As shown, the gate driving method includes:

[0501] Step S101: The sensing control circuit, in response to the control of the valid level signal provided by the random signal input terminal, writes the signal provided by the sensing signal input terminal to the sensing control node.

[0502] Step S102: The first sensing input circuit, in response to the control of the valid level signal at the sensing control node, writes the signal provided by the clock control signal input terminal to the first pull-up node.

[0503] Step S103: The first drive output circuit, in response to the control of the effective level signal at the first pull-up node, writes the signal provided by the first drive clock signal input terminal to the first drive signal output terminal.

[0504] For a detailed description of steps S101 to S103 above, please refer to the content in the previous embodiments, which will not be repeated here.

[0505] Figure 38 A flowchart of another gate driving method provided in this disclosure embodiment is shown below. Figure 38 As shown, the gate driving method at this time includes not only steps S101 to S103, but also step S104 after step S103.

[0506] Step S104: In response to the signal provided by the sensing reset signal input terminal and the effective level signal at the sensing control node, the first sensing reset circuit writes the ineffective level signal provided by the second power supply terminal to the first pull-up node.

[0507] Step S104 allows the voltage at the first pull-up node to be reset using the first sensing reset circuit after the sensing output phase ends.

[0508] Figure 39 A flowchart of yet another gate driving method provided in this disclosure embodiment is shown below. Figure 39 As shown, in some embodiments, the shift register unit is provided with a first display input circuit, a second drive output circuit, and a first cascaded output circuit. The gate driving method includes:

[0509] Step S201: The first display input circuit, in response to the control of the valid level signal provided by the display signal input terminal, writes the valid level signal provided by the third power supply terminal to the first pull-up node.

[0510] Step S201: The second drive output circuit, in response to the control of the effective level signal at the first pull-up node, writes the signal provided by the second drive clock signal input terminal to the second drive signal output terminal; the first cascade output circuit, in response to the control of the effective level signal at the first pull-up node, writes the signal provided by the first cascade clock signal input terminal to the first cascade signal output terminal.

[0511] Step S203: The sensing control circuit, in response to the control of the valid level signal provided by the random signal input terminal, writes the valid level signal provided by the sensing signal input terminal to the sensing control node.

[0512] Step S204: In response to the control of the valid level signal at the sensing control node, the first sensing input circuit writes the invalid signal provided by the clock control signal input terminal to the first pull-up node.

[0513] Step S204 starts synchronously with step S203, and step S204 ends at the start of the sensing output phase.

[0514] Step S205: The first sensing input circuit, in response to the control of the valid level signal at the sensing control node, writes the valid signal provided by the clock control signal input terminal to the first pull-up node.

[0515] Step S205 is performed during the sensing output stage.

[0516] Step S206: The sensing control circuit, in response to the control of the valid level signal provided by the random signal input terminal, writes the invalid level signal provided by the sensing signal input terminal to the sensing control node.

[0517] Step S206 is executed after the sensing output phase ends.

[0518] For a detailed description of steps S201 to S206, please refer to the previous section. Figure 11 The relevant description of the working timing is shown.

[0519] Figure 40 A flowchart of another gate driving method provided in the embodiments of this disclosure is shown below. Figure 40 As shown, in some embodiments, the shift register unit is provided with not only a first display input circuit, a second drive output circuit and a first cascaded output circuit, but also a first sensing reset circuit. The gate driving method not only includes the above steps S201 to S206, but also includes step S206a between steps S205 and S206.

[0520] Step S206a: In response to the signal provided by the sensing reset signal input terminal and the effective level signal at the sensing control node, the first sensing reset circuit writes the ineffective level signal provided by the second power supply terminal to the first pull-up node.

[0521] For a detailed description of each step in the gate driving method provided in this embodiment, please refer to the previous section. Figure 12 and Figure 15 The relevant description of the working timing is shown.

[0522] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A shift register unit, wherein, include: A sensing control circuit, connected to a sensing signal input terminal, a random signal input terminal, and a sensing control node, is configured to write the signal provided by the sensing signal input terminal to the sensing control node in response to a valid level signal provided by the random signal input terminal. A first sensing input circuit is connected to a clock control signal input terminal, the sensing control node, and a first pull-up node. The first sensing input circuit is configured to write the signal provided by the clock control signal input terminal to the first pull-up node only in response to the control of a valid level signal at the sensing control node. The first drive output circuit is connected to the first pull-up node, the first drive clock signal input terminal, and the first drive signal output terminal, and is configured to write the signal provided by the first drive clock signal input terminal to the first drive signal output terminal in response to the control of the effective level signal at the first pull-up node. A first display input circuit is connected to a display signal input terminal, a third power supply terminal, and a first pull-up node, and is configured to write the valid level signal provided by the third power supply terminal to the first pull-up node in response to the control of the valid level signal provided by the display signal input terminal. The second drive output circuit is connected to the first pull-up node, the second drive clock signal input terminal, and the second drive signal output terminal, and is configured to write the signal provided by the second drive clock signal input terminal to the second drive signal output terminal in response to the control of the effective level signal at the first pull-up node. The first cascaded output circuit is connected to the first pull-up node, the first cascaded clock signal input terminal, and the first cascaded signal output terminal, and is configured to write the signal provided by the first cascaded clock signal input terminal to the first cascaded signal output terminal in response to the control of the effective level signal at the first pull-up node.

2. The shift register unit according to claim 1, wherein, The first sensing input circuit includes: a second transistor; The control electrode of the second transistor is connected to the sensing control node, the first electrode of the second transistor is connected to the clock control signal input terminal, and the second electrode of the second transistor is connected to the first pull-up node.

3. The shift register unit according to claim 1, wherein, Also includes: A first voltage control circuit is connected to a third power supply terminal, a first pull-up node, and a first voltage control node. The first voltage control circuit is configured to write the effective level signal provided by the third power supply terminal to the first voltage control node in response to the control of the effective level signal at the first pull-up node. The shift register unit further includes: a first sensing input leakage protection circuit, wherein the first sensing input circuit is connected to the clock control signal input terminal through the first sensing input leakage protection circuit, the first sensing input circuit and the first sensing input leakage protection circuit are connected to the first sensing input leakage protection node, and the first sensing input leakage protection node is connected to the first voltage control node; The first sensing input leakage protection circuit is connected to the sensing control node. The first sensing input leakage protection circuit is configured to form a path between the first sensing input leakage protection node and the clock control signal input terminal in response to the control of an effective level signal at the sensing control node, and to disconnect the first sensing input leakage protection node from the clock control signal input terminal in response to the control of an ineffective level signal at the sensing control node.

4. The shift register unit according to claim 3, wherein, The first voltage control circuit includes: the twentieth transistor; The control electrode of the twentieth transistor is connected to the first pull-up node, the first electrode of the twentieth transistor is connected to the third power supply terminal, and the second electrode of the twentieth transistor is connected to the first voltage control node. The first sensing input leakage protection circuit includes: a third transistor; The control electrode of the third transistor is connected to the sensing control node, the first electrode of the third transistor is connected to the clock control signal input terminal, and the second electrode of the third transistor is connected to the first sensing input leakage protection node.

5. The shift register unit according to claim 1, wherein, It also includes: a first sensing input leakage protection circuit, wherein the first sensing input circuit is connected to the clock control signal input terminal through the first sensing input leakage protection circuit, and the first sensing input circuit and the first sensing input leakage protection circuit are connected to the first sensing input leakage protection node; The first sensing input leakage protection circuit is connected to a preset input control signal input terminal and a first cascaded signal output terminal. The first sensing input leakage protection circuit is configured to form a path between the first sensing input leakage protection node and the clock control signal input terminal in response to the control of an effective level signal provided by the preset input control signal input terminal, and to disconnect the circuit between the first sensing input leakage protection node and the clock control signal input terminal in response to the control of an ineffective level signal provided by the preset input control signal input terminal. When the circuit between the first sensing input leakage protection node and the clock control signal input terminal is disconnected, the effective level signal is written to the first sensing input leakage protection node in response to the control of an effective level signal provided by the first cascaded signal output terminal.

6. The shift register unit according to claim 5, wherein, The first sensing input leakage protection circuit includes: a third transistor and a fourth transistor; The control electrode of the third transistor is connected to the preset input control signal input terminal, the first electrode of the third transistor is connected to the clock control signal input terminal, and the second electrode of the third transistor is connected to the first sensing input leakage protection node. The control electrode and the first electrode of the fourth transistor are both connected to the first cascaded signal output terminal, and the second electrode of the fourth transistor is connected to the first sensing input leakage protection node.

7. The shift register unit according to claim 1, wherein, Also includes: A first global reset circuit is connected to a global reset signal input terminal, a second power supply terminal, and a first pull-up node, and is configured to write an invalid level signal provided by the second power supply terminal to the first pull-up node in response to the control of an effective level signal provided by the global reset signal input terminal. A first display reset circuit is connected to a display reset signal input terminal, a second power supply terminal, and a first pull-up node, and is configured to write an invalid level signal provided by the second power supply terminal to the first pull-up node in response to the control of an effective level signal provided by the display reset signal input terminal. The first pull-down control circuit is connected to the second power supply terminal, the fifth power supply terminal, the first pull-up node, and the first pull-down node, and is configured to write a voltage that is opposite to the voltage at the first pull-up node to the first pull-down node. The first pull-up noise reduction circuit is connected to the second power supply terminal, the first pull-up node and the first pull-down node, and is configured to write the ineffective level signal provided by the second power supply terminal to the first pull-up node in response to the control of the effective level signal at the first pull-down node. The first cascaded output circuit is also connected to the first pull-down node and the second power supply terminal, and is configured to write the ineffective level signal provided by the second power supply terminal to the first cascaded signal output terminal in response to the control of the effective level signal at the first pull-down node. The first drive output circuit is also connected to the first pull-down node and the fourth power supply terminal. The first drive output circuit is also configured to write the inactive level signal provided by the fourth power supply terminal to the first drive signal output terminal in response to the control of the active level signal at the first pull-down node. The second drive output circuit is also connected to the first pull-down node and the fourth power supply terminal. The second drive output circuit is also configured to write an invalid level signal provided by the fourth power supply terminal to the second drive signal output terminal in response to the control of an effective level signal at the first pull-down node.

8. The shift register unit according to claim 7, wherein, Also includes: A first voltage control circuit is connected to a third power supply terminal, a first pull-up node, and a first voltage control node. The first voltage control circuit is configured to write the effective level signal provided by the third power supply terminal to the first voltage control node in response to the control of the effective level signal at the first pull-up node. The shift register unit further includes at least one of a first leakage protection circuit, a second leakage protection circuit, and a third leakage protection circuit; The first global reset circuit is connected to the second power supply terminal through the first leakage protection circuit. The first global reset circuit and the first leakage protection circuit are connected to the first leakage protection node. The first leakage protection node is connected to the first voltage control node. The first leakage protection circuit is connected to the global reset signal input terminal. The first leakage protection circuit is configured to form a path between the first leakage protection node and the second power supply terminal in response to the control of the valid level signal provided by the global reset signal input terminal, and to disconnect the circuit between the first leakage protection node and the second power supply terminal in response to the control of the invalid level signal provided by the global reset signal input terminal. The first display reset circuit is connected to the second power supply terminal through the second leakage protection circuit. The first display reset circuit and the second leakage protection circuit are connected to the second leakage protection node. The second leakage protection node is connected to the first voltage control node. The second leakage protection circuit is connected to the display reset signal input terminal. The second leakage protection circuit is configured to form a path between the second leakage protection node and the second power supply terminal in response to the control of the valid level signal provided by the display reset signal input terminal, and to disconnect the circuit between the second leakage protection node and the second power supply terminal in response to the control of the invalid level signal provided by the display reset signal input terminal. The first pull-up noise reduction circuit is connected to the second power supply terminal through the third leakage protection circuit. The first pull-up noise reduction circuit and the third leakage protection circuit are connected to the third leakage protection node. The third leakage protection node is connected to the first voltage control node. The third leakage protection circuit is connected to the first pull-down node. The third leakage protection circuit is configured to form a path between the third leakage protection node and the second power supply terminal in response to the control of an effective level signal at the first pull-down node, and to disconnect the circuit between the third leakage protection node and the second power supply terminal in response to the control of an ineffective level signal at the first pull-down node.

9. The shift register unit according to claim 1, wherein, Also includes: A first sensing reset circuit is connected to a sensing reset signal input terminal, the sensing control node, the first pull-up node, and a second power supply terminal. It is configured to write an invalid level signal provided by the second power supply terminal to the first pull-up node in response to the control of the signal provided by the sensing reset signal input terminal and the valid level signal at the sensing control node.

10. The shift register unit according to claim 9, wherein, The first sensing reset circuit includes: A first sensing reset control circuit is connected to the sensing reset signal input terminal, the first sensing reset control node, the sensing control node, and the second power supply terminal. It is configured to write the valid level signal at the sensing control node to the first sensing reset control node in response to the control of the inactive level signal provided by the sensing reset signal input terminal and the valid level signal at the sensing control node. A first switching circuit, connected to the first sensing reset control node, the first pull-up node, and the second power supply terminal, is configured to form a path between the second power supply terminal and the first pull-up node in response to a valid level signal at the first sensing reset control node, and to form an open circuit between the second power supply terminal and the first pull-up node in response to an invalid level signal at the first sensing reset control node.

11. The shift register unit according to claim 10, wherein, The first sensing reset control circuit includes a seventy-first transistor and a seventy-second transistor, and the first switching circuit includes a seventy-third transistor; The control electrode and the first electrode of the seventy-first transistor are both connected to the sensing control node, and the second electrode of the seventy-first transistor is connected to the first sensing reset control node; The control electrode of the seventy-second transistor is connected to the sensing reset signal input terminal, the first electrode of the seventy-second transistor is connected to the first sensing reset control node, and the second electrode of the seventy-second transistor is connected to the second power supply terminal. The control electrode of the seventy-third transistor is connected to the first sensing reset control node, the first electrode of the seventy-third transistor is connected to the first pull-up node, and the second electrode of the seventy-third transistor is connected to the second power supply terminal.

12. The shift register unit according to claim 10 or 11, wherein, Also includes: A first voltage control circuit is connected to a third power supply terminal, a first pull-up node, and a first voltage control node. The first voltage control circuit is configured to write the effective level signal provided by the third power supply terminal to the first voltage control node in response to the control of the effective level signal at the first pull-up node. The shift register unit further includes: a first sensing reset leakage protection circuit, the first switching circuit being connected to the second power supply terminal through the first sensing reset leakage protection circuit, the first switching circuit and the first sensing reset leakage protection circuit being connected to the first sensing reset leakage protection node, and the first sensing reset leakage protection node being connected to the first voltage control node; The first sensing reset leakage protection circuit is connected to the first sensing reset control node. The first sensing reset leakage protection circuit is configured to form a path between the first sensing reset leakage protection node and the second power supply terminal in response to the control of an effective level signal at the first sensing reset control node, and to form an open circuit between the first sensing reset leakage protection node and the second power supply terminal in response to the control of an ineffective level signal at the first sensing reset control node.

13. The shift register unit according to claim 12, wherein, The first voltage control circuit includes: a twentieth transistor; The control electrode of the twentieth transistor is connected to the first pull-up node, the first electrode of the twentieth transistor is connected to the third power supply terminal, and the second electrode of the twentieth transistor is connected to the first voltage control node. The first sensing reset leakage protection circuit includes: a seventy-fourth transistor; The control electrode of the seventy-fourth transistor is connected to the first sensing reset control node, the first electrode of the seventy-fourth transistor is connected to the first sensing reset leakage protection node, and the second electrode of the seventy-fourth transistor is connected to the second power supply terminal.

14. The shift register unit according to claim 9, wherein, The first sensing reset circuit includes: a second switching circuit and a third switching circuit connected in series between the first pull-up node and the second power supply terminal, wherein the second switching circuit is located between the third switching circuit and the first pull-up node; One of the second switching circuit and the third switching circuit is connected to the sensing reset signal input terminal, and the other is connected to the sensing control node; The second and third switching circuits are configured to provide a path between the second power supply terminal and the first pull-up node in response to a valid level signal provided by the sensing reset signal input terminal and a valid level signal at the sensing control node, and to provide an open circuit between the second power supply terminal and the first pull-up node in response to a low level signal provided by at least one of the sensing reset signal input terminal and the sensing control node.

15. The shift register unit according to claim 14, wherein, The second switching circuit includes a seventy-first transistor, and the third switching circuit includes a seventy-second transistor; The control electrode of one of the seventy-first transistors and the seventy-second transistor is connected to the sensing reset signal input terminal, and the control electrode of the other transistor is connected to the sensing control node. The first terminal of the seventy-first transistor is connected to the first pull-up node, the second terminal of the seventy-first transistor is connected to the first terminal of the seventy-second transistor, and the second terminal of the seventy-second transistor is connected to the second power supply terminal.

16. The shift register unit according to claim 14, wherein, Also includes: A first voltage control circuit is connected to a third power supply terminal, a first pull-up node, and a first voltage control node. The first voltage control circuit is configured to write the effective level signal provided by the third power supply terminal to the first voltage control node in response to the control of the effective level signal at the first pull-up node. The shift register unit further includes: a first sensing reset leakage protection circuit; The second switching circuit is connected to the sensing reset signal input terminal. The second switching circuit is connected to the third switching circuit through the first sensing reset leakage protection circuit. The second switching circuit and the first sensing reset leakage protection circuit are connected to the first sensing reset leakage protection node. The first sensing reset leakage protection node is connected to the first voltage control node. The first sensing reset leakage protection circuit is connected to the sensing reset signal input terminal. The first sensing reset leakage protection circuit is configured to form a path between the first sensing reset leakage protection node and the third switching circuit in response to the control of an effective level signal at the sensing reset signal input terminal, and to form an open circuit between the first sensing reset leakage protection node and the third switching circuit in response to the control of an ineffective level signal at the sensing reset signal input terminal. Alternatively, the third switching circuit is connected to the sensing reset signal input terminal, the third switching circuit is connected to the second power supply terminal through the first sensing reset leakage protection circuit, the third switching circuit and the first sensing reset leakage protection circuit are connected to the first sensing reset leakage protection node, and the first sensing reset leakage protection node is connected to the first voltage control node. The first sensing reset leakage protection circuit is connected to the sensing reset signal input terminal. The first sensing reset leakage protection circuit is configured to form a path between the first sensing reset leakage protection node and the second power supply terminal in response to the control of an effective level signal at the sensing reset signal input terminal, and to form an open circuit between the first sensing reset leakage protection node and the second power supply terminal in response to the control of an ineffective level signal at the sensing reset signal input terminal.

17. The shift register unit according to claim 16, wherein, The first voltage control circuit includes: a twentieth transistor; The control electrode of the twentieth transistor is connected to the first pull-up node, the first electrode of the twentieth transistor is connected to the third power supply terminal, and the second electrode of the twentieth transistor is connected to the first voltage control node. The first sensing reset leakage protection circuit includes: a seventy-fourth transistor, the control electrode of the seventy-fourth transistor is connected to the sensing reset signal input terminal, and the first electrode of the seventy-fourth transistor is connected to the first sensing reset leakage protection node; When the second switching circuit is connected to the sensing reset signal input terminal, the second terminal of the seventy-fourth transistor is connected to the third switching circuit; When the third switching circuit is connected to the sensing reset signal input terminal, the second terminal of the seventy-fourth transistor is connected to the second power supply terminal.

18. The shift register unit according to claim 14, wherein, Also includes: The second sensing input circuit is connected to the clock control signal input terminal, the sensing control node, and the second pull-up node, and is configured to write the signal provided by the clock control signal input terminal to the second pull-up node in response to the control of the effective level signal at the sensing control node. The second display input circuit is connected to the display signal input terminal and the second pull-up node, and is configured to write the valid level signal to the second pull-up node in response to the control of the valid level signal provided by the display signal input terminal; The third drive output circuit is connected to the second pull-up node, the third drive clock signal input terminal, and the third drive signal output terminal, and is configured to write the signal provided by the third drive clock signal input terminal to the third drive signal output terminal in response to the control of the effective level signal at the second pull-up node. The fourth drive output circuit is connected to the second pull-up node, the fourth drive clock signal input terminal, and the fourth drive signal output terminal, and is configured to write the signal provided by the fourth drive clock signal input terminal to the fourth drive signal output terminal in response to the control of the effective level signal at the second pull-up node.

19. The shift register unit according to claim 18, wherein, The second sensing input circuit includes: a thirty-second transistor; The control electrode of the thirty-second transistor is connected to the sensing control node, the first electrode of the thirty-second transistor is connected to the clock control signal input terminal, and the second electrode of the thirty-second transistor is connected to the second pull-up node.

20. The shift register unit according to claim 18, wherein, When a first sensing input leakage protection circuit is provided in the shift register unit, the second sensing input circuit is connected to the first sensing input leakage protection node, so as to be connected to the clock control signal input terminal through the first sensing input leakage protection node and the first sensing input leakage protection circuit.

21. The shift register unit according to claim 18, wherein, Also includes: The second cascaded output circuit is connected to the second pull-up node, the second cascaded clock signal input terminal, and the second cascaded signal output terminal, and is configured to write the signal provided by the second cascaded clock signal input terminal to the second cascaded signal output terminal in response to the control of the effective level signal at the second pull-up node. The shift register unit further includes: a second sensing input leakage protection circuit, wherein the second sensing input circuit is connected to the clock control signal input terminal through the second sensing input leakage protection circuit, and the second sensing input circuit and the second sensing input leakage protection circuit are connected to the second sensing input leakage protection node; The second sensing input leakage protection circuit is connected to a preset input control signal input terminal and a second cascaded signal output terminal. The second sensing input leakage protection circuit is configured to form a path between the second sensing input leakage protection node and the clock control signal input terminal in response to the control of an effective level signal provided by the preset input control signal input terminal, and to disconnect the second sensing input leakage protection node from the clock control signal input terminal in response to the control of an ineffective level signal provided by the preset input control signal input terminal. When the second sensing input leakage protection node is disconnected from the clock control signal input terminal, it writes an effective level signal to the second sensing input leakage protection node in response to the control of an effective level signal provided by the second cascaded signal output terminal.

22. The shift register unit according to claim 21, wherein, The second sensing input leakage protection circuit includes: a thirty-third transistor and a thirty-fourth transistor; The control electrode of the thirty-third transistor is connected to the preset input control signal input terminal, the first electrode of the thirty-third transistor is connected to the clock control signal input terminal, and the second electrode of the thirty-third transistor is connected to the second sensing input leakage protection node. The control electrode and the first electrode of the thirty-fourth transistor are both connected to the second cascaded signal output terminal, and the second electrode of the thirty-fourth transistor is connected to the second sensing input leakage protection node.

23. The shift register unit according to claim 18, wherein, Also includes: The second global reset circuit is connected to the global reset signal input terminal, the first inactive level supply terminal, and the second pull-up node, and is configured to write the inactive level signal provided by the first inactive level supply terminal to the second pull-up node in response to the control of the active level signal provided by the global reset signal input terminal. The second display reset circuit is connected to the display reset signal input terminal, the first inactive level supply terminal, and the second pull-up node, and is configured to write the inactive level signal provided by the first inactive level supply terminal to the second pull-up node in response to the control of the active level signal provided by the display reset signal input terminal. The second pull-down control circuit is connected to the second power supply terminal, the sixth power supply terminal, the second pull-up node, and the second pull-down node, and is configured to write a voltage that is opposite to the voltage at the second pull-up node to the second pull-down node; The second pull-up noise reduction circuit is connected to the first inactive level supply terminal, the second pull-up node, and the second pull-down node, and is configured to write the inactive level signal provided by the first inactive level supply terminal to the second pull-up node in response to the control of the active level signal at the second pull-down node. The third drive output circuit is also connected to the second pull-down node and the fourth power supply terminal. The third drive output circuit is also configured to write the ineffective level signal provided by the fourth power supply terminal to the third drive signal output terminal in response to the control of the effective level signal at the second pull-down node. The fourth drive output circuit is also connected to the second pull-down node and the fourth power supply terminal. The fourth drive output circuit is also configured to write an invalid level signal provided by the fourth power supply terminal to the fourth drive signal output terminal in response to the control of an effective level signal at the second pull-down node.

24. The shift register unit according to claim 23, wherein, The first non-active level supply terminal is the second power supply terminal; Alternatively, the shift register unit includes a first voltage control circuit, and the first non-active level supply terminal is the first voltage control node connected to the first voltage control circuit.

25. The shift register unit according to claim 24, wherein, The first non-active level supply terminal is the second power supply terminal; The shift register unit further includes: The second voltage control circuit is connected to the effective level supply terminal, the second pull-up node, and the second voltage control node. The second voltage control circuit is configured to write the effective level signal provided by the effective level supply terminal to the second voltage control node in response to the control of the effective level signal at the second pull-up node. The shift register unit further includes at least one of the following: a fourth leakage protection circuit, a fifth leakage protection circuit, and a sixth leakage protection circuit; The second global reset circuit is connected to the second power supply terminal through the fourth leakage protection circuit. The second global reset circuit and the fourth leakage protection circuit are connected to the fourth leakage protection node. The fourth leakage protection node is connected to the second voltage control node. The fourth leakage protection circuit is connected to the global reset signal input terminal. The fourth leakage protection circuit is configured to form a path between the fourth leakage protection node and the second power supply terminal in response to the control of an effective level signal provided by the global reset signal input terminal, and to disconnect the fourth leakage protection node from the second power supply terminal in response to the control of an ineffective level signal provided by the global reset signal input terminal. The second display reset circuit is connected to the second power supply terminal through the fifth leakage protection circuit. The second display reset circuit and the fifth leakage protection circuit are connected to the fifth leakage protection node. The fifth leakage protection node is connected to the second voltage control node. The fifth leakage protection circuit is connected to the display reset signal input terminal. The fifth leakage protection circuit is configured to form a path between the fifth leakage protection node and the second power supply terminal in response to the control of an effective level signal provided by the display reset signal input terminal, and to disconnect the circuit between the fifth leakage protection node and the second power supply terminal in response to the control of an ineffective level signal provided by the display reset signal input terminal. The second pull-up noise reduction circuit is connected to the second power supply terminal through the sixth leakage protection circuit. The second pull-up noise reduction circuit and the sixth leakage protection circuit are connected to the sixth leakage protection node. The sixth leakage protection node is connected to the second voltage control node. The sixth leakage protection circuit is connected to the second pull-down node. The sixth leakage protection circuit is configured to form a path between the sixth leakage protection node and the second power supply terminal in response to the control of an effective level signal at the second pull-down node, and to disconnect the circuit between the sixth leakage protection node and the second power supply terminal in response to the control of an ineffective level signal at the second pull-down node.

26. The shift register unit according to any one of claims 18, wherein, The shift register unit includes a first sensing reset circuit, and the first sensing reset circuit includes a first sensing reset control circuit and a first switching circuit. The shift register unit further includes: a second sensing reset circuit, the second sensing reset circuit comprising: The second sensing reset control circuit is connected to the sensing reset signal input terminal, the second sensing reset control node, the second power supply terminal, and the second sensing reset control node. It is configured to write the valid level signal at the sensing control node to the second sensing reset control node in response to the control of the inactive level signal provided by the sensing reset signal input terminal and the valid level signal at the sensing control node. A fourth switching circuit is connected to the second sensing reset control node, the second pull-up node, and the second inactive level supply terminal. The fourth switching circuit is configured to form a path between the second inactive level supply terminal and the second pull-up node in response to the control of the active level signal at the second sensing reset control node, and to form an open circuit between the second inactive level supply terminal and the second pull-up node in response to the control of the inactive level signal at the second sensing reset control node.

27. The shift register unit according to claim 26, wherein, The second sensing reset control circuit includes an eighty-first transistor and an eighty-second transistor, and the fourth switching circuit includes an eighty-third transistor; The control electrode and the first electrode of the eighty-first transistor are both connected to the sensing control node, and the second electrode of the eighty-first transistor is connected to the second sensing reset control node; The control electrode of the 82nd transistor is connected to the sensing reset signal input terminal, the first electrode of the 82nd transistor is connected to the second sensing reset control node, and the second electrode of the 82nd transistor is connected to the second power supply terminal. The control electrode of the 83rd transistor is connected to the second sensing reset control node, the first electrode of the 83rd transistor is connected to the second pull-up node, and the second electrode of the 83rd transistor is connected to the second inactive level supply terminal.

28. The shift register unit according to claim 26, wherein, The second non-active level supply terminal is the second power supply terminal; The shift register unit further includes: The second voltage control circuit is connected to the third power supply terminal, the second pull-up node, and the second voltage control node. The second voltage control circuit is configured to write the effective level signal provided by the third power supply terminal to the second voltage control node in response to the control of the effective level signal at the second pull-up node. The shift register unit further includes: a second sensing reset leakage protection circuit, the fourth switching circuit being connected to the second power supply terminal through the second sensing reset leakage protection circuit, the fourth switching circuit and the second sensing reset leakage protection circuit being connected to the second sensing reset leakage protection node, and the second sensing reset leakage protection node being connected to the second voltage control node; The second sensing reset leakage protection circuit is connected to the second sensing reset control node. The second sensing reset leakage protection circuit is configured to form a path between the second sensing reset leakage protection node and the second power supply terminal in response to the control of an effective level signal at the second sensing reset control node, and to form an open circuit between the second sensing reset leakage protection node and the second power supply terminal in response to the control of an ineffective level signal at the second sensing reset control node.

29. The shift register unit according to claim 28, wherein, The second voltage control circuit includes: a fiftieth transistor; The control electrode of the fiftieth transistor is connected to the second pull-up node, the first electrode of the fiftieth transistor is connected to the third power supply terminal, and the second electrode of the fiftieth transistor is connected to the second voltage control node. The second sensing reset leakage protection circuit includes: an eighty-fourth transistor; The control electrode of the 84th transistor is connected to the second sensing reset control node, the first electrode of the 84th transistor is connected to the second sensing reset leakage protection node, and the second electrode of the 84th transistor is connected to the second power supply terminal.

30. The shift register unit according to claim 26, wherein, The shift register unit includes a first voltage control circuit, and the second inactive level supply terminal is the first voltage control node connected to the first voltage control circuit.

31. The shift register unit according to claim 18, wherein, The shift register unit includes a first sensing and reset circuit, and the first sensing and reset circuit includes a second switching circuit and the third switching circuit; The shift register unit further includes: a second sensing reset circuit, the second sensing reset circuit including: a fifth switch circuit and a sixth switch circuit connected in series between the second pull-up node and the second power supply terminal, the fifth switch circuit being located between the sixth switch circuit and the second pull-up node; One of the fifth switch circuit and the sixth switch circuit is connected to the sensing reset signal input terminal, and the other is connected to the sensing control node; The fifth and sixth switching circuits are configured to, in response to the control of a valid level signal provided by the sensing reset signal input terminal and a valid level signal at the sensing control node, provide a path between the second power supply terminal and the second pull-up node, and in response to the control of a low level signal provided by at least one of the sensing reset signal input terminal and the sensing control node, provide an open circuit between the second power supply terminal and the second pull-up node.

32. The shift register unit according to claim 31, wherein, The fifth switching circuit includes an eighty-first transistor, and the sixth switching circuit includes an eighty-second transistor; The control electrode of one of the eighty-first transistors and the eighty-second transistor is connected to the sensing reset signal input terminal, and the control electrode of the other transistor is connected to the sensing control node. The first terminal of the eighty-first transistor is connected to the first pull-up node, the second terminal of the eighty-first transistor is connected to the first terminal of the eighty-second transistor, and the second terminal of the eighty-second transistor is connected to the second power supply terminal.

33. The shift register unit according to claim 31, wherein, Also includes: The second voltage control circuit is connected to the third power supply terminal, the second pull-up node, and the second voltage control node. The second voltage control circuit is configured to write the effective level signal provided by the third power supply terminal to the second voltage control node in response to the control of the effective level signal at the second pull-up node. The shift register unit further includes: a second sensing reset leakage protection circuit; The fifth switching circuit is connected to the sensing reset signal input terminal. The fifth switching circuit is connected to the sixth switching circuit through the second sensing reset leakage protection circuit. The second switching circuit and the second sensing reset leakage protection circuit are connected to the second sensing reset leakage protection node. The second sensing reset leakage protection node is connected to the second voltage control node. The second sensing reset leakage protection circuit is connected to the sensing reset signal input terminal. The second sensing reset leakage protection circuit is configured to form a path between the second sensing reset leakage protection node and the sixth switching circuit in response to the control of an effective level signal at the sensing reset signal input terminal, and to form an open circuit between the second sensing reset leakage protection node and the sixth switching circuit in response to the control of an ineffective level signal at the sensing reset signal input terminal. Alternatively, the fifth switching circuit is connected to the sensing reset signal input terminal, the sixth switching circuit is connected to the second power supply terminal through the second sensing reset leakage protection circuit, the sixth switching circuit and the second sensing reset leakage protection circuit are connected to the second sensing reset leakage protection node, and the second sensing reset leakage protection node is connected to the second voltage control node; The second sensing reset leakage protection circuit is connected to the sensing reset signal input terminal. The second sensing reset leakage protection circuit is configured to form a path between the second sensing reset leakage protection node and the second power supply terminal in response to the control of an effective level signal at the sensing reset signal input terminal, and to form an open circuit between the second sensing reset leakage protection node and the second power supply terminal in response to the control of an ineffective level signal at the sensing reset signal input terminal.

34. The shift register unit according to claim 33, wherein, The second voltage control circuit includes: a fiftieth transistor; The control electrode of the fiftieth transistor is connected to the second pull-up node, the first electrode of the fiftieth transistor is connected to the third power supply terminal, and the second electrode of the fiftieth transistor is connected to the second voltage control node. The second sensing reset leakage protection circuit includes: an eighty-fourth transistor, the control electrode of the eighty-fourth transistor is connected to the second sensing reset control node, and the first electrode of the eighty-fourth transistor is connected to the second sensing reset leakage protection node; When the fifth switching circuit is connected to the sensing reset signal input terminal, the second terminal of the eighty-fourth transistor is connected to the third switching circuit; When the sixth switch circuit is connected to the sensing reset signal input terminal, the second terminal of the eighty-fourth transistor is connected to the second power supply terminal.

35. The shift register unit according to any one of claims 18, wherein, The shift register unit includes a first sensing and reset circuit, and the first sensing and reset circuit includes a second switching circuit and a third switching circuit, and the first shift register unit includes a first voltage control circuit; The shift register unit further includes: a second sensing reset circuit, the second sensing reset circuit comprising: The seventh switching circuit is connected to the second pull-up node, the sensing reset signal input terminal, and the first voltage control node connected to the first voltage control circuit. The seventh switching circuit is configured to form a path between the second pull-up node and the first voltage control node in response to the control of the valid level signal provided by the sensing reset signal input terminal, and to form an open circuit between the second pull-up node and the first voltage control node in response to the control of the control of the invalid level signal provided by the sensing reset signal input terminal.

36. The shift register unit according to claim 35, wherein, The seventh switching circuit includes: an eighty-fifth transistor; The control electrode of the 85th transistor is connected to the sensing reset signal input terminal, the first electrode of the 85th transistor is connected to the second pull-up node, and the second electrode of the 85th transistor is connected to the first control voltage node.

37. A shift register unit, wherein, include: A sensing control circuit, connected to a sensing signal input terminal, a random signal input terminal, and a sensing control node, is configured to write the signal provided by the sensing signal input terminal to the sensing control node in response to a valid level signal provided by the random signal input terminal. A first sensing input circuit is connected to an effective level supply terminal, a clock control signal input terminal, the sensing control node, and a first pull-up node. The first sensing input circuit is controlled by the signal at the sensing control node and the signal provided by the clock control signal input terminal. The first sensing input circuit is configured to write the effective level signal provided by the effective level supply terminal to the first pull-up node in response to the control of the effective level signal at the sensing control node and the effective level signal provided by the clock control signal input terminal. A first sensing reset circuit is connected to a sensing reset signal input terminal, the sensing control node, the first pull-up node, and the second power supply terminal. It is configured to write an invalid level signal provided by the second power supply terminal to the first pull-up node in response to the control of the signal provided by the sensing reset signal input terminal and the valid level signal at the sensing control node. The first drive output circuit is connected to the first pull-up node, the first drive clock signal input terminal, and the first drive signal output terminal, and is configured to write the signal provided by the first drive clock signal input terminal to the first drive signal output terminal in response to the control of the effective level signal at the first pull-up node. A first display input circuit is connected to a display signal input terminal, a third power supply terminal, and a first pull-up node, and is configured to write the valid level signal provided by the third power supply terminal to the first pull-up node in response to the control of the valid level signal provided by the display signal input terminal. The second drive output circuit is connected to the first pull-up node, the second drive clock signal input terminal, and the second drive signal output terminal, and is configured to write the signal provided by the second drive clock signal input terminal to the second drive signal output terminal in response to the control of the effective level signal at the first pull-up node. The first cascaded output circuit is connected to the first pull-up node, the first cascaded clock signal input terminal, and the first cascaded signal output terminal, and is configured to write the signal provided by the first cascaded clock signal input terminal to the first cascaded signal output terminal in response to the control of the effective level signal at the first pull-up node.

38. The shift register unit according to claim 37, wherein, The effective level supply terminal is the clock control signal input terminal.

39. A gate driving circuit, wherein, include: A cascaded plurality of shift register units, wherein the shift register units are any of the shift register units described in claims 1 to 38.

40. A gate driving method, wherein, The gate driving method is based on any one of the shift register units of claims 1 to 38, and the gate driving method includes: The sensing control circuit, in response to the effective level signal provided by the random signal input terminal, writes the signal provided by the sensing signal input terminal to the sensing control node; The first sensing input circuit, in response to the control of the valid level signal at the sensing control node, writes the signal provided by the clock control signal input terminal to the first pull-up node; The first drive output circuit, in response to the control of the effective level signal at the first pull-up node, writes the signal provided by the first drive clock signal input terminal to the first drive signal output terminal.

41. The gate driving method according to claim 40, wherein, The shift register unit is the shift register unit described in claim 1; The step of the sensing control circuit writing the signal provided by the sensing signal input terminal to the sensing control node in response to the control of the valid level signal provided by the random signal input terminal includes: The sensing control circuit, in response to the control of the valid level signal provided by the random signal input terminal, writes the valid level signal provided by the sensing signal input terminal to the sensing control node; The sensing control circuit, in response to the control of the valid level signal provided by the random signal input terminal, writes the invalid level signal provided by the sensing signal input terminal to the sensing control node; Before the step of the sensing control circuit writing the valid level signal provided by the sensing signal input terminal to the sensing control node in response to the control of the valid level signal provided by the random signal input terminal, the method further includes: The first display input circuit, in response to the control of the valid level signal provided by the display signal input terminal, writes the valid level signal provided by the third power supply terminal to the first pull-up node; The second drive output circuit, in response to the control of the effective level signal at the first pull-up node, writes the signal provided by the second drive clock signal input terminal to the second drive signal output terminal; the first cascade output circuit, in response to the control of the effective level signal at the first pull-up node, writes the signal provided by the first cascade clock signal input terminal to the first cascade signal output terminal. From the moment the sensing control circuit writes the valid level signal provided by the sensing signal input terminal to the sensing control node in response to the valid level signal provided by the random signal input terminal, until the start of the sensing output phase, the first sensing input circuit writes the invalid signal provided by the clock control signal input terminal to the first pull-up node in response to the valid level signal at the sensing control node. During the sensing output phase, the first sensing input circuit, in response to the control of the valid level signal at the sensing control node, writes the valid signal provided by the clock control signal input terminal to the first pull-up node. The step of the sensing control circuit writing an invalid level signal provided by the sensing signal input terminal to the sensing control node in response to the control of the valid level signal provided by the random signal input terminal is performed after the end of the sensing output stage.

42. The gate driving method according to claim 40, wherein, The shift register unit is the shift register unit described in claim 9; After the step of the first drive output circuit writing the signal provided by the first drive clock signal input terminal to the first drive signal output terminal in response to the control of the effective level signal at the first pull-up node, the method further includes: The first sensing reset circuit, in response to the signal provided by the sensing reset signal input terminal and the control of the valid level signal at the sensing control node, writes the invalid level signal provided by the second power supply terminal to the first pull-up node.

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