An automatic calibration method for single-ended transmission links based on FPGA

Abstract

The present invention discloses an automatic calibration method based on a single-ended transmission link of an FPGA, and the steps are as follows: (1) the transmitting end generates calibration data, and the test data is divided into two parts: a synchronization word and a prbs7 random number; (2) the receiving end performs bit sequence calibration by receiving the calibration data of the transmitting end; (3) by setting the delay step of the Idelay and Odelay devices, the verification result after delay of each data line is traversed; (4) the traversed test results are statistically calculated to find the center position of each data line for clock sampling; (5) finally, the calibrated data bus is verified. The present invention realizes high-speed and stable data transmission function through multi-chip FPGA prototype verification or high real-time signal processing system, and meets the requirements of stability and low delay of data transmission between multiple FPGAs.

Description

Technical Field

[0001] The invention relates to the technical field of signal processing and prototype verification, in particular to an automatic calibration method based on a FPGA single-ended transmission link. Background Art

[0002] As the chip size becomes larger and the bus bandwidth becomes higher, the requirements for inter-FPGA communication in the prototype verification system are also increasing. Reducing the communication delay of inter-chip transmission will help improve the system main frequency of the prototype verification platform and improve the verification efficiency of the prototype verification platform. The inter-FPGA transmission of the prototype verification system is carried out with the help of cables to ensure the flexibility of the verification system.

[0003] The existing FPGA inter-chip parallel transmission solution uses Xilinx's IP solution, which is not flexible enough to meet the increasing performance requirements of prototype verification. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide an automatic calibration method based on an FPGA single-ended transmission link, which realizes high-speed and stable data transmission function through multi-chip FPGA prototype verification or high-real-time signal processing system, thereby meeting the requirements of stability and low latency of data transmission between multiple FPGAs.

[0005] In order to solve the above technical problems, the present invention provides an automatic calibration method based on an FPGA single-ended transmission link, comprising:

[0006] Step 1: The transmitter generates calibration data. The test data is divided into two parts: synchronization word and prbs7 random number;

[0007] Step 2: The receiving end performs bit sequence calibration by receiving the calibration data from the sending end;

[0008] Step 3: By setting the delay step of Idelay and Odelay devices, the verification results after each data line delay are traversed;

[0009] Step 4: Perform statistical calculations on the traversed test results to find the center position of each data line for clock sampling;

[0010] Step 5: Finally, perform a verification test on the calibrated data bus.

[0011] Furthermore, the specific steps of generating link calibration data at the interface transmitting end in step 1 are as follows:

[0012] Step 1.1: Send a total of 1024 packets of data, each packet of data includes a 10 microsecond synchronization word and 100us PRBS7 calibration data;

[0013] Step 1.2: Each data line transmits data in bytes, and data serialization conversion is required to queue the 8-bit data in order from high to low and transmit them through the double edges of the clock;

[0014] Step 1.3: The sending end has an Odelay device, which is used to delay the sending phase of the sending data relative to the sending clock. There are 512 groups of step delays, and each group of delay units is 4ps. The first 512 data packets are sent with a delay of 0, and the next 512 packets are sent with a delay of 512.

[0015] Step 1.4: The sending end and the interface end have a slow bus to exchange status information. Before sending each calibration data packet, the sending end sends a calibration instruction to the receiving end through the slow bus.

[0016] Furthermore, in step 2, the receiving end performs bit sequence calibration on each piece of data by receiving the calibration data from the sending end. The specific steps of the calibration are as follows:

[0017] Step 2.1: The receiving end calibrates the bit sequence through the Iddr device and the shift register. The Iddr converts the data transmitted by the double edge of the clock into the single edge of the clock data.

[0018] Step 2.2: Send the single edge data to an 8-bit shift register for shift check. When the value of the 8-bit register is detected to be equal to the synchronization word, a synchronization pulse is generated to reset the cycle counter with a period of 4. Every time the counter is 4, the value of the shift register is read out;

[0019] Furthermore, in step 3, the specific steps of the receiving end performing a traversal test on the phase of each data line by receiving the calibration data from the transmitting end are as follows:

[0020] Step 3.1: Configure the delay of the Odelay device at the transmitting end and the Idelay device at the receiving end to delay the sampling phase of the received data relative to the receiving clock;

[0021] Step 3.2: The receiving end receives the calibration command from the slow bus, resets the calibration circuit, and the Idelay device delays by 1. Then the receiving circuit is checked to determine whether the data after the bit sequence calibration is consistent with the sent data, and the result is filled into a register group for storage;

[0022] Step 3.3: The shift register reads out the result of the bit sequence calibration. When the calibrated data is equal to the calibration data of the transmitter, the synchronization word and prbs7 are both verified, and 1 is filled in the verification result register, otherwise 0 is filled.

[0023] Furthermore, in step 4, the specific steps of performing statistical calculation on the traversed test results and finding the center position of each data line for clock sampling are as follows:

[0024] Step 4.1: After the calibration is completed, read the result from the calibration result register, find the position of each data line relative to the clock sampling through the connected domain calibration method, find the left and right edges of the data effective phase, and calculate the center position of the data effective phase;

[0025] Step 4.2: If the data phase is ahead of the clock sampling phase, the register that stores the calibration results will read the results of two connected domains. It is necessary to first compare which connected domain is larger, and then calculate the effective phase center of the data.

[0026] Furthermore, the specific steps of performing the final verification test on the calibrated data bus in step 5 are as follows:

[0027] The calculated delay value corresponding to the center phase is filled back into the Idelay and Odelay devices, and the sending end is notified through the slow bus to send another end prbs7 pseudo-random code for verification to ensure that the calibration result is valid.

[0028] The beneficial effects of the present invention are:

[0029] 1. The present invention adopts a single-ended transmission solution. The pins of FPGA are limited. The existing FPGA inter-chip transmission solution is differential and requires two pins. The single-ended method improves the physical transmission bandwidth.

[0030] 2. The present invention adopts a new bit alignment calibration technology, which improves the calibration efficiency compared with the traditional bit alignment calibration technology.

[0031] 3. Under the same interface bit width condition, the single-ended transmission scheme of the present invention can reduce the transmission delay by 25% and improve the system main frequency of the verification platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a transmission schematic diagram of a calibration system in a specific embodiment;

[0033] Figure 2 It is a block diagram of the interface circuit design in a specific embodiment;

[0034] Figure 3 It is a schematic diagram of the bit sequence calibration in a specific embodiment;

[0035] Figure 4 A schematic diagram of clock and data phases in a specific embodiment;

[0036] Figure 5 FIG. 4 is a flow chart of an automatic calibration system in a specific embodiment. DETAILED DESCRIPTION

[0037] like Figure 1 As shown, the present invention discloses an automatic calibration method based on a FPGA single-ended transmission link. The whole calibration scheme is Figure 1 The interface is implemented on the interface circuit, which consists of three parts: a clock, multiple parallel data lines and a serial bus. The serial bus is used for the transmitter and receiver to exchange training instructions and parameters. Figure 5 As shown, it mainly consists of four parts: the data sending end generates calibration data, the receiving end uses the calibration data to complete the data bus phase traversal search and bit sequence calibration functions, uses the traversal search phase result to calculate the center position of the data effective phase and the calibrated data verification.

[0038] Step 1: The transmitter sends 1024 packets of calibration data and control instructions to the receiver through data serialization. Each packet of calibration data includes a synchronization word and a prbs7 random code.

[0039] The details are as follows: The data transmitter is composed of two devices, OSerDes and Odelay. The data is serialized through the OSerDes device, and then the data line transmission delay is performed through the Odelay device. The data transmitter sends 1024 packets of calibration data under the accompanying clock. The delay parameter of Odelay is configured as "0" for the first 512 packets of data, and the delay parameter of Odelay is configured as "512" for the last 512 packets of data. Each packet of data contains synchronization words and prbs7 pseudo-random code verification data. At the same time, before sending each packet of calibration data, the transmitter first sends a training instruction through the serial port;

[0040] Step 2: The receiving end uses the synchronization word from the sending end to receive data using Iddr to achieve the bit sequence calibration function;

[0041] The details are as follows: The bit sequence calibration function is implemented by two parts: the Iddr device and the bit sequence calibration module. The specific implementation principle is as follows Figure 3 As shown, the data line is transmitted serially with double edges according to 8 bits per byte. IDDR first decodes the double-edge data to a single edge, which is consistent with the bus data in the schematic diagram. Then an 8-bit left shift register is defined to put the IDDR data into the lowest two bits of the register. Then, assuming that the default synchronization word is "ABCDEFGH", it is determined whether the value of the shift register is equal to the synchronization word. If it is equal, it is possible to find the correct bit order. First, a synchronization enable is generated as shown in the figure to reset the loop counter. Whenever the loop counter is equal to "0", the value of the shift register is the value sent, such as Figure 3 The calibration result signal.

[0042] Step 3: The receiving end verifies the data after the receiving end bit sequence calibration using the data bus Delay device according to the control instruction of the sending end, and stores the results of different phase delays in the status register;

[0043] The details are as follows: The receiving end interface circuit is as follows: Figure 2 As shown, it includes Idelay device, Iddr device and bit sequence calibration module. After receiving the calibration instruction from the transmitter, the receiver first steps 1 to set the delay parameter of Idelay, then calibrates the bit sequence of the received data, and then verifies it with pseudo-random data, and fills the verified result into the register. Each delay parameter corresponds to a register;

[0044] Step 4: Use the calibration results under different phase delays to calculate the effective central phase of the data through the connected domain calibration method;

[0045] The details are as follows: Calculate the data phase center of the clock sampling along the line. Because the invention adopts a single-ended transmission method, considering the impact of PCB and connector signal integrity on data transmission quality, we expect the clock sampling edge to be located at the center of the effective bit width of each data line, such as Figure 4 The phase relationship between the desired clock and data is Figure 4 Schematic point 1 indicates that the data phase lags the clock sampling, and schematic point 2 indicates that the data phase leads the clock sampling. According to the data in the register storing the calibration result in step 2, the valid left and right edges of the data are found through the connected domain calibration method, and the center position of the valid data phase is calculated.

[0046] Step 5: Fill the calculated center phase corresponding phase delay value back into the Delay device, and notify the sender through the slow bus to send another prbs7 pseudo-random code for verification to ensure that the calibration result is valid.

[0047] The details are as follows: According to the center position calculated in step 4, the delay parameters of Idelay and Odelay are converted, and the delay parameters are filled back into the Odelay and Idelay devices. Then the calibration data is sent to the MCU via the serial bus. The verification data only requires a packet of pseudo-random code verification data with a longer time. If the verification is correct, the circuit calibration is completed. If the verification fails, the above operation is reset and re-verified (where the Delay device includes the Odelay and Idelay devices).

Claims

1. An automatic calibration method based on FPGA single-ended transmission link, characterized in that: The steps include: Step 1: The transmitter generates calibration data, which consists of two parts: synchronization word and prbs7 random number; Step 2: The receiving end performs bit sequence calibration by receiving the calibration data from the sending end; Step 3: By setting the delay step of Idelay and Odelay devices, the verification results after each data line delay are traversed; Step 4: Perform statistical calculations on the traversed test results to find the center position of each data line for clock sampling; Step 5: Finally, perform a verification test on the calibrated data bus; In step 3, the receiving end performs a traversal test on the phase of each data line by receiving the calibration data of the transmitting end. The specific steps are as follows: Step 3.1: Configure the delay of the Odelay device at the transmitting end and the Idelay device at the receiving end to delay the sampling phase of the received data relative to the receiving clock; Step 3.2: The receiving end receives the calibration command from the slow bus, resets the calibration circuit, and the Idelay device delays by 1 step; then starts to check the receiving circuit to determine whether the data after the bit sequence calibration is consistent with the sent data, and fills the result into a register group for storage; Step 3.3: The shift register reads out the result of the bit sequence calibration. When the calibrated data is equal to the calibration data of the transmitter, the synchronization word and prbs7 are both verified, and 1 is filled in the verification result register, otherwise 0 is filled; In step 4, the specific steps of performing statistical calculation on the traversed test results and finding the center position of each data line for clock sampling are as follows: Step 4.1: After the calibration is completed, read the result from the calibration result register, find the position of each data line relative to the clock sampling through the connected domain calibration method, find the left and right edges of the data effective phase, and calculate the center position of the data effective phase; Step 4.2: If the data phase leads the clock sampling phase, the register that stores the calibration results will read the results of two connected domains. It is necessary to first compare which connected domain is larger and then calculate the effective phase center of the data.

2. The automatic calibration method based on FPGA single-ended transmission link according to claim 1, characterized in that: The specific steps of generating link calibration data at the interface transmitting end in step 1 are as follows: Step 1.1: Send a total of 1024 packets of data, each packet of data includes a 10us synchronization word and 100us prbs7 calibration data; Step 1.2: Each data line transmits data in bytes, and data serialization conversion is required to queue the 8-bit data in order from high to low and transmit them through the double edges of the clock; Step 1.3: The sending end has an Odelay device, which is used to delay the sending phase of the sending data relative to the sending clock. There are 512 groups of step delays, and the delay unit of each group is 4ps. The first 512 data packets are sent with a delay of 0, and the next 512 packets are sent with a delay of 512. Step 1.4: The sending end and the interface end have a slow bus to exchange status information; before sending each calibration data packet, the sending end sends a calibration instruction to the receiving end through the slow bus.

3. The automatic calibration method based on FPGA single-ended transmission link according to claim 1, characterized in that: In step 2, the receiving end performs bit sequence calibration on each piece of data by receiving the calibration data from the sending end. The specific steps of the calibration are as follows: Step 2.1: The receiving end calibrates the bit sequence through the Iddr device and the shift register; the Iddr converts the data transmitted by the double edge of the clock into the single edge of the clock data; Step 2.2: Send the single-edge data to an 8-bit shift register for shift check; when it is detected that the value of the 8-bit register is equal to the synchronization word, a synchronization pulse is generated to reset the cyclic counter with a period of 4. Every time the counter is 4, the value of the shift register is read out.

4. The automatic calibration method based on FPGA single-ended transmission link according to claim 1, characterized in that: The specific steps of performing the final verification test on the calibrated data bus in step 5 are as follows: The calculated delay value corresponding to the center phase is backfilled into the Idelay and Odelay devices, and the sending end is notified through the slow bus to send another end prbs7 pseudo-random code for verification to ensure that the calibration result is valid.

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