Semiconductor device and method of manufacturing the same

Abstract

The semiconductor device and the preparation method thereof provided by the embodiments of the present disclosure increase the spacing between the first semiconductor layers (and semiconductor pillars) adjacent in the first direction by thinning the first semiconductor layer, break through the limitation caused by the insufficient thickness of the second semiconductor layer in epitaxy, and are conducive to the increase of the integration density of the semiconductor device. In addition, the embodiments of the present disclosure provide a new preparation method, which forms a gate structure layer first and then forms a bit line and a capacitor, which is conducive to expanding the application of the semiconductor device.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more particularly to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each typically including a transistor and a capacitor. To meet the requirements of high storage density and high integration, DRAM and other memory devices have gradually evolved from two-dimensional structures to three-dimensional structures. The manufacturing process of DRAM and other semiconductor structures with three-dimensional structures requires the formation of a superlattice stack structure of semiconductor layers and sacrificial layers through deposition processes. This superlattice stack structure typically uses epitaxial processes to form a SiG layer on a Si layer. However, due to the lattice mismatch between the SiGe layer and the Si layer, the epitaxial thickness of the SiGe layer on the Si layer is limited. This limited epitaxial thickness restricts the vertical spacing of the semiconductor devices, increasing the difficulty of the manufacturing process and hindering the increase of integration density. Summary of the Invention

[0003] The technical problem to be solved by this disclosure is to provide a semiconductor device and its fabrication method, which can overcome the limitations imposed by the epitaxial thickness of the SiGe layer and is conducive to increasing the integration density.

[0004] To address the aforementioned problems, this disclosure provides a method for fabricating a semiconductor device, comprising: forming a substrate and a stacked structure on the substrate, the stacked structure including a first semiconductor layer and a second semiconductor layer alternately stacked along a first direction, the stacked structure including a capacitor region, a word line region, and a bit line region, the first direction being a direction perpendicular to the top surface of the substrate; removing the second semiconductor layer to form a first gap; thinning the first semiconductor layer along the first gap; removing a portion of the first semiconductor layer to form a plurality of semiconductor pillars, each semiconductor pillar extending along a third direction and the plurality of semiconductor pillars being arranged in an array along the first direction and a second direction, the second direction being a direction parallel to the top surface of the substrate, the third direction being a direction parallel to the top surface of the substrate, and the second direction intersecting the third direction; forming a gate structure layer on the surface of the semiconductor pillars; and in the capacitor region, removing the gate structure layer on the surface of the semiconductor pillars and forming a capacitor structure layer, the capacitor structure layer covering the surface of the semiconductor pillars.

[0005] In one embodiment, a method for forming a stacked structure on the substrate includes: forming a first semiconductor layer and a second semiconductor layer alternately stacked along a first direction on the substrate; forming a plurality of first openings arranged along a second direction in the bit line region, the first openings penetrating the first semiconductor layer and the second semiconductor layer along the first direction; removing a portion of the second semiconductor layer between adjacent first openings along the first openings to form an initial gap between adjacent first semiconductor layers; and forming a first support layer within the initial gap.

[0006] In one embodiment, a method for removing a portion of the second semiconductor layer between adjacent first openings along the first opening includes: filling the first opening with an insulating layer; removing a portion of the insulating layer, the remaining insulating layer serving as a protective layer covering the two sidewalls of the first opening disposed opposite each other in the third direction, the remaining area of ​​the first opening serving as a second opening; removing the second semiconductor layer exposed along the sidewalls of the second opening along the second opening, forming the initial gap between adjacent first semiconductor layers; and after the step of forming the first support layer, removing the protective layer to expose the first semiconductor layer and the second semiconductor layer.

[0007] In one embodiment, a method for removing a portion of the first semiconductor layer to form a plurality of semiconductor pillars includes: forming a first mask layer on the stacked structure, the first mask layer including a plurality of first graphic windows, each of the first graphic windows extending along a third direction, and the plurality of first graphic windows being arranged along a second direction; removing a portion of the first semiconductor layer along the first graphic windows to form the semiconductor pillars.

[0008] In one embodiment, the projection of the first patterned window onto the substrate overlaps the projection of the first opening onto the substrate; after the step of thinning the first semiconductor layer, the method further includes: filling the first gap with a first isolation layer; the step of removing a portion of the first semiconductor layer along the first patterned window to form the semiconductor pillars includes: removing a portion of the first isolation layer located in the first opening, retaining the first isolation layer between the semiconductor pillars arranged in the first direction; performing ion implantation on the semiconductor pillars to form doped semiconductor pillars; and removing the first isolation layer between the semiconductor pillars arranged in the first direction.

[0009] In one embodiment, a method for forming a gate structure layer on the surface of the semiconductor pillar includes: forming a gate dielectric layer on the surface of the semiconductor pillar; forming a gate material layer on the surface of the gate dielectric layer, wherein the gate material layers located on the same semiconductor pillar surface are connected in a first direction; and filling a second isolation layer between adjacent gate structure layers in the first direction.

[0010] In one embodiment, the method includes: removing the first support layer, the gate structure layer, and the semiconductor pillars in the bit line region to form a bit line trench, the bit line trench penetrating the stacked structure; further removing a portion of the gate structure layer along the sidewall of the bit line trench to form a recess; forming a second support layer that fills the spaces between the first semiconductor layers exposed in the recess; forming a bit line material layer in the bit line trench; patterning the bit line material layer to form bit lines spaced apart along a second direction, each bit line being connected to a plurality of semiconductor pillars arranged along the first direction; and forming a third isolation layer between the bit lines.

[0011] In one embodiment, the step of forming the bit line trench includes: forming a second mask layer on the surface of the stacked structure, the second mask layer having a second patterned window extending along a second direction; and removing the first support layer, the gate structure layer, and the semiconductor pillar along the second patterned window to form the bit line trench.

[0012] In one embodiment, after forming bit lines spaced apart along the second direction, the method further includes forming a third support layer at the boundary between the capacitor region and the word line region, the third support layer supporting the semiconductor pillar.

[0013] In one embodiment, the method of forming the third support layer includes: forming a third mask layer on the surface of the stacked structure, the third mask layer having a third patterned window extending along a second direction and corresponding to the boundary between the capacitor region and the word line region; removing the gate structure layer along the third patterned window; and filling with a support material to form the third support layer.

[0014] In one embodiment, a method for removing the gate structure layer on the surface of the semiconductor pillar and forming a capacitor structure layer in the capacitor region includes: removing the gate structure layer on the surface of the semiconductor pillar in the capacitor region to expose the semiconductor pillar surface; forming a lower electrode that covers the exposed semiconductor pillar surface; forming a dielectric layer that covers the lower electrode surface; and forming an upper electrode that covers the dielectric layer surface.

[0015] In one embodiment, after forming the upper electrode, the method further includes the following step: forming a polysilicon layer, wherein the polysilicon layer fills the gaps between the upper electrodes.

[0016] In one embodiment, the capacitor region, the word line region, and the bit line region are arranged along the third direction. The stacked structure includes two capacitor regions and two word line regions. The bit line region is disposed between the two word line regions, and the two word line regions are disposed between the two capacitor regions.

[0017] This disclosure also provides a semiconductor device, including: a substrate; a plurality of semiconductor pillars located on the substrate, the plurality of semiconductor pillars being arranged in an array in a first direction and a second direction and extending along a third direction, the first direction being a direction perpendicular to the top surface of the substrate, the second direction being a direction parallel to the top surface of the substrate, the third direction being a direction parallel to the top surface of the substrate, and the second direction intersecting the third direction; a first spacing between adjacent semiconductor pillars in the first direction is greater than a first spacing between adjacent semiconductor pillars in the second direction.

[0018] In one embodiment, the semiconductor pillar includes a capacitor region and a word line region, and the semiconductor device further includes: a gate structure layer located on the surface of the semiconductor pillar in the word line region; and a capacitor structure layer located on the surface of the semiconductor pillar in the capacitor region.

[0019] The semiconductor device fabrication method provided in this disclosure increases the first spacing between adjacent first semiconductor layers (and semiconductor pillars) by thinning the first semiconductor layer, overcoming the limitation caused by insufficient epitaxial thickness of the second semiconductor layer, which is beneficial to increasing the integration density of semiconductor devices. This disclosure also provides a new fabrication method that first forms a gate structure layer and then forms bit lines and capacitors, which is beneficial to expanding the application of semiconductor devices. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0021] Figures 2-20 This is a schematic diagram of the main process structure in the fabrication of semiconductor devices according to an embodiment of this disclosure. Detailed Implementation

[0022] The specific embodiments of the semiconductor device fabrication method provided in this disclosure will be described in detail below with reference to the accompanying drawings.

[0023] This disclosure provides a method for fabricating a semiconductor device. Figure 1 This is a schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of this disclosure. Figures 2-20 This is a schematic diagram of the main process structure in the fabrication of a semiconductor device according to an embodiment of this disclosure. In this embodiment, the semiconductor device may be, but is not limited to, DRAM.

[0024] Please see Figure 1 and Figure 8 In step S10, a substrate 20 and a stacked structure 21 located on the substrate 20 are formed. The stacked structure 21 includes a first semiconductor layer 210 and a second semiconductor layer 220 alternately stacked along a first direction D1. The stacked structure 21 includes a capacitor region A1, a word line region A2 and a bit line region A3. The first direction D1 is perpendicular to the top surface of the substrate 20 and the second direction D2 is parallel to the top surface of the substrate 20.

[0025] In this embodiment, the first direction D1 is the Z-axis direction in the Cartesian coordinate system, and the second direction D2 is the Y-axis direction in the Cartesian coordinate system, as an example for explanation.

[0026] The substrate 20 may be, but is not limited to, a silicon substrate. This embodiment uses a silicon substrate as an example for illustration. In other examples, the substrate 20 may be a semiconductor such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 20 is used to support the stacked structure 21 located on its top surface.

[0027] The alternating stacking of the first semiconductor layer 210 and the second semiconductor layer 220 refers to the following steps: after forming a first semiconductor layer 210, a second semiconductor layer 220 is formed on the first semiconductor layer 210, and then the steps of forming the first semiconductor layer 210 and the second semiconductor layer 220 on the first semiconductor layer 210 are repeated sequentially. In this embodiment, the first semiconductor layer 210 is a silicon layer, and the second semiconductor layer 220 is a silicon-germanium layer. Since the substrate 20 is a silicon substrate, a second semiconductor layer 220 is epitaxially formed on the substrate 20, the first semiconductor layer 210 is deposited on the second semiconductor layer, and then the second semiconductor layer 220 is epitaxially formed on the first semiconductor layer 210, and so on, to form a stacked structure 21. In this embodiment, the top layer of the stacked structure 21 is the second semiconductor layer 220.

[0028] The capacitor region A1, word line region A2, and bit line region A3 are arranged along a third direction D3. In this embodiment, the stacked structure 21 includes two capacitor regions A1, two word line regions A2, and one bit line region A3. The bit line region A3 is disposed between the two word line regions A2, and the two word line regions A2 are disposed between the two capacitor regions A1, thus forming a symmetrical structure with the center line of the bit line region A3 as the axis of symmetry. In other embodiments, it may also include only one capacitor region A1, one word line region A2, and one bit line region A3 arranged sequentially.

[0029] In bit line region A3, multiple first openings 230 arranged along the second direction D2 penetrate the first semiconductor layer 210 and the second semiconductor layer 220 along the first direction D1, that is, the first openings 230 expose the substrate 20, and parts of the sides of the first semiconductor layer 210 and the second semiconductor layer 220 are exposed to the inner wall of the first openings 230. In the region between adjacent first openings 230, a first support layer 240 is disposed between the first semiconductor layers 210.

[0030] The region between adjacent first openings 230 refers to the region corresponding to the stacked structure 21 between adjacent first openings 230. In this region, a first support layer 240 partially replaces the second semiconductor layer 220 and is disposed between adjacent first semiconductor layers 210, with the sidewalls of the first support layer 240 also exposed to the inner wall of the first opening 230. Specifically, in the region between adjacent first openings 230, on the third direction D3, within the same layer, the first support layer 240 bisects the second semiconductor layer 220 into two parts, with the first support layer 240 disposed between these two parts of the second semiconductor layer 220.

[0031] As an example, this disclosure provides a method for forming a stacked structure 21 on a substrate 20.

[0032] Please see Figure 2 In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), and (c) is a cross-sectional view along line B-B' in (a), wherein a first semiconductor layer 210 and a second semiconductor layer 220 are alternately stacked along the first direction D1 on the substrate 20. The second semiconductor layer 220 can be formed on the first semiconductor layer 210 using an epitaxial process.

[0033] Please see Figure 3 In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), and (c) is a cross-sectional view along line B-B' in (a). In the bit line region A3, a plurality of first openings 230 are formed along the second direction D2. The first openings 230 penetrate the first semiconductor layer 210 and the second semiconductor layer 220 along the first direction D1. In this step, photolithography and etching processes can be used to form the first openings 230. The number of first openings 230 can be specifically set according to the structural dimensions of the semiconductor device; this embodiment does not limit this.

[0034] Please see Figure 6In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), (c) is a cross-sectional view along line B-B' in (a), and (d) is a cross-sectional view along line C-C' in (a). Along the first opening 230, a portion of the second semiconductor layer 220 between adjacent first openings 230 is removed, forming an initial gap 211 between adjacent first semiconductor layers 210.

[0035] Specifically, in this embodiment, the method of removing a portion of the second semiconductor layer 220 between adjacent first openings 230 along the first opening 230 includes:

[0036] Please see Figure 4 In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), and (c) is a cross-sectional view along line B-B' in (a). After forming the first opening 230, an insulating layer 231 is filled into the first opening 230, and the insulating layer 231 covers the inner wall of the first opening 230. The insulating layer 231 may be a silicon oxide layer.

[0037] Please see Figure 5 In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), and (c) is a cross-sectional view along line B-B' in (a). Part of the insulating layer 231 is removed, and the remaining insulating layer 231 serves as a protective layer 234 covering the two sidewalls of the first opening 230 that are opposite each other in the third direction D3. The remaining area of ​​the first opening 230 serves as the second opening 232. A dry etching process can be used to remove part of the insulating layer 231. In this step, the two sidewalls of the first opening 230 that are opposite each other in the second direction D2 are partially exposed, and the two sidewalls that are opposite each other in the third direction D3 are covered by the protective layer 234. The exposed sidewalls of the first opening 230 and the sidewalls of the protective layer 234 form the second opening 232. It is understood that, due to the thickness of the protective layer 234, the edges of the two sidewalls of the first opening 230 that are opposite each other in the second direction D2 are also covered by the protective layer 234.

[0038] Please see Figure 6 Along the second opening 232, the second semiconductor layer 220 exposed on the sidewall of the second opening 232 is removed, forming an initial gap 211 between adjacent first semiconductor layers 210. In this step, the topmost second semiconductor layer 220 is removed, the top first semiconductor layer 210 is exposed as the topmost layer, and the protective layer 234 corresponding to the topmost second semiconductor layer 220 is also removed accordingly.

[0039] Please see Figure 7In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), (c) is a cross-sectional view along line B-B' in (a), and (d) is a cross-sectional view along line C-C' in (a), forming a first support layer 240 within the initial void 211. Specifically, the method for forming the first support layer 240 includes: depositing support layer material in the stacked structure 21; etching away the support layer material on the upper surface of the stacked structure 21 (i.e., the surface of the topmost first semiconductor layer 210) and within the second opening 232, leaving the support layer material retained within the initial void 211 as the first support layer 240. The first support layer 240 may be a silicon nitride layer.

[0040] Please see Figure 8 The protective layer 234 is removed, exposing the first semiconductor layer 210 and the second semiconductor layer 220. In this step, a dry etching process can be used to remove the protective layer 234.

[0041] Please see Figure 1 and Figure 9 ,exist Figure 9 In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), (c) is a cross-sectional view along line B-B' in (a), and (d) is a cross-sectional view along line C-C' in (a). In step S11, the second semiconductor layer 220 is removed to form a first gap 212. In this step, the second semiconductor layer 220 is completely removed, exposing the surface of the first semiconductor layer 210. Specifically, in this embodiment, the second semiconductor layer 220 of the capacitor region A1, word line region A2, and bit line region A3 is removed along the first opening 230 to form the first gap 212. In this step, the second semiconductor layer 220 is completely removed, exposing the surface of the first semiconductor layer 210.

[0042] In this embodiment, an epitaxial process is used to form a second semiconductor layer 220 on the first semiconductor layer 210. However, due to the lattice mismatch between the second semiconductor layer 220 and the first semiconductor layer 210, the epitaxial thickness of the second semiconductor layer 220 on the first semiconductor layer 210 is limited. After removing the second semiconductor layer 220, the first spacing d1 between two adjacent first semiconductor layers 210 in the first direction D1 is small. The small first spacing d1 between two adjacent first semiconductor layers 210 limits the spacing of the semiconductor structure in the first direction D1 in subsequent processes. For example, the first spacing d1 between two adjacent first semiconductor layers 210 can define the distance between adjacent bit lines formed subsequently. If the first spacing d1 between two adjacent first semiconductor layers 210 is too small, the distance between adjacent bit lines will be affected, and it may even affect the spacing of the word line structure formed subsequently, increasing the difficulty of the process, which is not conducive to increasing the integration density. It may even prevent the word line structure on the same layer from being connected, affecting the reliability of the semiconductor device.

[0043] Therefore, the fabrication method provided in this disclosure increases the spacing between the first semiconductor layers 210 by thinning the first semiconductor layer 210. Specifically, please refer to... Figure 1 and Figure 10 ,exist Figure 10 In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), (c) is a cross-sectional view along line B-B' in (a), and (d) is a cross-sectional view along line C-C' in (a). In step S12, the first semiconductor layer 210 is thinned along the first gap 212 to increase the first spacing d1 between adjacent first semiconductor layers 210 in the first direction D1. In this step, a lateral etching process is used to etch the first semiconductor layer 210 through the first gap 212, that is, to thin the first semiconductor layer 210 from the upper and lower surfaces of the first semiconductor layer 210, thereby increasing the first spacing d1 between adjacent first semiconductor layers 210 in the first direction D1.

[0044] Please see Figure 1 Please see Figure 14 ,exist Figure 14In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), (c) is a cross-sectional view along line B-B' in (a), (d) is a cross-sectional view along line C-C' in (a), and (e) is a cross-sectional view along line D-D' in (a). In step S13, a portion of the first semiconductor layer 210 is removed to form multiple semiconductor pillars 240. Each semiconductor pillar 240 extends along a third direction D3, and the multiple semiconductor pillars 240 are arranged in an array along a first direction D1 and a second direction D2. The third direction D3 is parallel to the top surface of the substrate 20, and the second direction D2 intersects the third direction D3. In this embodiment, the third direction D3 is taken as the X-axis direction in a Cartesian coordinate system for illustration. Because the first semiconductor layer 210 is thinned, that is, the first spacing d1 between adjacent semiconductor pillars 240 in the first direction D1 is increased, for example, it is greater than the second spacing d2 between adjacent semiconductor pillars 240 in the second direction D2, thereby avoiding the distance between adjacent bit lines being affected and reducing the difficulty of the process.

[0045] As an example, this disclosure provides a method for removing a portion of a first semiconductor layer 210 to form a plurality of semiconductor pillars 240. The method includes the following steps:

[0046] Please see Figure 11 ,exist Figure 11 In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), (c) is a cross-sectional view along line B-B' in (a), and (d) is a cross-sectional view along line C-C' in (a). The first isolation layer 213 is filled in the first gap 212.

[0047] In this embodiment, the first isolation layer 213 is an oxide layer that fills the first gaps 212 between the first semiconductor layers 210 to support the first semiconductor layers 210. Due to limitations in semiconductor processes, in some embodiments, the first isolation layer 213 also covers the top surface of the stacked structure 21. In this case, the step may also include removing the first isolation layer 213 from the top surface of the stacked structure 21 to expose the first semiconductor layers 210 on the top surface, thus preventing the first isolation layer 213 from covering the surface of the semiconductor pillars 240 formed in subsequent processes, which would affect the contact between the gate structure layer formed in subsequent processes and the surface of the semiconductor pillars 240.

[0048] Please see Figure 12 ,exist Figure 12In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), (c) is a cross-sectional view along line B-B' in (a), and (d) is a cross-sectional view along line C-C' in (a). A first mask layer 300 is formed on the stacked structure 21. The first mask layer 300 includes a plurality of first pattern windows 301, each of which extends along a third direction D3, and the plurality of first pattern windows 301 are arranged along a second direction D2. Specifically, in this step, a mask material layer is first coated, and then the mask material layer is patterned to form mask strips arranged at intervals. The spaces between adjacent mask strips are the first pattern windows 301. In this embodiment, the first pattern window 301 exposes a first opening 230, so in subsequent processes, the first isolation layer 213 filled in the first opening 230 can be completely removed to avoid affecting the structure of the semiconductor pillar 240. In this embodiment, the first mask layer 300 may be a photoresist layer; in other embodiments, the first mask layer 300 may also be a hard mask layer. The projection of the first pattern window 301 on the substrate 20 covers the projection of the first opening 230 on the substrate 20, that is, the first pattern window 301 exposes the first isolation layer 213 filled in the first opening 230.

[0049] Please see Figure 13 ,exist Figure 13 In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), (c) is a cross-sectional view along line B-B' in (a), (d) is a cross-sectional view along line C-C' in (a), and (e) is a cross-sectional view along line D-D' in (a). Along the first graphics window 301, a portion of the first semiconductor layer 210 is removed to form semiconductor pillars 240. In this step, a portion of the first isolation layer 213 is removed, while the first isolation layer 213 between the semiconductor pillars 240 arranged in the first direction D1 is retained to support the semiconductor pillars 240. In this step, the first support layer 240 in the corresponding area of ​​the first graphics window 301 is also removed.

[0050] Following this step, the process further includes performing ion implantation on the semiconductor pillar 240 to form a doped semiconductor pillar 240, in preparation for the subsequent formation of transistor and capacitor structures. In other embodiments of this disclosure, ion implantation may also be performed during the formation of the first semiconductor layer 210.

[0051] Please see Figure 14 The first isolation layer 213 between the semiconductor pillars 240 arranged in the first direction D1 is removed, exposing the surface of the semiconductor pillars 240. Specifically, the first isolation layer 213 can be removed using an etching process. In this step, the first mask layer 300 is also removed.

[0052] Please see Figure 15 ,exist Figure 15 In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), (c) is a cross-sectional view along line B-B' in (a), (d) is a cross-sectional view along line C-C' in (a), and (e) is a cross-sectional view along line D-D' in (a). In step S14, a gate structure layer 260 is formed on the surface of the semiconductor pillar 240. The gate structure layer 260 corresponding to the word line region A2 serves as the gate, and the semiconductor pillar 240 corresponding to the gate serves as the channel region. The gate structure layer 260 includes a gate dielectric layer 261 and a gate material layer 262.

[0053] As an example, the step of forming a gate structure layer 260 on the surface of the semiconductor pillar 240 includes:

[0054] A gate dielectric layer 261 is formed on the surface of the semiconductor pillar 240, that is, the gate dielectric layer 261 covers the surface of the semiconductor pillar 240. The gate dielectric layer 261 can be silicon oxide or a high-k dielectric layer. The gate dielectric layer 261 can be formed using processes such as chemical vapor deposition or atomic layer deposition.

[0055] A gate material layer 262 is formed on the surface of the gate dielectric layer 261, meaning the gate material layer 262 covers the surface of the gate dielectric layer 261. Gate material layers 262 located in the same layer are connected in the first direction D1. Specifically, each semiconductor pillar 240 extends along the third direction D3. Semiconductor pillars 240 arranged sequentially in the second direction D2 are in the same layer, while semiconductor pillars 240 arranged sequentially in the first direction D1 are in different layers. In this embodiment, the gate material layers 262 covering the surfaces of the semiconductor pillars 240 in the same layer are connected to form an integral structure. The gate material layer 262 may be a tungsten layer.

[0056] A second isolation layer 263 is filled in the gap between adjacent gate structure layers 260 in the first direction D1, and the second isolation layer 263 fills the stacked structure 21 to provide support. In this embodiment, the second isolation layer 263 also covers the top surface of the stacked structure 21. The second isolation layer 263 includes, but is not limited to, a silicon dioxide layer.

[0057] The fabrication method also includes a step of forming bit lines. For details, please refer to [link to documentation]. Figure 18 ,exist Figure 18In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), (c) is a cross-sectional view along line B-B' in (a), (d) is a cross-sectional view along line C-C' in (a), and (e) is a cross-sectional view along line D-D' in (a). In the bit line region A3, the first support layer 240, the gate structure layer 260, and the semiconductor pillars 240 are removed to form multiple bit lines 270. Each bit line 270 extends along a first direction D1 and a third direction D3, and the multiple bit lines 270 are spaced apart along a second direction D2. In the semiconductor structure formed in this step, the semiconductor pillars 240 located on both sides of the bit line 270 are connected to the bit line 270, and both share the same bit line 270.

[0058] As an example, embodiments of this disclosure also provide a method for forming a plurality of bit lines 270, the method comprising the following steps:

[0059] Please see Figure 16 ,exist Figure 16 In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), (c) is a cross-sectional view along line B-B' in (a), (d) is a cross-sectional view along line C-C' in (a), and (e) is a cross-sectional view along line D-D' in (a). In the bit line region A3, the first support layer 240, the gate structure layer 260, and the semiconductor pillar 240 are removed to form a bit line trench 271, which penetrates the stacked structure 21. Further removal of a portion of the gate structure layer 260 along the sidewall of the bit line trench 271 forms a recess 272. In this step, while further removing a portion of the gate structure layer 260 along the sidewall of the bit line trench 271, the second isolation layer 263 is also partially removed. In the semiconductor structure formed in this step, the semiconductor pillar 240 is divided into two parts disposed on opposite sides of the bit line trench 271, and the recess 272 is recessed in a direction away from the center of the bit line trench 271. In this step, a dry etching process can be used to form bit line trenches 271, and a lateral etching process can be used to form grooves 272.

[0060] As an example, this disclosure provides a method for forming a bit line trench 271, the method comprising: forming a second mask layer on the surface of a stacked structure 21, the second mask layer having a second patterned window extending along a second direction D2; and removing a first support layer 240, a gate structure layer 260, and a semiconductor pillar 240 along the second patterned window to form the bit line trench 271. In this step, the second mask layer is a photoresist layer, and the bit line trench 271 is formed using photolithography and etching processes. In other embodiments, the second mask layer may also be a mask structure such as a hard mask.

[0061] Please see Figure 17 ,exist Figure 17In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), (c) is a cross-sectional view along line B-B' in (a), (d) is a cross-sectional view along line C-C' in (a), and (e) is a cross-sectional view along line D-D' in (a), forming a second support layer 250. The second support layer 250 fills the spaces between the first semiconductor layer 210 exposed in the groove 272. The second support layer 250 is used not only to support the semiconductor pillar 240 but also to isolate the bit line 270 from the gate. Specifically, in this embodiment, a silicon nitride layer is deposited and filled within the groove 272 as the second support layer 250. In this step, the second mask layer used when forming the bit line trench 271 can be used as a mask layer when depositing the second support material.

[0062] Please see Figure 18 A bit line material layer is formed within the bit line trench; the bit line material layer is patterned to form bit lines 270 spaced apart along the second direction D2, and each bit line 270 is connected to a plurality of semiconductor pillars 240 arranged along the first direction D1; a third isolation layer 273 is formed between the bit lines 270, the third isolation layer 273 being used to isolate adjacent bit lines 270 in the second direction D2. In this embodiment, the third isolation layer 273 includes, but is not limited to, silicon dioxide.

[0063] Please see Figure 19 ,exist Figure 19 In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), (c) is a cross-sectional view along line B-B' in (a), (d) is a cross-sectional view along line C-C' in (a), and (e) is a cross-sectional view along line D-D' in (a). In this embodiment, after forming the bit lines 270 spaced along the second direction D2, the fabrication method further includes forming a third support layer 280 at the junction of the capacitor region A1 and the word line region A2. The third support layer 280 supports the semiconductor pillars 240. The third support layer 280 not only supports the semiconductor pillars 240 but also isolates the word line region A2 and the capacitor region A1, preventing them from being electrically connected, thereby affecting the reliability of the semiconductor device. The gate structure layer 260 located between the second support layer 250 and the third support layer 280 serves as the gate structure of the transistor, and its corresponding semiconductor pillars 240 are the channel region of the transistor.

[0064] As an example, this disclosure provides a method for forming a third support layer 280, the method comprising: forming a third mask layer 281 on the surface of a stacked structure 21, the third mask layer 281 having a third patterned window 282 extending along a second direction D2 and corresponding to the boundary between capacitor region A1 and word line region A2; removing the gate structure layer 260 along the third patterned window 282; and filling with a support material to form the third support layer 280. In this embodiment, the third mask layer 281 may be a photoresist layer, and the third support layer 280 may be a silicon nitride layer.

[0065] Please see Figure 20 ,exist Figure 20 In the diagram, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), (c) is a cross-sectional view along line C-C' in (a), (d) is a cross-sectional view along line D-D' in (a), and (e) is a cross-sectional view along line E-E' in (a). In step S15, in capacitor region A1, the gate structure layer 260 on the surface of semiconductor pillar 240 is removed, and a capacitor structure layer 290 is formed, which covers the surface of semiconductor pillar 240. In this embodiment, capacitor structure layers 290 are formed in both capacitor regions A1. The capacitor structure layer 290 includes a lower electrode 291, a dielectric layer 292, and an upper electrode 293. The lower electrode 291 may be titanium nitride, the dielectric layer 292 may be a high-k dielectric layer, and the upper electrode 293 may be titanium nitride.

[0066] As an example, this disclosure provides a method for forming a capacitor structure layer 290, the method comprising: removing the gate structure layer 260 on the surface of a semiconductor pillar 240 in a capacitor region A1 to expose the surface of the semiconductor pillar 240; forming a lower electrode 291 covering the surface of the semiconductor pillar 240; forming a dielectric layer 292 covering the surface of the lower electrode 291; and forming an upper electrode 293 covering the surface of the dielectric layer 292.

[0067] In this embodiment, after forming the upper electrode 293, the following steps are also included: forming a polysilicon layer 294, wherein the polysilicon layer 294 fills the gaps between the upper electrodes 293.

[0068] The semiconductor device fabrication method provided in this disclosure increases the spacing between adjacent first semiconductor layers 210 in the first direction D1 by thinning the first semiconductor layer 210, thereby reducing the difficulty of the manufacturing process, which is beneficial for increasing integration density and improving the reliability of the semiconductor device. Furthermore, the fabrication method provided in this disclosure is a novel method for fabricating semiconductor devices, which forms the capacitor structure after forming the gate structure and bit line 270, rather than forming the gate structure and bit line 270 after forming the capacitor structure.

[0069] Furthermore, in some embodiments of this disclosure, the step of thinning the first semiconductor layer is performed before the step of forming the semiconductor pillars, which can better control the spacing (e.g., the second spacing d2) between semiconductor pillars (adjacent in the second direction D2) in the same layer, making it easier to bond the gate structure layers in the same layer. It is understood that in other embodiments of this disclosure, the step of thinning the semiconductor pillars may also be performed after the semiconductor pillars are formed.

[0070] This disclosure also provides a semiconductor device prepared using the above-described preparation method. Please refer to [link to relevant documentation]. Figures 1 to 20 The semiconductor device includes a substrate 20 and a plurality of semiconductor pillars 240 located on the substrate 20. The plurality of semiconductor pillars 240 are arranged in an array along a first direction D1 and a second direction D2 and extend along a third direction D3. The first direction D1 is perpendicular to the top surface of the substrate 20, the second direction D2 is parallel to the top surface of the substrate 20, and the third direction D3 is parallel to the top surface of the substrate 20, and the second direction D2 and the third direction D3 intersect. In this embodiment, the first direction D1 is the Z-axis direction in the Cartesian coordinate system, the second direction D2 is the Y-axis direction in the Cartesian coordinate system, and the third direction D3 is the X-axis direction in the Cartesian coordinate system, as an example for explanation.

[0071] Please see Figure 14 The first spacing d1 between adjacent semiconductor pillars 240 in the first direction D1 is greater than the second spacing d2 between adjacent semiconductor pillars 240 in the second direction D2, which can reduce the process difficulty of fabricating semiconductor devices.

[0072] In some embodiments, the semiconductor pillar 240 includes a capacitor region A1 and a word line region A2. The semiconductor device also includes a gate structure layer 260 located on the surface of the semiconductor pillar 240 in the word line region A2 and a capacitor structure layer 290 located on the surface of the semiconductor pillar 240 in the capacitor region A1. The gate structure layer 260 and the capacitor structure layer 290 are aligned through the same semiconductor pillar 240, which helps to improve the reliability of the semiconductor device.

[0073] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate and a stacked structure located on the substrate are formed. The stacked structure includes a first semiconductor layer and a second semiconductor layer that are alternately stacked along a first direction. The stacked structure includes a capacitor region, a word line region, and a bit line region. The first direction is a direction perpendicular to the top surface of the substrate. Remove the second semiconductor layer to form the first void; Thin the first semiconductor layer along the first gap; A portion of the first semiconductor layer is removed to form a plurality of semiconductor pillars, each of which extends along a third direction and the plurality of semiconductor pillars are arranged in an array in the first direction and the second direction, the second direction being a direction parallel to the top surface of the substrate, the third direction being a direction parallel to the top surface of the substrate, and the second direction intersecting the third direction. A gate structure layer is formed on the surface of the semiconductor pillar; In the capacitor region, the gate structure layer on the surface of the semiconductor pillar is removed, and a capacitor structure layer is formed, which covers the surface of the semiconductor pillar.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, A method for forming a stacked structure on the substrate includes: The first semiconductor layer and the second semiconductor layer are formed on the substrate, which are alternately stacked along the first direction; In the bit line region, a plurality of first openings are formed along the second direction, and the first openings penetrate the first semiconductor layer and the second semiconductor layer along the first direction. A portion of the second semiconductor layer between adjacent first openings is removed along the first opening to form an initial void between adjacent first semiconductor layers; A first support layer is formed within the initial void.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, A method for removing portions of the second semiconductor layer between adjacent first openings along the first opening includes: An insulating layer is filled into the first opening; A portion of the insulating layer is removed, and the remaining insulating layer serves as a protective layer covering the two side walls of the first opening that are disposed opposite each other in the third direction. The remaining area of ​​the first opening serves as the second opening. The second semiconductor layer exposed along the second opening sidewall is removed, forming the initial gap between adjacent first semiconductor layers; After the step of forming the first support layer, the protective layer is removed to expose the first semiconductor layer and the second semiconductor layer.

4. The method for fabricating a semiconductor device according to claim 2, characterized in that, A method for removing a portion of the first semiconductor layer to form a plurality of semiconductor pillars includes: A first mask layer is formed on the stacked structure. The first mask layer includes a plurality of first graphic windows, each of which extends along the third direction, and the plurality of first graphic windows are arranged along the second direction. A portion of the first semiconductor layer is removed along the first graphics window to form the semiconductor pillar.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The projection of the first graphics window onto the substrate overlaps the projection of the first opening onto the substrate; The step of thinning the first semiconductor layer further includes filling the first gap with a first insulating layer; The step of removing a portion of the first semiconductor layer along the first graphics window to form the semiconductor pillars includes: removing a portion of the first isolation layer while retaining the first isolation layer between the semiconductor pillars arranged in the first direction; Ion implantation is performed on the semiconductor pillar to form a doped semiconductor pillar; Remove the first isolation layer between the semiconductor pillars arranged in the first direction.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, A method for forming a gate structure layer on the surface of the semiconductor pillar includes: A gate dielectric layer is formed on the surface of the semiconductor pillar; A gate material layer is formed on the surface of the gate dielectric layer, and the gate material layers located on the surface of the same semiconductor pillar are connected in the first direction; A second isolation layer is filled between adjacent gate structure layers in the first direction.

7. The method for fabricating a semiconductor device according to claim 2, characterized in that, The method includes: In the bit line region, the first support layer, the gate structure layer and the semiconductor pillar are removed to form a bit line trench, which penetrates the stacked structure. Further removal of a portion of the gate structure layer along the sidewall of the bit line trench forms a groove; A second support layer is formed, which fills the spaces between the first semiconductor layers exposed in the groove; A bit line material layer is formed within the bit line trench; The bit line material layer is patterned to form bit lines spaced apart along the second direction, and each bit line is connected to a plurality of semiconductor pillars arranged along the first direction. A third isolation layer is formed between the bit lines.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The steps of forming the bit line trench include: A second mask layer is formed on the surface of the stacked structure, the second mask layer having a second pattern window extending along a second direction; The first support layer, the gate structure layer, and the semiconductor pillar are removed along the second graphic window to form the bit line trench.

9. The method for fabricating a semiconductor device according to claim 7, characterized in that, After the step of forming bit lines spaced apart along the second direction, the method further includes: forming a third support layer at the boundary between the capacitor region and the word line region, the third support layer supporting the semiconductor pillar.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The method for forming the third support layer includes: A third mask layer is formed on the surface of the stacked structure. The third mask layer has a third graphic window that extends along a second direction and corresponds to the boundary between the capacitor area and the word line area. Remove the gate structure layer along the third graphic window; Fill with support material to form the third support layer.

11. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method for removing the gate structure layer on the surface of the semiconductor pillar and forming the capacitor structure layer in the capacitor region includes: In the capacitor region, the gate structure layer on the surface of the semiconductor pillar is removed to expose the surface of the semiconductor pillar; A lower electrode is formed, which covers the exposed surface of the semiconductor pillar; A dielectric layer is formed, which covers the surface of the lower electrode. An upper electrode is formed, which covers the surface of the dielectric layer.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, After forming the upper electrode, the process further includes the following steps: forming a polycrystalline silicon layer, wherein the polycrystalline silicon layer fills the gaps between the upper electrodes.

13. The method for fabricating a semiconductor device according to claim 1, characterized in that, The capacitor region, the word line region, and the bit line region are arranged along the third direction. The stacked structure includes two capacitor regions and two word line regions. The bit line region is disposed between the two word line regions, and the two word line regions are disposed between the two capacitor regions.

14. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1-13, and the semiconductor device comprises: Substrate; A plurality of semiconductor pillars are located on a substrate, the plurality of semiconductor pillars are arranged in an array in a first direction and a second direction and extend along a third direction, the first direction being a direction perpendicular to the top surface of the substrate, the second direction being a direction parallel to the top surface of the substrate, and the third direction being a direction parallel to the top surface of the substrate, and the second direction intersects the third direction; a first spacing between adjacent semiconductor pillars in the first direction is greater than a second spacing between adjacent semiconductor pillars in the second direction.

15. The semiconductor device according to claim 14, characterized in that, The semiconductor pillar includes a capacitor region and a word line region, and the semiconductor device further includes: The gate structure layer is located on the surface of the semiconductor pillar in the word line region; A capacitor structure layer located on the surface of the semiconductor pillar in the capacitor region.

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