Base current compensation circuit for high-precision low-offset low-noise reference voltage source

Abstract

The application discloses a base current compensation circuit suitable for a high-precision low-offset low-noise reference voltage source, effectively suppresses the Early effect of a bipolar transistor, improves the base current replication precision, and by injecting an accurate base current into a band gap reference core circuit, avoids the nonlinearity introduced by the change of the forward current gain beta of the bipolar transistor in the band gap reference core circuit with the external conditions, thereby improving the temperature coefficient of the reference voltage source and the offset of the reference output voltage under different process angles.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a base current compensation circuit for a high-precision, low-offset, low-noise reference voltage source. Background Technology

[0002] The bandgap reference voltage source is responsible for providing a temperature-independent reference voltage to the circuit. This voltage is achieved by converting the base-emitter voltage V of the bipolar transistor. BE and its difference ΔV BE The weighted summation is achieved as follows: (1), where α is the proportionality coefficient. In previous studies, some scholars have proposed a low-offset, low-noise reference voltage source structure based on the current mode to reduce the impact of input offset and low-frequency noise of the error amplifier in the reference source on the accuracy of the reference output. The reference voltage source structure is as follows: Figure 1 As shown. Figure 1 The output voltage of the medium bandgap reference voltage source is: (2). Compared to the traditional structure, this structure significantly improves the input offset and low-frequency noise of the reference source, but it still has errors. The output voltage of the reference source will deviate significantly under different process angles, thus reducing the output accuracy. Summary of the Invention

[0003] To address the aforementioned problems in the prior art, this invention provides a base current compensation circuit suitable for a high-precision, low-offset, and low-noise reference voltage source.

[0004] The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a base current compensation circuit suitable for a high-precision, low-offset, and low-noise reference voltage source, comprising: a bias current replication circuit, a current mirror circuit, and a base current replication circuit.

[0006] The bias current replication circuit is used to accurately replicate the bias current of the key transistors that cause errors in the core circuit of the bandgap reference.

[0007] The current mirror circuit is used to mirror the bias current of the bipolar transistor in the bias current replication circuit on a 1:1 scale.

[0008] The base current replication circuit is used to generate a base current for compensation, and the generated base current is replicated proportionally and injected into the bandgap reference core circuit for compensation.

[0009] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0010] The base current compensation circuit provided by this invention effectively suppresses the Erlich effect of bipolar transistors, improves the accuracy of base current replication, and avoids the nonlinearity introduced by the change of the forward current gain β of bipolar transistors with external conditions by injecting precise base current into the bandgap reference core circuit, thereby improving the temperature coefficient of the reference voltage source and the offset of the reference output voltage under different process angles.

[0011] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0012] Figure 1 This is a circuit diagram of a low offset and low noise reference voltage source provided in an embodiment of the present invention;

[0013] Figure 2A V is provided in the embodiments of the present invention. BE A schematic diagram of PTAT error;

[0014] Figure 2B V is provided in the embodiments of the present invention. BE A schematic diagram of nonlinear error;

[0015] Figure 2C The ΔV provided in the embodiments of the present invention BE A schematic diagram of PTAT error and nonlinear error;

[0016] Figure 3 This is a schematic diagram of the base current compensation circuit for a high-precision, low-offset, low-noise reference voltage source provided in an embodiment of the present invention.

[0017] Figure 4 This is a base current compensation circuit for a high-precision, low-offset, low-noise reference voltage source provided in this embodiment of the invention;

[0018] Figure 5 yes Figure 4 The base current compensation circuit shown is... Figure 1 The overall circuit of the reference voltage source circuit shown;

[0019] Figure 6 These are exemplary temperature scan curves of the reference output at various process corners under different conditions, with and without base current compensation, provided by embodiments of the present invention.

[0020] Figure 7 These are exemplary temperature scan curves of the reference output at various process corners, provided by embodiments of the present invention, with and without base current compensation, when there is adjustment. Detailed Implementation

[0021] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0022] The inventors in this case discovered, based on simulation and test results, that when the process angle of the transistor changes, Figure 1 The output voltage of the reference source (i.e., the reference voltage source) with the structure shown will vary significantly, causing the temperature compensation circuit to require more TRIM bits, which greatly affects the output accuracy of the reference source under different process angles. Specifically, in formula (2), the resistor ratios R2 / R3 and R2 / R1 are relatively accurate and do not change with PVT, thus affecting the reference voltage V. REF The only factor affecting accuracy is V. BE1 and ΔV BE The following is an analysis of these errors.

[0023] 1) From the saturation current I S Caused error

[0024] Assuming in V BE middle, I S There exists a very small perturbation ΔI S (ΔI S < S According to Maclaurin's formula, we have formula (3):

[0025] (3);

[0026] Therefore, from ΔI S The resulting error can be expressed as formula (4):

[0027] (4);

[0028] Equation (4) shows that, ignoring ΔI S / I S Under the premise of temperature characteristics, I S The disturbance to V BE The effect is directly proportional to the absolute temperature, such as Figure 2A As shown. Since this PTAT error has only one degree of freedom, it can be calibrated by adjusting it at a single temperature point.

[0029] 2) Based on collector current I C Caused error

[0030] exist Figure 1 The collector current I of the BJT in the reference source shown C As a bias current, its value is related to V REF The accuracy is also affected. C It is the PTAT current, which is the difference ΔV between the base-emitter voltages of the two BJTs. BE ​The voltage drop occurs across resistor R1. External factors such as manufacturing process, power supply voltage, and temperature affect the voltage across the two BJTs. BE The effects are the same, therefore ΔV BE It remains relatively constant. However, external factors have a significant impact on the resistance value of R1, and R1 is what makes I... C Key factors that change with changing external conditions. When R1 changes, I... C There exists a very small change ΔI C (ΔI C < C When ), we have formula (5):

[0031] (5);

[0032] Ignore ΔI C / I C The temperature characteristics of I C Changes in V BE An additional PTAT item has been introduced. Similarly, this item can be calibrated through adjustments.

[0033] 3) Error caused by forward current gain β

[0034] exist Figure 1 In the reference source shown, according to the 1:1 mirror relationship of the current mirror, the two main branches carry equal currents. Due to the clamping effect of the operational amplifier, the voltages at points A and B are equal, so the two currents flowing through resistor R3 are also equal. Therefore, we have formula (6):

[0035] (6);

[0036] In formula (6), I C2 Let ' be the collector current of a single BJT in Q2. For Q1, we have formula (7):

[0037] (7);

[0038] When there is a small perturbation Δβ (Δβ << β) in β, we have formula (8):

[0039] (8);

[0040] Formula (8) shows that, due to V BE1 The presence of the multiplication factor 2 / (β-2) in the last term will cause a change in β in V. BE1 Introducing non-PTAT items, such as Figure 2B As shown. This results in V BE1 The error has more than one degree of freedom, therefore, adjustment alone cannot reduce or completely eliminate the error.

[0041] ​4) ΔV BE error

[0042] exist Figure 1 The reference source shown employs offset and noise cancellation techniques to reduce the impact of input offset and low-frequency noise. However, according to formula (6), since I B1 I B2 The existence of I C2 'and I C1 The magnitude of ΔV is not strictly equal to the ratio of the number of Q1 to Q2, which in turn affects the PTAT voltage ΔV. BE There is an error. The analysis is as follows:

[0043] For Q2, we have formula (9):

[0044] (9);

[0045] Based on formulas (6), (7), and (9), we can obtain formula (10):

[0046] (10);

[0047] When β has a very small change Δβ (Δβ << β), we have formula (11):

[0048] (11);

[0049] From formulas (10) and (11), it can be seen that in I B1 I B2 Under the influence of ΔV BE An additional PTAT term is introduced, which will affect ΔV as β changes. BE Introducing non-PATA terms, such as Figure 2C As shown. Similarly, this error cannot be calibrated by adjusting at a single temperature point.

[0050] In summary, the inventors discovered that, Figure 1 In the reference source shown, due to the flow through P M1 and P M2 The current in the two branches exists as I. B1 I B2 The difference lies in the fact that when factors such as manufacturing process, power supply voltage, and temperature change, the forward current gain β of the BJT will change, and consequently, the voltage will also change. BE1 and ΔV BE The introduction of nonlinear offsets, which cannot be calibrated by adjustment, affects the accuracy of the reference output and ΔV at various process angles. REF The offset.

[0051] Based on this discovery, the present invention provides a base current compensation circuit suitable for a high-precision, low-offset, low-noise reference voltage source. Utilizing the clamping effect of an operational amplifier, the BJT used for current replication is connected to... Figure 1 The BJTs in the bandgap reference core circuit shown have the same collector-emitter voltage, which effectively avoids the Erlich effect of bipolar transistors. It accurately replicates the base current of the key transistor that causes errors in the bandgap reference core circuit and injects it into the bandgap reference core circuit to compensate for the inherent error of this type of bandgap reference core circuit.

[0052] Figure 3 This is a schematic diagram of a base current compensation circuit for a high-precision, low-offset, low-noise reference voltage source, provided by an embodiment of the present invention. The base current compensation circuit includes a bias current replication circuit, a current mirror circuit, and a base current replication circuit. The bias current replication circuit is used to accurately replicate the bias current of the critical transistor in the bandgap reference core circuit that causes errors. The current mirror circuit is used to mirror the bias current of the bipolar transistor in the bias current replication circuit at a 1:1 ratio. The base current replication circuit is used to generate a base current for compensation, and after proportionally replicating the generated base current, it is injected into the bandgap reference core circuit for compensation.

[0053] Here, the key transistor causing the error is NPN transistor Q2. The bipolar transistors in the core bandgap reference circuit are NPN transistors Q1 and Q2, where the base of NPN transistor Q2 is connected to the collector of NPN transistor Q1.

[0054] In some embodiments, the bias current replication circuit includes: an NPN transistor Q3, an operational amplifier OP1, and a low threshold voltage NMOS transistor N. M1 The base of NPN transistor Q3 is connected to the base of NPN transistor Q2 in the bandgap reference core circuit, the emitter of NPN transistor Q3 is grounded, and the collector of NPN transistor Q3 is connected to the low threshold voltage NMOS transistor N. M1 The source of the circuit is connected to the inverting input of operational amplifier OP1, the non-inverting input of operational amplifier OP1 is connected to the collector of NPN transistor Q2 in the bandgap reference core circuit, and the output of operational amplifier OP1 is connected to the low threshold voltage NMOS transistor N. M1 The gate of the low threshold voltage NMOS transistor M1 The drain of the transistor is connected to the current mirror circuit. The introduction of operational amplifier OP1 ensures that the collector voltage of NPN transistor Q3 is equal to the collector voltage of NPN transistor Q2 in the bandgap reference core circuit, thus avoiding current replication errors caused by the Erlich effect of bipolar transistors and improving current replication accuracy.

[0055] In some embodiments, the current mirror circuit includes: a PMOS transistor P M5 PMOS transistor PM6 Among them, PMOS transistor P M5 The drain of the PMOS transistor P M5 The gate of the PMOS transistor P M6 The low threshold voltage NMOS transistor in the gate and bias current replication circuit M1 The drains of the PMOS transistor are connected, and the PMOS transistor P M5 The source of the PMOS transistor P M6 The source is connected to V. DD PMOS transistor P M6 The drain and base current replication circuit are connected.

[0056] In some embodiments, the base current replication circuit includes: an NPN transistor Q4 and a PMOS transistor P. M7 Operational amplifier OP2, low threshold voltage PMOS transistor P M8 and low threshold voltage PMOS transistor P M9 Among them, PMOS transistor P M7 The source, the non-inverting input of operational amplifier OP2, and the PMOS transistor P M6 The drains of the PMOS transistor are connected, and the PMOS transistor P M7 The gate of the PMOS transistor P M7 The drain of the NPN transistor Q4 is connected to the collector of the NPN transistor Q4, the emitter of the NPN transistor Q4 is grounded, and the base of the NPN transistor Q4 is connected to the low threshold voltage PMOS transistor P. M8 The drain of the low threshold voltage PMOS transistor P M8 Gate, low threshold voltage PMOS transistor P M9 The gates of the two are connected, the inverting input of operational amplifier OP2, the output of operational amplifier OP2, and the low threshold voltage PMOS transistor P. M8 The source of the low threshold voltage PMOS transistor P M9 The source is connected to the low threshold voltage PMOS transistor P M9 The drain of the transistor is connected to the base of the NPN transistor Q1 in the bandgap reference core circuit. Operational amplifier OP2 acts as a buffer to prevent the current mirror in the base current replication circuit from being shunted from the bias current of the bipolar transistor.

[0057] Here, the current mirror in the base current replication circuit is controlled by a low threshold voltage PMOS transistor P. M8 and low threshold voltage PMOS transistor P M9 Composition, and, low threshold voltage PMOS transistor P M8 and low threshold voltage PMOS transistor P M9 The ratio of the number of items is 1:3.

[0058] For example, Figure 4This invention provides a base current compensation circuit suitable for a high-precision, low-offset, low-noise reference voltage source. For example... Figure 4 As shown, the base of NPN transistor Q3 is used to connect to the base of NPN transistor Q2 in the bandgap reference core circuit (i.e., Figure 4 Point C in the diagram), the emitter of NPN transistor Q3 is connected to GND, and the collector of NPN transistor Q3 is connected to the low threshold voltage NMOS transistor N. M1 The source of the transistor is connected to the inverting input of operational amplifier OP1; the non-inverting input of operational amplifier OP1 is used to connect to the collector of NPN transistor Q2 in the bandgap reference core circuit. Figure 4 Point D in the diagram), the output of operational amplifier OP1 is connected to the low threshold voltage NMOS transistor N. M1 Gate of the NMOS transistor with low threshold voltage. M1 The drain of the PMOS transistor P M5 The drain of the PMOS transistor P M5 The gate of the PMOS transistor P M6 The gates of the PMOS transistors are connected; PMOS transistor P M5 The source of the PMOS transistor P M6 The source is connected to V. DD PMOS transistor P M6 The drain of the PMOS transistor P M7 The source of the PMOS transistor is connected to the non-inverting input of the operational amplifier OP2; PMOS transistor P M7 The gate of the PMOS transistor P M7 The drain of the transistor is connected to the collector of the NPN transistor Q4, and the emitter of the NPN transistor Q4 is grounded; the base of the NPN transistor Q4 and the low threshold voltage PMOS transistor P are connected. M8 The drain of the low threshold voltage PMOS transistor P M8 Gate, low threshold voltage PMOS transistor P M9 The gates are connected; the inverting input of operational amplifier OP2, the output of operational amplifier OP2, and the low threshold voltage PMOS transistor P M8 The source of the low threshold voltage PMOS transistor P M9 The source is connected; low threshold voltage PMOS transistor P M9 The drain is used to connect to the base of NPN transistor Q1 in the bandgap reference core circuit.

[0059] Here, Q3 and Q4 are exactly the same as Q2. In the base current compensation circuit, Q3 is connected to the base of Q2, and OP1 clamps the collectors of Q2 and Q3 (i.e., Figure 4 Points D and E in the diagram are used to ensure the collector-emitter voltage V of Q3 and Q2. CE Equal current replication avoids errors caused by the Erlich effect. OP2 acts as a buffer, preventing current mirroring errors. M8 PM9 From P M6 The drain of Q4 carries away current, thus making the collector current of Q4 exactly equal to the collector current of Q3, i.e., I4. C4 =I C3 =I C2 According to V BE =V T ln(I C / I S ), has V BE2 =V BE3 =V BE4 Therefore, it is only necessary to set V. CE4 =V CE2 Q4 can accurately replicate the base current of Q2, which is achieved by adjusting P. M7 The aspect ratio is achieved. Because the base of Q3 is also located in the P-band of the bandgap reference core circuit... M1 One branch is extracted with a size equal to I. B2 The base current, therefore, setting P M8 and P M9 With a ratio of 1:3, the base current used for compensation can be obtained, and its value is equal to 3I. B2 The compensation current is injected into the base of Q1 in the bandgap reference core circuit (i.e., Figure 4 Point A in the diagram reduces the nonlinear offset introduced by the two base currents, while also avoiding the I drawn by the base current compensation circuit. B2 The reference voltage V output by the core circuit of the bandgap reference. REF This reduces the impact of external factors, thereby improving the temperature coefficient and output accuracy of the reference voltage source when external factors change.

[0060] For example, Figure 5 for Figure 4 The base current compensation circuit shown is... Figure 1 The complete circuit of the reference voltage source circuit is shown. Figure 5 As shown, the core circuit of the bandgap reference includes: NPN transistors Q1 and Q2, two resistors R1, R2, two resistors R3, and a PMOS transistor P. M1 PMOS transistor P M2 PMOS transistor P M3 And operational amplifier OP. Specifically, the base of NPN transistor Q1, the upper end of the first resistor R1, the upper end of the first resistor R3, and PMOS transistor P... M1 The drain of the NPN transistor Q1 is connected to the inverting input of the operational amplifier OP. The collector of the NPN transistor Q1 and the lower end of the first resistor R1 are connected to the base of the NPN transistor Q2. The collector of the NPN transistor Q2 is connected to the lower end of the second resistor R1. The upper end of the second resistor R1, the upper end of the second resistor R3, and the PMOS transistor P... M2The drain of the PMOS transistor is connected to the non-inverting input of the operational amplifier OP. M1 The gate of the PMOS transistor P M2 The gate of the PMOS transistor P M3 The gate of the PMOS transistor is connected to the output of the operational amplifier OP. M3 The drain of the PMOS transistor is connected to the upper end of resistor R2. M1 The source of the PMOS transistor P M2 The source of the PMOS transistor P M3 The source terminal V DD The emitter of NPN transistor Q1, the emitter of NPN transistor Q2, the lower end of resistor R2, and the lower ends of the two resistors R3 are connected to GND.

[0061] It is worth noting that the base current compensation circuit proposed in this invention is not only applicable to the specific bandgap reference core circuit structure proposed in this invention, but also applicable to any NPN transistor Q1 and NPN transistor Q2 according to... Figure 1 The positive feedback structure formed by the connection shown is that the base of NPN transistor Q2 is connected to the collector of NPN transistor Q1.

[0062] To further illustrate the effectiveness of the base current compensation circuit for a high-precision, low-offset, low-noise reference voltage source provided by this invention, some experimental results are presented below.

[0063] Table 1 shows the maximum, minimum, and variation values ​​of the reference output voltage at various process corners, with and without base current compensation, without any adjustment. Figure 6 This is the corresponding temperature scan curve.

[0064] Table 1

[0065]

[0066] According to Table 1 and Figure 6 When using the base current compensation circuit provided by this invention, the reference output voltage V at each process corner is... REF The temperature coefficients are significantly better than those without base current compensation. Furthermore, with base current compensation at each process corner, the deviation ΔV of the reference output voltage is significantly lower. REF =12.932mV, lower than the offset ΔV of the reference output voltage without base current compensation. REF =14.412mV. Clearly, the base current compensation circuit provided by this invention is effective.

[0067] Table 2 shows the maximum, minimum, and variation values ​​of the reference output voltage at various process corners, with and without base current compensation, under the condition of adjustment. Figure 7This is the corresponding temperature scan curve.

[0068] Table 2

[0069]

[0070] According to Table 2 and Figure 7 It can be seen that, when using the base current compensation circuit provided by this invention, the temperature coefficient of the reference output voltage at process corners TT and SS is significantly better than that without base current compensation, while at process corner FF the two are approximately the same. Furthermore, with base current compensation, the offset ΔV of the reference output voltage at each process corner is... REF =1.272mV, lower than the offset ΔV of the reference output voltage without base current compensation. REF =1.485mV. Clearly, the base current compensation circuit provided by this invention is effective.

[0071] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0072] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0073] In this specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. While different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce a good effect.

[0074] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A base current compensation circuit suitable for a high-precision, low-offset, low-noise reference voltage source, characterized in that, include: Bias current replication circuit, current mirror circuit and base current replication circuit; The bias current replication circuit is used to accurately replicate the bias current of the key transistors that cause errors in the core circuit of the bandgap reference. The current mirror circuit is used to mirror the bias current of the bipolar transistor in the bias current replication circuit on a 1:1 scale. The base current replication circuit is used to generate a base current for compensation, and after proportionally replicating the generated base current, it is injected into the bandgap reference core circuit for compensation. The key transistor is the NPN transistor Q2 in the bandgap reference core circuit; The bias current replication circuit includes: an NPN transistor Q3, an operational amplifier OP1, and a low-threshold NMOS transistor N. M1 ; The base of NPN transistor Q3 is connected to the base of NPN transistor Q2, the emitter of NPN transistor Q3 is grounded, and the collector of NPN transistor Q3 is connected to the low threshold voltage NMOS transistor N. M1 The source of the transistor is connected to the inverting input of the operational amplifier OP1, the non-inverting input of the operational amplifier OP1 is connected to the collector of the NPN transistor Q2, and the output of the operational amplifier OP1 is connected to the low threshold voltage NMOS transistor N. M1 The gate of the low threshold voltage NMOS transistor N M1 The drain of the device is connected to the current mirror circuit.

2. The base current compensation circuit for a high-precision, low-offset, low-noise reference voltage source according to claim 1, characterized in that, The current mirror circuit includes: a PMOS transistor P M5 PMOS transistor P M6 ; The PMOS transistor P M5 The drain of the PMOS transistor P M5 The gate of the PMOS transistor P M6 The gate of the low threshold voltage NMOS transistor N M1 The drain of the PMOS transistor is connected to the PMOS transistor P. M5 The source of the PMOS transistor P M6 The source is connected to V. DD The PMOS transistor P M6 The drain is connected to the base current replication circuit.

3. The base current compensation circuit for a high-precision, low-offset, low-noise reference voltage source according to claim 2, characterized in that, The base current replication circuit includes: an NPN transistor Q4 and a PMOS transistor P. M7 Operational amplifier OP2, low threshold voltage PMOS transistor P M8 and low threshold voltage PMOS transistor P M9 ; The PMOS transistor P M7 The source of the PMOS transistor, the non-inverting input of the operational amplifier OP2, and the PMOS transistor P M6 The drain of the PMOS transistor is connected to the PMOS transistor P. M7 The gate of the PMOS transistor P M7 The drain of the transistor is connected to the collector of the NPN transistor Q4, the emitter of the NPN transistor Q4 is grounded, and the base of the NPN transistor Q4 is connected to the low threshold voltage PMOS transistor P. M8 The drain of the low threshold voltage PMOS transistor P M8 The gate of the low threshold voltage PMOS transistor P M9 The gate of the operational amplifier OP2 is connected to the inverting input terminal of the operational amplifier OP2, the output terminal of the operational amplifier OP2, and the low threshold voltage PMOS transistor P. M8 The source of the low threshold voltage PMOS transistor P M9 The source of the low threshold voltage PMOS transistor is connected to the source. M9 The drain of the transistor is connected to the base of the NPN transistor Q1 in the bandgap reference core circuit.

4. The base current compensation circuit for a high-precision, low-offset, low-noise reference voltage source according to claim 1, characterized in that, The operational amplifier OP1 is introduced to make the collector voltage of the NPN transistor Q3 equal to the collector voltage of the NPN transistor Q2.

5. The base current compensation circuit for a high-precision, low-offset, low-noise reference voltage source according to claim 3, characterized in that, The operational amplifier OP2 is used as a buffer to prevent the current mirror in the base current replication circuit from being diverted from the bias current of the bipolar transistor.

6. The base current compensation circuit for a high-precision, low-offset, low-noise reference voltage source according to claim 1, characterized in that, The core circuit of the bandgap reference includes: NPN transistors Q1 and Q2, two resistors R1 and R2, two resistors R3, and a PMOS transistor P. M1 PMOS transistor P M2 PMOS transistor P M3 and operational amplifiers (OP); Among them, the base of the NPN transistor Q1, the upper end of the first resistor R1, the upper end of the first resistor R3, and the PMOS transistor P M1 The drain of the NPN transistor Q1 is connected to the inverting input terminal of the operational amplifier OP. The collector of the NPN transistor Q1 and the lower end of the first resistor R1 are connected to the base of the NPN transistor Q2. The collector of the NPN transistor Q2 is connected to the lower end of the second resistor R1. The upper end of the second resistor R1, the upper end of the second resistor R3, and the PMOS transistor P are connected to the base of the NPN transistor Q2. M2 The drain of the PMOS transistor is connected to the non-inverting input of the operational amplifier OP. M1 The gate of the PMOS transistor P M2 The gate of the PMOS transistor P M3 The gate of the PMOS transistor is connected to the output terminal of the operational amplifier OP. M3 The drain of the PMOS transistor is connected to the upper end of the resistor R2 and the PMOS transistor P. M1 The source of the PMOS transistor P M2 The source of the PMOS transistor P M3 The source terminal V DD The emitter of the NPN transistor Q1, the emitter of the NPN transistor Q2, the lower end of the resistor R2, and the lower ends of the two resistors R3 are grounded.

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