A multi-chip parallel full-bridge package structure and a packaging method

Abstract

The application relates to the technical field of chip packaging, and particularly discloses a full-bridge packaging structure and a packaging method for multiple chips in parallel. The packaging structure comprises a heat dissipation bottom plate, a copper-coated ceramic substrate, power semiconductor chips, bonding wires, driving resistors, thermistors, positive and negative copper bars, pouring glue, a shell and wiring terminals. The copper-coated ceramic substrate is welded on the heat dissipation bottom plate, the power semiconductor chips, the thermistors and the wiring terminals are welded on the DBC substrate, and the surface electrodes of the power semiconductor chips are electrically connected with the DBC substrate through the bonding wires. The packaging structure provided by the application realizes a compact, compatible, multiple-chip parallel, high-reliability, low-stray-inductance and current-sharing packaging module through reasonable DBC substrate layout optimization, the driving circuit adopts a Kelvin structure, the negative feedback influence of common-source parasitic inductance on the driving circuit is reduced, and the switching speed is improved. The corresponding method enables the packaging structure to be realized at low cost and with reliable processing quality.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, in particular to a multi-chip parallel full-bridge packaging structure and a packaging method. BACKGROUND

[0002] Power electronics technology is widely used in aerospace, rail transportation, electric vehicles and power systems, and full circuits are widely used in the industry due to their simple structure and strong scalability. The existing commercial modules have problems such as large parasitic inductance, uneven current of switching tubes, and low current-carrying capacity. SUMMARY

[0003] To solve the above problems, the present application provides a multi-chip parallel full-bridge packaging structure, which can improve the current-carrying capacity of the module and reduce the parasitic inductance of the main circuit. The present application also provides a packaging method.

[0004] To achieve the above purpose, the technical scheme adopted by the present application is as follows:

[0005] In the first technical scheme, a multi-chip parallel full-bridge packaging structure includes a DBC substrate, the DBC substrate has a circuit layer, the circuit layer includes an A area copper foil and a B area copper foil, the A area copper foil includes a negative DC- copper foil and an alternating current AC copper foil of a lower bridge located on both sides of the negative DC- copper foil, the B area copper foil includes a positive DC+ copper foil and an alternating current AC copper foil of an upper bridge located on both sides of the positive DC+ copper foil, and the A area copper foil and the B area copper foil are symmetrically arranged, and the alternating current AC copper foil of the lower bridge and the alternating current AC copper foil of the upper bridge are connected by copper blocks respectively;

[0006] N chips of a first part of the lower bridge are welded on one alternating current AC copper foil of the lower bridge, and N chips of a second part of the lower bridge are welded on another alternating current AC copper foil of the lower bridge; N chips of a first part of the upper bridge are welded on the positive DC+ copper foil and close to one alternating current AC copper foil of the upper bridge, and N chips of a second part of the upper bridge are welded on the positive DC+ copper foil and close to another alternating current AC copper foil of the upper bridge, and N is a positive integer greater than 2;

[0007] The N chips of the first part of the lower bridge, the N chips of the second part of the lower bridge, the N chips of the first part of the upper bridge, and the N chips of the second part of the upper bridge are connected in parallel, and the N chip groups of the first part of the lower bridge, the N chip groups of the second part of the lower bridge, the N chip groups of the first part of the upper bridge, and the N chip groups of the second part of the upper bridge are connected in series to form a full-bridge packaging.

[0008] In the first technical scheme, as a preferred embodiment, the N chip groups of the first part of the lower bridge, the N chip groups of the second part of the lower bridge, the N chip groups of the first part of the upper bridge, and the N chip groups of the second part of the upper bridge are all linearly arranged chips.

[0009] In the first technical solution, as preferred, the N groups of chips of the first part of the lower bridge and the N groups of chips of the second part of the lower bridge are mirror arranged; the N groups of chips of the first part of the upper bridge and the N groups of chips of the second part of the upper bridge are mirror arranged.

[0010] In the first technical solution, as preferred, the AC copper foils of the two lower bridges on both sides of the negative DC-copper foil have the same width and are symmetric to the center line of the negative DC-copper foil.

[0011] In the first technical solution, as preferred, the AC copper foils of the two upper bridges on both sides of the positive DC-copper foil have the same width and are symmetric to the center line of the positive DC-copper foil.

[0012] In the first technical solution, as preferred, the DBC substrate further has a DC+ terminal and a DC- terminal, the DC+ terminal is electrically connected to the positive DC-copper foil through ultrasonic welding process, and the DC- terminal is electrically connected to the negative DC-copper foil through ultrasonic welding process.

[0013] In the first technical solution, as preferred, the copper foil in the A area and the chips welded on the copper foil in the A area constitute a lower bridge driving circuit, and the copper foil in the B area and the chips welded on the copper foil in the B area constitute an upper bridge driving circuit.

[0014] The upper bridge driving circuit is symmetric up and down and symmetric left and right.

[0015] The lower bridge driving circuit is symmetric up and down and symmetric left and right.

[0016] In the first technical solution, as preferred, the DBC substrate has a lower copper foil, and a circle of small holes is etched at a certain distance from the edge of the lower copper foil.

[0017] In the first technical solution, as preferred, the outermost edge of the upper copper foil is arranged at a distance of 1 mm from the edge of the ceramic substrate, and the outermost edge of the lower copper foil is arranged at a distance of 1 mm from the edge of the ceramic substrate.

[0018] In the first technical solution, a packaging method is used to package the full-bridge packaging structure of the multi-chip parallel connection as described in any one of the first technical solutions, which comprises the following steps,

[0019] S1. A corresponding copper-clad ceramic substrate is prepared according to the structure of the power module to be packaged, and the front metal layer and the bottom metal layer of the copper-clad ceramic substrate are etched, followed by surface nickel plating treatment.

[0020] S2. The power chips are welded or sintered to the corresponding copper foil positions of the copper-clad ceramic substrate by using the first solder.

[0021] S3, electrically connecting the surface electrode of the power semiconductor chip and the copper foil of the copper clad ceramic substrate by a wire bonding process;

[0022] S4, welding the driving resistor and the thermistor to the corresponding position of the upper surface metal layer of the insulating substrate by using the second solder;

[0023] S5, fixing the shell on the heat dissipation substrate, and electrically connecting the driving terminal and the alternating current (AC) terminal in the shell with the corresponding metal layer of the insulating substrate by using a wire bonding process, and electrically connecting the direct current (DC) positive terminal and the DC negative terminal in the shell with the substrate by using an ultrasonic bonding process.

[0024] S6, injecting the insulating gel into the shell, vacuumizing, and then heating or standing at room temperature to solidify the insulating gel; and obtaining the packaged power module after installing the cover plate.

[0025] The beneficial effects of using the present application are:

[0026] The multi-chip parallel full-bridge packaging structure can improve the current carrying capacity of the module, the copper foil on the front surface of the DBC substrate is divided into two areas, and the structure is symmetrical, the main loop parasitic inductance is small, the positive and negative large copper bar terminals can improve the current intensity of the current to the chip, the processing method is reliable, the packaging structure can be realized, the cost is low, and the reliability is high. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 It is a structure diagram of the copper clad ceramic substrate of the multi-chip parallel full-bridge packaging structure of the present application.

[0028] Figure 2 It is a front view of the copper clad ceramic substrate.

[0029] Figure 3 It is a back view of the copper clad ceramic substrate.

[0030] Figure 4 It is a side view of the copper clad ceramic substrate.

[0031] Figure 5 It is a top view of the chip layout.

[0032] Figure 6 It is an axial side view of the chip layout.

[0033] Figure 7 It is an axial side view of the internal structure.

[0034] Figure 8 It is a top view of the internal structure.

[0035] Figure 9Fig. 1 is a schematic diagram of a main circuit terminal structure.

[0036] Figure 10 Fig. 2 is a schematic diagram of an external structure.

[0037] Figure 11 Fig. 3 is a circuit topology diagram.

[0038] Figure 12 Fig. 4 is a packaging method flowchart. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the present technical solution clearer and more apparent, the present technical solution will be further described in detail below with reference to specific embodiments. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present technical solution.

[0040] As shown in Figures 1-4 The present embodiment proposes a multi-chip parallel full-bridge packaging structure. The structure of the copper-clad ceramic substrate is divided into an A region and a B region. The copper-clad ceramic substrate is a rectangular plate structure. The middle layer is a ceramic substrate A2, and the two sides are DBC substrates A1. The lower layer of the ceramic substrate A2 is covered with a lower copper foil A3. The lower copper foil A3 is provided with dimple holes A4 around the four sides. The middle length direction is the first direction, and the width direction is the second direction. The front surface of the copper-clad ceramic substrate has multiple copper foils. The front copper foils of the A region and the front copper foils of the B region are arranged in mirror symmetry in the length direction. The negative DC-copper foil A6 is in the middle and occupies the main area. The lower bridge AC copper foils A5 and A7 are arranged on both sides of the negative DC-copper foil A6 in the second direction. The lower bridge gate drive copper foils A8 and the lower bridge auxiliary source drive copper foils A9 are arranged on the outer side of the lower bridge AC copper foils A5 and A7 in the second direction. The gate resistor port copper foil A10 is another port copper foil where the gate resistor is located. The solder resist A11 on the upper copper foil is arranged at the corresponding position of the upper copper foil.

[0041] The B region is arranged in mirror symmetry with the A region. Therefore, the DBC substrate B1, the ceramic substrate B2, the lower copper foil B3, the dimple holes B4 of the lower copper foil, the upper bridge AC copper foils B5 and B7, the positive DC+ copper foil B6, the upper bridge gate drive copper foils B8, the upper bridge auxiliary source drive copper foils B9, the gate resistor port copper foil B10, and the solder resist B11 on the upper copper foil are arranged in the same way as in the A region, and will not be described again.

[0042] The copper clad ceramic substrate is a three-layer structure, the upper and lower layers are conductor layers, and the middle layer is a ceramic substrate A2, B2. The upper conductor layer is etched to form multiple independent conductor layers, which together with the power chip, bonding wire, terminal, etc. form a circuit topology. The ceramic substrate A2, B2 in the middle layer serves as an insulator and a heat conductor. The lower copper foil A3, B3 is generally connected to the heat sink through a thermal interface material and serves as a heat conductor. In this embodiment, the conductor layer is high-conductivity oxygen-free copper, hereinafter referred to as copper foil, and the surface of the copper foil can be treated by electroplating to prevent oxidation. The ceramic substrate in the middle layer can generally be selected from alumina, aluminum nitride, zirconium-doped alumina, silicon nitride, etc. In this embodiment, in order to improve the heat dissipation performance, the ceramic substrate is selected to be aluminum nitride ceramic with high thermal conductivity. The lower copper foil is also etched with a circle of dimple holes A4, B4 at a certain distance from the edge, and the small holes help to release the thermal stress of the copper foil edge and improve the reliability. The outer edges of the upper and lower copper foils are at a certain distance from the edges of the ceramic substrate A2, B2, and this distance is determined according to the voltage withstand requirement of the module. In this embodiment, the outermost edge of the upper copper foil is set to be 1mm from the edge of the ceramic substrate A2, B2, and the outermost edge of the lower copper foil A3, B3 is set to be 1mm from the edge of the ceramic substrate A2, B2. The upper copper foil is processed to form a circuit pattern, which serves as a conductor and a heat conductor. In this embodiment, the upper copper foil has a solder resist layer A11, B11, which prevents the solder from overflowing after melting. The topology circuit proposed in this embodiment can be an IGBT, MOSFET, etc. The bonding wire material connecting the surface electrodes of the power semiconductor chip includes copper, aluminum, gold, etc. In this embodiment, the bonding wire is selected to be aluminum bonding wire, which is the most commonly used and has low cost.

[0043] As shown in Figure 5 and Figure 6 , the upper bridge first part chips HQ1, HQ2, HQ3, HQ4, HQ5 have five, the upper bridge second part chips HQ6, HQ7, HQ8, HQ9, HQ10 have five, the lower bridge first part chips LQ1, LQ2, LQ3, LQ4, LQ5 have five, and the lower bridge second part chips LQ6, LQ7, LQ8, LQ9, LQ10 have five. Each of the above twenty chips has a corresponding auxiliary source bonding wire, gate drive bonding wire, power source bonding wire, and drive resistor.

[0044] The above bridge first part chip HQ5 is taken as an example, which has a gate drive bonding wire HQ5-1, an auxiliary source bonding wire HQ5-2, a power source bonding wire HQ5-3 and a drive resistance HQ5-4. The above bridge second part chip HQ10 is taken as an example, which has a gate drive bonding wire HQ10-1, an auxiliary source bonding wire HQ10-2, a power source bonding wire HQ10-3, a drive resistance HQ10-4. The below bridge first part chip LQ1 is taken as an example, which has a gate drive bonding wire LQ1-1, an auxiliary source bonding wire LQ1-2, a power source bonding wire LQ1-3 and a drive resistance LQ1-4. The below bridge second part chip LQ6 is taken as an example, which has a gate drive bonding wire LQ6-1, an auxiliary source bonding wire LQ6-2, a power source bonding wire LQ6-3, a drive resistance LQ6-4. The bonding wires and drive resistances of the rest of the chips are not described again.

[0045] In order to improve the flow capacity, the power source bonding wires HQ5-3, HQ10-3, LQ1-3, LQ6-3 are generally composed of a plurality of thick bonding wires in parallel, in the embodiment, the source power bonding wires HQ5-3, HQ10-3, LQ1-3, LQ6-3 are each composed of 8 aluminum bonding wires with a diameter of 15 mil in parallel, in actual application, as many bonding wires as possible can be selected according to the size of the bondable area on the chip. In the embodiment, considering the small size of the chip gate, the gate drive bonding wires HQ5-1, HQ10-1, LQ1-1, LQ6-1 and the auxiliary source bonding wires HQ5-2, HQ10-2, LQ1-2, LQ6-2 are each composed of one aluminum bonding wire with a diameter of 5 mil.

[0046] As shown in Figure 7 and Figure 8 The two copper blocks 2, 3 are used to connect the lower bridge alternating current copper foils A5, A7 on the two sides of the copper base plate 1 and the upper bridge alternating current copper foils B5, B7. In addition, DC+ terminal 4, DC- terminal 5, AC terminal 6-1, 6-2, upper bridge gate drive terminal 7, 9, upper bridge auxiliary source terminal 8, 10, lower bridge gate drive terminal 11, 13, lower bridge auxiliary source terminal 12, 14, thermistor terminal 15, 16, connection bonding wires 17-26, 27-1, 27-2 of the terminals and a plastic shell 28 are also provided. In the embodiment, the connection bonding wires of the terminals all use aluminum bonding wires with a diameter of 20 mil. In order to improve the corrosion resistance of the terminals in humid, moldy and salt spray environments, the surface of the terminals selected in the embodiment is plated with nickel, and in addition, gold plating can also be selected.

[0047] Specifically, the drain of the ten chips HQ1-HQ10 of the upper bridge is welded to the positive DC+ copper foil B6 by the first solder, and the positive DC+ copper foil B6 is connected to the DC+ terminal 4 by ultrasonic welding technology; the gate of the ten chips HQ1-HQ10 of the upper bridge is connected to the gate drive copper foil B8 by the gate drive bonding wires HQ1-1-HQ10-1, the gate drive copper foil B8 is connected to the copper foil B10 of the upper bridge through the corresponding drive resistors HQ1-4-HQ10-4, and finally connected to the gate drive terminals 7, 9 by the bonding wires 17, 19. The auxiliary source of the ten chips HQ1-HQ10 of the upper bridge is connected to the auxiliary source copper foil B9 by the auxiliary source bonding wires HQ1-2-HQ10-2, and then connected to the auxiliary source terminals 8, 10 of the upper bridge by the bonding wires 18, 20. The drain of the ten chips LQ1-LQ10 of the lower bridge is welded to the AC copper foils A5, A7 by the first solder, and then connected to the AC copper foils B5, B7 through the copper blocks 2, 3, and finally connected to the AC terminals 6-1, 6-2 by the bonding wires 27-1, 27-2; the gate of the ten chips LQ1-LQ10 of the lower bridge is connected to the gate drive copper foil A8 by the gate drive bonding wires LQ1-1-LQ10-1, the gate drive copper foil A8 is connected to the copper foil A10 of the lower bridge through the corresponding drive resistors LQ1-4-LQ10-4, and finally connected to the gate drive terminals 11, 13 by the bonding wires 21, 23. The auxiliary source of the ten chips LQ1-LQ10 of the lower bridge is connected to the auxiliary source copper foil A9 by the auxiliary source bonding wires LQ1-2-LQ10-2, and then connected to the auxiliary source terminals 12, 14 of the lower bridge by the bonding wires 22, 24.

[0048] As shown in Figure 9 , the AC terminal is electrically connected to the AC copper foils B5, B7 by the bonding wires 27-1, 27-2. The DC+ terminal 4 and the DC- terminal 5 are electrically connected to the negative DC- copper foil A6 and the positive DC+ copper foil B6 by ultrasonic welding technology. In addition, the ultrasonic welding terminal improves the current flow intensity, thereby improving the current intensity flowing to the chip, improving the performance of the chip, and increasing the service life of the terminal.

[0049] As shown in Figure 10 , the external structure is composed of a plastic shell 28, a copper substrate 1, terminals 4-16, a connecting nut 30 and a plastic cover plate 29.

[0050] The circuit topology of the packaged chip formed by the multi-chip parallel full-bridge packaging structure is as shown in Figure 11As shown, it is mainly formed by the upper bridge gate drive terminals 7 and 9, the lower bridge gate drive terminals 11 and 13, the upper bridge auxiliary source terminals 8 and 10, the lower bridge auxiliary source terminals 12 and 14, the DC+ terminal 4, the AC terminals 6-1 and 6-2, the DC- terminal 5, and the thermistor terminals 15 and 16, as well as the electrical connections between them.

[0051] In this embodiment, the power chips HQ1-HQ5 in the first part of the upper bridge and HQ6-HQ10 in the second part of the upper bridge are symmetrical vertically, as are the power chips LQ1-LQ5 in the first part of the lower bridge and LQ6-LQ10 in the second part of the lower bridge. Furthermore, the upper bridge chips HQ1-HQ10 and the lower bridge chips LQ1-LQ10 are equidistant from the central axis. The DC+ terminals 4, DC- terminals 5, and AC terminals 6-1 and 6-2 are symmetrical horizontally, and the DC+ terminals 4 and DC- terminals 5 are symmetrical vertically. In addition, the upper bridge drive circuit and the lower bridge drive circuit are also symmetrical vertically and horizontally. This achieves symmetry in the power commutation circuit and drive circuit of the parallel chips, improving the current sharing characteristics of the parallel chips.

[0052] like Figure 12 As shown, the present invention also proposes a packaging method for a power module corresponding to the above-mentioned multi-chip parallel full-bridge packaging structure, comprising the following steps:

[0053] (1) Prepare a corresponding copper-clad ceramic substrate according to the structure of the power module to be packaged, etch the front metal layer and the bottom metal layer of the copper-clad ceramic substrate, and then perform surface nickel plating.

[0054] (2) The power chip is soldered or sintered onto the corresponding copper foil position of the copper-clad ceramic substrate using the first solder;

[0055] (3) The surface electrode of the power semiconductor chip is electrically connected to the copper foil of the copper-clad ceramic substrate by wire bonding process;

[0056] (4) Use a second solder to weld the driving resistor and the thermistor to the corresponding positions on the upper surface metal layer of the insulating substrate;

[0057] (5) Fix the outer shell on the heat dissipation substrate, use wire bonding technology to electrically connect the drive terminals and AC terminals in the outer shell to the corresponding metal layers of the insulating substrate, and use ultrasonic bonding technology to electrically connect the DC positive terminal (DC+) and DC negative terminal (DC-) in the outer shell to the substrate.

[0058] (6) Inject the insulating gel into the housing, evacuate, and then heat or let it stand at room temperature to cure the insulating gel; after installing the cover plate, the encapsulated power module is obtained.

[0059] The above merely describes the preferred embodiments of the present application, and for those skilled in the art, many changes can be made to the specific implementation and application range based on the technical content of the present application, as long as the changes do not deviate from the concept of the present application, and all fall within the protection scope of the present patent.

Claims

1. A multi-chip parallel full-bridge package structure, characterized in that: DBC substrate, the DBC substrate has a circuit layer, the circuit layer includes A area copper foil and B area copper foil, the A area copper foil includes negative DC-copper foil and lower bridge alternating current AC copper foil located on both sides of the negative DC-copper foil, the B area copper foil includes positive DC+ copper foil and upper bridge alternating current AC copper foil located on both sides of the positive DC+ copper foil, and the A area copper foil and the B area copper foil are symmetrically arranged, the lower bridge alternating current AC copper foil and the upper bridge alternating current AC copper foil are connected by copper blocks respectively; N chips of the first part of the lower bridge are welded on one lower bridge alternating current AC copper foil, and N chips of the second part of the lower bridge are welded on another lower bridge alternating current AC copper foil;N chips of the first part of the upper bridge are welded on the negative DC-copper foil and close to one upper bridge alternating current AC copper foil, and N chips of the second part of the upper bridge are welded on the negative DC-copper foil and close to another lower bridge alternating current AC copper foil, and N is a positive integer greater than 2; The N chips of the first part of the lower bridge are connected in parallel, the N chips of the second part of the lower bridge are connected in parallel, the N chips of the first part of the upper bridge are connected in parallel, and the N chips of the second part of the upper bridge are connected in parallel, and the N chip groups of the first part of the lower bridge, the N chip groups of the second part of the lower bridge, the N chip groups of the first part of the upper bridge and the N chip groups of the second part of the upper bridge are connected in series to form a full-bridge package; The A area copper foil and the chips welded on the A area copper foil constitute a lower bridge drive circuit, and the B area copper foil and the chips welded on the B area copper foil constitute an upper bridge drive circuit; The upper bridge drive circuit is symmetric on the upper and lower sides and symmetric on the left and right sides; The lower bridge drive circuit is symmetric on the upper and lower sides and symmetric on the left and right sides.

2. The full-bridge package structure of multiple chips in parallel according to claim 1, characterized in that: The N chip groups of the first part of the lower bridge, the N chip groups of the second part of the lower bridge, the N chip groups of the first part of the upper bridge and the N chip groups of the second part of the upper bridge are all linearly arranged chips.

3. The full-bridge parallel multi-chip package structure of claim 1, wherein: The N chip groups of the first part of the lower bridge and the N chip groups of the second part of the lower bridge are mirror image arranged, and the N chip groups of the first part of the upper bridge and the N chip groups of the second part of the upper bridge are mirror image arranged.

4. The full-bridge parallel multi-chip package structure of claim 1, wherein: The two lower bridge alternating current AC copper foils on both sides of the negative DC-copper foil have the same width and are symmetric with the center line of the negative DC-copper foil.

5. The full-bridge parallel multi-chip package structure of claim 1, wherein: The two upper bridge alternating current AC copper foils on both sides of the positive DC+ copper foil have the same width and are symmetric with the center line of the positive DC+ copper foil.

6. The full-bridge parallel multi-chip package structure of claim 1, wherein: The DBC substrate further has a DC+ terminal and a DC- terminal, the DC+ terminal is electrically connected with the positive DC+ copper foil by ultrasonic welding process, and the DC- terminal is electrically connected with the negative DC-copper foil by ultrasonic welding technology.

7. The full-bridge parallel multi-chip package structure of claim 1, wherein: The DBC substrate has a lower copper foil, and a small hole is also etched at a certain distance from the edge of the lower copper foil.

8. A packaging method for packaging the full-bridge packaging structure of the multi-chip parallel connection according to any one of claims 1-7, characterized in that: The method comprises the following steps, S1, a corresponding copper clad ceramic substrate is prepared according to the structure of the power module to be packaged, the front metal layer and the bottom metal layer of the copper clad ceramic substrate are etched, and then surface nickel plating treatment is carried out; S2, the power chip is welded or sintered to the corresponding copper foil position of the copper clad ceramic substrate by using the first solder; S3, the surface electrode of the power semiconductor chip is electrically connected with the copper foil of the copper clad ceramic substrate by wire bonding process. S4, using the second solder to weld the driving resistance and the thermistor to the corresponding position of the upper surface metal layer of the insulating substrate; S5, fixing the shell on the heat dissipation substrate, using the wire bonding process to electrically connect the driving terminal and the alternating current AC terminal in the shell with the corresponding metal layer of the insulating substrate, and using the ultrasonic bonding process to electrically connect the direct current positive DC+ and direct current negative DC- terminals in the shell with the substrate; S6, injecting the insulating gel into the shell, vacuumizing, and then heating or standing at room temperature to solidify the insulating gel; obtaining the packaged power module after installing the cover plate.

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