A test circuit and a test method for wafer-level system integration assembly

Abstract

The present invention provides a test circuit and a test method for wafer-level system integration and assembly. The test circuit includes: a wafer-level transfer test circuit, which includes a wafer, connection pads, and metal bumps. The wafer includes a test area and a functional area. Through-silicon vias are provided in the wafer. The connection pads are connected to the through-silicon vias, and the metal bumps are connected to the through-silicon vias. Conductive connections in the test area are located on the side of the connection pads away from the wafer and are used to connect two connection pads; a test structure, which is a test circuit built inside a functional chip. The functional chip where the test structure is located is on the side of the connection pads away from the wafer, and the welding of the preselected connection pads and through-silicon vias is good. The technical solution provided by the embodiments of the present invention realizes the testing of the wafer-level system in wafer-level system integration and assembly, can timely detect production defects, monitor and warn of product failures, and provide necessary diagnostic information for early isolation, repair, or replacement of the wafer-level system.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer-level device testing, and particularly to a test circuit and a test method for wafer-level system integration and assembly. Background Art

[0002] Wafer-level systems offer extremely high integration density, providing advantages in terms of performance, power consumption, etc. that cannot be matched by board-level systems. On the other hand, high-density integration places high demands on the reliability of the assembly process, and missing defects during the testing phase and failures occurring during the product life cycle can cause relatively significant losses.

[0003] In the current industrial community, wafer-level systems have not been widely commercialized, and there is no systematic test circuit and test method. Summary of the Invention

[0004] The present invention provides a test circuit and a test method for wafer-level system integration and assembly to test the wafer-level system during wafer-level system integration and assembly, promptly detect production defects, monitor and warn of product failures, and provide necessary diagnostic information for early isolation, repair, or replacement of the wafer-level system.

[0005] According to one aspect of the present invention, there is provided a test circuit for wafer-level system integration and assembly, including:

[0006] A wafer-level transfer test circuit, the wafer-level transfer test circuit including a wafer, connection pads, and metal bumps. The wafer includes a test area and a functional area. Through-silicon vias are provided in the wafer. The connection pads are located on a first surface of the wafer and are connected to the through-silicon vias. The metal bumps are located on a second surface of the wafer opposite to the first surface, and the metal bumps are connected to the through-silicon vias. Conductive lines in the test area are located on a side of the connection pads away from the wafer and are used to connect two connection pads;

[0007] During the preprocessing stage of the wafer-level system, the conduction condition of two metal bumps in the test area of the wafer-level transfer test circuit is used to detect whether the welding between the connection pads and the through-silicon vias in the test area is good; whether the welding between the connection pads and the through-silicon vias in the test area is good is used to determine whether the welding between the connection pads and the through-silicon vias in the functional area is good, so as to complete the test of the through-silicon via path in the functional area;

[0008] A test structure, the test structure being a test circuit built inside a functional chip. The functional chip where the test structure is located is on a side of the connection pads away from the wafer. Pins of the functional chip where the test structure is located are in one-to-one contact with preselected connection pads, and the welding between the preselected connection pads and the through-silicon vias is good;

[0009] During the chip packaging and testing stage of the wafer-level system, whether there is a preset electrical signal at the metal bumps corresponding to the preselected connection pads in the test area, which is used to detect whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads is good; whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads in the test area is good, which is used to determine whether the edge of the functional chip in the functional area warps after being packaged on the connection pads.

[0010] During the reliability test stage of the wafer-level system, the electrical performance of the preselected test structure is used to detect the reliability of the life cycle of the wafer-level system integration and assembly, where the connection between the pins of the functional chip where the preselected test structure is located and the preselected connection pads is good.

[0011] Optionally, it further includes a lithography process alignment test circuit, which is located in the test area, and the lithography process alignment test circuit is used to determine whether the connection between the wafer surface in the functional area and / or the metal lines formed by two lithography processes in the wafer is good.

[0012] Optionally, the test structure includes an inverter circuit, and the attenuation of the frequency of the preselected test structure is used to detect the reliability of the life cycle of the wafer-level system integration and assembly.

[0013] Optionally, the lithography process alignment test circuit includes:

[0014] The first metal bumps are located on the surface of the wafer in the test area and are arranged at intervals in the first direction;

[0015] The second metal bumps are located on the surface of the wafer in the test area and are arranged at intervals in the first direction. In the second direction, the second metal bumps and the first metal bumps are arranged at intervals in a one-to-one correspondence;

[0016] Multiple first metal lines with different line widths are formed by the first lithography and etching processes, and the first metal lines are connected to the first metal bumps in a one-to-one correspondence;

[0017] Multiple second metal lines with different line widths are formed by the second lithography and etching processes. Among them, the second metal lines are connected to the second metal bumps in a one-to-one correspondence, and the second metal lines are connected to the first metal lines in a one-to-one correspondence, and the line widths of the connected first metal lines and second metal lines are the same;

[0018] Whether the first metal bumps and the second metal bumps can conduct is used to detect whether the connection between the connected first metal lines and second metal lines in the second direction is good;

[0019] The line widths of the well-connected first metal wire and second metal wire are used to determine the line width range that ensures good connection between the first metal wire and the second metal wire, and further to determine the line width range in which the metal wires formed by two photolithography processes can be well connected;

[0020] The line width range in which the metal wires formed by two photolithography processes can be well connected is used to determine whether the connection between the wafer surface in the functional area and / or the metal wires formed by two photolithography processes within the wafer is good.

[0021] Optionally, a plurality of preselected connection pads and a plurality of metal bumps are correspondingly arranged at each corner of the functional chip where the test structure is located;

[0022] During the chip packaging and testing stage of the wafer-level system, whether there is a preset electrical signal at the metal bumps corresponding to the preselected connection pads at the four corners of the functional chip where the test structure is located in the test area is used to detect whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads is good.

[0023] Optionally, the test area is multiplexed as the functional area, and a fuse is arranged between the two metal bumps on the second surface of the wafer. After the fuse is blown, the two metal bumps are disconnected.

[0024] According to another aspect of the present invention, there is provided a test method for wafer-level system integration and assembly, including:

[0025] During the preprocessing stage of the wafer-level system, the conduction condition of the two metal bumps in the test area of the wafer-level transfer test circuit is used to detect whether the connection between the connection pad and the through-silicon via in the test area is good;

[0026] Wherein, the wafer-level transfer test circuit includes a wafer, the connection pad, the metal bump. The wafer includes a test area and a functional area. A through-silicon via is arranged in the wafer. The connection pad is located on the first surface of the wafer and is connected to the through-silicon via. The metal bump is located on the second surface of the wafer opposite to the first surface, and the metal bump is connected to the through-silicon via. The conductive connection line in the test area is located on the side of the connection pad away from the wafer and is used to connect two connection pads;

[0027] According to whether the connection between the connection pad and the through-silicon via in the test area of the wafer-level transfer test circuit is good, it is judged whether the connection between the connection pad and the through-silicon via in the functional area is good, so as to complete the test of the through-silicon via path in the functional area;

[0028] In the chip packaging and testing stage of the wafer-level system, by testing whether there is a preset electrical signal at the metal bumps corresponding to the preselected connection pads in the test area, it is detected whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads is good. Among them, the welding between the preselected connection pads and the through-silicon vias is good. The test structure is a test circuit built inside the functional chip. The functional chip where the test structure is located is on the side of the connection pads away from the wafer. The pins at the corners of the functional chip where the test structure is located are in one-to-one contact with the preselected connection pads;

[0029] According to whether the connection between the pins at the corners of the functional chip where the test structure is located in the test area and the preselected connection pads is good, it is judged whether the edge of the functional chip in the functional area warps after being packaged on the connection pads;

[0030] In the reliability test stage of the wafer-level system, through the electrical performance of the preselected test structure, the reliability of the life cycle of the wafer-level system integration and assembly is detected. Among them, the connection between the pins of the functional chip where the preselected test structure is located and the preselected connection pads is good.

[0031] Optionally, in the chip packaging and testing stage of the wafer-level system, before detecting whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads is good by testing whether there is a preset electrical signal at the metal bumps corresponding to the preselected connection pads in the test area, it further includes:

[0032] Align the test circuit through a lithography process to determine whether the connection between the wafer surface in the functional area and / or the metal lines formed by two lithography processes in the wafer is good. Among them, the lithography process for aligning the test circuit is located in the test area;

[0033] In the chip packaging and testing stage of the wafer-level system, detecting whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads is good by testing whether there is a preset electrical signal at the metal bumps corresponding to the preselected connection pads in the test area includes:

[0034] In the chip packaging and testing stage of the wafer-level system, by testing whether there is a preset electrical signal at the metal bumps corresponding to the preselected connection pads in the preset test area, it is detected whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads is good. Among them, the preset test area is the area where the connection between the wafer surface in the test area and / or the metal lines formed by two lithography processes in the wafer is good.

[0035] Optionally, in the reliability test stage of the wafer-level system, detecting the reliability of the life cycle of the wafer-level system integration and assembly through the electrical performance of the preselected test structure includes:

[0036] In the reliability test stage of the wafer-level system, the reliability of the life cycle of the wafer-level system integration and assembly is detected by the attenuation of the frequency of a preselected test structure, wherein the test structure includes an inverter circuit.

[0037] Optionally, aligning the test circuit through a lithography process to determine whether the connection between the wafer surface in the functional area and / or the metal wires formed by two lithography processes within the wafer is good includes:

[0038] Forming a plurality of first metal bumps arranged at intervals in a first direction on the surface of the wafer in the test area;

[0039] Forming a plurality of second metal bumps arranged at intervals in a first direction on the surface of the wafer in the test area, and in a second direction, the second metal bumps and the first metal bumps are arranged at intervals in one-to-one correspondence;

[0040] Forming a plurality of first metal wires with different line widths through a first lithography and etching process, and the first metal wires are connected to the first metal bumps in one-to-one correspondence;

[0041] Forming a plurality of second metal wires with different line widths through a second lithography and etching process, wherein the second metal wires are connected to the second metal bumps in one-to-one correspondence, and the second metal wires are connected to the first metal wires in one-to-one correspondence, and the line widths of the mutually connected first metal wires and second metal wires are the same;

[0042] By detecting whether the first metal bumps and the second metal bumps can be conducted, it is detected whether the connection between the connected first metal wires and second metal wires in the second direction is good;

[0043] According to the line widths of the first metal wires and the second metal wires with good connections, determine the line width range that ensures good connection between the first metal wires and the second metal wires, so as to determine the line width range in which the metal wires formed by two lithography processes can be connected well;

[0044] According to the line width range in which the metal wires formed by two lithography processes can be connected well, determine whether the connection between the wafer surface in the functional area and / or the metal wires formed by two lithography processes within the wafer is good.

[0045] Optionally, in the chip packaging test stage of the wafer-level system, by testing whether there is a preset electrical signal at the metal bumps corresponding to the preselected connection pads in the test area, detecting whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads is good includes:

[0046] During the chip packaging and testing stage of the wafer-level system, by testing whether there is a preset electrical signal at the metal bumps corresponding to the preselected connection pads at the four corners of the functional chip where the test structure is located in the test area, it is detected whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads is good. Among them, multiple preselected connection pads and multiple metal bumps are correspondingly arranged at each corner of the functional chip where the test structure is located.

[0047] Optionally, the test area is reused as the functional area. During the preprocessing stage of the wafer-level system, after detecting whether the welding between the connection pads and the through-silicon vias in the test area is good by detecting the conduction condition of the two metal bumps in the test area of the wafer-level transfer test circuit, it further includes:

[0048] Fusing the fuse connecting the two metal bumps. Among them, a fuse is arranged between the two metal bumps on the second surface of the wafer. After the fuse is fused, the two metal bumps are disconnected.

[0049] The technical solution provided by the embodiments of the present invention, on the basis of ensuring that the electrical connection between the through-silicon vias and the metal bumps on the wafer is unobstructed, the wafer-level system judges whether the welding between the connection pads and the through-silicon vias in the functional area is good according to whether the welding between the connection pads and the through-silicon vias in the test area of the wafer-level transfer test circuit is good during the preprocessing stage, so as to complete the test of the through-silicon via path in the functional area; whether the connection between the pins at the corners of the functional chip where the test structure is located in the test area and the preselected connection pads is good is used to judge whether the edge of the functional chip is warped after being packaged on the connection pads in the functional area; during the reliability test stage of the wafer-level system, the electrical performance of the preselected test structure is used to detect the reliability of the life cycle of the wafer-level system integration and assembly. Therefore, the above technical solution realizes testing the wafer-level system during the preprocessing stage of the wafer-level system integration and assembly, the chip packaging and testing stage of the wafer-level system, and the reliability test stage of the wafer-level system, timely discovering production defects, monitoring and warning product failures, and providing necessary diagnostic information for the wafer-level system to be isolated, repaired or replaced in advance.

[0050] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Brief Description of the Drawings

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0052] Figure 1 It is a schematic diagram of the test area structure of a test circuit for wafer-level system integration assembly provided according to an embodiment of the present invention;

[0053] Figure 2 It is a schematic diagram of the structure of a test circuit for wafer-level system integration assembly provided according to an embodiment of the present invention;

[0054] Figure 3 It is a schematic diagram of a test structure including an inverter circuit provided according to an embodiment of the present invention;

[0055] Figure 4 It is a schematic diagram of the structure of a lithography process alignment test circuit provided according to an embodiment of the present invention;

[0056] Figure 5 It is a schematic diagram of the structure of a test circuit for another wafer-level system integration device provided according to an embodiment of the present invention;

[0057] Figure 6 It is a schematic diagram of the structure of a test circuit for yet another wafer-level system integration device provided according to an embodiment of the present invention;

[0058] Figure 7 It is a schematic diagram of the flow of a test method for wafer-level system integration assembly provided according to an embodiment of the present invention;

[0059] Figure 8 It is a schematic diagram of the flow of another test method for wafer-level system integration assembly provided according to an embodiment of the present invention;

[0060] Figure 9 is Figure 8 a schematic diagram of the flow of the test method included in S1301;

[0061] Figure 10 It is a comparison chart of the size parameters of two interconnection technologies, QSFP optical module and UCIe;

[0062] Figure 11 It is a schematic diagram of a wafer-level system;

[0063] Figure 12 It is a schematic diagram of the process of wafer-level system integration provided according to an embodiment of the present invention. Detailed implementation manners

[0064] To enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0065] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or elements does not necessarily have to be limited to those steps or elements clearly listed, but may include other steps or elements not clearly listed or inherent to these processes, methods, products or devices.

[0066] In order to test the wafer-level system in wafer-level system integration assembly, timely detect production defects, monitor and warn of product failures, and provide necessary diagnostic information for early isolation, repair or replacement of the wafer-level system, the embodiments of the present invention provide the following technical solutions:

[0067] As Figure 1 shown, Figure 1 is a schematic structural diagram of a test area of a test circuit for wafer-level system integration assembly according to an embodiment of the present invention. The test circuit for wafer-level system integration assembly includes:

[0068] A wafer-level transfer test circuit 100, which includes a wafer 101, connection pads 102, and metal bumps 103. The wafer 101 includes a test area and a functional area. Through-silicon vias TSV1 are provided in the wafer 101. The connection pads 102 are located on the first surface of the wafer 101 and are connected to the through-silicon vias TSV1. The metal bumps 103 are located on the second surface of the wafer 101 opposite to the first surface, and the metal bumps 103 are connected to the through-silicon vias TSV1. Conductive traces 104 in the test area are located on the side of the connection pads 102 away from the wafer 101 and are used to connect two connection pads 102.

[0069] In the prebond stage of the wafer-level system, the conduction condition of the two metal bumps 103 in the test area of the wafer-level transfer test circuit is used to detect whether the welding of the connection pads 102 and the through-silicon vias TSV1 in the test area is good. Figure 1Among them, it is to test whether the welding between the connection pad 102 and the through-silicon via TSV1 in the test area is good, so as to judge whether the welding between the connection pad 102 and the through-silicon via TSV1 in the functional area is good, so as to complete the test of the through-silicon via path in the functional area.

[0070] As Figure 2 shown, Figure 2 FIG. is a schematic structural diagram of a test circuit for wafer-level system integration and assembly according to an embodiment of the present invention. The test circuit for wafer-level system integration and assembly further includes a test structure, and the test structure is a test circuit built inside the functional chip 200. The functional chip 200 where the test structure is located is on the side of the connection pad 102 away from the wafer 101. The pins 201 of the functional chip 200 where the test structure is located are in one-to-one contact with the preselected connection pad 102, and the welding between the preselected connection pad 102 and the through-silicon via TSV1 is good.

[0071] During the chip package test stage of the wafer-level system, whether there is a preset electrical signal at the metal bump 103 corresponding to the preselected connection pad 102 in the test area is used to detect whether the connection between the pin 201 of the corner 200a of the functional chip 200 where the test structure is located and the preselected connection pad 102 is good. Whether the connection between the pin 201 of the corner 200a of the functional chip 200 where the test structure is located and the preselected connection pad 102 in the test area is good is used to judge whether the back edge of the functional chip is warped after being packaged on the connection pad in the functional area.

[0072] As Figure 3 shown, Figure 3 FIG. is a schematic structural diagram inside a test structure according to an embodiment of the present invention. During the reliability test stage of the wafer-level system, the electrical performance of the preselected test structure is used to detect the reliability of the life cycle of the wafer-level system integration and assembly. Among them, the connection between the pin 201 of the functional chip 200 where the preselected test structure is located and the preselected connection pad 102 is good.

[0073] It should be noted that Figure 1 FIG. shows the wafer 101 in the test area, and there is no conductive connection 104 on the surface of the connection pad 102 on the first surface of the wafer 101 in the functional area. The welding process between the connection pad 102 and the wafer 101 in the test area is the same as the welding process between the connection pad 102 and the wafer 101 in the functional area.

[0074] And in this embodiment, in the wafer-level transfer test circuit 100, the electrical connection between the through-silicon via TSV1 and the metal bump 103 is unobstructed.

[0075] On the basis of ensuring unobstructed electrical connection between the through-silicon via TSV1 and the metal bump 103, in the preprocessing stage of the wafer-level system, in the wafer-level transfer test circuit 100, the conductive connection line 104 connects the two connection pads 102. The two connection pads 102 are connected to the corresponding metal bumps 103 through the through-silicon via TSV1. On the wafer-level test machine platform, the metal bumps 103 are in contact with the probes, forming a loop composed of the conductive connection line 104, the connection pads 102, the through-silicon via TSV1, the metal bumps 103, and the probes. If the welding quality between the connection pad 102 and the through-silicon via TSV1 in the test area is poor, resulting in the inability to transmit electrical signals between the connection pad 102 and the through-silicon via TSV1 in the test area, then electrical signals cannot be transmitted between the two metal bumps 103 in the test area of the wafer-level transfer test circuit, and it can be determined that the welding quality between the connection pad 102 and the through-silicon via TSV1 in the test area is poor. If the welding between the connection pad 102 and the through-silicon via TSV1 in the test area is good, then electrical signals can be transmitted between the two metal bumps 103 in the test area of the wafer-level transfer test circuit, and it can be determined that the welding between the connection pad 102 and the through-silicon via TSV1 in the test area is good. The above technical solution can achieve the conduction condition of the two metal bumps 103 in the test area of the wafer-level transfer test circuit in the preprocessing stage of the wafer-level system, and is used to detect whether the welding between the connection pad 102 and the through-silicon via TSV1 in the test area is good.

[0076] In the chip packaging and testing stage of the wafer-level system, on the wafer-level testing machine table, the metal bumps 103 corresponding to the preselected connection pads 102 are in contact with the probes. Whether there is a preset electrical signal in the metal bumps 103 corresponding to the preselected connection pads 102 is used to detect whether the connection between the pins 201 of the corner 200a of the functional chip 200 where the test structure is located and the preselected connection pads 102 is good. If the connection quality between the pins 201 of the corner 200a of the functional chip 200 where the test structure is located and the preselected connection pads 102 is poor, the functional chip 200 where the test structure is located cannot transmit the electrical signal to the corresponding metal bumps 103 through the pins 201 of the corner 200a, the preselected connection pads 102, and the through-silicon via TSV1, and the metal bumps 103 cannot detect the preset electrical signal. If the connection between the pins 201 of the corner 200a of the functional chip 200 where the test structure is located and the preselected connection pads 102 is good, the functional chip 200 where the test structure is located transmits the electrical signal to the corresponding metal bumps 103 through the pins 201 of the corner 200a, the preselected connection pads 102, and the through-silicon via TSV1, and the metal bumps 103 can detect the preset electrical signal. The above technical solution can realize that in the chip packaging and testing stage of the wafer-level system, whether there is a preset electrical signal at the metal bumps 103 corresponding to the preselected connection pads 102 in the test area is used to detect whether the connection between the pins 201 of the corner 200a of the functional chip 200 where the test structure is located and the preselected connection pads 102 is good. If there is a preset electrical signal at the metal bumps 103 corresponding to the preselected connection pads 102 in the test area, the connection between the pins 201 of the corner 200a of the functional chip 200 where the test structure is located and the preselected connection pads 102 is good, and it is determined that the functional chip in the functional area will not warp after being packaged on the rear edge of the connection pad. Otherwise, it is determined that the functional chip in the functional area warps after being packaged on the rear edge of the connection pad.

[0077] In the reliability testing stage of the wafer-level system, the functional chip 200 where the test structure is located is on the side of the connection pad 102 away from the wafer 101. The pins 201 of the functional chip 200 where the test structure is located are in one-to-one contact with the preselected connection pads 102. The welding between the preselected connection pads 102 and the through-silicon via TSV1 is good. On the wafer-level testing machine table, the metal bumps 103 corresponding to the preselected connection pads 102 are in contact with the probes, and the electrical performance of the preselected test structure is used to detect the reliability of the life cycle of the wafer-level system integration and assembly. Optionally, as Figure 3 shown, the test structure includes an inverter circuit, and the attenuation of the frequency of the preselected test structure is used to detect the reliability of the life cycle of the wafer-level system integration and assembly. The actual test circuit can select a multi-tap structure, which can control the starting position of the inverter loop, so as to accurately locate in case of failure.

[0078] The basic principle of the technical solution provided by the embodiment of the present invention is to utilize the spare area in the functional area of the wafer 101 to establish a test area for testing the through-silicon via TSV1 path, and interconnect the through-silicon vias TSV1 using conductive connections 104. On the second surface of the wafer 101, during the process of completing chip-to-wafer (C2W) heterogeneous integration and fabricating metal bumps 103, the metal bumps 103 in the test area are simultaneously fabricated. At the wafer-level test station, the test of the through-silicon via path can be completed through probes. By collecting the test results of all through-silicon via paths in the test area, it is determined whether the welding between the connection pads 102 and the through-silicon vias TSV1 in the functional area is good, so as to complete the test of the through-silicon via path in the functional area. Among them, chip-to-wafer heterogeneous integration can achieve the interconnection between chips with different technology nodes and different sizes, and has the advantage of high flexibility. At the same time, C2W can greatly improve the yield by selecting known good die (kgd) to perform bonding with the wafer.

[0079] For the technical solution provided by the embodiment of the present invention, on the basis of ensuring the smooth electrical connection between the through-silicon via TSV1 and the metal bump 103, the wafer-level system determines whether the welding between the connection pads 102 and the through-silicon vias TSV1 in the functional area is good according to whether the welding between the connection pads 102 and the through-silicon vias TSV1 in the test area of the wafer-level transfer test circuit is good during the prebond stage, so as to complete the test of the through-silicon via path in the functional area; determines whether the connection between the pin 201 at the corner 200a of the functional chip 200 where the test structure is located in the test area and the preselected connection pad 102 is good, which is used to judge whether the edge of the functional chip in the functional area warps after being packaged on the connection pad; and during the reliability test stage of the wafer-level system, the electrical performance of the preselected test structure is used to detect the reliability of the life cycle of the wafer-level system integration and assembly. Therefore, the above technical solution realizes the testing of the wafer-level system during the prebond stage of the wafer-level system integration and assembly, the chip packaging test stage of the wafer-level system, and the reliability test stage of the wafer-level system, timely discovers production defects, monitors and warns of product failures, and provides necessary diagnostic information for the early isolation, repair or replacement of the wafer-level system.

[0080] Optionally, on the basis of the above technical solution, as Figure 4 , Figure 4 FIG. is a schematic structural diagram of a lithography process alignment test circuit according to an embodiment of the present invention. The test circuit of the wafer-level system integration and assembly further includes a lithography process alignment test circuit. The lithography process alignment test circuit is located in the test area and is used to determine whether the connection between the metal lines formed by two lithography processes on the surface of the wafer 101 and / or within the wafer 101 in the functional area is good.

[0081] As shown Figure 4 in the figure, the lithography process alignment test circuit includes: a first metal bump 103e, the first metal bump 103e is located on the surface of the wafer in the test area, and is arranged at intervals in the first direction (the Y direction in the figure); a second metal bump 103f, the second metal bump 103f is located on the surface of the wafer in the test area, and is arranged at intervals in the first direction (the Y direction in the figure), and in the second direction (the X direction in the figure), the second metal bump 103f and the first metal bump 103e are arranged at intervals in a one-to-one correspondence; a plurality of first metal lines 104a with different line widths are formed by the first lithography and etching processes, and the first metal lines 104a are connected to the first metal bumps 103e in a one-to-one correspondence; a plurality of second metal lines 104b with different line widths are formed by the second lithography and etching processes, wherein the second metal lines 104b are connected to the second metal bumps 103f in a one-to-one correspondence, and the second metal lines 104b are connected to the first metal lines 104a in a one-to-one correspondence, and the line widths of the mutually connected first metal lines 104a and second metal lines 104b are the same.

[0082] Whether the first metal bump 103e and the second metal bump 103f can be conducted is used to detect whether the connection between the connected first metal line 104a and the second metal line 104b is good in the second direction (the X direction in the figure). The line widths of the first metal line 104a and the second metal line 104b with good connections are used to determine the line width range that ensures good connection between the first metal line 104a and the second metal line 104b, and further determine the line width range in which the metal lines formed by the two lithography processes can be connected well. The line width range in which the metal lines formed by the two lithography processes can be connected well is used to determine whether the connection between the metal lines formed by the two lithography processes on the surface of the wafer in the functional area and / or within the wafer is good. At the same time, the line width range in which the metal lines formed by the two lithography processes can be connected well can also estimate the alignment error of the two lithography processes. Specifically, if the first metal bump 103e and the second metal bump 103f can be conducted, it proves that the connection between the connected first metal line 104a and the second metal line 104b is good in the second direction (the X direction in the figure), and the first metal line 104a and the second metal line 104b realized by the two lithographies can be aligned. Otherwise, in the second direction (the X direction in the figure), the first metal line 104a and the second metal line 104b realized by the two lithographies are not aligned and are disconnected.

[0083] Figure 4 Among them, the line widths of the first metal lines 104a include 1x width, 2x width... kx width. The line widths of the second metal lines 104b include 1x width, 2x width... kx width.

[0084] To achieve wafer-level system integration, it is usually necessary to fabricate wafer-level redistribution layers (RDLs) or wafer-level interposers. However, the actual photomasks cannot exceed the window of the actual lithography machine. Therefore, stitching technology is required to implement patterns larger than the photomask window. However, stitching alignment introduces errors and there is a possibility of failure (open circuit). For the stitching area, specific test patterns are also used and different line widths are designed. In the case of failure, the alignment error can be estimated.

[0085] Specifically, some key technologies in the wafer-level system integration process include wafer-level RDL, wafer-level interposer, photomask limitation, stitching technology, and the application of test patterns.

[0086] Wafer-level RDL and wafer-level interposer: These two technologies are both methods for achieving wafer-level system integration. Wafer-level RDL realizes the interconnection between chips by fabricating RDL (redistribution layer) on the wafer, while wafer-level interposer realizes the interconnection between chips by fabricating an interposer on the wafer and using the interposer to provide the interconnection.

[0087] Photomask limitation: In the actual lithography process, since the size of the photomask window exposed by the lithography machine is limited, it is impossible to completely cover the entire chip pattern with a single photomask. This requires stitching between multiple photomasks, and this stitching technology is called stitching technology.

[0088] Stitching technology: Stitching technology is a technology that stitches the patterns of multiple photomasks together. Since this stitching process may introduce alignment errors, there is a possibility of failure (such as open circuit).

[0089] Test patterns: To evaluate the effect and quality of stitching technology, specific test patterns are usually designed for the stitching area and different line widths are designed. In the case of failure, the alignment error between two lithography processes can be estimated by observing the failure of the test patterns.

[0090] All of the above technologies are for achieving wafer-level system integration, improving the performance and reliability of chips. At the same time, these technologies can also help us better understand and optimize the process flow of wafer-level system integration.

[0091] Optionally, on the basis of the above technical solutions, such as Figure 2 and Figure 5 , Figure 5FIG. 0 is a schematic structural diagram of a test circuit of another wafer-level system integration device provided according to an embodiment of the present invention. At each corner 200a of a functional chip 200 where the test structure is located, a plurality of preselected connection pads 102 and a plurality of metal bumps 103 are correspondingly arranged; in the chip package test stage of the wafer-level system, whether there is a preset electrical signal at the metal bumps 103 corresponding to the preselected connection pads 102 at the four corners 200a of the functional chip 200 where the test structure is located is used to detect whether the connection between the pins 201 of the functional chip 200 where the test structure is located and the preselected connection pads 102 is good. As Figure 2 shown, at each corner 200a of a functional chip 200 where the test structure is located, a plurality of preselected connection pads 102 and a plurality of metal bumps 103 are correspondingly arranged. Among them, the preselected connection pads 102 and the plurality of metal bumps 103 are arranged in an array.

[0092] Figure 2 and Figure 5 FIG. 8 shows the test circuit after C2W. Since the wafer-level integration area is very large, the warping problem needs to be particularly concerned about, and the four corners of the die are often the positions where the warping is the most serious. Therefore, Figure 2 FIG. 10 shows that the functional chip where the test structure is located is generally placed at the four corners of the die. Figure 2 FIG. 12 shows the test pattern, which is divided into two parts. One part is the through-silicon via TSV1 in the interposer (wafer 101). Metal bumps 103 are prepared on the second surface and interconnected on the printed circuit board to form a test loop path. Figure 3 FIG. 14 shows a test structure composed of an inverter ring. The actual test circuit can select a multi-tap structure, so that the starting position of the inverter ring can be controlled, so as to accurately locate in case of failure.

[0093] Optionally, on the basis of the above technical solution, as Figure 6 shown, Figure 6 FIG. 21 is a schematic structural diagram of a test circuit of another wafer-level system integration device provided according to an embodiment of the present invention. The test area is multiplexed as a functional area. A fuse 105 is arranged between two metal bumps on the second surface of the wafer 101. After the fuse 105 is blown, the two metal bumps are disconnected to make the test area multiplexed as a functional area. A fuse 105 is arranged between the metal bump 103a and the metal bump 103b, and a fuse 105 is arranged between the metal bump 103c and the metal bump 103d.

[0094] In the preprocessing stage of the wafer-level system, after detecting whether the welding of the test internal connection pads and the through-silicon vias is good by the conduction condition of the two metal bumps in the test area of the wafer-level transfer test circuit, as Figure 6As shown, after the fuse 105 is blown, the two metal bumps are disconnected, so that the test area can be reused as a functional area. After the fuse 105 disposed between the metal bump 103a and the metal bump 103b is blown, the connection between the metal bump 103a and the metal bump 103b is disconnected. After the fuse 105 disposed between the metal bump 103c and the metal bump 103d is blown, the connection between the metal bump 103c and the metal bump 103d is disconnected, so that the test area can be reused as a functional area, reducing the influence of the test area on the functional area.

[0095] The embodiment of the present invention also provides a test method for wafer-level system integration and assembly. Figure 7 It is a schematic flowchart of a test method for wafer-level system integration and assembly according to an embodiment of the present invention.

[0096] As Figure 7 shown, the test method for wafer-level system integration and assembly includes:

[0097] S110. In the preprocessing stage of the wafer-level system, the conduction condition of the two metal bumps in the test area of the wafer-level transfer test circuit is detected to check whether the welding of the connection pad and the through-silicon via in the test area is good.

[0098] Among them, as Figure 1 shown, the wafer-level transfer test circuit 100 includes a wafer 101, connection pads 102, and metal bumps 103. The wafer 101 includes a test area and a functional area. A through-silicon via TSV1 is disposed in the wafer 101. The connection pad 102 is located on the first surface of the wafer 101 and is connected to the through-silicon via TSV1. The metal bump 103 is located on the second surface of the wafer 101 opposite to the first surface, and the metal bump 103 is connected to the through-silicon via TSV1. The conductive connection line 104 in the test area is located on the side of the connection pad 102 away from the wafer 101 and is used to connect the two connection pads 102.

[0099] It should be noted that Figure 1 what is shown is the wafer 101 in the test area, and there is no conductive connection line 104 on the surface of the connection pad 102 on the first surface of the wafer 101 in the functional area. And in this embodiment, in the wafer-level transfer test circuit 100, the electrical connection between the through-silicon via TSV1 and the metal bump 103 is unobstructed. The welding process of the connection pad 102 in the test area and the wafer 101 is the same as that of the connection pad 102 in the functional area and the wafer 101.

[0100] On the basis of ensuring smooth electrical connection between the through-silicon via TSV1 and the metal bump 103, in the preprocessing stage of the wafer-level system, in the wafer-level transfer test circuit 100, the conductive connection line 104 connects the two connection pads 102. The two connection pads 102 are connected to the corresponding metal bumps 103 through the through-silicon via TSV1. On the wafer-level test machine platform, the metal bumps 103 are in contact with the probes, forming a loop composed of the conductive connection line 104, the connection pads 102, the through-silicon via TSV1, the metal bumps 103, and the probes. If the welding quality between the connection pad 102 and the through-silicon via TSV1 in the test area is poor, resulting in the inability to transmit electrical signals between the connection pad 102 and the through-silicon via TSV1 in the test area, then electrical signals cannot be transmitted between the two metal bumps 103 in the test area of the wafer-level transfer test circuit, and it can be determined that the welding quality between the connection pad 102 and the through-silicon via TSV1 in the test area is poor. If the welding between the connection pad 102 and the through-silicon via TSV1 in the test area is good, then electrical signals can be transmitted between the two metal bumps 103 in the test area of the wafer-level transfer test circuit, and it can be determined that the welding between the connection pad 102 and the through-silicon via TSV1 in the test area is good. The above technical solution can realize the conduction condition of the two metal bumps 103 in the test area of the wafer-level transfer test circuit in the preprocessing stage of the wafer-level system, for the effect of detecting whether the welding between the connection pad 102 and the through-silicon via TSV1 in the test area is good.

[0101] S120. According to whether the welding between the connection pad and the through-silicon via in the test area of the wafer-level transfer test circuit is good, determine whether the welding between the connection pad and the through-silicon via in the functional area is good, so as to complete the test of the through-silicon via path in the functional area.

[0102] In this embodiment, no conductive connection line 104 is provided on the surface of the connection pad 102 on the first surface of the wafer 101 in the functional area. Except for this, the structure of the functional area and the structure and process of the result test area are exactly the same. Therefore, Figure 1 in, whether the welding between the connection pad 102 and the through-silicon via TSV1 in the test area is good is used for whether the welding between the connection pad 102 and the through-silicon via TSV1 in the functional area is good, so as to complete the test of the through-silicon via path in the functional area.

[0103] S130. In the chip packaging test stage of the wafer-level system, by testing whether there is a preset electrical signal at the metal bump corresponding to the preselected connection pad in the test area, detect whether the connection between the pin at the corner of the functional chip where the test structure is located and the preselected connection pad is good. Among them, the welding between the preselected connection pad and the through-silicon via is good, the test structure is a test circuit built inside the functional chip, the functional chip where the test structure is located is on the side of the connection pad away from the wafer, and the pins at the corners of the functional chip where the test structure is located are in one-to-one contact with the preselected connection pads.

[0104] If the connection quality between the pin 201 of the corner 200a of the functional chip 200 where the test structure is located and the preselected connection pad 102 is poor, the functional chip 200 where the test structure is located cannot transmit the electrical signal to the corresponding metal bump 103 through the pin 201 of the corner 200a, the preselected connection pad 102, and the through-silicon via TSV1, and the metal bump 103 cannot detect the preset electrical signal. If the connection between the pin 201 of the corner 200a of the functional chip 200 where the test structure is located and the preselected connection pad 102 is good, the functional chip 200 where the test structure is located transmits the electrical signal to the corresponding metal bump 103 through the pin 201 of the corner 200a, the preselected connection pad 102, and the through-silicon via TSV1, and the metal bump 103 can detect the preset electrical signal. The above technical solution can realize whether there is a preset electrical signal at the metal bump 103 corresponding to the preselected connection pad 102 in the test area during the chip package test stage of the wafer-level system, and is used to detect whether the connection between the pin 201 of the corner 200a of the functional chip 200 where the test structure is located and the preselected connection pad 102 is good.

[0105] S140. According to whether the connection between the pin of the corner of the functional chip where the test structure is located in the test area and the preselected connection pad is good, determine whether the edge of the functional chip in the functional area warps after being packaged on the connection pad.

[0106] There is a preset electrical signal at the metal bump 103 corresponding to the preselected connection pad 102 in the test area, and the connection between the pin 201 of the corner 200a of the functional chip 200 where the test structure is located and the preselected connection pad 102 is good. It is determined that the edge of the functional chip in the functional area will not warp after being packaged on the connection pad. Otherwise, it is determined that the edge of the functional chip in the functional area warps after being packaged on the connection pad.

[0107] S150. During the reliability test stage of the wafer-level system, detect the reliability of the life cycle of the wafer-level system integrated assembly through the electrical performance of the preselected test structure, where the connection between the pin of the functional chip where the preselected test structure is located and the preselected connection pad is good.

[0108] Optionally, on the basis of the above technical solution, during the reliability test stage of the wafer-level system in S150, detecting the reliability of the life cycle of the wafer-level system integrated assembly through the electrical performance of the preselected test structure includes:

[0109] During the reliability test stage of the wafer-level system, detect the reliability of the life cycle of the wafer-level system integrated assembly through the attenuation of the frequency of the preselected test structure, where the test structure includes an inverter circuit.

[0110] During the reliability test phase of the wafer-level system, the functional chip 200 where the test structure is located is on the side of the connection pad 102 away from the wafer 101. The pins 201 of the functional chip 200 where the test structure is located are in one-to-one contact with the preselected connection pads 102. The welding between the preselected connection pads 102 and the through-silicon via TSV1 is good. On the wafer-level test machine platform, the metal bumps 103 connected to the preselected connection pads 102 are in contact with the probes, and the electrical performance of the preselected test structure is used to detect the reliability of the life cycle of the wafer-level system integration and assembly. Optionally, as Figure 3 shown, the test structure includes an inverter circuit, and the attenuation of the frequency of the preselected test structure is used to detect the reliability of the life cycle of the wafer-level system integration and assembly. The actual test circuit can select a multi-tap structure, which can control the starting position of the inverter loop, so as to accurately locate in case of failure.

[0111] Based on the technical solution provided by the embodiment of the present invention, on the premise of ensuring smooth electrical connection between the through-silicon via TSV1 and the metal bump 103 on the wafer, during the prebond stage of the wafer-level system, according to whether the welding between the connection pad 102 and the through-silicon via TSV1 in the test area of the wafer-level transfer test circuit is good, it is judged whether the welding between the connection pad 102 and the through-silicon via TSV1 in the functional area is good, so as to complete the test of the through-silicon via path in the functional area; whether the connection between the pin 201 of the functional chip 200 where the test structure is located and the preselected connection pad 102 in the test area is good is used to judge whether the edge of the functional chip package in the functional area warps after being packaged on the connection pad; during the reliability test phase of the wafer-level system, the electrical performance of the preselected test structure is used to detect the reliability of the life cycle of the wafer-level system integration and assembly. Therefore, the above technical solution realizes the testing of the wafer-level system during the prebond stage (prebond) of the wafer-level system integration and assembly, the chip package test stage (C2W FT test) of the wafer-level system, and the reliability test stage (Reliability Monitoring) of the wafer-level system, discovers production defects in time, monitors and warns of product failures, and provides necessary diagnostic information for the early isolation, repair or replacement of the wafer-level system.

[0112] As Figure 8 shown, Figure 8 is a schematic flow chart of another test method for wafer-level system integration and assembly provided according to the embodiment of the present invention. Before S130, during the chip package test stage of the wafer-level system, by testing whether there is a preset electrical signal at the metal bump connected to the preselected connection pad in the test area, it is detected whether the connection between the pin at the corner of the functional chip where the test structure is located and the preselected connection pad is good.

[0113] S1301. Align the test circuit through the lithography process to determine whether the connection between the wafer surface in the functional area and / or the metal wires formed by two lithography processes within the wafer is good. The lithography process alignment test circuit is located in the test area.

[0114] As Figure 4 shown, the lithography process alignment test circuit includes: a first metal bump 103e, which is located on the surface of the wafer in the test area and is arranged at intervals in the first direction (the Y direction in the figure); a second metal bump 103f, which is located on the surface of the wafer in the test area and is arranged at intervals in the first direction (the Y direction in the figure), and in the second direction (the X direction in the figure), the second metal bump 103f and the first metal bump 103e are arranged at intervals in a one-to-one correspondence; a plurality of first metal wires 104a with different line widths, which are formed by the first lithography and etching processes, and the first metal wires 104a are connected to the first metal bumps 103e in a one-to-one correspondence; a plurality of second metal wires 104b with different line widths, which are formed by the second lithography and etching processes. Among them, the second metal wires 104b are connected to the second metal bumps 103f in a one-to-one correspondence, and the second metal wires 104b are connected to the first metal wires 104a in a one-to-one correspondence. The line widths of the mutually connected first metal wires 104a and second metal wires 104b are the same.

[0115] Whether the first metal bump 103e and the second metal bump 103f can conduct is used to detect whether the connection between the connected first metal wire 104a and the second metal wire 104b in the second direction (the X direction in the figure) is good. The line widths of the first metal wire 104a and the second metal wire 104b with good connections are used to determine the line width range that ensures good connection between the first metal wire 104a and the second metal wire 104b, and further determine the line width range in which the metal wires formed by two lithography processes can be connected well. The line width range in which the metal wires formed by two lithography processes can be connected well is used to determine whether the connection between the wafer surface in the functional area and / or the metal wires formed by two lithography processes within the wafer is good. At the same time, the line width range in which the metal wires formed by two lithography processes can be connected well can also estimate the alignment error of the two lithography processes. Specifically, if the first metal bump 103e and the second metal bump 103f can conduct, it proves that the connection between the connected first metal wire 104a and the second metal wire 104b in the second direction (the X direction in the figure) is good, and the first metal wire 104a and the second metal wire 104b realized by the two lithographies can be aligned. Otherwise, in the second direction (the X direction in the figure), the first metal wire 104a and the second metal wire 104b realized by the two lithographies are not aligned and are disconnected.

[0116] Figure 4Among them, the line widths of the first metal lines 104a include 1x width, 2x width... kx width. The line widths of the second metal lines 104b include 1x width, 2x width... kx width.

[0117] To achieve wafer-level system integration, it is usually necessary to fabricate a wafer-level redistribution layer (RDL) or a wafer-level Interposer. However, the actual photomask cannot exceed the window of the actual lithography machine. Therefore, the stitching technology is required to implement patterns larger than the photomask window. However, stitching alignment will introduce errors, and there is a possibility of failure (open circuit). For the stitching area, specific test patterns are also used, and different line widths are designed. In the case of failure, the alignment error can be estimated.

[0118] In the chip package test stage of the S130 wafer-level system, by testing whether there is a preset electrical signal at the metal bumps corresponding to the preselected connection pads in the test area, it is detected whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads is good, including:

[0119] S1302. In the chip package test stage of the wafer-level system, by testing whether there is a preset electrical signal at the metal bumps corresponding to the preselected connection pads in the preset test area, it is detected whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads is good, where the preset test area is an area with good connection of the metal lines formed by two lithography processes on the wafer surface and / or inside the wafer in the test area.

[0120] In the chip packaging and testing stage of the wafer-level system, on the basis that the connection of the metal wires formed by two lithography processes on the surface of the wafer 101 in the functional area and / or within the wafer 101 is good, if the connection quality between the pin 201 of the corner 200a of the functional chip 200 where the test structure is located and the preselected connection pad 102 is poor, the functional chip 200 where the test structure is located cannot transmit the electrical signal to the corresponding metal bump 103 through the pin 201 of the corner 200a, the preselected connection pad 102, and the through-silicon via TSV1, and the metal bump 103 cannot detect the preset electrical signal. If the connection between the pin 201 of the corner 200a of the functional chip 200 where the test structure is located and the preselected connection pad 102 is good, the functional chip 200 where the test structure is located transmits the electrical signal to the corresponding metal bump 103 through the pin 201 of the corner 200a, the preselected connection pad 102, and the through-silicon via TSV1, and the metal bump 103 can detect the preset electrical signal. The above technical solution can realize whether there is a preset electrical signal at the metal bump 103 corresponding to the preselected connection pad 102 in the preset test area during the chip packaging and testing stage of the wafer-level system, so as to detect whether the connection between the pin 201 of the corner 200a of the functional chip 200 where the test structure is located and the preselected connection pad 102 is good.

[0121] As Figure 9 shown, Figure 9 is Figure 8 a schematic flowchart of the test method included in S1301. S1301 aligns the test circuit through the lithography process. Determining whether the connection of the metal wires formed by two lithography processes on the surface of the wafer in the functional area and / or within the wafer is good includes:

[0122] S1301a. Form a plurality of first metal bumps arranged at intervals in the first direction on the surface of the wafer in the test area.

[0123] As Figure 4 shown, a plurality of first metal bumps 103e arranged at intervals in the first direction (the Y direction in the figure) are formed on the surface of the wafer 101 in the test area.

[0124] S1301b. Form a plurality of second metal bumps arranged at intervals in the first direction on the surface of the wafer in the test area. In the second direction, the second metal bumps and the first metal bumps are arranged at intervals in a one-to-one correspondence.

[0125] As Figure 4 shown, a plurality of second metal bumps 103f arranged at intervals in the first direction (the Y direction in the figure) are formed on the surface of the wafer in the test area. In the second direction (the X direction in the figure), the second metal bumps 103f and the first metal bumps 103e are arranged at intervals in a one-to-one correspondence.

[0126] S1301c. Form a plurality of first metal lines with different line widths through the first photolithography and etching processes, and connect the first metal lines to the first metal bumps in a one-to-one correspondence.

[0127] As Figure 4 shown, form a plurality of first metal lines 104a with different line widths through the first photolithography and etching processes, and connect the first metal lines 104a to the first metal bumps 103e in a one-to-one correspondence.

[0128] S1301d. Form a plurality of second metal lines with different line widths through the second photolithography and etching processes, wherein the second metal lines are connected to the second metal bumps in a one-to-one correspondence, and the second metal lines are connected to the first metal lines in a one-to-one correspondence, and the line widths of the mutually connected first metal lines and second metal lines are the same.

[0129] As Figure 4 shown, form a plurality of second metal lines 104b with different line widths through the second photolithography and etching processes, wherein the second metal lines 104b are connected to the second metal bumps 103f in a one-to-one correspondence, and the second metal lines 104b are connected to the first metal lines 104a in a one-to-one correspondence, and the line widths of the mutually connected first metal lines 104a and second metal lines 104 are the same.

[0130] S1301e. Detect whether the connection between the connected first metal line and the second metal line is good in the second direction by detecting whether the first metal bump and the second metal bump can conduct.

[0131] Whether the first metal bump 103e and the second metal bump 103f can conduct is used to detect whether the connection between the connected first metal line 104a and the second metal line 104b is good in the second direction (the X direction in the figure).

[0132] S1301f. Determine the line width range that ensures good connection between the first metal line and the second metal line according to the line widths of the first metal line and the second metal line with good connection, so as to determine the line width range in which the metal lines formed by the two photolithography processes can be connected well.

[0133] The line widths of the first metal line 104a and the second metal line 104b with good connection are used to determine the line width range that ensures good connection between the first metal line 104a and the second metal line 104b, and further determine the line width range in which the metal lines formed by the two photolithography processes can be connected well.

[0134] S1301g. Determine whether the connection between the metal lines formed by the two photolithography processes on the wafer surface and / or in the wafer in the functional area is good according to the line width range in which the metal lines formed by the two photolithography processes can be connected well.

[0135] The wire width range in which the metal wires formed by two lithography processes can be well connected is used to determine whether the connection between the wafer surface in the functional area and / or the metal wires formed by two lithography processes within the wafer is good. At the same time, the wire width range in which the metal wires formed by two lithography processes can be well connected can also estimate the alignment error between the two lithography processes. Specifically, the first metal bump 103e and the second metal bump 103f can be electrically connected, proving that the connection between the connected first metal wire 104a and the second metal wire 104b in the second direction (the X direction in the figure) is good, and the first metal wire 104a and the second metal wire 104b realized by two lithography processes can be aligned. Otherwise, in the second direction (the X direction in the figure), the first metal wire 104a and the second metal wire 104b realized by two lithography processes are not aligned and are disconnected.

[0136] Figure 4 Among them, the wire width of the first metal wire 104a includes 1x width, 2x width... kx width. The wire width of the second metal wire 104b includes 1x width, 2x width... kx width.

[0137] To achieve wafer-level system integration, it is usually necessary to fabricate a wafer-level redistribution layer (RDL) or a wafer-level Interposer, but the actual photomask cannot exceed the window of the actual lithography machine. Therefore, the stitching technology is needed to implement a pattern larger than the photomask window. However, stitching alignment will introduce errors and there is a possibility of failure (open circuit). For the stitching area, a specific test pattern is also adopted, and different wire widths are designed. In the case of failure, the alignment error can be estimated.

[0138] Optionally, based on the above technical solution, in the chip package test stage of the S130 wafer-level system, by testing whether there is a preset electrical signal at the metal bump corresponding to the preselected connection pad in the test area, detecting whether the connection between the pin at the corner of the functional chip where the test structure is located and the preselected connection pad is good includes:

[0139] In the chip package test stage of the wafer-level system, by testing whether there is a preset electrical signal at the metal bump corresponding to the preselected connection pad at the four corners of the functional chip where the test structure is located, detecting whether the connection between the pin of the functional chip where the test structure is located and the preselected connection pad is good, where multiple preselected connection pads and multiple metal bumps are correspondingly arranged at each corner of the functional chip where the test structure is located.

[0140] Such as Figure 2 and Figure 5, at each corner 200a of the functional chip 200 where the test structure is located, a plurality of preselected connection pads 102 and a plurality of metal bumps 103 are correspondingly arranged; during the chip package test stage of the wafer-level system, whether there is a preset electrical signal at the metal bumps 103 correspondingly connected to the preselected connection pads 102 at the four corners 200a of the functional chip 200 where the test structure is located is used to detect whether the connection between the pins 201 of the functional chip 200 where the test structure is located and the preselected connection pads 102 is good. As Figure 2 As shown, at each corner 200a of the functional chip 200 where the test structure is located, a plurality of preselected connection pads 102 and a plurality of metal bumps 103 are correspondingly arranged. Among them, the preselected connection pads 102 and the plurality of metal bumps 103 are arranged in an array.

[0141] Figure 2 and Figure 5 represent the test circuit after C2W. Since the wafer-level integration area is very large, the warping problem needs to be particularly concerned about, and the four corners of the die are often the positions where the warping is the most serious. Therefore, Figure 2 shows that the test circuit is generally placed at the four corners of the die. Figure 2 shows the test pattern, which is divided into two parts. One part is the through-silicon via TSV1 in the interposer (wafer 101). Metal bumps 103 are prepared on the second surface and interconnected on the printed circuit board to form a test loop path. The actual test circuit can select a multi-tap structure, so that the starting position of the inverter loop can be controlled, and thus, in case of failure, accurate positioning can be carried out.

[0142] Optionally, on the basis of the above technical solution, the test area is reused as a functional area. After the wafer-level system S110 detects whether the welding between the test internal connection pads and the through-silicon vias is good by detecting the conduction condition of the two metal bumps in the test area of the wafer-level transfer test circuit during the preprocessing stage, it further includes:

[0143] Fusing the fuse between the two metal bumps. Among them, on the second surface of the wafer, a fuse is arranged between the two metal bumps. After the fuse is fused, the two metal bumps are disconnected.

[0144] As Figure 5 shown, the test area is reused as a functional area. A fuse is arranged between the two metal bumps on the second surface of the wafer 101. After the fuse is fused, the two metal bumps are disconnected to enable the test area to be reused as a functional area. A fuse 105 is arranged between the metal bump 103a and the metal bump 103b, and a fuse 105 is arranged between the metal bump 103c and the metal bump 103d.

[0145] In the preprocessing stage of the wafer-level system, after detecting whether the welding of the test internal connection pads and the through-silicon vias is good by checking the conduction of the two metal bumps in the test area of the wafer-level transfer test circuit, as Figure 6 shown, after the fuse 105 is blown, the two metal bumps are disconnected, so that the test area can be reused as a functional area. After the fuse 105 arranged between the metal bump 103a and the metal bump 103b is blown, the connection between the metal bump 103a and the metal bump 103b is disconnected. After the fuse 105 arranged between the metal bump 103c and the metal bump 103d is blown, the connection between the metal bump 103c and the metal bump 103d is disconnected, so that the test area can be reused as a functional area, reducing the influence of the test area on the functional area. In the current industrial community, wafer-level systems have not been widely commercialized, and no systematic test methods have been formed. The present invention proposes a test method for wafer-level system integration and assembly, and designs a test circuit to support this method. The test method can cover production testing, reliability testing, and failure monitoring requirements during the life cycle.

[0146] Wafer-level integration is widely regarded as the development trend of system integration technology. Figure 10 It is a comparison chart of the size parameters of two interconnection technologies, QSFP optical module and UCIe.

[0147] Figure 10 It clearly shows the interface density of different system integrations. Here, the QSFP28 optical module and the interface interconnection based on serial transceivers are used as examples to illustrate the advantages of wafer-level integration.

[0148] The QSFP28 optical module is a high-density optical communication module. The size of the QSFP28 optical module is shown in Figure 10 , and it uses four 25Gbps channels for parallel transmission to achieve an Ethernet transmission rate of 100Gbps. However, the size of this module is relatively large, which may limit its use in some applications.

[0149] The QSFP28 optical module and the interface interconnection based on serial transceivers can increase the interface (line) density by more than 8 times. This interconnection technology realizes the interface inside the wafer system by using a silicon dielectric layer or a redistribution layer, thus achieving high-density interconnection. While improving the interface density, this technology can also reduce signal noise and improve signal quality.

[0150] Furthermore, taking UCIe-A as an example, the interface density can be increased by another 4 times. UCIe-A is a general high-speed interface for inter-chip communication. It is based on serial transceivers and uses a silicon interposer to achieve high-density interface interconnection. By using this technology, the interface density can be further increased to meet the growing data transmission requirements.

[0151] Generally speaking, wafer-level integration can achieve high-density and high-speed inter-chip communication by implementing interface interconnections within the wafer system, thus meeting the requirements of modern electronic devices for high performance, high reliability, and low power consumption. This technology represents an important development trend in system integration technology.

[0152] As Figure 11 shown, Figure 11 is a schematic diagram of a wafer-level system. Each module with a black border represents a computing die, and the square between the black borders represents the high-speed interconnection between the dies. The bandwidth between the dies is particularly important for realizing the cluster training / inference of AI large models. The wafer-level system has significant architectural advantages in this field.

[0153] As Figure 12 shown, Figure 12 is a schematic flowchart of wafer-level system integration provided according to an embodiment of the present invention. The left side shows the process of typical wafer-level integration, including a computing chip and an interposer (wafer). After CP / FT testing and prebond testing respectively, the next step is chip to wafer integration (C2W). Due to the large area and high density of wafer-level integration, there are failure problems in this step, and FT (final test) needs to be done well before the next step of system integration. After completing system integration, system-level testing (SLT) is carried out and then deployed. During the deployment of the wafer-level system, special attention should be paid to the reliability of the through-silicon via TSV1 and the metal bumping. And the specific test circuit designed in the test stage can be used as a reliability monitor during the life cycle to monitor and warn of system failures.

[0154] The prebond test, C2W test, and Reliability Monitoring in the right block diagram are included in the test circuit and test method of the present invention. Among them, the test in the preprocessing stage of assembling the wafer-level system corresponds to the prebond test in the figure, the chip packaging test stage of the wafer-level system corresponds to the C2W FT test in the figure, and the reliability test stage of the wafer-level system corresponds to the Reliability Monitoring in the figure.

[0155] It should be understood that various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. There is no limitation herein.

[0156] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A test circuit for wafer-level system integration assembly, characterized in that Comprising: A wafer-level interconnection test circuit, which includes a wafer, connection pads, and metal bumps. The wafer includes a test area and a functional area. Through-silicon vias are provided in the wafer. The connection pads are located on the first surface of the wafer and are connected to the through-silicon vias. The metal bumps are located on the second surface of the wafer opposite to the first surface, and the metal bumps are connected to the through-silicon vias. Conductive traces in the test area are located on the side of the connection pads away from the wafer and are used to connect two connection pads; In the preprocessing stage of the wafer-level system, the conduction condition of two metal bumps in the test area of the wafer-level interconnection test circuit is used to detect whether the welding between the connection pads and the through-silicon vias in the test area is good; whether the welding between the connection pads and the through-silicon vias in the test area is good is used to judge whether the welding between the connection pads and the through-silicon vias in the functional area is good, so as to complete the test of the through-silicon via path in the functional area; A test structure, which is a test circuit built inside a functional chip. The functional chip where the test structure is located is on the side of the connection pads away from the wafer. The pins of the functional chip where the test structure is located are in one-to-one contact with preselected connection pads, and the welding between the preselected connection pads and the through-silicon vias is good; In the chip packaging test stage of the wafer-level system, whether there is a preset electrical signal at the metal bumps corresponding to the preselected connection pads in the test area is used to detect whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads is good; whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads in the test area is good is used to judge whether the edge of the functional chip after being packaged on the connection pads in the functional area is warped; In the reliability test stage of the wafer-level system, the electrical performance of the preselected test structure is used to detect the reliability of the life cycle of the wafer-level system integration and assembly, wherein the connection between the pins of the functional chip where the preselected test structure is located and the preselected connection pads is good; It further includes a lithography process alignment test circuit, which is located in the test area and is used to determine whether the connection between the metal lines formed by two lithography processes on the wafer surface and / or inside the wafer in the functional area is good; The lithography process alignment test circuit includes: First metal bumps, which are located on the surface of the wafer in the test area and are arranged at intervals in the first direction; Second metal bumps, which are located on the surface of the wafer in the test area and are arranged at intervals in the first direction. In the second direction, the second metal bumps and the first metal bumps are arranged at intervals in one-to-one correspondence; Multiple first metal lines with different line widths are formed through the first lithography and etching processes, and the first metal lines are connected to the first metal bumps in one-to-one correspondence; A plurality of second metal lines with different line widths are formed through a second photolithography and etching process. Among them, the second metal lines are connected to the second metal bumps one by one, and the second metal lines are connected to the first metal lines one by one. The line widths of the mutually connected first metal lines and second metal lines are the same; Whether the first metal bumps and the second metal bumps can conduct is used to detect whether the connection between the connected first metal lines and second metal lines is good in the second direction; The line widths of the well-connected first metal lines and second metal lines are used to determine the line width range that ensures good connection between the first metal lines and the second metal lines, and further used to determine the line width range in which the metal lines formed by two photolithography processes can be well connected; The line width range in which the metal lines formed by two photolithography processes can be well connected is used to determine whether the connection between the metal lines formed by two photolithography processes on the wafer surface and / or within the wafer in the functional area is good.

2. The test circuit for wafer-level system integration assembly according to claim 1, wherein The test structure includes an inverter circuit. The attenuation of the frequency of the preselected test structure is used to detect the reliability of the life cycle of the wafer-level system integration and assembly.

3. The test circuit for wafer-level system integration assembly according to claim 1, wherein A plurality of preselected connection pads and a plurality of metal bumps are correspondingly arranged at each corner of the functional chip where the test structure is located; During the chip packaging and testing stage of the wafer-level system, whether there is a preset electrical signal at the metal bumps corresponding to the preselected connection pads at the four corners of the functional chip where the test structure is located in the test area is used to detect whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads is good.

4. The test circuit for wafer-level system integration assembly according to claim 1, wherein, The test area is reused as the functional area. A fuse is arranged between the two metal bumps on the second surface of the wafer. After the fuse is blown, the two metal bumps are disconnected.

5. A test method for wafer-level system integration assembly, characterized in that, Including: During the preprocessing stage of the wafer-level system, the conduction of the two metal bumps in the test area of the wafer-level transfer test circuit is used to detect whether the connection between the connection pads and the through-silicon vias in the test area is good; Among them, the wafer-level transfer test circuit includes a wafer, the connection pads, and the metal bumps. The wafer includes a test area and a functional area. Through-silicon vias are arranged in the wafer. The connection pads are located on the first surface of the wafer and are connected to the through-silicon vias. The metal bumps are located on the second surface of the wafer opposite to the first surface. The metal bumps are connected to the through-silicon vias. The conductive connection lines in the test area are located on the side of the connection pads away from the wafer and are used to connect two connection pads; According to whether the connection between the connection pads and the through-silicon vias in the test area of the wafer-level transfer test circuit is good, it is judged whether the connection between the connection pads and the through-silicon vias in the functional area is good, so as to complete the test of the through-silicon via path in the functional area. During the chip packaging and testing phase of the wafer-level system, by testing whether there is a preset electrical signal at the metal bumps corresponding to the preselected connection pads in the test area, it is detected whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads is good. Among them, the welding between the preselected connection pads and the through-silicon vias is good. The test structure is a test circuit built inside the functional chip. The functional chip where the test structure is located is on the side of the connection pads away from the wafer. The pins at the corners of the functional chip where the test structure is located are in one-to-one contact with the preselected connection pads; According to whether the connection between the pins at the corners of the functional chip where the test structure is located in the test area and the preselected connection pads is good, it is judged whether warping occurs at the rear edge of the functional chip encapsulated in the connection pads in the functional area; During the reliability testing phase of the wafer-level system, through the electrical performance of the preselected test structure, the reliability of the life cycle of the wafer-level system integration and assembly is detected. Among them, the connection between the pins of the functional chip where the preselected test structure is located and the preselected connection pads is good; Before the wafer-level system detects whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads is good by testing whether there is a preset electrical signal at the metal bumps corresponding to the preselected connection pads in the test area during the chip packaging and testing phase, it also includes: Aligning the test circuit through a lithography process to determine whether the connection between the metal lines formed by two lithography processes on the wafer surface and / or inside the wafer in the functional area is good. Among them, the lithography process for aligning the test circuit is located in the test area; When the wafer-level system detects whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads is good by testing whether there is a preset electrical signal at the metal bumps corresponding to the preselected connection pads in the test area during the chip packaging and testing phase, it includes: During the chip packaging and testing phase of the wafer-level system, by testing whether there is a preset electrical signal at the metal bumps corresponding to the preselected connection pads in the preset test area, it is detected whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pads is good. Among them, the preset test area is the area where the connection between the metal lines formed by two lithography processes on the wafer surface and / or inside the wafer in the test area is good; Aligning the test circuit through a lithography process to determine whether the connection between the metal lines formed by two lithography processes on the wafer surface and / or inside the wafer includes: Forming a plurality of first metal bumps arranged at intervals in the first direction on the surface of the wafer in the test area; Forming a plurality of second metal bumps arranged at intervals in the first direction on the surface of the wafer in the test area. In the second direction, the second metal bumps and the first metal bumps are arranged at intervals in one-to-one correspondence; Forming a plurality of first metal lines with different line widths through the first lithography and etching processes. The first metal lines are connected to the first metal bumps in one-to-one correspondence; Multiple second metal lines with different line widths are formed through a second lithography and etching process. Among them, the second metal lines are connected to the second metal bumps in a one-to-one correspondence, and the second metal lines are connected to the first metal lines in a one-to-one correspondence. The line widths of the connected first metal lines and second metal lines are the same; By detecting whether the first metal bumps and the second metal bumps can conduct, it is detected whether the connection between the connected first metal lines and second metal lines in the second direction is good; According to the line widths of the first metal lines and the second metal lines with good connections, the line width range that ensures good connection between the first metal lines and the second metal lines is determined, so as to determine the line width range in which the metal lines formed by the two lithography processes can be connected well; According to the line width range in which the metal lines formed by the two lithography processes can be connected well, it is determined whether the connection between the metal lines formed by the two lithography processes on the wafer surface and / or within the wafer in the functional area is good.

6. The test method for wafer-level system integration and assembly according to claim 5, characterized in that During the reliability test stage of the wafer-level system, the reliability of the life cycle of the wafer-level system integration and assembly is detected through the electrical performance of a preselected test structure, including: During the reliability test stage of the wafer-level system, the reliability of the life cycle of the wafer-level system integration and assembly is detected through the attenuation of the frequency of a preselected test structure, where the test structure includes an inverter circuit.

7. The test method for wafer-level system integration assembly according to claim 5, characterized in that, During the chip packaging test stage of the wafer-level system, by testing whether there is a preset electrical signal at the metal bump corresponding to the preselected connection pad in the test area, it is detected whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pad is good, including: During the chip packaging test stage of the wafer-level system, by testing whether there is a preset electrical signal at the metal bump corresponding to the preselected connection pad at the four corners of the functional chip where the test structure is located in the test area, it is detected whether the connection between the pins at the corners of the functional chip where the test structure is located and the preselected connection pad is good, where multiple preselected connection pads and multiple metal bumps are correspondingly arranged at each corner of the functional chip where the test structure is located.

8. The test method for wafer-level system integration assembly according to claim 5, characterized in that The test area is reused as the functional area. After detecting whether the welding between the connection pad and the through-silicon via in the test area is good by the conduction of the two metal bumps in the test area of the wafer-level transfer test circuit during the pretreatment stage of the wafer-level system, it further includes: Fusing the fuse between the two metal bumps. A fuse is arranged between the two metal bumps on the second surface of the wafer. After the fuse is fused, the two metal bumps are disconnected.

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