Dielectric isolated two-stage gate metal oxide thin film transistor structure and method of manufacturing the same

Abstract

The application relates to a dielectric isolation two-segment gate metal oxide thin film transistor structure and a manufacturing method thereof. The dielectric isolation two-segment gate metal oxide thin film transistor structure comprises a substrate, a gate layer, a gate dielectric layer and a channel layer which are sequentially stacked from bottom to top above the substrate, and source and drain layers which are respectively arranged on the left and right sides of the upper surface of the channel layer; wherein the gate layer comprises a first metal gate segment, an isolation dielectric segment and a second metal gate segment which are sequentially spliced in the horizontal direction, and the work function of the second metal gate segment is lower than that of the first metal gate segment. The application greatly reduces the leakage problem of the IGZO TFT device.

Description

Technical Field

[0001] This invention relates to the field of transistors, and in particular to an asymmetric dielectric-isolated two-section gate metal-oxide thin-film transistor structure and its manufacturing method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) plays a crucial role in the development of cloud computing, edge computing, the Internet of Things (IoT), and artificial intelligence. In recent years, DRAM has faced the well-known "memory wall" problem, namely the performance difference between the CPU and the main memory. Simultaneously, with the miniaturization of feature sizes and chip areas, the size of transistors and capacitors in the traditional 1T1C DRAM architecture continues to shrink, leading to challenges such as increased leakage current, shortened hold time, and increased power consumption.

[0003] Indium gallium zinc oxide thin-film transistors (IGZO TFTs) possess characteristics such as low leakage current, high mobility, low-temperature large-area deposition, and low cost. Capacitorless 2T0C DRAMs composed of IGZO TFTs hold promise for solving the "memory wall" problem of traditional 1T1C DRAMs. To improve the hold time of DRAM devices, reducing the leakage current of IGZO TFTs has become a new challenge.

[0004] Currently, the most common process for reducing leakage current in IGZO TFTs is thermal annealing, which repairs material defects, but its effectiveness in reducing leakage current is nearing its limit.

[0005] Therefore, this invention is proposed. Summary of the Invention

[0006] The main objective of this invention is to provide a dielectric-isolated two-stage gate metal-oxide thin-film transistor structure and its manufacturing method, which significantly reduces the leakage current problem of the device.

[0007] To achieve the above objectives, the present invention provides the following technical solutions.

[0008] A first aspect of the present invention provides a dielectric-isolated two-stage gate metal-oxide thin-film transistor structure, comprising: Substrate; Stacked sequentially from bottom to top on the substrate are: a gate layer, a gate dielectric layer, and a channel layer; The source layer and drain layer are respectively disposed on the left and right sides of the upper surface of the channel layer; The gate layer comprises a first metal gate segment, an isolation dielectric segment, and a second metal gate segment sequentially spliced ​​in a horizontal direction, wherein the work function of the second metal gate segment is lower than that of the first metal gate segment.

[0009] Further improvements can be made based on this, as listed below.

[0010] Furthermore, the difference between the work function of the first metal gate segment and the work function of the second metal gate segment is 0.05V~1.5V.

[0011] Furthermore, the first metal gate segment is made of Mo, and the second metal gate segment is made of Al.

[0012] Furthermore, the second metal gate segment is covered by only one of the source layer and the drain layer, and the first metal gate segment is covered by only the other; and the length of the first metal gate segment covered is greater than the length of the second metal gate segment covered, and the length direction is along the splicing direction.

[0013] Furthermore, the second metal gate segment is only covered by the drain layer.

[0014] Furthermore, the channel layer is made of at least one of IGZO, IZO, ITO, InO, ZnO, and TiO.

[0015] Furthermore, the isolation medium segment adopts at least one of oxides, nitrides, carbides, and organic compounds.

[0016] Furthermore, the source and drain layers are made of Mo.

[0017] Furthermore, the gate dielectric layer covers the upper surface and sidewalls of the gate layer, the channel layer covers the upper surface and sidewalls of the gate dielectric layer, and both the source layer and the drain layer cover the upper surface and sidewalls of the channel layer.

[0018] A second aspect of the present invention provides a method for manufacturing a dielectric-isolated two-segment gate metal-oxide thin-film transistor structure as described in the first aspect, comprising: A first metal layer is formed on the substrate; An isolation dielectric layer is formed on the first metal layer, wherein the dielectric isolation layer forms a first sidewall at least on one sidewall of the first metal layer; Thin the insulating dielectric layer to expose the upper surface of the first metal layer; A second metal layer is formed to cover the isolation medium layer and the first metal layer, and the second metal layer forms a second sidewall on the sidewall of the first sidewall, wherein the work function of the second metal layer is less than the work function of the first metal layer; Thin the second metal layer to expose the upper surface of the first metal layer; A gate dielectric layer is formed, covering the first metal layer, the isolation dielectric layer, and the second metal layer; A channel layer is formed to cover the gate dielectric layer; A conductive layer is formed above the channel layer; The conductive layer is patterned to form a source layer and a drain layer, respectively.

[0019] In summary, compared with the prior art, the present invention achieves the following technical effects: (1) By splicing two metals with different work functions into a gate layer, the leakage current problem of the device can be reduced by utilizing the difference in their work functions. (2) The two metals with different work functions are separated by an isolation medium, which will affect the electric field in the channel, thereby further reducing the leakage current problem of the device; (3) Optimizing the difference between the work function of the first metal grid segment and the work function of the second metal grid segment can further improve the leakage problem; (4) Optimizing the size difference between the first metal gate segment and the second metal gate segment covered by the source / drain can also further improve the leakage problem; (5) The manufacturing method provided is simple and compatible with existing integrated processes. Attached Figure Description

[0020] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0021] Figure 1 A schematic diagram of the dielectric-isolated two-section gate metal-oxide thin-film transistor structure provided by the present invention; Figures 2 to 9 This is a schematic diagram of the structure obtained in each step of the manufacturing method provided by the present invention. Detailed Implementation

[0022] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0023] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0024] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0025] This invention provides a method such as Figure 1 The dielectric-isolated two-section gate metal-oxide thin-film transistor structure shown includes: a substrate (not shown); and a gate layer, a gate dielectric layer 4, and a channel layer 5 stacked sequentially from bottom to top on the substrate; a source layer 61 and a drain layer 62 are respectively disposed on the left and right sides of the upper surface of the channel layer 5.

[0026] The gate layer comprises a first metal gate segment 1, an isolation dielectric segment 2, and a second metal gate segment 3, which are sequentially spliced ​​in a horizontal direction, and the work function of the second metal gate segment 3 is lower than that of the first metal gate segment 1. Although Figure 1 The diagram only illustrates the structure where the first metal gate segment 1 is located on the left side, but this does not limit the scope of the invention. The splicing in this invention can be from left to right or from right to left. In other words, the first metal gate segment and the source layer can be on the same side, and the second metal gate segment and the drain layer can be on the same side; alternatively, the second metal gate segment and the source layer can be on the same side, and the first metal gate segment and the drain layer can be on the same side. Typically, to significantly reduce leakage current, the second metal gate segment is covered by only one of the source and drain layers, and the first metal gate segment is covered by only the other.

[0027] Therefore, by using two metals with different work functions to form a gate and isolating them with a dielectric, this invention can reduce leakage current in the device, thus overcoming the shortcomings of traditional thermal annealing processes. Furthermore, the structure of this invention can be further integrated with thermal annealing processes; this invention is not limited in this regard.

[0028] exist Figure 1 In the transistor shown, the substrate can be any substrate commonly used in semiconductor devices. It can be a silicon-based substrate, such as one of bulk silicon, SOI, strained silicon, GeSi, or silicon oxide, or a substrate made of group III-V materials.

[0029] The first metal gate segment 1 and the second metal gate segment 3 can be independently selected from TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, Ti, Al, Cr, Au, Cu, Ag, HfRu, and RuOx, as long as the selection of the two meets the requirement of work function difference.

[0030] In some implementations, the difference between the work function of the first metal gate segment 1 and the work function of the second metal gate segment 3 is 0.05V to 1.5V.

[0031] In some implementations, the first metal gate segment 1 is made of Mo, and the second metal gate segment 3 is made of Al.

[0032] The isolation dielectric segment 2 can be one or more of the following materials stacked together: aluminum oxide, silicon oxide, silicon oxynitride, tantalum oxide, hafnium oxide, silicon nitride, tantalum oxide, or zirconium oxide.

[0033] The gate dielectric layer 4 can be one or more of the following materials stacked together: aluminum oxide, silicon oxide, silicon oxynitride, tantalum oxide, hafnium oxide, silicon nitride, tantalum oxide, or zirconium oxide.

[0034] The channel layer 5 can be at least one of IGZO, IZO, ITO, InO, ZnO, and TiO to obtain higher field-effect mobility and better electrical stability.

[0035] The source layer 61 and drain layer 62 can be made of conductive materials such as metals or doped semiconductors, for example, TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, Ti, Al, Cr, Au, Cu, Ag, HfRu, and RuOx. The materials of the source layer and drain layer can be the same or different.

[0036] In some implementations, the length of the first metal gate segment 1 covered is greater than the length of the second metal gate segment 3 covered, with the length direction along the splicing direction. Here, "covered" refers to being covered by either the source or drain layer; this dimensional difference can further reduce leakage current. For example... Figure 1 As shown, the length covered by the first metal grid segment 1 is L1, and the length covered by the second metal grid segment 3 is L2, where L1 > L2.

[0037] In some implementations, the gate layer, gate dielectric layer 4, channel layer 5, and source / drain layer are stacked in a "wrap-around" shape, for example... Figure 1 As shown, the gate dielectric layer 4 covers the upper surface and sidewalls of the gate layer, the channel layer 5 covers the upper surface and sidewalls of the gate dielectric layer 4, and the source layer 61 and the drain layer 62 both cover the upper surface and sidewalls of the channel layer.

[0038] In some embodiments, the source layer 61 and the drain layer 62 can be isolated by a suitable dielectric material. Figure 1 It is not shown in the text.

[0039] The present invention also provides Figure 1 The method for manufacturing the transistor shown is simple and includes the following steps.

[0040] Step S1: Form a first metal layer 1' on the substrate using methods such as sputtering, for example... Figure 2 As shown, this layer serves as Figure 1 The first metal gate segment.

[0041] Step S2, forming an isolation dielectric layer 2' on the first metal layer, wherein the isolation dielectric layer 2' forms a first sidewall on at least one sidewall of the first metal layer, such as... Figure 3 As shown. Typically, to reduce operational difficulty, first sidewalls are formed on both opposite sidewalls of the first metal layer 1', allowing one sidewall to be removed in subsequent processes. Alternatively, in actual manufacturing, it can be done in one step, using methods such as masking to form the first sidewall only on the right or left side of the first metal layer.

[0042] Step S3, thinning the isolation dielectric layer 2', can be achieved by means of CMP or other methods, so that the upper surface of the first metal layer is exposed.

[0043] Step S4: A second metal layer 3' is formed using sputtering or other methods, covering the isolation dielectric layer 2' and the first metal layer 1', and the second metal layer 3' forms a second sidewall on the sidewall of the first sidewall 21, such as... Figure 4 As shown, the work function of the second metal layer 3' is less than that of the first metal layer 1'. In actual manufacturing, the formation order of the first metal layer 1' and the second metal layer 3' can be interchanged, but it is usually preferred to form the first metal layer 1' first because of its larger size.

[0044] Step S5: Thin the second metal layer 3' using CMP or similar methods to expose the upper surface of the first metal layer 1'; then remove the first sidewall 21 and the second sidewall 31 on the left side, as shown below. Figure 5 As shown. The first sidewall 21 is retained as Figure 1 The isolation medium section, the second sidewall 31 is retained as Figure 1 The second metal gate segment.

[0045] Step S6, forming a gate dielectric layer 4, covering the first metal layer 1', the isolation dielectric layer 2', and the second metal layer 3', as follows: Figure 6 As shown.

[0046] Step S7, forming the channel layer 5 and covering the gate dielectric layer 4, as shown. Figure 7 As shown.

[0047] Step S8, a conductive layer 6 is formed above the channel layer 5, such as... Figure 8 As shown.

[0048] Step S9: Pattern the conductive layer 6 to form the source layer 61 and the drain layer 62, as shown below. Figure 9 As shown.

[0049] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A dielectric-isolated two-stage gate metal-oxide thin-film transistor structure, characterized in that, include: Substrate; Stacked sequentially from bottom to top on the substrate are: a gate layer, a gate dielectric layer, and a channel layer; The source layer and drain layer are respectively disposed on the left and right sides of the upper surface of the channel layer; The gate layer comprises a first metal gate segment, an isolation dielectric segment, and a second metal gate segment sequentially spliced ​​in a horizontal direction, wherein the work function of the second metal gate segment is lower than that of the first metal gate segment.

2. The dielectric-isolated two-stage gate metal-oxide thin-film transistor structure according to claim 1, characterized in that, The difference between the work function of the first metal gate segment and the work function of the second metal gate segment is 0.05V~1.5V.

3. The dielectric-isolated two-stage gate metal-oxide thin-film transistor structure according to claim 1, characterized in that, The second metal gate segment is covered by only one of the source layer and the drain layer, and the first metal gate segment is covered by only the other.

4. The dielectric-isolated two-stage gate metal-oxide thin-film transistor structure according to claim 3, characterized in that, The length covered by the first metal grid segment is greater than the length covered by the second metal grid segment, and the length direction is along the splicing direction.

5. The dielectric-isolated two-stage gate metal-oxide thin-film transistor structure according to claim 3, characterized in that, The second metal gate segment is covered only by the drain layer.

6. The dielectric-isolated two-stage gate metal-oxide thin-film transistor structure according to any one of claims 1-5, characterized in that, The channel layer is made of at least one of IGZO, IZO, ITO, InO, ZnO, and TiO.

7. The dielectric-isolated two-stage gate metal-oxide thin-film transistor structure according to any one of claims 1-5, characterized in that, The isolation medium section uses at least one of oxides, nitrides, carbides, and organic compounds.

8. The dielectric-isolated two-stage gate metal-oxide thin-film transistor structure according to any one of claims 1-5, characterized in that, The source and drain layers are made of Mo.

9. The dielectric-isolated two-stage gate metal-oxide thin-film transistor structure according to any one of claims 1-5, characterized in that, The gate dielectric layer covers the upper surface and sidewalls of the gate layer, the channel layer covers the upper surface and sidewalls of the gate dielectric layer, and both the source layer and the drain layer cover the upper surface and sidewalls of the channel layer.

10. A method for manufacturing a dielectric-isolated two-stage gate metal-oxide thin-film transistor structure according to any one of claims 1-9, characterized in that, include: A first metal layer is formed on the substrate; An isolation dielectric layer is formed on the first metal layer, wherein the dielectric isolation layer forms a first sidewall at least on one sidewall of the first metal layer; Thin the insulating dielectric layer to expose the upper surface of the first metal layer; A second metal layer is formed to cover the isolation medium layer and the first metal layer, and the second metal layer forms a second sidewall on the sidewall of the first sidewall, wherein the work function of the second metal layer is less than the work function of the first metal layer; Thin the second metal layer to expose the upper surface of the first metal layer; A gate dielectric layer is formed, covering the first metal layer, the isolation dielectric layer, and the second metal layer; A channel layer is formed to cover the gate dielectric layer; A conductive layer is formed above the channel layer; The conductive layer is patterned to form a source layer and a drain layer, respectively.

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