Three-level dc converter based on capacitive clamping and reduced input current ripple

Abstract

This invention relates to the field of photovoltaic power generation technology and discloses a three-level DC-DC converter based on capacitor clamping and reduced input current ripple. The converter includes an input inductor branch, a control switch branch, a unidirectional conductive branch, and an output capacitor branch. The unidirectional conductive branch contains seven unidirectional conductive units connected in series, designated as the first unidirectional conductive unit to the seventh unidirectional conductive unit. The output capacitor branch includes capacitors C0 and C6. In practical use, the circuit of this invention forms a three-level output structure, a clamping structure, and a zero-input current ripple structure. Multiplexed components exist within these three mechanisms, thereby reducing the overall number of components in the DC-DC converter while achieving three-level output, reducing input current ripple, and suppressing voltage and current spikes.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic power generation technology, and more specifically to a three-level DC-DC converter based on capacitor clamping and reduced input current ripple. Background Technology

[0002] In the field of photovoltaic power generation, DC-DC converters are often used to boost the output voltage of photovoltaic panels so that the final output voltage meets grid connection requirements. Currently, existing DC-DC converters have the following problems when boosting the output voltage of photovoltaic panels:

[0003] First, since photovoltaic panels are equivalent to current sources, the current ripple input to the DC-DC converter is large, and a large input current ripple will reduce the output power of the photovoltaic panel; moreover, the existing structures for reducing input current ripple can only reduce the current ripple and cannot be reused with other components in the DC-DC converter.

[0004] Second: The large parasitic capacitance of photovoltaic panels will cause a large leakage current. The leakage current will flow from the positive terminal of the photovoltaic panel through the DC converter and finally back to the ground, causing significant losses and voltage and current distortion, which will reduce the quality of the power input to the grid.

[0005] Third: Currently, when DC-DC converters output three levels, the only way to increase the number of transformer windings is to increase the number of windings, which usually requires more than three windings. This increases the cost and size of the DC-DC converter and brings a large voltage static error. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the present invention provides a three-level DC-DC converter based on capacitor clamping and reduced input current ripple.

[0007] To solve the above technical problems, the present invention provides the following technical solution: a three-level DC-DC converter based on capacitor clamping and reduced input current ripple, comprising an input inductor branch, a control switch branch, a unidirectional conductive branch, and an output capacitor branch; the unidirectional conductive branch is provided with seven unidirectional conductive units connected in series, the seven unidirectional conductive units being the first unidirectional conductive unit to the seventh unidirectional conductive unit; the output capacitor branch includes capacitor C0 and capacitor C6;

[0008] The input terminal of the input inductor branch is used to be electrically connected to the positive terminal of the external power supply. The output terminal of the input inductor branch is electrically connected to the input terminal of the first unidirectional conductive unit. The output terminal of the seventh unidirectional conductive unit is electrically connected to one end of capacitor C0. The other end of capacitor C0 is electrically connected to one end of capacitor C6. The other end of capacitor C6 is used to be electrically connected to the negative terminal of the external power supply.

[0009] The control switch branch is electrically connected to the output terminal of the input inductor circuit and the other end of capacitor C6, and is used to control the on / off state of the output terminal of the input inductor circuit and the other end of capacitor C6;

[0010] The output terminal of the first unidirectional conductive unit is electrically connected to one end of capacitor C2. The other end of capacitor C2 is electrically connected to one end of capacitor C5, one end of capacitor C7, one end of inductor L2, and one end of capacitor C3. The other end of capacitor C5 is electrically connected to the output terminal of the fifth unidirectional conductive unit. The other end of capacitor C7 is electrically connected to the middle node of the input inductor branch. The other end of capacitor C3 is electrically connected to the output terminal of the third unidirectional conductive unit and one end of capacitor C6. The other end of inductor L2 is electrically connected to the output terminal of the fourth unidirectional conductive unit and one end of capacitor C4. The other end of capacitor C4 is electrically connected to the input terminal of the seventh unidirectional conductive unit. The second unidirectional conductive unit is electrically connected to the output terminal of the fourth unidirectional conductive unit through capacitor C1.

[0011] In one embodiment, the input inductor branch includes inductor L0 and inductor L1. One end of inductor L0 is the input terminal of the input inductor branch, and the other end of inductor L0 is electrically connected to one end of inductor L1 and is the intermediate node of the input inductor branch. The other end of inductor L1 is the output terminal of the input inductor branch, and inductor L1 is coupled to inductor L2.

[0012] In one implementation, the inductance values ​​of inductor L1 and inductor L2 are the same.

[0013] In one embodiment, the control switch branch includes an NMOS transistor S, the drain of which is electrically connected to the output terminal of the input inductor branch, the source of which is electrically connected to the other end of capacitor C6, and the gate of which is used to input a drive signal.

[0014] In one implementation, the driving signal is a PWM signal.

[0015] In one embodiment, the first unidirectional conductive unit includes a diode D6, the anode of which is the input terminal of the first unidirectional conductive unit, and the cathode of which is the output terminal of the first unidirectional conductive unit.

[0016] In one embodiment, the second unidirectional conductive unit includes a diode D2, the anode of which is the input terminal of the second unidirectional conductive unit, and the cathode of which is the output terminal of the second unidirectional conductive unit.

[0017] In one embodiment, the third unidirectional conductive unit includes a diode D1, the anode of which is the input terminal of the third unidirectional conductive unit, and the cathode of which is the output terminal of the third unidirectional conductive unit.

[0018] In one embodiment, the fourth unidirectional conductive unit includes a diode D3, the anode of which is the input terminal of the fourth unidirectional conductive unit, and the cathode of which is the output terminal of the fourth unidirectional conductive unit.

[0019] In one embodiment, the fifth unidirectional conductive unit includes a diode D5, the anode of which is the input terminal of the fifth unidirectional conductive unit, and the cathode of which is the output terminal of the fifth unidirectional conductive unit.

[0020] The sixth unidirectional conductive unit includes a diode D4, the anode of which is the input terminal of the sixth unidirectional conductive unit, and the cathode of which is the output terminal of the sixth unidirectional conductive unit.

[0021] The seventh unidirectional conductive unit includes a diode D0, the anode of which is the input terminal of the seventh unidirectional conductive unit, and the cathode of the diode D7 is the output terminal of the seventh unidirectional conductive unit.

[0022] The beneficial effects of this invention compared to the prior art are as follows: In this invention, capacitors C0 and C6 form a three-level output structure, and the first unidirectional conductive unit, capacitors C2, C3, and C6 form a clamping structure. The clamping structure is used to suppress voltage and current spikes in the current. The input inductor branch, the first unidirectional conductive unit, capacitors C2, C3, C6, and C7 form a zero-input current ripple structure. The zero-input current ripple structure can make the input current ripple zero, thereby reducing electromagnetic interference and improving circuit stability. In addition, the three-level output structure, clamping structure, and zero-input current ripple structure of this invention contain reused components, thereby reducing the overall number of components in the DC-DC converter while achieving three-level output, reducing input current ripple, and suppressing voltage and current spikes. Attached Figure Description

[0023] Figure 1 The circuit diagram showing the connection between the present invention and the load R in the embodiment is shown. Detailed Implementation

[0024] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0025] like Figure 1As shown, a three-level DC-DC converter based on capacitor clamping and reduced input current ripple includes an input inductor branch 1, a control switch branch 2, a unidirectional conductive branch 3, and an output capacitor branch 4. The unidirectional conductive branch 3 is provided with seven unidirectional conductive units connected in series, namely the first unidirectional conductive unit 30 to the seventh unidirectional conductive unit 36. The output capacitor branch 4 includes capacitors C0 and C6.

[0026] In this embodiment, the connection relationships of the input inductor branch 1, the control switch branch 2, the unidirectional conductive branch 3, and the output capacitor branch 4 are as follows:

[0027] The input terminal of the input inductor branch 1 is used to be electrically connected to the positive terminal of the external power supply Vin. The output terminal of the input inductor branch 1 is electrically connected to the input terminal of the first unidirectional conductive unit 30. The output terminal of the seventh unidirectional conductive unit 36 ​​is electrically connected to one end of the capacitor C0. The other end of the capacitor C0 is electrically connected to one end of the capacitor C6. The other end of the capacitor C6 is used to be electrically connected to the negative terminal of the external power supply Vin.

[0028] The control switch branch 2 is electrically connected to the output terminal of the input inductor circuit 1 and the other end of the capacitor C6, and is used to control the on / off state of the output terminal of the input inductor circuit 1 and the other end of the capacitor C6;

[0029] The output terminal of the first unidirectional conductive unit 30 is electrically connected to one end of capacitor C2. The other end of capacitor C2 is electrically connected to one end of capacitor C5, one end of capacitor C7, one end of inductor L2, and one end of capacitor C3. The other end of capacitor C5 is electrically connected to the output terminal of the fifth unidirectional conductive unit 34. The other end of capacitor C7 is electrically connected to the intermediate node of the input inductor branch 1. The other end of capacitor C3 is electrically connected to the output terminal of the third unidirectional conductive unit 32 and one end of capacitor C6. The other end of inductor L2 is electrically connected to the output terminal of the fourth unidirectional conductive unit 33 and one end of capacitor C4. The other end of capacitor C4 is electrically connected to the input terminal of the seventh unidirectional conductive unit 36. The second unidirectional conductive unit 31 is electrically connected to the output terminal of the fourth unidirectional conductive unit 33 through capacitor C1.

[0030] exist Figure 1 In the input inductor branch 1, there are inductors L0 and L1. One end of inductor L0 is the input terminal of input inductor branch 1, and the other end of inductor L0 is electrically connected to one end of inductor L1 and is the intermediate node of input inductor branch 1. The other end of inductor L1 is the output terminal of input inductor branch 1.

[0031] exist Figure 1In this circuit, control switch branch 2 includes an NMOS transistor S. The drain of NMOS transistor S is electrically connected to the output terminal of input inductor branch 1, and the source of NMOS transistor S is electrically connected to the other end of capacitor C6. The gate of NMOS transistor S is used to input a drive signal, which is a PWM signal. In practical use, the on-time of NMOS transistor S in one cycle can be controlled by controlling the duty cycle of the high-level drive signal, and the gain of this invention can be controlled by controlling the on-time of NMOS transistor S in one cycle.

[0032] Specifically, in Figure 1 In the first unidirectional conductive unit 30, there is a diode D6, the anode of the diode D6 is the input terminal of the first unidirectional conductive unit 30, and the cathode of the diode D6 is the output terminal of the first unidirectional conductive unit 30.

[0033] The second unidirectional conductive unit 31 includes a diode D2, the anode of which is the input terminal of the second unidirectional conductive unit 31, and the cathode of which is the output terminal of the second unidirectional conductive unit 31.

[0034] The third unidirectional conductive unit 32 includes a diode D1, the anode of which is the input terminal of the third unidirectional conductive unit 32, and the cathode of which is the output terminal of the third unidirectional conductive unit 32.

[0035] The fourth unidirectional conductive unit 33 includes a diode D3, the anode of which is the input terminal of the fourth unidirectional conductive unit 33, and the cathode of which is the output terminal of the fourth unidirectional conductive unit 33.

[0036] The fifth unidirectional conductive unit 34 includes a diode D5, the anode of which is the input terminal of the fifth unidirectional conductive unit 34, and the cathode of which is the output terminal of the fifth unidirectional conductive unit 34.

[0037] The sixth unidirectional conductive unit 35 includes a diode D4, the anode of which is the input terminal of the sixth unidirectional conductive unit 35, and the cathode of which is the output terminal of the sixth unidirectional conductive unit 35.

[0038] The seventh unidirectional conductive unit 36 ​​includes a diode D0, the anode of which is the input terminal of the seventh unidirectional conductive unit 36, and the cathode of which is the output terminal of the seventh unidirectional conductive unit 36.

[0039] In this embodiment, capacitors C0 through C7 have positive and negative terminals, as detailed below:

[0040] The end of capacitor C0 that is electrically connected to diode D0 is the positive terminal, and the other end of capacitor C0 is the negative terminal;

[0041] The end of capacitor C1 that is electrically connected to diode D3 is the positive terminal, and the other end of capacitor C1 is the negative terminal;

[0042] The end of capacitor C2 that is electrically connected to diode D6 is the negative terminal, and the other end of capacitor C2 is the positive terminal;

[0043] The end of capacitor C3 that is electrically connected to capacitor C2 is the positive terminal, and the other end of capacitor C3 is the negative terminal;

[0044] The end of capacitor C4 that is electrically connected to diode D4 is the positive terminal, and the other end of capacitor C4 is the negative terminal;

[0045] The end of capacitor C5 that is electrically connected to diode D4 is the positive terminal, and the other end of capacitor C5 is the negative terminal;

[0046] The end of capacitor C6 that is electrically connected to capacitor C0 is the positive terminal, and the other end of capacitor C6 is the negative terminal;

[0047] The end of capacitor C7 that is electrically connected to inductor L0 is the positive terminal, and the other end of capacitor C7 is the negative terminal.

[0048] for Figure 1 In the circuit, capacitors C1-C5 and diodes D1-D5 form a boost converter structure. The charging and discharging process of capacitors C0 and C6 by the boost converter structure is as follows:

[0049] When the NMOS transistor S is turned on, inductor L2 charges capacitor C3 through diode D3, and inductor L2 and capacitor C1 charge capacitor C2 together through diode D2. Inductor L2 and capacitor C5 also charge capacitor C4 through diode D4.

[0050] When NMOS transistor S is turned off, inductor L2 charges capacitor C5 through diode D5, and inductor L2 and capacitor C3 charge capacitor C1 through diode D1. Capacitor C4 charges capacitor C0 through diode D0. External power supply Vin charges capacitor C6 through inductor L1, capacitor C2, and capacitor C3 through diode D6. When inductor L1 and inductor L2 are of equal value, the voltages of capacitor C0 and capacitor C6 are equal, both being 0.5 times the output voltage, forming a three-level structure. This improves power transmission efficiency and reduces system losses. The output voltage is the voltage at the end where capacitors C0 and C6 are electrically connected. In this embodiment, inductor L1 is coupled to inductor L2, forming a transformer structure.

[0051] for Figure 1In the circuit, diode D6, capacitor C2, capacitor C3, and capacitor C6 form a clamping structure. In actual use, when the NMOS transistor S is turned on, capacitors C2 and C3, together with diodes D2 and D3, form a boost unit. When the NMOS transistor S is turned off, the leakage inductance is transferred to capacitor C6 through diode D6, capacitors C2 and C3, thereby suppressing voltage and current spikes in the DC-DC converter.

[0052] for Figure 1 In the circuit, inductor L1, diode D6, capacitors C2, C3, C6, C7, and inductor L0 form a zero-input current ripple structure. In actual use, when the NMOS transistor S is turned on, the current in inductor L1 increases linearly, and the current flowing through capacitor C7 is discharged through capacitors C3 and C6, the external power supply Vin, and inductor L0.

[0053] When the current in inductor L1 rises to a level greater than that in inductor L0, the current flowing through capacitor C7 charges inductor L1, NMOS transistor S, capacitor C6, and capacitor C3.

[0054] When NMOS transistor S is turned off, the current in inductor L1 decreases linearly. The current flowing through capacitor C7 charges inductor L1, diode D6, and capacitor C2. When the current in inductor L1 drops below the current in inductor L0, the current flowing through capacitor C7 discharges it through capacitors C3 and C6, the external power supply Vin, and inductor L0. The superposition of the currents in inductor L1 and capacitor C7 results in zero input current ripple. This reduces electromagnetic interference and improves circuit stability.

[0055] In addition, the boost structure, clamping structure and zero input current ripple structure in the BOOST converter of this invention reuse components, thereby reducing the overall number of components in the DC converter while realizing three-level output of the DC converter, reducing input current ripple and suppressing voltage and current spikes, thereby reducing circuit cost and circuit size.

[0056] Based on the above description, those skilled in the art can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A three-level DC / DC converter based on capacitive clamping and reducing input current ripple, characterized in that, It includes an input inductor branch, a control switch branch, a unidirectional conductive branch, and an output capacitor branch; the unidirectional conductive branch is provided with seven unidirectional conductive units connected in series, which are the first unidirectional conductive unit to the seventh unidirectional conductive unit; the output capacitor branch includes capacitor C0 and capacitor C6; The input terminal of the input inductor branch is used to be electrically connected to the positive terminal of the external power supply. The output terminal of the input inductor branch is electrically connected to the input terminal of the first unidirectional conductive unit. The output terminal of the seventh unidirectional conductive unit is electrically connected to one end of capacitor C0. The other end of capacitor C0 is electrically connected to one end of capacitor C6. The other end of capacitor C6 is used to be electrically connected to the negative terminal of the external power supply. The control switch branch is electrically connected to the output terminal of the input inductor branch and the other end of capacitor C6, and is used to control the on / off state of the output terminal of the input inductor branch and the other end of capacitor C6; The output terminal of the first unidirectional conductive unit is electrically connected to one end of capacitor C2. The other end of capacitor C2 is electrically connected to one end of capacitor C5, one end of capacitor C7, one end of inductor L2, and one end of capacitor C3. The other end of capacitor C5 is electrically connected to the output terminal of the fifth unidirectional conductive unit. The other end of capacitor C7 is electrically connected to the middle node of the input inductor branch. The other end of capacitor C3 is electrically connected to the output terminal of the third unidirectional conductive unit and one end of capacitor C6. The other end of inductor L2 is electrically connected to the output terminal of the fourth unidirectional conductive unit and one end of capacitor C4. The other end of capacitor C4 is electrically connected to the input terminal of the seventh unidirectional conductive unit. The second unidirectional conductive unit is electrically connected to the output terminal of the fourth unidirectional conductive unit through capacitor C1.

2. The three-level DC-DC converter based on capacitor clamping and reduced input current ripple according to claim 1, characterized in that, The input inductor branch includes inductor L0 and inductor L1. One end of inductor L0 is the input terminal of the input inductor branch. The other end of inductor L0 is electrically connected to one end of inductor L1 and is the intermediate node of the input inductor branch. The other end of inductor L1 is the output terminal of the input inductor branch. Inductor L1 is coupled to inductor L2.

3. The three-level DC-DC converter based on capacitor clamping and reduced input current ripple according to claim 2, characterized in that, Inductor L1 and inductor L2 have the same inductance value.

4. The three-level DC-DC converter based on capacitor clamping and reduced input current ripple according to claim 1, characterized in that, The control switch branch includes an NMOS transistor S. The drain of the NMOS transistor S is electrically connected to the output terminal of the input inductor branch, the source of the NMOS transistor S is electrically connected to the other end of the capacitor C6, and the gate of the NMOS transistor S is used to input the drive signal.

5. The three-level DC-DC converter based on capacitor clamping and reduced input current ripple according to claim 4, characterized in that, The driving signal is a PWM signal.

6. The three-level DC-DC converter based on capacitor clamping and reduced input current ripple according to any one of claims 1-5, characterized in that, The first unidirectional conductive unit includes a diode D6, the anode of which is the input terminal of the first unidirectional conductive unit, and the cathode of which is the output terminal of the first unidirectional conductive unit.

7. The three-level DC-DC converter based on capacitor clamping and reduced input current ripple according to any one of claims 1-5, characterized in that, The second unidirectional conductive unit includes a diode D2, the anode of which is the input terminal of the second unidirectional conductive unit, and the cathode of which is the output terminal of the second unidirectional conductive unit.

8. The three-level DC-DC converter based on capacitor clamping and reduced input current ripple according to any one of claims 1-5, characterized in that, The third unidirectional conductive unit includes a diode D1, with the anode of the diode D1 being the input terminal of the third unidirectional conductive unit and the cathode of the diode D1 being the output terminal of the third unidirectional conductive unit.

9. The three-level DC-DC converter based on capacitor clamping and reduced input current ripple according to any one of claims 1-5, characterized in that, The fourth unidirectional conductive unit includes a diode D3, with the anode of the diode D3 being the input terminal of the fourth unidirectional conductive unit and the cathode of the diode D3 being the output terminal of the fourth unidirectional conductive unit.

10. The three-level DC-DC converter based on capacitor clamping and reduced input current ripple according to any one of claims 1-5, characterized in that, The fifth unidirectional conductive unit includes a diode D5, the anode of which is the input terminal of the fifth unidirectional conductive unit, and the cathode of which is the output terminal of the fifth unidirectional conductive unit. The sixth unidirectional conductive unit includes a diode D4, the anode of which is the input terminal of the sixth unidirectional conductive unit, and the cathode of which is the output terminal of the sixth unidirectional conductive unit. The seventh unidirectional conductive unit includes a diode D0, the anode of which is the input terminal of the seventh unidirectional conductive unit, and the cathode of the diode D7 is the output terminal of the seventh unidirectional conductive unit.

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