Edgeless Storage Cluster

Abstract

This application relates to edgeless storage clusters. Systems, devices, and techniques are described for eliminating gaps between clusters by creating groups of clusters (e.g., domains) that are active at a given time and using drivers within inactive clusters to perform array termination functions on adjacent active clusters. Tiles at the edge of a cluster can have drivers that operate both that cluster and an adjacent cluster, with circuitry (e.g., multiplexers) on those drivers to enable operation of both clusters.

Description

[0001] Cross Reference

[0002] This patent application is a national phase application of International Patent Application No. PCT / US2022 / 073788, filed by Castro et al. on July 15, 2022, entitled “EDGELESS MEMORY CLUSTERS,” which claims priority to U.S. Patent Application No. 17 / 385,682, filed by Castro et al. on July 26, 2021, entitled “EDGELESS MEMORY CLUSTERS,” each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to edgeless storage clusters. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, consumer devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by a logical 1 or a logical 0. In some instances, a single memory cell can support more than two states and store any of these states. To access stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program a state into the memory device.

[0005] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, etc. Memory cells can be volatile or non-volatile. Summary of the Invention

[0006] An apparatus is described. The apparatus may include a set of memory clusters, each memory cluster in the set of memory clusters comprising: a plurality of tiles having a driver; a memory array positioned above the plurality of tiles and having a plurality of memory cells; and a plurality of electrodes coupled to the plurality of memory cells for addressing each of the plurality of memory cells, wherein the driver of a first tile of a first memory cluster in the set of memory clusters is coupled to an electrode of the plurality of electrodes of a second tile of a second memory cluster in the set of memory clusters, and wherein the first memory cluster and the second memory cluster are configured to operate in an active mode during mutually exclusive periods.

[0007] A memory cluster is described. The memory cluster may include: a plurality of tiles having a driver; a memory array positioned above the plurality of tiles and having a plurality of memory cells; and a plurality of electrodes coupled to the driver via respective socket connections, the plurality of electrodes coupled to the plurality of memory cells for addressing each of the plurality of memory cells, wherein a tile of the plurality of tiles includes a first portion of the driver and a second portion of the driver, the second portion of the driver being configured for accessing memory cells of an adjacent memory cluster when the memory cluster is inactive.

[0008] An apparatus is described. The apparatus may include: a first memory cluster comprising: a first memory array having a first plurality of memory cells; a first driver coupled to a subset of the first plurality of memory cells; and a first driver circuit configured to enable the first driver when the first memory cluster is active; and a second memory cluster comprising: a second memory array having a second plurality of memory cells, wherein the first driver is coupled to at least one memory cell of the second plurality of memory cells; and a second driver coupled to a subset of the second plurality of memory cells, wherein the first driver circuit is further configured to enable the first driver when the second memory cluster is active and the first memory cluster is inactive.

[0009] A method is described. The method may include: determining to access a first memory array of a first memory cluster, the first memory cluster including a first plurality of tiles including a first plurality of drivers coupled to the first memory array; inhibiting a first portion of tiles from a second plurality of tiles of a second memory cluster, the second memory cluster including a second memory array, the second plurality of tiles including a second plurality of drivers coupled to the second memory array, drivers of the second plurality of drivers being coupled to the first memory array and positioned on second portions of the tiles, in response to determining to access the first memory array of the first memory cluster; and enabling the drivers on the second portions of the tiles of the second memory cluster to access the first memory array of the first memory cluster, based at least in part on the determination to access the first memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An example of a system supporting edgeless storage clustering according to examples disclosed herein is described.

[0011] Figure 2 An example of a memory die supporting an edgeless memory cluster according to examples disclosed herein is illustrated.

[0012] Figure 3 An example of a memory cell array supporting edgeless memory clustering according to examples disclosed herein is described.

[0013] Figure 4A and 4B An example of a memory module supporting edgeless memory clustering according to examples disclosed herein is described.

[0014] Figure 5 A simplified floor plan diagram illustrating a memory die supporting edgeless memory clusters according to examples disclosed herein.

[0015] Figure 6A and 6B A simplified floor plan diagram illustrating a memory die supporting edgeless memory clusters according to examples disclosed herein.

[0016] Figure 7 A block diagram showing a memory device supporting edgeless memory clustering according to examples disclosed herein.

[0017] Figure 8 A flowchart illustrating a method of supporting edgeless storage clusters according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0018] Patchwork architectures have been used in some memories, where drivers are arranged in tiles below the memory cells. Memory groups or arrays of memory cells that decode as a single group can be organized into clusters or partitions. A cluster can include tiles below the memory cells. In a cluster, the memory cell array has breaks to allow electrodes to connect to the drivers below, called socket connections. With this architecture, some of the electrodes contacting the memory cells associated with a tile can extend beyond the tile's footprint to contact memory cells associated with adjacent tiles. The memory cells can be attached to drivers on one of the adjacent tiles. In some cases, adjacent clusters have gaps between them to allow for the placement of array termination tiles that contain additional drivers with their socket connections to electrodes outside the cluster's footprint.

[0019] But the array termination tiles do not have associated memory cells, wasting valuable space between adjacent clusters. Removing the array termination tiles (and therefore the gaps) between adjacent clusters would allow adjacent clusters to be positioned closer together. However, this would remove the extra driver that has its socket connected to an electrode outside the cluster's footprint.

[0020] Systems, devices, and techniques for edgeless storage clustering are presented herein. Specifically, systems, devices, and techniques are described for eliminating gaps between clusters by creating groups of clusters (e.g., domains) that are active at a given time and using drivers within inactive clusters to perform array termination functions on adjacent active clusters. Tiles on the edge of a cluster can have drivers that operate on both the cluster and the adjacent cluster, with circuitry (e.g., multiplexers) on the drivers to enable operation on both clusters.

[0021] Eliminating the gaps between clusters allows for a substantial reduction in logic size. It also reduces stress on the electrodes by reducing density variations in the electrode layers.

[0022] First, in reference Figure 1 and 2 Features of the present disclosure are described in the context of the memory systems and dies described herein. Figures 3 to 5 Features of the present disclosure are further described in the context of the arrays and systems described herein. Figures 4A to 8 These and other features of the present disclosure are further illustrated and described with reference to the block diagrams, device diagrams, and flow diagrams described in connection with edgeless memory clusters.

[0023] Figure 1An example of a system 100 supporting an edgeless memory cluster according to examples disclosed herein is illustrated. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 may include one or more memory devices, but aspects of the one or more memory devices 110 may be described in the context of a single memory device, such as the memory device 110.

[0024] System 100 may comprise a portion of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or the like. Memory device 110 may be a component of the system operable to store data for one or more other components of system 100.

[0025] At least a portion of system 100 may be an example of a host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to perform processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, a system-on-a-chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0026] Memory device 110 may be a standalone device or component operable to provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to operate with one or more different types of host devices 105. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: a modulation scheme used to modulate signals, various pin configurations for communicating signals, various form factors for physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0027] Memory device 110 is operable to store data for components of host device 105. In some examples, memory device 110 may act as a secondary or slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 through external memory controller 120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0028] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (e.g., one or more peripheral components or one or more input / output controllers). The components of host device 105 may be coupled to each other using a bus 135.

[0029] The processor 125 is operable to provide control or other functionality for at least a portion of the system 100 or at least a portion of the host device 105. The processor 125 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, the processor 125 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a SoC, among other examples. In some examples, the external memory controller 120 can be implemented by or be part of the processor 125.

[0030] BIOS component 130 may be a software component including a BIOS operating as firmware that may initialize and run the various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and the various components of system 100 or host device 105. BIOS component 130 may include a program or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0031] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more sectors), each of which is operable to store at least one bit of data. A memory device 110 that includes two or more memory dies 160 may be referred to as a multi-die memory, a multi-die package, a multi-chip memory, or a multi-chip package.

[0032] Memory die 160 may be an example of a two-dimensional (2D) memory cell array or an example of a three-dimensional (3D) memory cell array. A 2D memory die 160 may include a single memory array 170. A 3D memory die 160 may include two or more memory arrays 170 that may be stacked on top of each other or positioned in close proximity to each other (e.g., relative to a substrate). In some examples, the memory arrays 170 in a 3D memory die 160 may be referred to as levels, tiers, layers, or dies. A 3D memory die 160 may include any number of stacked memory arrays 170 (e.g., more than two, more than three, more than four, more than five, more than six, more than seven, more than eight). In some 3D memory dies 160, different levels may share at least one common access line, such that some levels may share one or more row or column lines. In some 3D memory dies 160, common access lines may be shared by contiguous clusters of memory arrays.

[0033] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may combine with the local memory controller 165 of the memory die 160 to control the operation of the memory device 110 described herein.

[0034] A local memory controller 165 (e.g., local to the memory die 160) may include circuitry, logic, or components operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate with the device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some examples, the memory device 110 may not include a device memory controller 155, and the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0035] The external memory controller 120 is operable to enable communication of one or more of information, data, or commands between components of the system 100 or host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 may convert or translate communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105, or their functionality described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or its functionality described herein may be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0036] Components of host device 105 can exchange information with memory device 110 using one or more channels 115. Channels 115 can operate to support communication between external memory controller 120 and memory device 110. Each channel 115 can be an example of a transmission medium that carries information between host device 105 and the memory device. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. A signal path can be an example of a conductive path that is operable to carry a signal. For example, a channel 115 can include a first terminal that includes one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. A pin can be an example of a conductive input or output point of a device of system 100, and a pin can be operable to serve as part of a channel.

[0037] Lanes 115 (and associated signal paths and terminals) can be dedicated to conveying one or more types of information. For example, lanes 115 may include one or more command and address (CA) lanes 186, one or more clock signal (CK) lanes 188, one or more data (DQ) lanes 190, one or more other lanes 192, or a combination thereof. In some examples, signaling can be conveyed via lanes 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal can be registered for each clock cycle (e.g., on either the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal can be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0038] Figure 2 An example of a memory die 200 supporting an edgeless memory cluster according to examples disclosed herein is illustrated. The memory die 200 may be a reference Figure 1 1 . An example of a memory die 160 is described. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die 200 may include one or more memory cells 205, each of which may be programmed to store a different logical state (e.g., a programming state of a set of two or more possible states). For example, the memory cell 205 may be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, the memory cell 205 (e.g., a multi-level memory cell 205) may be operable to store more than one bit of information at a time (e.g., a logic 00, a logic 01, a logic 10, a logic 11). In some examples, the memory cells 205 may be arranged in an array, such as with reference to FIG. Figure 1 Memory array 170 is described.

[0039] Memory cell 205 may use a configurable material (which may be referred to as a memory element, memory storage element, material element, material storage element, material portion, or polarity write material portion, etc.) to store logic states. Memory cell 205 may include a capacitor or other memory storage component to store charge representing a programmable state. For example, a charged and uncharged capacitor may each represent two logic states, or a chalcogenide material may represent different states depending on its crystal structure or other properties. The configurable material of memory cell 205 may refer to a chalcogenide-based storage component. For example, a chalcogenide storage element may be used in a phase change memory (PCM) cell, a threshold memory cell, or a self-select memory cell.

[0040] Memory die 200 may include access lines (e.g., row lines 210 and column lines 215) arranged in a pattern, such as a grid-like pattern. The access lines may be formed from one or more conductive materials. In some examples, row lines 210 may be referred to as word lines. In some examples, column lines 215 may be referred to as digit lines or bit lines. Access lines, row lines, column lines, word lines, digit lines, bit lines, or the like may be referred to interchangeably without loss of understanding or operation. Memory cells 205 may be positioned at the intersection of row lines 210 and column lines 215.

[0041] Memory die 200 can be arranged using a patchwork architecture. In a patchwork architecture, tiles with similarly configured components can be arranged in an array. A memory device constructed in this manner can be expanded or contracted by adding or reducing tiles. A tile can be a building block of memory die 200. The support circuitry (not shown) of the memory die can be positioned below the memory cell array in the tile. As used herein, a patchwork architecture can refer to a memory array that includes multiple memory modules. For example, a memory die with a patchwork architecture can include memory modules in a repeating pattern. In some examples, a memory module can include tiles and circuitry and memory cells positioned on and above the tiles.

[0042] In some examples of patchwork architectures, some memory cells located above a tile can be addressed and accessed using support circuitry (not shown) located on adjacent tiles. Consequently, at the boundaries of the memory cell array, some memory cells are not addressable or accessible. To address these inaccessibility issues, boundary tiles can be located beyond the boundaries of the memory cell array to ensure that the tile's memory cells are accessible.

[0043] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting an access line (e.g., one or more of row lines 210 or column lines 215), which can be referred to as an access operation. By biasing row lines 210 and column lines 215 (e.g., applying a voltage to row lines 210 or column lines 215), a single memory cell 205 can be accessed at their intersection. The intersection of row lines 210 and column lines 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of memory cell 205. An access line can be a conductive line coupled to a memory cell 205 and can be used to perform an access operation on the memory cell 205.

[0044] Access to the memory cells 205 may be controlled by a row decoder 220 or a column decoder 225. For example, the row decoder 220 may receive a row address from the local memory controller 245 and activate the row lines 210 based on the received row address. The column decoder 225 may receive a column address from the local memory controller 245 and activate the column lines 215 based on the received column address. In a patchwork architecture, the row decoder 220 and the column decoder 225 may be located on a tile below the memory array. However, the row decoder 220 or the column decoder 225, or both, may or may not be located on a tile located directly below the accessed memory cell.

[0045] Sensing component 230 is operable to detect the state of memory cell 205 (e.g., material state, resistance, threshold state) and determine the logic state of memory cell 205 based on the storage state. Sensing component 230 may include one or more sense amplifiers to amplify or otherwise convert the signal resulting from accessing memory cell 205. Sensing component 230 may compare the signal detected from memory cell 205 with a reference 235 (e.g., a reference voltage). The detected logic state of memory cell 205 may be provided as an output of sensing component 230 (e.g., to input / output 240) and may indicate the detected logic state to another component of the memory device including memory die 200. In a patchwork architecture, sensing component 230 may be located on a tile below the memory array. However, sensing component 230 may or may not be located on a tile located directly below the accessed memory cell.

[0046] The local memory controller 245 can control access to the memory cell 205 through various components (such as the row decoder 220, the column decoder 225, and the sensing component 230). The local memory controller 245 can be a reference Figure 11. An example of a local memory controller 165 is described. In some examples, one or more of the row decoder 220, the column decoder 225, and the sense component 230 can be co-located with the local memory controller 245. The local memory controller 245 can be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the commands or data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 245 can generate row signals and column address signals to activate the target row lines 210 and the target column lines 215. The local memory controller 245 can also generate and control various voltages or currents used during operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may vary and may differ for the various operations discussed in operating the memory die 200 .

[0047] The local memory controller 245 is operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, the access operations may be performed or otherwise coordinated by the local memory controller 245 in response to various access commands (e.g., from the host device 105). The local memory controller 245 is operable to perform other access operations not listed here or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0048] Figure 3 An example of a memory array 300 according to the examples disclosed herein is illustrated. The memory array 300 may be a reference Figure 1 and 2 3. An example of a portion of a memory array or memory die is depicted in FIG. Memory array 300 can include a first level 305 of memory cells positioned above a substrate layer 315 and a second level 310 of memory cells atop the first array or level 305. Although the example of memory array 300 includes two levels 305, 310, memory array 300 can include any number of levels (e.g., one or more than two) positioned above substrate layer 315. Memory array 300 can be included as part of a patchwork architecture such that memory cells of a portion of the memory array are positioned above substrate layer 315, which can include support components for accessing the memory cells, such as, for example, decoders and amplifiers.

[0049] The memory cells of the memory array 300 may include a storage element, an electrode, and / or a select element. In some examples, a single component may serve as both a storage element and a select element. Figure 3 In the example shown in FIG, one or more memory cells of the first level 305 may include one or more of an electrode 325-a, a storage element 320-a, or an electrode 325-b. One or more memory cells of the second level 310 may include an electrode 325-c, a storage element 320-b, and an electrode 325-d. In some cases, the storage element 320 may be an example of a chalcogenide material, such as a phase change memory element, a threshold memory element, or a self-select memory element. Although included in Figure 3 Some elements in the drawings are labeled with numerical indicators, while other corresponding elements are not labeled, but are the same or should be understood to be similar, in an effort to improve visibility and clarity of the depicted features.

[0050] The memory array 300 may also include row lines 210 (eg, row lines 210-a, 210-b, 210-c, and 210-d) and column lines 215 (eg, column lines 215-a and 215-b), which may be reference lines. Figure 2 3. An example of row lines 210 and column lines 215 is depicted. One or more memory cells in the first level 305 and the second level 310 may include one or more chalcogenide materials in the pillars between the access lines. For example, a single stack between the access lines may include one or more of a first electrode, a first chalcogenide material (e.g., a selector element), a second electrode, a second chalcogenide material (e.g., a storage element), or a third electrode.

[0051] In some examples, the memory cells of the first level 305 and the second level 310 may have a common conductive line such that corresponding memory cells of one or more levels 305 and one or more levels 310 may share a column line 215 or a row line 210. For example, an electrode 325-c of the second level 310 and an electrode 325-b of the first level 305 may be coupled with a column line 215-a such that the column line 215-a may be shared by vertically adjacent memory cells.

[0052] In some examples, the common conductive lines can be coupled to support components used to access the memory cells. For example, in a patchwork architecture, the electrodes of a layer can correspond to horizontally extending row lines 210 and column lines 215. The electrodes can be coupled to corresponding drivers and decoders on a tile of substrate layer 315 via vertical connectors (not shown) extending downward through the layer.

[0053] In some examples, the material of the memory element 320 may include a chalcogenide material or other alloy including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some examples, a chalcogenide material primarily composed of selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG alloy. In some examples, a SAG alloy may also include silicon (Si), and such a chalcogenide material may be referred to as a SiSAG alloy. In some examples, a SAG alloy may include silicon (Si) or indium (In), or a combination thereof, and such a chalcogenide material may be referred to as a SiSAG alloy or an InSAG alloy, respectively, or a combination thereof. In some examples, the chalcogenide glass may include additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form.

[0054] In some examples, the storage element 320 may be an example of a phase change memory cell. In such examples, the material used in the storage element 320 may be based on an alloy (such as the alloys listed above) and may be operated so as to undergo a phase change, or change to a different physical state, during normal operation of the memory cell. For example, a phase change memory cell may have an amorphous state (such as a relatively disordered atomic configuration) and a crystalline state (such as a relatively ordered atomic configuration) that can be used to indicate the logical state of the memory cell.

[0055] In some examples, the architecture of memory array 300 may be referred to as a cross-point architecture, in which memory cells are formed at the topological intersections between row lines 210 and column lines 215. This cross-point architecture may provide relatively high-density data storage at a lower production cost than other memory architectures. For example, a cross-point architecture may have memory cells with reduced areas and, therefore, have an increased memory cell density over other architectures. For example, a cross-point architecture may have a memory cell area of ​​4F2, where F is the minimum feature size, compared to other architectures (e.g., architectures with three-terminal selector elements) having a memory cell area of ​​6F2. For example, a DRAM may use a transistor (which is a three-terminal device) as a selector element for each memory cell and may have a larger memory cell area than a cross-point architecture.

[0056] Although Figure 3 The example shows two memory levels, but other configurations are possible. In some examples, a single memory level of memory cells can be constructed above the substrate, which can be referred to as a two-dimensional memory. In some examples, additional memory levels can be constructed above the two memory levels to form a 3D vertical structure with similar alternating row and column lines. In some examples, two or more levels of memory cells can be configured in a similar manner into a three-dimensional cross-point architecture. Furthermore, in some cases, Figure 3 Display or reference Figure 3 The elements described may be electrically coupled to each other as shown or described but physically rearranged (e.g., memory element 320 and possibly select element or electrode 325 may be electrically connected in series between row line 210 and column line 215, but need not be in a pillar or stacked configuration). In some examples, the layers or levels may be arranged vertically. That is, each memory level may extend vertically and may be separated horizontally from each other.

[0057] A memory die may include a substrate layer and memory cells positioned above the substrate layer. The memory cells may be partitioned into memory clusters, each having a memory cell array that can be decoded as a single group of memory cells. Each memory cluster may include support circuitry for the memory cell array, such as, for example, a driver, a decoder, and a sense amplifier. Each memory cluster may include tiles formed on a portion of the substrate layer and a portion of the memory cell array formed above each tile. The support circuitry may be positioned within the tiles.

[0058] Figure 4A and 4B Examples of memory modules 400 - a and 400 - b supporting edgeless memory clustering according to examples disclosed herein are illustrated. Figure 4A and 4B is an example of an architecture in which electrode drivers are distributed across the footprint of an active memory module. The memory module may implement reference Figures 1 to 3 For example, memory modules 400 - a and 400 - b may be part of memory array 170 .

[0059] A memory array may include a memory cell array positioned above a group of tiles. Each tile and the portion of the memory cell array positioned above the tile (which may extend beyond the boundaries of the tile) may be considered a memory module. (In Figure 4A and 4B In the example, the memory cells of the memory module have been removed for clarity. ) The memory module can be used as part of a patchwork architecture. In a patchwork architecture, multiple tiles with a common component (e.g., driver) configuration can be arranged in an array. Figure 5 Discussed in more detail, the tiles may be arranged in a repeating pattern.

[0060] According to one example, Figure 4A The memory module 400-a illustrated in FIG may include a tile 405 formed on a substrate. The tile 405 may include support components for accessing the memory cells of the memory array, such as, for example, a driver. The tile may be partitioned into multiple sub-arrays, which may be referred to as "tiles." The tiles may together define a larger repeating unit of the tile. Figure 4AIn the example of FIG, four tiles 410 (e.g., tiles 410-a, 410-b, 410-c, and 410-d) correspond to tile 405. In other examples, a tile may include other numbers of tiles, such as, for example, 2, 4, 8, 12, 16, or 32 tiles.

[0061] One or more drivers may be positioned generally within the footprint of each block, under the memory cells, and near or at the periphery of the block. For example, one or more word line drivers 415 and / or one or more bit line drivers 420 may be positioned on each block 410. It should be understood that each shaded area may include a driver region that may include multiple driver circuits and, therefore, may represent a group of drivers. Figure 4A The row driver represented by the word line driver 415 in FIG. 1 may be elongated in the column or y direction and may be elongated in the column or y direction. Figure 4A The column drivers, represented by bit line drivers 420 in FIG. 4 , may be elongated in the row or x-direction. Signal paths traversing a path in the x- or y-direction may alternate through row and column driver regions.

[0062] Access lines (e.g., conductors or electrodes) may be included on each level for accessing memory cells. For example, word line electrodes 425 and bit line electrodes 430 may be coupled to memory cells located above block 410. Word line electrodes 425 may extend in one direction (e.g., the x-direction) and bit line electrodes 430 may extend in a different direction (e.g., the y-direction).

[0063] The drivers can be electrically coupled to access lines (e.g., access line electrodes). For example, word line driver 415 and bit line driver 420 can be electrically coupled to word line electrode 425 and bit line electrode 430, respectively. Because the drivers can be positioned along the periphery of the block, the drivers can be coupled to the word line electrodes and bit line electrodes through interconnect regions 435, which can extend upward from the block boundary. Interconnect regions 435 can be referred to as socket regions. The memory cell array directly above interconnect regions 435 can have a break to allow vertical connectors to pass through interconnect regions 435 between the drivers and the electrodes.

[0064] The connection between the driver and the electrode can be referred to as a socket connection. The connection point (also referred to as a socket) between each access line electrode 425, 430 and its driver 415, 420 can be indicated by a dot along the electrode. The connection point (socket) can be located anywhere along the corresponding electrode. In some examples, the connection point (socket) can be located at the end of the electrode. In some examples, the connection point (socket) can be between the two ends of the electrode (e.g., at the center of the electrode). The word line electrode and the bit line electrode can cross the boundaries between adjacent blocks and can also cross the boundaries of other driver areas. In some examples, the word line electrode 425 and the bit line electrode 430 can extend laterally beyond the outer boundaries (e.g., the footprint) of the tile 405.

[0065] In some examples, the access line electrodes can be staggered or shifted. For example, adjacent word line electrodes 425 can be shifted relative to each other along their elongated axes (x-axis) and adjacent bit line electrodes 430 can be shifted relative to each other along their elongated axes (y-axis). By dividing the word line and bit line driver groups and interconnect areas into smaller blocks and staggering the access line electrodes or access line electrode groups in alternating rows, as Figure 4A 4 , word line electrodes 425 and bit line electrodes 430 can extend through the memory array and through the interconnect region 435. Thus, both the interconnect region and the driver locations are not limited to the edge of the memory array.

[0066] According to one example, Figure 4B The memory module 400-b illustrated in FIG. 4 may include a tile 450 formed on a substrate. Like the tile 405, the tile 450 may be divided into a plurality of blocks 410 having word line drivers 415 and bit line drivers 420. Figure 4B In the example of , tile 450 includes 16 tiles 410 in a 4x4 arrangement. The tiles 410 can be arranged in a repeating pattern.

[0067] To access memory cells located above tile 450, word line electrodes 425 (eg, word line electrodes 425-a through 425-g) and bit line electrodes 430 (eg, bit line electrodes 430-a through 430-g) may be used. Figure 4B The word line electrodes 425-a to 425-g and the bit line electrodes 430-a to 430-g can be considered as being coupled to the memory cells of the memory module 400-b to address each memory cell of the tile 450. Figure 4A , the word line driver 415 and the bit line driver 420 may be electrically coupled to the word line electrode 425 and the bit line electrode 430, respectively, via socket connections through the interconnection region to connection points (sockets) represented by dots in the figure.

[0068] Furthermore, many of the electrodes are configured to address and access memory cells corresponding to one of tiles 455 as well as tile 450. For example, word line electrodes 425-b, 425-d, and 425-g are illustrated as extending over tiles 450 and 455-a to access memory cells of both tiles. Thus, word line electrodes 425-b, 425-d, and 425-g can be considered to be coupled to one or more memory cells of a memory tile different from the memory tile that includes the drivers for addressing each memory cell of tiles 450 and 455.

[0069] Tile 450 can be configured to couple with adjacent tiles 455 (e.g., tiles 455-a, 455-b, 455-c, and 455-d) to address and access memory cells of a memory array. Note that only a portion of each tile 455 is shown. In some examples, circuitry (e.g., decoders and amplifiers) located on adjacent tiles 455 can be configured to address and access memory cells located above tile 450. For example, to address and access memory cells located above tile 450, word line electrodes 425-d and 425-f can be coupled to word line drivers 415 on adjacent tiles 455-a and 455-c, respectively; and bit line electrodes 430-b and 430-d can be coupled to bit line drivers 420 on adjacent tiles 455-b and 455-d, respectively. In this manner, tile 450 may not be configured to operate as a fully independent unit. Rather, tile 450 may rely on the circuitry of neighboring tile 455 to provide full functionality to tile 450. Remove any of the neighboring tiles 455 and one or more of the memory cells above tile 450 are inaccessible.

[0070] If a tile of a cluster is positioned on an edge of the cluster, no adjacent tile extends beyond the edge to provide array termination functionality (e.g., to access memory cells using drivers thereon). Consequently, one or more memory cells positioned above an edge tile are inaccessible to the cluster. For example, if tile 450 is positioned on the right edge of the first cluster, the cluster may not include adjacent tile 455-a. Consequently, memory cells positioned above tile 450 and normally accessed by word line electrode 425-d of tile 455-a are inaccessible to the first cluster. As another example, if tile 450 is positioned on the bottom edge of the cluster, the cluster may not include adjacent tile 455-b. Consequently, memory cells positioned above tile 450 and normally accessed by bit line electrode 430-b of tile 455-b are inaccessible to the first cluster. However, in some instances, if the adjacent tile 455-a or 455-b is an edge tile of a second cluster adjacent to the first cluster, then the tile can be used to address and access memory cells from outside the first cluster (e.g., through the second cluster).

[0071] Figure 5 A simplified floor plan diagram illustrating a memory die 500 supporting edgeless memory clusters according to examples disclosed herein. Figure 5 An example of using one or more tiles of an adjacent cluster to access memory cells of a cluster is described. Memory die 500 may implement reference Figure 1 4. For example, the memory die 500 may be a reference Figure 1 and 2 An example of a memory die 160 or 200 is discussed.

[0072] Memory die 500 may include memory partitioned into a memory array corresponding to a plurality of clusters 505, such as clusters 505-a, 505-b, 505-c, and 505-d. Each cluster 505 may include a plurality of tiles 510 in a repeating pattern. For example, cluster 505-a may include tiles 510-a, 510-b, and 510-c; cluster 505-b may include tiles 510-d and 510-e; cluster 505-c may include tiles 510-f and 510-g; and cluster 505-d may include tile 510-h. Tiles 510 may include electrodes, such as, for example, word line electrodes 525 and bit line electrodes 530. (For clarity, Figure 5 Only a few electrodes are shown above). Block 510 can be used as a reference Figure 4B The example of the block 450 discussed. The word line electrode 525 and the bit line electrode 530 can be referenced Figure 4B Examples of word line electrodes 425 and bit line electrodes 430 are discussed.

[0073] As reference Figure 4B As discussed, one or more memory cells positioned above an edge tile of a cluster may be inaccessible to the cluster due to the lack of an adjacent tile that would normally provide array termination functionality (e.g., accessing the memory cells using drivers thereon). In some instances, array termination functionality for these memory cells may be provided by another cluster. This may allow access to the memory cells from outside the cluster (e.g., through other clusters). In some instances, memory cells of a first cluster may be accessed using drivers on an edge tile of a second cluster adjacent to the first cluster. For example, edge tiles 510-d and 510-e of cluster 505-b may include word line drivers 515 (on the left) that provide access to memory cells positioned above edge tiles 510-a and 510-b adjacent to cluster 505-a via word line electrodes 525. Figure 5 ), and the edge tiles 510-f and 510-g of the cluster 505-c may include a bit line driver 520 (in the embodiment of the embodiment of the present invention) that provides access to memory cells located above the edge tiles 510-a and 510-c of the adjacent cluster 505-a via a bit line electrode 530. Figure 5 (highlighted in FIG. ). Thus, clusters 505-b and 505-c can provide array termination functionality for cluster 505-a. Each overlapping electrode can be considered coupled to memory cells of more than one memory cluster. That is, each overlapping electrode can be considered an electrode of both memory clusters it overlaps.

[0074] Although not shown, it should be understood that array termination functionality can be provided in two ways. That is, adjacent clusters can provide array termination functionality for each other. For example, edge tiles 510-a, 510-b, and 510-c of cluster 505-a can similarly provide access to memory cells of tiles 510-d, 510-e, 510-f, and 510-g of clusters 505-b and 505-c (e.g., in opposite directions).

[0075] In this way, memory cells of a cluster that are not accessible by a cluster can be accessed using tiles from an adjacent adjacent cluster. Thus, gaps between clusters are eliminated without losing memory functionality. This can achieve a substantial reduction in die size.

[0076] In some examples, an edge tile of a cluster can access memory cells of an adjacent cluster in a similar manner as a tile accesses memory cells located above an adjacent tile in its own cluster (e.g., the tile can use similar drivers connected to similar electrodes in a similar manner via similar socket connections). For example, a tile can use the same drivers (e.g., wordline driver 515 and bitline driver 520) and electrodes (e.g., wordline electrode 525 and bitline electrode 530) to access an adjacent cluster that it uses in its own cluster. This can reduce stress on the electrodes by reducing density variations in the electrode layers.

[0077] In some examples, a driver can operate both its own cluster and an adjacent cluster using the same electrodes. That is, a driver can provide access to the memory cells of its own cluster and provide array termination functionality for an adjacent cluster via the same electrodes. In some examples, a driver can be operable to access memory cells within its own cluster when its own cluster is active and can be operable to provide array termination (e.g., access to memory cells within an adjacent cluster) for an adjacent cluster when its own cluster is inactive. The driver can have different parameters when used to provide array termination functionality than during normal operation. In some examples, circuitry (e.g., a multiplexer) can be coupled to the driver to control the driver (e.g., select which input signal to use) depending on which cluster the driver is used for at any given time.

[0078] In some examples, a first driver circuit can be configured to enable a driver to access one or more memory cells of its own cluster via an electrode, e.g., when the memory cluster is active. A second driver circuit can be configured to enable a driver to access one or more memory cells of an adjacent memory cluster via the same electrode, e.g., when the adjacent memory cluster is active.

[0079] A tile may include multiple drivers, some of which may be used to provide array termination functionality for adjacent clusters. The multiple drivers may be divided into: a first portion, which may include drivers not used to provide termination functionality; and a second portion, which may include drivers used to provide array termination functionality. In some examples, the first and second portions of the tile may be active (e.g., available) to access the memory cells of the cluster when the cluster is active. The second portion of the tile may be active (e.g., available) to provide array termination (e.g., access to memory cells within the adjacent cluster) for the adjacent cluster when the cluster is inactive.

[0080] In some examples, a tile of a first cluster can be divided into a first and a second portion. The first portion of the tile can include, for example, a first portion of a driver, and the second portion of the tile can include, for example, a second portion of a driver. After deciding to access memory cells of an adjacent second cluster, the first portion of the tile can be inhibited (e.g., the first portion of the driver can be disabled) and the second portion of the tile can be enabled to access memory cells of the second cluster. When the first portion is inhibited, the tile can serve as a terminating tile for the second cluster, and the second portion of the driver can be enabled. In some cases, the second portion of the driver can each be coupled to memory cells of both the first and second clusters via the same respective electrodes. In such cases, the driver can be activated to access memory cells of the second cluster via the respective electrodes without accessing memory cells of the first cluster.

[0081] In some examples, an adjacent second cluster may include similar tiles as the first cluster and may provide array termination functionality to the first cluster in a similar manner. In this way, each cluster may provide array termination functionality (e.g., accessing memory cells using the drives thereon) to the other clusters.

[0082] In some examples, adjacent clusters can be activated during mutually exclusive periods. That is, while a cluster may be in active mode, clusters adjacent to it may be inactive. For example, while cluster 505-a may be active, clusters 505-b and 505-c may be inactive. Cluster 505-d may be active or inactive because it is not located near active cluster 505-a. When either cluster 505-b or 505-c (or both) are active, cluster 505-a will be inactive. Cluster 505-d will be inactive because it is adjacent to clusters 505-b and 505-c, at least one of which is active.

[0083] Activating adjacent clusters during mutually exclusive periods can isolate active clusters from each other so that tiles within an inactive cluster can provide array termination functionality for the active cluster. For example, edge tiles of an inactive cluster can be configured to behave as termination tiles for edge tiles of an active cluster.

[0084] In some examples, clusters may be assigned to different groups (domains) whose clusters are not adjacent to each other and the domains may be active at different, mutually exclusive times.

[0085] Figure 6A and 6B Simplified floor plan diagram illustrating memory dies 600-a and 600-b supporting edgeless memory clusters according to examples disclosed herein. The die may implement reference Figures 1 to 5 For example, the die denoted as 600-a and 600-b may be referenced to Figure 1 and 2 Examples of dies 160 or 200 are discussed. Figure 6A and 6B Each illustrates multiple contiguous clusters of dies 605. The clusters 605 can be assigned to different groups (domains) based on their location with respect to each other.

[0086] Figure 6A A two-domain system is illustrated in which each cluster 605 can be assigned to either a first domain (designated "A") or a second domain (designated "B"). The assignment can be made so that clusters that are adjacent to each other are in different domains. That is, clusters in domain A may not be adjacent to other clusters in domain A and clusters in domain B may not be adjacent to other clusters in domain B. By assigning clusters in this manner, clusters in one of the domains (e.g., domain A) can be in active mode (e.g., the domain can be active) and clusters in the other domain (e.g., domain B) can be inactive (e.g., the domain can be inactive), while array termination functionality can be provided for the active cluster. As long as the domains are active at mutually exclusive times (e.g., not active at the same time), the active clusters can be isolated from each other, regardless of which domain is active.

[0087] Figure 6B A four-domain system is illustrated in which each cluster 605 can be assigned to one of four domains (labeled "A," "B," "C," and "D"). Figure 6A , the assignment can be made so that clusters that are adjacent to each other are in different domains. Thus, the clusters of one of the domains (e.g., domain A) can be in active mode at the same time and the clusters of the other domains (e.g., domains B, C, and D) can be inactive, but array termination functionality can be provided for the active cluster. As long as the domains are active at mutually exclusive times (e.g., one active at a time), the active clusters can be isolated from each other, regardless of which domain is active. In some examples, the assignment can be made so that when more than one domain is active, the active clusters can be isolated from each other. For example, Figure 6B Domains A and C can be active concurrently because none of their clusters are adjacent to each other. Similarly, domains B and D can be active concurrently because none of their clusters are adjacent to each other.

[0088] Figure 7A block diagram 700 is shown of a memory device 720 supporting edgeless memory clusters according to examples disclosed herein. The memory device 720 may be a reference Figure 1 6. Memory device 720 or its various components may be examples of means for performing various aspects of the edgeless memory cluster described herein. For example, memory device 720 may include a determination component 725, a suppression manager 730, a driver manager 735, an activation manager 740, or any combination thereof. Each of these components may communicate with each other, directly or indirectly (e.g., via one or more buses).

[0089] The determination component 725 may be configured to or otherwise support means for determining access to a first memory array of a first memory cluster, the first memory cluster comprising a first plurality of tiles including a first plurality of drivers coupled to the first memory array. The inhibition manager 730 may be configured to or otherwise support means for inhibiting a first portion of tiles from a second plurality of tiles of a second memory cluster in response to determining access to the first memory array of the first memory cluster based at least in part on determining access to the first memory array, the second memory cluster comprising a second memory array, the second plurality of tiles comprising a second plurality of drivers coupled to the second memory array, drivers in the second plurality of drivers being coupled to the first memory array and positioned on a second portion of the tiles. The driver manager 735 may be configured to or otherwise support means for enabling drivers on the second portion of the tiles of the second memory cluster to access the first memory array of the first memory cluster based at least in part on determining access to the first memory array.

[0090] In some examples, the second portion of the tile can serve as a termination tile for the first memory cluster when the first portion of the tile is inhibited.

[0091] In some examples, activation manager 740 may be configured to or otherwise support means for deactivating the second storage cluster before enabling drivers on the second portion of the tiles of the second storage cluster.

[0092] In some examples, a driver may be coupled with one or more memory cells of the first memory array and one or more memory cells of the second memory array via the same electrode.

[0093] In some examples, to support enabling drivers on a second portion of tiles of a second memory cluster, activation manager 740 may be configured to or otherwise support means for activating the drivers to access one or more memory cells of the first memory array via the electrodes without accessing one or more memory cells of the second memory array.

[0094] In some examples, to support throttling a first portion of tiles in the second plurality of tiles, driver manager 735 may be configured or otherwise support means for disabling one or more drivers of the first portion of tiles.

[0095] In some examples, the determination component 725 may be configured to or otherwise support means for determining access to a second memory array of the second memory cluster. In some examples, the inhibition manager 730 may be configured to or otherwise support means for inhibiting a first portion of a second tile of the first plurality of tiles of the first memory cluster in response to determining access to the second memory array of the second memory cluster, a second driver of the first plurality of drivers further coupled to the second memory array and positioned on a second portion of the second tile. In some examples, the driver manager 735 may be configured to or otherwise support means for enabling a second driver on a second portion of the second tile of the first memory cluster to access the second memory array of the second memory cluster.

[0096] Figure 8 A flowchart illustrating a method 800 for supporting edgeless memory clusters according to examples disclosed herein is shown. The operations of the method 800 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 800 may be implemented by reference to Figures 1 to 7 The memory device described herein performs the functions described herein. In some examples, the memory device may execute a set of instructions to control the functional elements of the device to perform the functions described herein. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the functions described herein.

[0097] At 805, the method may include determining to access a first memory array of a first memory cluster, the first memory cluster including a first plurality of tiles including a first plurality of drivers coupled to the first memory array. Operation 805 may be performed according to examples disclosed herein. In some examples, aspects of operation 805 may be described with reference to Figure 7 The described determination component 725 performs.

[0098] At 810, the method may include inhibiting a first portion of a tile in a second plurality of tiles of a second memory cluster in response to determining access to a first memory array of a first memory cluster based at least in part on determining access to the first memory array, the second memory cluster including a second memory array, the second plurality of tiles including a second plurality of drivers coupled to the second memory array, drivers in the second plurality of drivers coupled to the first memory array and positioned on a second portion of the tile. Operation 810 may be performed according to examples disclosed herein. In some examples, aspects of operation 810 may be implemented by reference to Figure 7 The described suppression manager 730 performs.

[0099] At 815, the method may include enabling a driver on a second portion of the tiles of the second memory cluster to access the first memory array of the first memory cluster based at least in part on determining to access the first memory array. Operation 815 may be performed according to examples disclosed herein. In some examples, aspects of operation 815 may be described with reference to Figure 7 The driver manager 735 described here performs the following operations.

[0100] In some examples, an apparatus described herein may perform one or more methods, such as method 800. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: determining to access a first memory array of a first memory cluster, the first memory cluster including a first plurality of tiles including a first plurality of drivers coupled to the first memory array; inhibiting a first portion of a tile in a second plurality of tiles of a second memory cluster, the second memory cluster including a second memory array, the second plurality of tiles including a second plurality of drivers coupled to the second memory array, drivers in the second plurality of drivers being coupled to the first memory array and positioned on a second portion of the tile, based at least in part on the determination to access the first memory array, in response to determining to access the first memory array of the first memory cluster; and enabling the drivers on the second portion of the tile of the second memory cluster to access the first memory array of the first memory cluster based at least in part on the determination to access the first memory array.

[0101] In some examples of the method 800 and apparatus described herein, the second portion of the tile can serve as a termination tile for the first memory cluster when the first portion of the tile can be suppressed.

[0102] Some examples of the method 800 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for: deactivating the second memory cluster before enabling the drivers on the second portion of the tile of the second memory cluster.

[0103] In some examples of the method 800 and apparatus described herein, the driver can be coupled with one or more memory cells of the first memory array and one or more memory cells of the second memory array via the same electrode.

[0104] In some examples of the method 800 and apparatus described herein, enabling the driver on the second portion of the tile of the second memory cluster may include operations, features, circuitry, logic, means, or instructions for activating the driver to access the one or more memory cells of the first memory array via the electrode and not access the one or more memory cells of the second memory array.

[0105] In some examples of the method 800 and apparatus described herein, inhibiting the first portion of the tiles in the second plurality may include operations, features, circuitry, logic, means, or instructions for disabling one or more drivers of the first portion of the tiles.

[0106] Some examples of the method 800 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: determining to access the second memory array of the second memory cluster; inhibiting a first portion of a second tile of the first plurality of tiles of the first memory cluster in response to determining to access the second memory array of the second memory cluster, a second driver of the first plurality of drivers being further coupled to the second memory array and positioned on a second portion of the second tile; and enabling the second driver on the second portion of the second tile of the first memory cluster to access the second memory array of the second memory cluster.

[0107] It should be noted that the methods described herein describe possible implementations, and that the operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0108] An apparatus is described. The apparatus may include a set of memory clusters, each memory cluster in the set of memory clusters including: a plurality of tiles having a driver; a memory array positioned above the plurality of tiles and having a plurality of memory cells; and a plurality of electrodes coupled to the plurality of memory cells for addressing each of the plurality of memory cells, wherein the driver of a first tile of a first memory cluster in the set of memory clusters is coupled to an electrode of the plurality of electrodes of a second tile of a second memory cluster in the set of memory clusters, and wherein the first memory cluster and the second memory cluster are configured to operate in an active mode during mutually exclusive periods.

[0109] In some instances of the device, the set of memory clusters may include a first subset of memory clusters that are non-adjacent to one another and a second subset of memory clusters that are non-adjacent to one another, the second subset not including the memory clusters of the first subset, wherein the device may be configured such that when the memory clusters of the first subset operate in the active mode, the memory clusters of the second subset operate in the inactive mode.

[0110] In some examples of the apparatus, the first subset of memory clusters includes the first memory cluster and the second subset of memory clusters includes the second memory cluster.

[0111] In some examples of the apparatus, the set of memory clusters further includes a third subset of memory clusters that are non-contiguous with one another, the third subset excluding the memory clusters of the first and second subsets.

[0112] In some examples of the apparatus, the first memory cluster is contiguous to the second memory cluster.

[0113] In some examples of the apparatus, each memory cluster of the set is adjacent to another memory cluster of the set.

[0114] In some examples of the apparatus, the apparatus may be configured such that memory clusters of the group that are adjacent to each other do not operate in the active mode simultaneously.

[0115] In some examples of the apparatus, for each memory cluster of the set, tiles in the plurality of tiles may have a common driver configuration and may be positioned in a repeating pattern.

[0116] In some examples of the apparatus, for each memory cluster of the set, the electrode of the plurality of electrodes may be coupled with the driver via a respective socket connection.

[0117] In some examples of the apparatus, one or more electrodes of the plurality of electrodes of the first memory cluster may also be in the plurality of electrodes of the second memory cluster.

[0118] In some examples of the apparatus, one or more electrodes may each be included in the plurality of electrodes of more than one memory cluster of the set.

[0119] Another apparatus is described. The apparatus may be a memory cluster. The memory cluster may include: a plurality of tiles having a driver; a memory array positioned above the plurality of tiles and having a plurality of memory cells; and a plurality of electrodes coupled to the driver via respective socket connections, the plurality of electrodes coupled to the plurality of memory cells for addressing each of the plurality of memory cells, wherein a tile in the plurality of tiles includes a first portion of the driver and a second portion of the driver, the second portion of the driver being configured for accessing memory cells of an adjacent memory cluster when the memory cluster is inactive.

[0120] In some instances of the apparatus, each driver of the second portion of the drivers includes a first driver circuit configured to enable the driver to access one or more memory cells of the plurality of memory cells via an electrode of the plurality of electrodes and a second driver circuit configured to enable the driver to access one or more memory cells of the adjacent memory cluster via the electrode of the plurality of electrodes.

[0121] In some examples of the apparatus, the first portion of the driver may be configured for accessing one or more memory cells of the memory cluster when the adjacent memory cluster may be inactive.

[0122] In some examples of the apparatus, tiles in the plurality of tiles can have a common driver configuration and can be positioned in a repeating pattern.

[0123] Another apparatus is described. The apparatus may include: a first memory cluster comprising: a first memory array having a first plurality of memory cells; a first driver coupled to a subset of the first plurality of memory cells; and a first driver circuit configured to enable the first driver when the first memory cluster is active; and a second memory cluster comprising: a second memory array having a second plurality of memory cells, wherein the first driver is coupled to at least one memory cell of the second plurality of memory cells; and a second driver coupled to a subset of the second plurality of memory cells, wherein the first driver circuit is further configured to enable the first driver when the second memory cluster is active and the first memory cluster is inactive.

[0124] In some examples of the apparatus, the first memory cluster is contiguous to the second memory cluster.

[0125] In some examples, the apparatus may include electrodes coupling the first driver with the subset of the first plurality of memory cells and coupling the second driver with the subset of the second plurality of memory cells.

[0126] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0127] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are said to be in electronic communication (or in conductive contact or connected or coupled) with each other if any conductive path exists between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact or connected or coupled) with each other may be open or closed based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components (such as switches, transistors, or other components). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (such as switches or transistors).

[0128] The term "coupling" refers to the condition of changing from an open-circuit relationship between components (where signals cannot currently communicate between the components via conductive paths) to a closed-circuit relationship between the components (where signals can communicate between the components via conductive paths). When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously prevented signal flow.

[0129] The term "isolation" refers to a relationship between components where signals are no longer able to flow between them. Components are isolated from one another if an open circuit exists between them. For example, when a switch positioned between two components is open, the components separated by the switch are isolated from one another. When a controller isolates two components, it causes a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0130] As used herein, the term "layer" or "step" refers to a layer or sheet of a geometric structure (e.g., relative to a substrate). Each layer or step can have three dimensions (e.g., height, width, and depth) and can cover at least a portion of a surface. For example, a layer or step can be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. A layer or step can include different elements, components, and / or materials. In some examples, a layer or step can be composed of two or more sub-layers or sub-steps.

[0131] As used herein, the term "substantially" means that the modified property (such as a verb or adjective modified by the term "substantially") need not be absolute but comes close enough to achieving the advantage of the property.

[0132] As used herein, the term "electrode" may refer to an electrical conductor and, in some examples, may serve as an electrical contact for a memory cell or other component of a memory array. An electrode may include a trace, a wire, a conductive line, a conductive layer, or the like that provides a conductive path between elements or components of a memory array.

[0133] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some cases, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or a subregion of the substrate, can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation during the initial formation or growth of the substrate, or by any other doping method.

[0134] The switch components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via conductive materials (e.g., metals). The source and drain can be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor can be "switched on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor gate, the transistor can be "off" or "deactivated."

[0135] The description set forth herein, in conjunction with the accompanying drawings, describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," rather than "preferred" or "advantageous over other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0136] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0137] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0138] For example, the various descriptive blocks and modules described in connection with the disclosure herein may be implemented or executed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0139] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0140] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Moreover, any connection is appropriately referred to as computer-readable media. For example, if coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is used to transmit software from a website, server or other remote source, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

[0141] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications of the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: A set of memory clusters, each memory cluster in the set of memory clusters comprising: a plurality of tiles having a driver; a memory array positioned over the plurality of tiles and having a plurality of memory cells, wherein memory cells of a first memory cluster in the set of memory clusters are positioned over a first plurality of tiles, and wherein memory cells of a second memory cluster in the set of memory clusters are positioned over a second plurality of tiles different from the plurality of tiles; and a plurality of electrodes coupled to the plurality of memory cells for addressing each of the plurality of memory cells, wherein a driver of a first tile of the first plurality of tiles is coupled to an electrode of the plurality of electrodes of the second plurality of tiles and is configured to access the memory cells of the second memory cluster located above the second plurality of tiles via the electrode based on the memory cells of the second memory cluster being configured to operate in an active mode, and wherein the memory cells of the first memory cluster positioned over the first plurality of tiles are configured to operate in an inactive mode while the memory cells of the second memory cluster positioned over the second plurality of tiles operate in an active mode.

2. The apparatus of claim 1 , wherein the set of memory clusters comprises: a first subset of memory clusters that are non-contiguous to each other; and A second subset of memory clusters that are non-contiguous to each other, the second subset excluding the memory clusters of the first subset, wherein the apparatus is configured such that when the memory clusters of the first subset operate in an active mode, the memory clusters of the second subset operate in an inactive mode. 3 . The apparatus of claim 2 , wherein the first subset of memory clusters includes the first memory cluster and the second subset of memory clusters includes the second memory cluster.

4. The apparatus of claim 2, wherein the set of memory clusters further comprises: A third subset of memory clusters that are non-contiguous, the third subset excluding the memory clusters of the first and second subsets.

5. The apparatus of claim 1, wherein the first memory cluster is contiguous to the second memory cluster.

6. The apparatus of claim 1, wherein each memory cluster of the set is adjacent to another memory cluster of the set. 7 . The apparatus of claim 1 , wherein the apparatus is configured such that memory clusters of the group that are adjacent to each other do not operate in active mode at the same time.

8. The apparatus of claim 1, wherein for each memory cluster of the set, tiles in the plurality of tiles have a common driver configuration and are positioned in a repeating pattern.

9. The apparatus of claim 1, wherein for each memory cluster of the set, an electrode of the plurality of electrodes is coupled with the driver via a respective socket connection.

10. The apparatus of claim 1, wherein one or more electrodes of the plurality of electrodes of the first memory cluster are also in the plurality of electrodes of the second memory cluster.

11. The apparatus of claim 1, wherein one or more electrodes are each included in the plurality of electrodes of more than one memory cluster of the set.

12. A first storage cluster, comprising: a first plurality of tiles having a driver; a memory array comprising a first plurality of memory cells positioned over the first plurality of tiles; and a plurality of electrodes coupled to the driver via respective socket connections, the plurality of electrodes coupled to the first plurality of memory cells for addressing each memory cell of the first plurality of memory cells positioned over the first plurality of tiles, wherein a tile of the first plurality of tiles comprises a first portion of the driver and a second portion of the driver, the second portion of the driver being configured to access the memory cells of the adjacent second memory cluster positioned above a second plurality of tiles different from the first plurality of tiles based on the memory cells of the adjacent second memory cluster being configured to operate in an active mode and the memory cells of the first plurality of memory cells positioned above the first plurality of tiles simultaneously operating in an inactive mode.

13. The first storage cluster of claim 12, wherein each driver of the second portion of drivers comprises: a first driver circuit configured to enable the driver to access one or more memory cells of the first plurality of memory cells via an electrode of the plurality of electrodes; and A second driver circuit is configured to enable the driver to access one or more memory cells of the adjacent second memory cluster via the electrode of the plurality of electrodes.

14. The first memory cluster of claim 12, wherein the first portion of the driver is configured for use in accessing one or more memory cells of the first memory cluster when the adjacent second memory cluster is inactive.

15. The first memory cluster of claim 12, wherein tiles in the first plurality of tiles have a common driver configuration and are positioned in a repeating pattern.

16. An apparatus comprising: A first storage cluster comprising: a first memory array having a first plurality of memory cells; a first driver coupled to a subset of the first plurality of memory cells, the first plurality of memory cells being positioned over the first driver; and a first driver circuit configured to enable the first driver while memory cells of the first plurality of memory cells are active; and A second storage cluster comprising: a second memory array having a second plurality of memory cells, wherein the first driver is coupled to at least one memory cell of the second plurality of memory cells; and a second driver coupled to a subset of the second plurality of memory cells positioned above the second driver that is different from the first driver, wherein the first driver circuit is further configured to enable the first driver to access memory cells of the second plurality of memory cells positioned above the first driver based on the memory cells of the second plurality of memory cells being configured to operate in an active mode and the memory cells of the first plurality of memory cells positioned above the second driver being simultaneously operated in an inactive mode.

17. The apparatus of claim 16, wherein the first memory cluster is contiguous to the second memory cluster.

18. The apparatus of claim 16, further comprising: An electrode couples the first driver with the subset of the first plurality of memory cells and the second driver with the subset of the second plurality of memory cells.

19. A method comprising: determining access to a memory cell of a first memory array of a first memory cluster, the first memory cluster comprising a first plurality of tiles including a first plurality of drivers coupled to the first memory array, the memory cell of the first memory array of the first memory cluster being positioned above the first plurality of tiles; inhibiting a first portion of a tile in a second plurality of tiles of a second memory cluster in response to determining to access the memory cells of the first memory array of the first memory cluster based at least in part on determining to access the first memory array, the second memory cluster comprising a second memory array including a second plurality of memory cells positioned over a second plurality of tiles different from the first plurality of tiles, the second plurality of tiles comprising a second plurality of drivers coupled to the second memory array, wherein drivers of the second plurality of drivers positioned over a second portion of the tile are coupled to the memory cells of the first memory array positioned over the first plurality of tiles; and Based at least in part on determining to access the first memory array, the driver on the second portion of the tile of the second memory cluster is enabled to access the memory cells of the first memory array of the first memory cluster based on the memory cells of the first memory array being configured to operate in an active mode and the memory cells of the second plurality of memory cells positioned above the tile of the second memory cluster being simultaneously operated in an inactive mode.

20. The method of claim 19, wherein the second portion of the shard serves as a terminated shard for the first memory cluster when the first portion of the shard is inhibited.

21. The method of claim 19, further comprising: Prior to enabling the drivers on the second portion of the tiles of the second storage cluster, the second storage cluster is deactivated.

22. The method of claim 19, wherein the driver is coupled with one or more memory cells of the first memory array and one or more memory cells of the second memory array via the same electrode.

23. The method of claim 22, wherein enabling the driver on the second portion of the tiles of the second storage cluster comprises: Activating the driver accesses the one or more memory cells of the first memory array via the electrode and does not access the one or more memory cells of the second memory array.

24. The method of claim 22, wherein suppressing the first portion of the tiles in the second plurality of tiles comprises: One or more drivers of the first portion of the tile are disabled.

25. The method of claim 19, further comprising: determining access to the second memory array of the second memory cluster; inhibiting a first portion of a second tile of the first plurality of tiles of the first memory cluster in response to determining to access the second memory array of the second memory cluster, a second driver of the first plurality of drivers further coupled to the second memory array and positioned over a second portion of the second tile; and The second driver on the second portion of the second tile of the first memory cluster is enabled to access the second memory array of the second memory cluster.

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