A self-biased LDO circuit applied to a radio frequency communication chip

Abstract

The application relates to the technical field of integrated circuits, in particular to a self-bias LDO circuit applied to a radio frequency communication chip. The self-bias LDO circuit comprises a core circuit module, a self-bias circuit module and an input selection circuit module. The core circuit module is used for generating an output voltage in fixed proportion to an input voltage; the self-bias circuit module is used for generating a reference voltage and a bias current irrelevant to a power supply voltage and providing the operation amplifier with the input voltage and the bias current; and the input selection circuit module is used for selecting the input voltage and the bias current for the operation amplifier. The core circuit module comprises an operation amplifier OP and resistors R1-R2; the positive input end of the operation amplifier OP is connected with the source end of an NMOS tube MN1 and the source end of an NMOS tube MN2; the negative input end is connected with the ground through the resistor R2 and connected with the output end VO through the resistor R1; and the output end VO is connected with the power supply end of the self-bias circuit module. The self-bias LDO circuit is used to solve the problem of the near-end phase noise deterioration of a phase-locked loop caused by the low-frequency noise of the power supply end.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a self-biased LDO circuit for use in radio frequency communication chips. Background Technology

[0002] Phase noise is critical in RF integrated circuits. Noise from the power supply and amplifiers, bias circuits, voltage-controlled oscillators (VCOs), environmental factors, and temperature all significantly impact phase noise. In this context, low-frequency noise in the power input can severely affect the phase noise near the PLL. Therefore, low-noise low-frequency (LDO) circuits are typically used to power high-performance RF chips, maintaining a relatively low phase noise level.

[0003] Therefore, a self-biased LDO circuit for use in radio frequency communication chips is proposed to solve the problem of near-end phase noise degradation of the phase-locked loop caused by low-frequency noise at the power supply. Summary of the Invention

[0004] The purpose of this invention is to provide a self-biased LDO circuit for use in radio frequency communication chips, so as to solve the problem of near-end phase noise degradation of the phase-locked loop caused by low-frequency noise at the power supply end.

[0005] To address the aforementioned technical problems, this invention provides a self-biased LDO circuit for use in radio frequency communication chips, comprising:

[0006] The core circuit module is used to generate an output voltage that is in a fixed proportion to the input voltage;

[0007] The self-biasing circuit module is used to generate a reference voltage and bias current independent of the supply voltage, and to provide input voltage and bias current to the operational amplifier.

[0008] The input selection circuit module is used to select the input voltage and bias current for the operational amplifier.

[0009] Preferably, the core circuit module includes an operational amplifier OP and resistors R1 to R2; the positive input terminal of the operational amplifier OP is connected to the source terminals of NMOS transistors MN1 and MN2, and the negative input terminal is connected to ground through resistor R2 and to the output terminal VO through resistor R1, respectively. The output terminal VO is connected to the power supply terminal of the self-biased circuit module.

[0010] Preferably, the self-biased circuit module includes PMOS transistors MP3 to MP9, NMOS transistors MN3 to MN9, resistors R4 to R6, and inverter INV;

[0011] The source terminals of PMOS transistors MP3 and MP4 are both connected to power supply VO; the drain terminal of PMOS transistor MP3 is simultaneously connected to the drain terminal of NMOS transistor MN3 and the input terminal of inverter INV, and the gate terminal of PMOS transistor MP3 is connected to the enable port EN; the drain terminal of PMOS transistor MP4 is simultaneously connected to the gate terminals of NMOS transistors MN3, MN4, MP6, and MN6, and the gate terminal of PMOS transistor MP4 is connected to the output terminal of inverter INV;

[0012] The source terminals of PMOS transistors MP5, MP6, and MP7 are all connected to power supply VO; the drain and gate terminals of PMOS transistors MP5, MP6, and MP7 are all connected to the drain terminal of NMOS transistor MN4; the drain terminal of PMOS transistor MP7 is simultaneously connected to the drain terminal of NMOS transistor MN7, the gate terminal of NMOS transistor MN7, and the gate terminal of NMOS transistor MN8.

[0013] The source terminals of PMOS transistor MP8 and PMOS transistor MP9 are both connected to power supply VO; the drain and gate terminals of PMOS transistor MP8 and the gate terminal of PMOS transistor MP9 are connected to the drain terminal of NMOS transistor MN8; the drain terminal of PMOS transistor MP9 is connected to the output current port Ibias2.

[0014] The source terminal of NMOS transistor MN3 is connected to the drain terminal of NMOS transistor MN5; the source terminal of NMOS transistor MN4 is grounded through resistor R4; the source terminal of NMOS transistor MN5 is grounded, and its gate terminal is connected to both the source terminal of NMOS transistor MN4 and the gate terminal of NMOS transistor MN6; the source terminal of NMOS transistor MN6 is grounded.

[0015] The source terminal of NMOS transistor MN7 is connected to the drain terminal of NMOS transistor MN9; the source terminal of NMOS transistor MN8 is connected to the output voltage port VREF2; the source terminal of NMOS transistor MN9 is grounded, and its gate terminal is grounded through resistor R6 and connected to the output voltage port VREF2 through resistor R5.

[0016] Preferably, the input selection circuit module includes PMOS transistors MP1 to MP2, NMOS transistors MN1 to MN2, and resistor R3;

[0017] The source terminal of the PMOS transistor MP1 is connected to the input voltage port VREF1, and the gate terminal is connected to the enable port EN1; the source terminal of the PMOS transistor MP2 is connected to the output current port Ibias2 of the self-biasing circuit module, the gate terminal is connected to the enable port EN2, and the drain terminal is connected to both the bias current port Ibias and the drain terminal of the PMOS transistor MP1 through resistor R3.

[0018] The drain of NMOS transistor MN1 is connected to the input voltage port VREF1, and the gate is connected to the enable port EN1; the drain of NMOS transistor MN2 is connected to the output voltage port VREF2 of the self-biased circuit module, and the gate is connected to the enable port EN2.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The self-biased LDO circuit in this invention reduces the noise impact caused by external input voltage and external bias current, achieving low-noise performance of the LDO and solving the problem of near-end phase noise degradation of the PLL caused by low-frequency noise at the power supply. First, the input signal EN1 is high (EN2 is low), at which point NMOS transistor MN1 is turned on, the positive input voltage of operational amplifier OP is VREF1, PMOS transistor MP1 is turned on, and current Ibias1 flows into operational amplifier OP through the Ibias branch; operational amplifier OP operates, generating output voltage VO, which provides the power supply voltage for the self-biased circuit. Second, the input signal EN of the self-biased circuit is low, at which point MP3 branch is turned on, the input voltage of inverter INV is VO, MP4 is turned on, and current flows through the drain of PMOS transistor MP4 into the drain of NMOS transistor MN6, turning on NMOS transistor MN4. Thus, the self-biased circuit escapes the "degenerate" bias point, generating output voltage VREF2 and output current Ibias2. Finally, when the input signal EN2 is high (EN1 is low), NMOS transistor MN2 is turned on, the voltage at the positive input terminal of operational amplifier OP is VREF2, PMOS transistor MP2 is turned on, and current Ibias2 flows into operational amplifier OP through the Ibias branch; operational amplifier OP operates, generating output voltage VO, which provides the power supply voltage for the self-biasing circuit. Therefore, this invention reduces the noise impact caused by external input voltage and external bias current, achieving low-noise performance of the LDO. Attached Figure Description

[0021] Figure 1 This is a connection diagram of a self-biased LDO circuit applied to a radio frequency communication chip according to the present invention.

[0022] Figure 2 The connection diagram is for the self-biased circuit module provided by the present invention. Detailed Implementation

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0024] like Figures 1-2 As shown, this embodiment of the invention specifically provides a self-biased LDO circuit applied to a radio frequency communication chip, comprising:

[0025] The core circuit module is used to generate an output voltage that is in a fixed proportion to the input voltage;

[0026] The self-biasing circuit module is used to generate a reference voltage and bias current independent of the supply voltage, and to provide input voltage and bias current to the operational amplifier.

[0027] The input selection circuit module is used to select the input voltage and bias current for the operational amplifier.

[0028] The core circuit module includes an operational amplifier OP and resistors R1 to R2. The positive input terminal of the operational amplifier OP is connected to the source terminals of NMOS transistors MN1 and MN2, and the negative input terminal is connected to ground through resistor R2 and to the output terminal VO through resistor R1. The output terminal VO is connected to the power supply terminal of the self-biased circuit module.

[0029] The self-biased circuit module includes PMOS transistors MP3 to MP9, NMOS transistors MN3 to MN9, resistors R4 to R6, and inverter INV;

[0030] The source terminals of PMOS transistors MP3 and MP4 are both connected to power supply VO; the drain terminal of PMOS transistor MP3 is simultaneously connected to the drain terminal of NMOS transistor MN3 and the input terminal of inverter INV, and the gate terminal of PMOS transistor MP3 is connected to the enable port EN; the drain terminal of PMOS transistor MP4 is simultaneously connected to the gate terminals of NMOS transistors MN3, MN4, MP6, and MN6, and the gate terminal of PMOS transistor MP4 is connected to the output terminal of inverter INV;

[0031] The source terminals of PMOS transistors MP5, MP6, and MP7 are all connected to power supply VO; the drain and gate terminals of PMOS transistors MP5, MP6, and MP7 are all connected to the drain terminal of NMOS transistor MN4; the drain terminal of PMOS transistor MP7 is simultaneously connected to the drain terminal of NMOS transistor MN7, the gate terminal of NMOS transistor MN7, and the gate terminal of NMOS transistor MN8.

[0032] The source terminals of PMOS transistor MP8 and PMOS transistor MP9 are both connected to power supply VO; the drain and gate terminals of PMOS transistor MP8 and the gate terminal of PMOS transistor MP9 are connected to the drain terminal of NMOS transistor MN8; the drain terminal of PMOS transistor MP9 is connected to the output current port Ibias2.

[0033] The source terminal of NMOS transistor MN3 is connected to the drain terminal of NMOS transistor MN5; the source terminal of NMOS transistor MN4 is grounded through resistor R4; the source terminal of NMOS transistor MN5 is grounded, and its gate terminal is connected to both the source terminal of NMOS transistor MN4 and the gate terminal of NMOS transistor MN6; the source terminal of NMOS transistor MN6 is grounded.

[0034] The source terminal of NMOS transistor MN7 is connected to the drain terminal of NMOS transistor MN9; the source terminal of NMOS transistor MN8 is connected to the output voltage port VREF2; the source terminal of NMOS transistor MN9 is grounded, and its gate terminal is grounded through resistor R6 and connected to the output voltage port VREF2 through resistor R5.

[0035] The input selection circuit module includes PMOS transistors MP1 to MP2, NMOS transistors MN1 to MN2, and resistor R3;

[0036] The source terminal of the PMOS transistor MP1 is connected to the input voltage port VREF1, and the gate terminal is connected to the enable port EN1; the source terminal of the PMOS transistor MP2 is connected to the output current port Ibias2 of the self-biasing circuit module, the gate terminal is connected to the enable port EN2, and the drain terminal is connected to both the bias current port Ibias and the drain terminal of the PMOS transistor MP1 through resistor R3.

[0037] The drain of NMOS transistor MN1 is connected to the input voltage port VREF1, and the gate is connected to the enable port EN1; the drain of NMOS transistor MN2 is connected to the output voltage port VREF2 of the self-biased circuit module, and the gate is connected to the enable port EN2.

[0038] The working principle is as follows: First, the input signal EN1 is high (EN2 is low). At this time, the NMOS transistor MN1 is turned on, the voltage at the positive input terminal of the operational amplifier OP is VREF1, the PMOS transistor MP1 is turned on, and the current Ibias1 flows into the operational amplifier OP through the Ibias branch. The operational amplifier OP works and generates the output voltage VO. The output voltage VO provides the power supply voltage for the self-biasing circuit.

[0039] Secondly, the self-biasing circuit works normally: when the input signal EN is low, the MP3 branch is open, the input voltage of the inverter INV is VO, MP4 is turned on, and the current flows through the drain of the PMOS transistor MP4 into the drain of the NMOS transistor MN6, and the NMOS transistor MN4 is turned on. Thus, the self-biasing circuit gets rid of the "degenerate" bias point and generates the output voltage VREF2 and the output current Ibias2.

[0040] Finally, when the input signal EN2 is high (EN1 is low), NMOS transistor MN2 is turned on, the voltage at the positive input terminal of operational amplifier OP is VREF2, PMOS transistor MP2 is turned on, and current Ibias2 flows into operational amplifier OP through the Ibias branch; operational amplifier OP works and generates output voltage VO, which provides power supply voltage for the self-biasing circuit.

[0041] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A self-biased LDO circuit for use in radio frequency communication chips, characterized in that, include: The core circuit module is used to generate an output voltage that is in a fixed proportion to the input voltage; The self-biasing circuit module is used to generate a reference voltage and bias current independent of the supply voltage, and to provide input voltage and bias current to the operational amplifier. The input selection circuit module is used to select the input voltage and bias current for the operational amplifier; The self-biased circuit module includes PMOS transistors MP3~MP9, NMOS transistors MN3~MN9, resistors R4~R6, and inverter INV; The source terminals of PMOS transistors MP3 and MP4 are both connected to power supply VO; the drain terminal of PMOS transistor MP3 is simultaneously connected to the drain terminal of NMOS transistor MN3 and the input terminal of inverter INV, and the gate terminal of PMOS transistor MP3 is connected to the enable port EN; the drain terminal of PMOS transistor MP4 is simultaneously connected to the gate terminals of NMOS transistors MN3, MN4, MP6, and MN6, and the gate terminal of PMOS transistor MP4 is connected to the output terminal of inverter INV; The source terminals of PMOS transistors MP5, MP6, and MP7 are all connected to power supply VO; the drain and gate terminals of PMOS transistors MP5, MP6, and MP7 are all connected to the drain terminal of NMOS transistor MN4; the drain terminal of PMOS transistor MP7 is simultaneously connected to the drain terminal of NMOS transistor MN7, the gate terminal of NMOS transistor MN7, and the gate terminal of NMOS transistor MN8. The source terminals of PMOS transistor MP8 and PMOS transistor MP9 are both connected to power supply VO; the drain and gate terminals of PMOS transistor MP8 and the gate terminal of PMOS transistor MP9 are connected to the drain terminal of NMOS transistor MN8; the drain terminal of PMOS transistor MP9 is connected to the output current port Ibias2. The source terminal of NMOS transistor MN3 is connected to the drain terminal of NMOS transistor MN5; the source terminal of NMOS transistor MN4 is grounded through resistor R4; the source terminal of NMOS transistor MN5 is grounded, and its gate terminal is connected to both the source terminal of NMOS transistor MN4 and the gate terminal of NMOS transistor MN6; the source terminal of NMOS transistor MN6 is grounded. The source terminal of NMOS transistor MN7 is connected to the drain terminal of NMOS transistor MN9; the source terminal of NMOS transistor MN8 is connected to the output voltage port VREF2; the source terminal of NMOS transistor MN9 is grounded, and its gate terminal is grounded through resistor R6 and connected to the output voltage port VREF2 through resistor R5.

2. The self-biased LDO circuit for use in radio frequency communication chips as described in claim 1, characterized in that, The core circuit module includes an operational amplifier OP and resistors R1~R2. The positive input terminal of the operational amplifier OP is connected to the source terminals of NMOS transistors MN1 and MN2 in the input selection circuit module. The negative input terminal is grounded through resistor R2 and connected to the output terminal VO through resistor R1. The output terminal VO is connected to the power supply terminal of the self-biasing circuit module. The drain terminal of NMOS transistor MN1 is connected to the input voltage port VREF1, and the gate terminal is connected to the enable port EN1. The drain terminal of NMOS transistor MN2 is connected to the output voltage port VREF2 of the self-biasing circuit module, and the gate terminal is connected to the enable port EN2.

3. The self-biased LDO circuit for use in radio frequency communication chips as described in claim 2, characterized in that, The input selection circuit module includes PMOS transistors MP1~MP2, NMOS transistors MN1~MN2 and resistor R3; The source terminal of the PMOS transistor MP1 is connected to the input voltage port VREF1, and the gate terminal is connected to the enable port EN1; the source terminal of the PMOS transistor MP2 is connected to the output current port Ibias2 of the self-biasing circuit module, the gate terminal is connected to the enable port EN2, and the drain terminal is connected to both the bias current port Ibias and the drain terminal of the PMOS transistor MP1 through resistor R3.

4. The self-biased LDO circuit for use in radio frequency communication chips as described in claim 3, characterized in that, It also includes the following working principles: First, the input signals EN1 are high and EN2 are low. At this time, NMOS transistor MN1 is turned on, the voltage at the positive input terminal of operational amplifier OP is VREF1, PMOS transistor MP1 is turned on, and current Ibias1 flows into operational amplifier OP through the Ibias branch. Operational amplifier OP works and generates output voltage VO. Output voltage VO provides power supply voltage for self-biasing circuit. Secondly, when the input signal EN of the self-biasing circuit module is low, the PMOS transistor MP3 branch is open, the input voltage of the inverter INV is VO, the PMOS transistor MP4 is turned on, and the current flows through the drain of the PMOS transistor MP4 into the drain of the NMOS transistor MN6, turning on the NMOS transistor MN4. Thus, the self-biasing circuit module gets rid of the "degenerate" bias point and generates the output voltage VREF2 and the output current Ibias2. Finally, when the input signal EN2 is high and EN1 is low, the NMOS transistor MN2 is turned on, the voltage at the positive input terminal of the operational amplifier OP is VREF2, the PMOS transistor MP2 is turned on, and the current Ibias2 flows into the operational amplifier OP through the Ibias branch; the operational amplifier OP works and generates the output voltage VO, which provides the power supply voltage for the self-biasing circuit.

Images