Debug methods, electronic devices, and media for chip FPGA prototype verification

Abstract

The present invention relates to the field of chip verification technology, and in particular to a debugging method, electronic device, and medium for chip FPGA prototype verification. The method comprises: step S1, obtaining simulation verification code for a chip to be verified; step S2, generating an FPGA prototype verification system; step S3, configuring the initial state of the FPGA prototype verification system, sending stimulus data to an input port of the FPGA prototype verification system, performing chip FPGA prototype verification, and transferring the stimulus data, clock data, and status data received by the input port to a storage module; step S4, when the FPGA prototype verification system runs to a target trigger point, obtaining target debug data from the storage module; and step S5, injecting the target debug data back into the RTL simulation model according to timing for debugging. The present invention improves the efficiency and accuracy of debugging for chip FPGA prototype verification.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and in particular to a debugging method, electronic equipment and medium for chip FPGA prototype verification. Background Art

[0002] With the continuous development of chip verification technology, the demand for more comprehensive verification of chip hardware logic in FPGA prototype systems is increasing. This inevitably requires debugging methods to be able to effectively address problems in various complex scenarios. FPGA prototype systems can only directly obtain data from input ports and cannot obtain the changes in internal signals. Traditional debugging methods, when applied to FPGA prototype verification systems, usually only provide limited information and are only applicable to problems in simple scenarios. However, when the chip hardware logic becomes more complex, the problems that arise are difficult to reproduce, or there are some physical characteristics after board installation, traditional debugging methods are difficult to quickly discover the problems and cannot accurately locate them. Therefore, how to provide a method that can solve some of the complex problems that arise during hardware logic verification on FPGA prototype systems, achieve more accurate and rapid problem location, and improve the efficiency and accuracy of debugging for chip FPGA prototype verification has become a technical problem that needs to be solved urgently. Summary of the Invention

[0003] The present invention aims to provide a debugging method, electronic equipment and medium for chip FPGA prototype verification, thereby improving the debugging efficiency and accuracy of chip FPGA prototype verification.

[0004] According to a first aspect of the present invention, a debugging method for chip FPGA prototype verification is provided, comprising:

[0005] Step S1, performing simulation verification on the chip to be verified based on an RTL simulation model, wherein the RTL simulation model is constructed based on the original RTL code of the chip to be verified, and updating the original RTL code of the chip to be verified according to the simulation verification result of the RTL simulation model to generate a simulation verification code for the chip to be verified;

[0006] Step S2: generating a gate-level netlist of the chip to be verified based on the simulation verification code of the chip to be verified, burning the gate-level netlist of the chip to be verified into the FPGA, and generating an FPGA prototype verification system;

[0007] Step S3, configuring the initial state of the FPGA prototype verification system, sending stimulus data to the input port of the FPGA prototype verification system, performing chip FPGA prototype verification in the FPGA prototype verification system, and transferring the stimulus data received by the input port, clock data corresponding to the stimulus data, and state data of the FPGA prototype verification system to a storage module;

[0008] Step S4: After the FPGA prototype verification system runs to a target trigger point, target debug data is obtained from the storage module, where the target debug data includes stimulus data within a target range, clock data corresponding to the stimulus data, and status data of the FPGA prototype verification system;

[0009] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, a computer-readable storage medium is provided, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0011] The present invention has significant advantages and beneficial effects compared to the prior art. Through the above-mentioned technical solution, the debug method, electronic device, and medium for chip FPGA prototype verification provided by the present invention can achieve considerable technological advancement and practicality, and has wide industrial application value, and has at least the following beneficial effects:

[0012] The present invention simulates and verifies a chip to be verified based on an RTL simulation model to obtain simulation verification code of the chip to be verified, builds an FPGA prototype verification system based on the simulation verification code of the chip to be verified, and then, during the chip FPGA prototype verification process performed by the FPGA prototype verification system, transfers stimulus data received by an input port, clock data corresponding to the stimulus data, and status data of the FPGA prototype verification system to a storage module, obtains target debug data from the storage module, and then feeds the target debug data back into the RTL simulation model, thereby implementing debugging of the chip FPGA prototype verification and improving the debugging efficiency and accuracy of the chip FPGA prototype verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 This is a flowchart of the debugging method for chip FPGA prototype verification provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0016] The embodiment of the present invention provides a debugging method for chip FPGA (Field-Programmable Gate Array) prototype verification, such as Figure 1 As shown, the following steps are included:

[0017] Step S1, simulate and verify the chip to be verified based on the original Register Transfer Level (RTL) simulation model, wherein the RTL simulation model is constructed based on the original RTL code of the chip to be verified, and the original RTL code of the chip to be verified is updated according to the simulation verification result of the RTL simulation model to generate the simulation verification code of the chip to be verified.

[0018] Specifically, the chip to be verified may be simulated and verified using a Universal Verification Methodology (UVM) method or a software simulation method, which will not be described in detail here.

[0019] Step S2: Generate a gate-level netlist of the chip to be verified based on the simulation verification code of the chip to be verified, burn the gate-level netlist of the chip to be verified into the FPGA, and generate an FPGA prototype verification system.

[0020] It is understandable that FPGA stands for Field Programmable Gate Array.

[0021] Step S3, configuring the initial state of the FPGA prototype verification system, sending stimulus data to the input port of the FPGA prototype verification system, performing chip FPGA prototype verification in the FPGA prototype verification system, and transferring the stimulus data received by the input port, the clock data corresponding to the stimulus data, and the status data of the FPGA prototype verification system to a storage module.

[0022] It should be noted that the input ports are grouped according to clocks. The stimulus data received by the transferred input ports can be all the stimulus data of the input ports, or the input stimulus data corresponding to Y clocks selected from the input ports can be used as the data to be transferred, and the size of the data to be transferred is X.

[0023] Step S4: After the FPGA prototype verification system runs to the target trigger point, target debug data is obtained from the storage module, where the target debug data includes stimulus data within a target range, clock data corresponding to the stimulus data, and status data of the FPGA prototype verification system.

[0024] Step S5: inject the target debug data back into the RTL simulation model according to the timing for debugging.

[0025] It should be noted that the signals in the FPGA prototype verification system cannot be directly read, while the signals in the RTL simulation model can be directly read. The FPGA prototype verification system is based on hardware implementation. The embodiment of the present invention adopts a combination of software and hardware technology to collect relevant data by setting trigger conditions in the FPGA prototype system verification. When the trigger conditions are met, the field data is saved and the data is fed back into the RTL simulation model to achieve a one-to-one restoration of the scene in the FPGA prototype system. By comparing the results, problems in the chip FPGA prototype verification can be quickly and accurately located.

[0026] During the FPGA prototype verification process, the state of the FPGA prototype verification system may remain unchanged in the initial state, or may change with the input of stimulus data. The storage module includes a first storage area and a second storage area. In step S3, the stimulus data received by the input port, the clock data corresponding to the stimulus data, and the state data of the FPGA prototype verification system are transferred to the storage module, including:

[0027] Step S31: take the excitation data received by the input port and the clock data corresponding to the excitation data as the data to be stored, and store the data to be stored in the first storage area in sequence. When the first storage area is full, return to the starting position of the first storage area to store the data to be stored in sequence in a circular covering manner.

[0028] Specifically, taking the FPGA prototype verification system input port as an example, the input stimulus data corresponding to Y clocks is selected from the input port as the data to be transferred, and the size of the data to be transferred is X, the first storage area includes N storage units (B1, B2, ..., B n ,…,B N ), B n The nth storage unit, n ranges from 1 to N, B n The size is greater than (X+Y); the software control module controls the data to be transferred corresponding to the selected Y clocks in the input port of the FPGA prototype verification module and the selected Y clock data as the data to be stored, according to B1, B2, ..., B n ,…,B N The data to be stored is stored in the first storage area in the order of n When storing the data to be stored in B, first determine n Is the current remaining storage space greater than or equal to (X+Y), if so, store the data to be stored in B n Otherwise, the data to be stored is stored in B n+1 When stored in B N And B N When the storage space in is less than (X+Y), the data to be stored is stored in B1. n When storing data in B n If there is data stored in B, it will be overwritten. n Store data in .

[0029] It should be noted that the first storage area is a part of the storage area in the storage module, that is, it is only a part of the storage module. The present invention stores the input excitation data and corresponding clock data of the input port of the FPGA prototype verification system in the first storage area in a circular overwriting manner. The input excitation data and corresponding clock data of the input port of the FPGA prototype verification system occupy the most storage space of the first storage area, rather than the space of the entire storage module, saving the input excitation data and corresponding clock data of the input port of the FPGA prototype verification system from occupying the storage space. In addition, data will continue to be stored in the space of the first storage area only when no abnormality is found. Therefore, the data covered in the first storage area are all non-target debug data. By means of circular overwriting, the first storage area always stores data close to the current moment for a period of time.

[0030] Step S32: storing the state data of the FPGA prototype verification system into the second storage area, and establishing a mapping relationship between the state data and the stimulus data of the FPGA prototype verification system.

[0031] As an embodiment, if the chip to be verified is a chip whose state remains unchanged, the initial state information is stored in the second storage area.

[0032] As an embodiment, if the chip to be verified is a state-variable chip, all state data appearing during the FPGA prototype verification process are recorded in the second storage area, and a mapping relationship between the state data and stimulus data of the FPGA prototype verification system is established. When a state data in the second storage area is completely overwritten by the data stored in the first storage area, the state data and the corresponding mapping relationship information are deleted from the second storage area.

[0033] As an embodiment, N storage units may also be provided in the second storage area, and the N storage units (B1, B2, ..., B n ,…,B N ) correspond one to one, each storage unit corresponds to the state data of the FPGA prototype verification system in which the stimulus data stored in a storage unit in the first storage area is stored.

[0034] It should be noted that bugs that generally appear on FPGA prototype verification systems only appear in more complex scenarios. Therefore, the embodiment of the present invention first implements a complex trigger mechanism, which takes the form of a finite state machine and implements the specific state machine through hardware. After being configured through software, the trigger mechanism can work effectively and achieve the purpose of catching complex bugs. As an embodiment, the FPGA prototype verification system also includes a trigger configuration table and a data processing module provided on the FPGA board, and the step S4 includes:

[0035] Step S401: The data processing module reads intermediate state data from a preset interface of the FPGA prototype system in real time, and determines a target trigger point based on the output data and a trigger configuration table.

[0036] As an embodiment, the trigger configuration table includes M pieces of trigger configuration information {A1, A2, ..., A m ,…,A M}, A m The mth trigger configuration information, m ranges from 1 to M, A m =(A1 m ,A2 m ,A3 m ), A1 m A m The trigger bit identification information, A2 m A mTrigger constraint information, A3 m A m Trigger execution instruction; A3 m Including jump to A j , determine the current moment as the target trigger point; the value range of j is 1 to M, A j ≠A m , set A1 as the initial target A m By setting each A m , can be applied to various complex application scenarios, each A1 in the trigger configuration table m 、A2 m and A3 m All A3 m The corresponding jump information can determine the corresponding process, and the trigger configuration table can be specifically implemented through a finite state machine.

[0037] Specifically, the software control module can configure the initial state of the FPGA prototype verification module and input stimulus information to the input port of the FPGA prototype verification module. It should be noted that the software control module also configures the initial state of the FPGA prototype verification module through the input port of the FPGA prototype verification module.

[0038] The FPGA prototype verification system starts running from the initial state, and performs FPGA prototype verification on the chip to be verified based on the stimulus information received at the input port. The data processing module reads the intermediate state data from the preset interface of the FPGA prototype system in real time. When the intermediate state data read by the module appears the current target A m Corresponding target A1 m When the intermediate state data read subsequently is determined to be consistent with the current target A m Corresponding target A2 m , when meeting target A2 m When the current target A m Corresponding target A3 m To determine the current moment as the target trigger point instruction, the current trigger point is determined as the target trigger point, otherwise, the target A3 m Corresponding A j Update to target A m , continue to read intermediate state data from the preset interface of the FPGA prototype system for judgment until the target trigger point is determined. It should be noted that the FPGA prototype system includes multiple interfaces, and users cannot directly read interface data. The data processing module set on the FPGA can read and combine it with the trigger configuration table to make judgments.

[0039] The number of bits of the preset interface of the FPGA prototype system is fixed, for example, 64 bits. Then the intermediate state data read from the preset interface of the FPGA prototype system is always 64 bits. The data processing module does not need to process all 64 bits of data every time, but may only process some bits of data. It can be flexibly set, thus further covering a variety of complex verification scenarios. As an embodiment, A1 m Including the first judgment bit A11 m and A11 m The corresponding first judgment value A12 m , A2 m Including the second judgment bit A21 m and A21 m Corresponding constraint A22 m The data processing module is used to read the intermediate state data from the preset interface of the FPGA prototype system in real time, and determine the current target A in the intermediate state data currently read. m Corresponding target A11 m Is the value of the current target A m Corresponding target A12 m If so, then determine the target A in the intermediate state data read subsequently m Corresponding target A21 m Whether the corresponding value meets target A m Corresponding target A22 m If it meets the requirements, then execute target A m Corresponding A3 m .

[0040] As an example, A22 m Including Target A21 m The corresponding value is greater than the preset constraint value A23 m Target A21 m The corresponding value is greater than or equal to the preset constraint value A23 m Target A21 m The corresponding value is less than the preset constraint value A23 m Target A21 m The corresponding value is less than or equal to the preset constraint value A23 m Target A21 m The corresponding value is equal to the preset constraint value A23 m The data processing module includes a comparator, which supports comparison operations of greater than, greater than or equal to, less than, less than or equal to, and equal to. m Target A21 m The corresponding value is greater than the preset constraint value A23 m Target A21 m The corresponding value is greater than or equal to the preset constraint value A23m Target A21 m The corresponding value is less than the preset constraint value A23 m Target A21 m The corresponding value is less than or equal to the preset constraint value A23 m Target A21 m The corresponding value is equal to the preset constraint value A23 m If any one of the following is true, the target A21 m Corresponding values and preset constraint values A23 m Input the comparator to determine the target A21 m Whether the corresponding value meets target A m Corresponding target A22 m The comparator will be based on the specific A22 m For input target A21 m Corresponding values and preset constraint values A23 m Compare to determine whether the target A22 is met m conclusion.

[0041] As an example, A22 m Including Target A21 m The corresponding value appears equal to the preset value A24 m The number of times reaches the preset value A25 m ; The data processing module is provided with a counter. If the target A22 m For the current target A m Corresponding target A11 m The value is equal to the current target A m Corresponding target A12 m , then enable the counter to start recording target A21 m The corresponding value appears equal to the preset value A24 m If the number of times reaches the preset value A25 m , then it is determined to meet the target A2 m .

[0042] As an example, A22 m Including entering target A m The time reaches the preset time length A26 m ; The data processing module includes a timer. If target A22 m To enter target A m The time reaches the preset time length A26 m , then start the timer, from the current target A m Corresponding target A11 m The value is equal to the current target A m Corresponding target A12m Start timing when the counted time reaches the preset time length A26 m , then it is determined to meet the target A2 m .

[0043] When the FPGA prototype verification system runs to the target trigger point, the software control module obtains the data stored in the first storage area as the target debug data based on the target trigger point. It should be noted that when obtaining the target debug data, only the amount of data corresponding to the first storage area needs to be processed, which greatly reduces the amount of data processing and improves the efficiency of obtaining the target debug data. The target trigger point is the point where debugging is required, and step S4 includes:

[0044] Step S41: After the FPGA prototype verification system runs to the target trigger point, the data to be stored is stored in the first storage area according to the preset storage ratio relative to the trigger point, and then the data in the first storage area is determined as the stimulated data within the target range and the clock data corresponding to the stimulated data.

[0045] After determining the target trigger point, you can obtain data in different ranges before and after the target trigger point according to different application requirements:

[0046] As an embodiment, when the FPGA prototype verification system runs to the target trigger point, the software control module sets the B corresponding to the target trigger point to n As an end point, no more data is stored in the first storage area, and the data currently in the first storage area is sorted according to the storage order to obtain the target debug data.

[0047] As an embodiment, when the FPGA prototype verification system runs to the target trigger point, the software control module sets the B corresponding to the target trigger point to n As a starting point, continue to obtain (N-1) data to be stored from the FPGA prototype verification system, store them in the first storage area in sequence, and then sort the data in the first storage area according to the storage order to obtain the target debug data.

[0048] As an embodiment, when the FPGA prototype verification system runs to the target trigger point, the software control module sets the B corresponding to the target trigger point to nAs a starting point, continue to obtain D×N / (C+D) data to be stored from the FPGA prototype verification system, store them in the first storage area in sequence, and then sort the data in the first storage area according to the storage order to obtain the target debug data, where C and D are proportion parameters. In the target debug data, the ratio of the target trigger point and the amount of data before the target trigger point to the amount of data after the target trigger point is C:D.

[0049] Step S42: Acquire, from the second storage area, the state data of the FPGA prototype verification system corresponding to the stimulus data within the target range.

[0050] As an embodiment, if the chip to be verified is a chip whose state remains unchanged, when the FPGA prototype verification system runs to the target trigger point, the software control module also determines the initial state information stored in the second storage area as the target debug data.

[0051] As an embodiment, if the chip to be verified is a state-variable chip, when the FPGA prototype verification system runs to the target trigger point, the software control module obtains the status information corresponding to each data determined as target debug data in the first storage area from the second storage area, and also determines the status information corresponding to each data determined as target debug data in the first storage area as target debug data.

[0052] As an embodiment, the target debug data includes (E1, E2, ..., E n ,…,E N ), E n For the nth group of target debug data, E n =(E1 n ,E2 n ,E3 n ), E1 n For E n Corresponding incentive data, E2 n E1 n Corresponding clock data, E3 n For E n The corresponding state data of the starting FPGA prototype verification system, E1, E2, ..., E n ,…,E N Sort by time. It should be noted that E1 n Includes multiple stimulus data arranged in execution order, E2 n Including multiple with E1 n The stimulus data in E3 corresponds to the clock data. nOnly one group E n The corresponding starting FPGA prototype verification system status data does not need to be stored E1 n The status data of the FPGA prototype verification system corresponding to each stimulus data.

[0053] The step S5 comprises:

[0054] Step S51: Set N RTL simulation models.

[0055] Step S52: Set the starting state of the nth RTL simulation model to E3 n .

[0056] Step S53, parallelize each E1 n Input the corresponding nth RTL simulation model for simulation, according to E1 n and E2 n The corresponding relationship is set to clock data, and the signal changes in each RTL simulation model are observed in real time to determine the target abnormal point.

[0057] Among them, the clock data corresponding to the excitation data is the clock frequency, so according to E1 n and E2 n Just set the clock frequency according to the corresponding relationship.

[0058] Through steps S51 to S53, on the premise that the state of the RTL simulation model is consistent with the state of the FPGA prototype verification system, the corresponding recorded data is sent to the RTL simulation model according to the timing of the FPGA prototype verification system, so that the data of the FPGA prototype verification system is reproduced on the RTL simulation model, and then the verification of the FPGA prototype verification system is realized based on the RTL simulation model.

[0059] It should be noted that if E1, E2, ..., E n ,…,E N It will be very slow. n The stimulus data, clock data and the status data of the corresponding starting FPGA prototype verification system have been included, so each set of target debug data can be reproduced independently in the RTL simulation model, and all E n , which can greatly improve the debugging efficiency of chip FPGA prototype verification.

[0060] As an embodiment, step S53 includes:

[0061] Step S531: parallelize each E1 nDuring the simulation process in the nth RTL simulation model corresponding to the input, if an abnormal point appears based on the nth RTL simulation model, the simulation operation of the (n+1)th RTL simulation model to the Nth RTL simulation model is terminated. After the simulation of the N RTL simulation models is completed, the abnormal point that appears first is determined as the target abnormal point.

[0062] It should be noted that the target abnormal point is at the front position, so when an abnormal point is found, the subsequent simulation process does not need to be paid attention to, so the simulation operation of the (n+1)th RTL simulation model to the Nth RTL simulation model is ended to save computing resources.

[0063] The embodiment of the present invention simulates and verifies a chip to be verified based on an RTL simulation model to obtain simulation verification code of the chip to be verified, builds an FPGA prototype verification system based on the simulation verification code of the chip to be verified, and then, during the chip FPGA prototype verification process performed by the FPGA prototype verification system, transfers stimulus data received by an input port, clock data corresponding to the stimulus data, and status data of the FPGA prototype verification system to a storage module, obtains target debug data from the storage module, and then feeds the target debug data back into the RTL simulation model, thereby implementing debugging of the chip FPGA prototype verification and improving the efficiency and accuracy of debugging of the chip FPGA prototype verification.

[0064] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0065] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0066] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0067] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A debug method for chip FPGA prototype verification, characterized in that: include: Step S1, performing simulation verification on the chip to be verified based on an RTL simulation model, wherein the RTL simulation model is constructed based on the original RTL code of the chip to be verified, and updating the original RTL code of the chip to be verified according to the simulation verification result of the RTL simulation model to generate a simulation verification code for the chip to be verified; Step S2: generating a gate-level netlist of the chip to be verified based on the simulation verification code of the chip to be verified, burning the gate-level netlist of the chip to be verified into the FPGA, and generating an FPGA prototype verification system; Step S3, configuring the initial state of the FPGA prototype verification system, sending stimulus data to the input port of the FPGA prototype verification system, performing chip FPGA prototype verification in the FPGA prototype verification system, and transferring the stimulus data received by the input port, clock data corresponding to the stimulus data, and state data of the FPGA prototype verification system to a storage module; Step S4: After the FPGA prototype verification system runs to a target trigger point, target debug data is obtained from the storage module, where the target debug data includes stimulus data within a target range, clock data corresponding to the stimulus data, and status data of the FPGA prototype verification system. The target trigger point is the point where debugging is required. Step S5: inject the target debug data back into the RTL simulation model according to the timing for debugging.

2. The method according to claim 1, characterized in that In step S1, the chip to be verified is simulated and verified using a UVM method or a software simulation method.

3. The method according to claim 1, characterized in that The storage module includes a first storage area and a second storage area. In step S3, the excitation data received by the input port, the clock data corresponding to the excitation data, and the status data of the FPGA prototype verification system are transferred to the storage module, including: Step S31: using the excitation data received by the input port and the clock data corresponding to the excitation data as data to be stored, and sequentially storing the data to be stored in the first storage area. When the first storage area is full, returning to the starting position of the first storage area to sequentially store the data to be stored in a cyclic overwriting manner; Step S32: storing the state data of the FPGA prototype verification system into the second storage area, and establishing a mapping relationship between the state data and the stimulus data of the FPGA prototype verification system.

4. The method according to claim 1, wherein The FPGA prototype verification system further includes a trigger configuration table and a data processing module provided on the FPGA board, and step S4 includes: Step S401: The data processing module reads intermediate state data from a preset interface of the FPGA prototype system in real time, and determines a target trigger point based on the intermediate state data and a trigger configuration table.

5. The method according to claim 3, characterized in that The step S4 comprises: Step S41: After the FPGA prototype verification system runs to a target trigger point, the data to be stored is stored in the first storage area according to a preset storage ratio relative to the trigger point, and the data in the first storage area is determined as excitation data within a target range and clock data corresponding to the excitation data; Step S42: Acquire, from the second storage area, the state data of the FPGA prototype verification system corresponding to the stimulus data within the target range.

6. The method according to claim 1, characterized in that The target debug data includes (E1, E2, ..., E n ,…,E N ), E n For the nth group of target debug data, E n =(E1 n ,E2 n ,E3 n ), E1 n For E n Corresponding incentive data, E2 n E1 n Corresponding clock data, E3 n For E n The corresponding state data of the starting FPGA prototype verification system, E1, E2, ..., E n ,…,E N According to the time sequence, step S5 includes: Step S51: Setting N RTL simulation models; Step S52: Set the starting state of the nth RTL simulation model to E3 n ; Step S53, parallelize each E1 n Input the corresponding nth RTL simulation model for simulation, according to E1 n and E2 n The corresponding relationship is set to clock data, and the signal changes in each RTL simulation model are observed in real time to determine the target abnormal point.

7. The method according to claim 6, characterized in that The step S53 includes: Step S531: parallelize each E1 n During the simulation process in the nth RTL simulation model corresponding to the input, if an abnormal point appears based on the nth RTL simulation model, the simulation operation of the (n+1)th RTL simulation model to the Nth RTL simulation model is terminated. After the simulation of the N RTL simulation models is completed, the abnormal point that appears first is determined as the target abnormal point.

8. The method according to any one of claims 1 to 7, characterized in that The clock data corresponding to the excitation data is the clock frequency.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 8.

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