A delay structure and delay circuit
By designing a delay structure composed of a MOSFET and a capacitor with a very small width-to-length ratio, and utilizing the deep subthreshold characteristic of the MOSFET, the problem of large area occupied by large delay cells in the absence of clock is solved, achieving the effect of large delay in small area.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KTMICRO ELECTRONICS
- Filing Date
- 2023-12-27
- Publication Date
- 2026-07-07
Smart Images
Figure CN117728802B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of circuit technology, and in particular to a delay structure and a delay circuit. Background Technology
[0002] With advancements in semiconductor technology, the size of MOS transistors has reached the deep nanometer scale, even achieving channel lengths of 1 nanometer. This significant reduction in chip size has, on the one hand, made chip area more expensive; on the other hand, it has enabled the integration of more relatively independent power-on / off systems onto a single chip. Since large delays are essential for adjusting power-on / off timing, and different power-on / off systems generally require more delay units (delays typically tens of microseconds or longer), this further increases the demand for cost-effectiveness of delay units (i.e., large delays in a small area). Therefore, the industry needs a delay unit with extremely high cost-effectiveness to meet the design requirements of highly integrated advanced CMOS systems.
[0003] Traditionally, large delay units are implemented using on-chip clock counters. However, during power-up / down control, the chip typically lacks an on-chip clock, making it impossible to use a clock counter for delay control. For delay units without a clock, inverters composed of MOSFETs are used. By minimizing the aspect ratio of the MOSFETs and then adding capacitors, a large delay is generated. To achieve delays of tens of microseconds or more, this structure usually requires tens or even hundreds of series-connected transistors, which consumes a significant amount of chip area and is unsuitable for applications with strict area requirements. Summary of the Invention
[0004] In view of this, the purpose of the present invention is to provide a delay structure and delay circuit that utilizes the deep subthreshold characteristic of MOSFETs to achieve a delay of tens of microseconds with a very small chip area, thus solving the problem that it is impossible to achieve a large delay with a small area in the absence of a clock.
[0005] In a first aspect, embodiments of the present invention provide a delay structure, comprising: a first inverter, a first capacitor, a second capacitor, a first output module, and a second output module; wherein the first output module includes a first MOSFET, and the second output module includes a second MOSFET; the first output module is provided with a first port, a second port, a third port, and a fourth port; the second output module is provided with a fifth port, a sixth port, a seventh port, and an eighth port; the first port and the fifth port are both used to connect to a power supply; the third port and the seventh port are used to ground; the fourth port is connected to the input terminal of the first inverter; the sixth port is connected to the output terminal of the first inverter; the source of the first MOSFET is connected to the first port; the gate of the second MOSFET is connected to the fourth port, and the source of the second MOSFET is connected to the fifth port; one end of the first capacitor is grounded, and the other end is connected to the fourth port; one end of the second capacitor is grounded, and the other end is connected to the eighth port; the second port is used to receive external signals; and the eighth port is used to output a delayed signal.
[0006] In some preferred embodiments of the present invention, the first output module further includes: a third MOS transistor and a fourth MOS transistor; the gates of the third MOS transistor and the fourth MOS transistor are both connected to the second port; the source of the third MOS transistor is connected to the first port; the drain of the third MOS transistor is connected to the source of the first MOS transistor; the drain of the fourth MOS transistor is connected to the fourth port; and the source of the fourth MOS transistor is connected to the third port.
[0007] In some preferred embodiments of the present invention, the second output module further includes: a fifth MOS transistor and a sixth MOS transistor; the gates of both the fifth MOS transistor and the sixth MOS transistor are connected to a sixth port; the source of the fifth MOS transistor is connected to a fifth port; the drain of the fifth MOS transistor is connected to the source of the second MOS transistor; the drain of the sixth MOS transistor is connected to an eighth port; and the source of the sixth MOS transistor is connected to a seventh port.
[0008] In some preferred embodiments of the present invention, the delay structure further includes: a signal inversion module; the input terminal of the signal inversion module is connected to the eighth port; and the output terminal of the signal inversion module is used to output a delay signal.
[0009] In some preferred embodiments of the present invention, the signal inversion module includes: a second inverter and a third inverter; the second inverter and the third inverter are connected in series; the input terminal of the second inverter is connected to the input terminal of the signal inversion module; and the output terminal of the third inverter is connected to the output terminal of the signal inversion module.
[0010] In some preferred embodiments of the present invention, the delay structure further includes: a fourth inverter; the output of the fourth inverter is connected to the second port; and the input of the fourth inverter is used to receive external signals.
[0011] In some preferred embodiments of the present invention, the delay structure further includes: a fifth inverter; the input terminal of the fifth inverter is connected to the eighth port; and the output terminal of the fifth inverter is used to output a delay signal.
[0012] In some preferred embodiments of the present invention, the delay structure further includes: a seventh MOS transistor and an eighth MOS transistor; the gates of both the seventh MOS transistor and the eighth MOS transistor are connected to the output terminal of the second inverter; the drain of the seventh MOS transistor is connected to the fourth port; the drain of the eighth MOS transistor is connected to the eighth port; and the sources of both the seventh MOS transistor and the eighth MOS transistor are used to connect to the operating power supply.
[0013] In some preferred embodiments of the present invention, the second output module further includes: a delay adjustment unit; the delay adjustment unit includes at least one MOS transistor; the delay adjustment unit is connected in series or in parallel with the second MOS transistor.
[0014] Secondly, embodiments of the present invention provide a delay circuit, which includes at least one of the above-described delay structures.
[0015] The embodiments of the present invention bring the following beneficial effects:
[0016] This invention provides a delay structure and delay circuit. The delay structure includes: a first inverter, a first capacitor, a second capacitor, a first output module, and a second output module. The first output module includes a first MOSFET, and the second output module includes a second MOSFET. The first output module has a first port, a second port, a third port, and a fourth port. The second output module has a fifth port, a sixth port, a seventh port, and an eighth port. The first and fifth ports are used to connect to a power supply. The third and seventh ports are used to ground. The fourth port is connected to the input terminal of the first inverter. The sixth port is connected to the output terminal of the first inverter. The source of the first MOSFET is connected to the first port. The gate of the second MOSFET is connected to the fourth port, and the source of the second MOSFET is connected to the fifth port. One end of the first capacitor is grounded, and the other end is connected to the fourth port. One end of the second capacitor is grounded, and the other end is connected to the eighth port. The second port is used to receive external signals. The eighth port is used to output a delayed signal. By utilizing the deep subthreshold characteristic of the MOSFET, a delay of tens of microseconds can be achieved using a very small chip area, solving the problem that large delays cannot be achieved with a small area in the absence of a clock. Attached Figure Description
[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of a time delay structure in the prior art;
[0019] Figure 2 This is a schematic diagram of a delay structure provided in an embodiment of the present invention;
[0020] Figure 3 This is a schematic diagram of another delay structure provided in an embodiment of the present invention;
[0021] Figure 4 This is a schematic diagram of the signal potential change inside a delay structure provided in an embodiment of the present invention;
[0022] Figure 5 This is a schematic diagram of another delay structure provided in an embodiment of the present invention;
[0023] Figure 6 This is a schematic diagram of a delay circuit provided in an embodiment of the present invention.
[0024] Icons: 100 - First output module; 110 - First MOSFET; 120 - Third MOSFET; 130 - Fourth MOSFET; 101 - First port; 102 - Second port; 103 - Third port; 104 - Fourth port; 200 - Second output module; 220 - Second MOSFET; 210 - Fifth MOSFET; 230 - Sixth MOSFET; 201 - Fifth port; 202 - Sixth port; 203 - Seventh port; 204 - Eighth port; 300 - First inverter; 410 - First capacitor; 420 - Second capacitor; 500 - Signal inversion module; 510 - Second inverter; 520 - Third inverter; 610 - Seventh MOSFET; 620 - Eighth MOSFET; 700 - Fourth inverter; 800 - Fifth inverter; 1000 - Delay structure; 2000 - Delay circuit. Detailed Implementation
[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0026] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0027] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0028] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0029] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0030] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0031] Traditionally, large delay units are implemented using an on-chip clock counter. However, during power-on / off control, the chip typically lacks an on-chip clock, making it impossible to use a clock counter for delay control. For delay units without a clock, see [link to relevant documentation]. Figure 1The diagram shows a schematic of a delay structure in the prior art. It uses MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) to form an inverter. By making the aspect ratio of the MOSFETs very small and then connecting capacitors, a large delay is generated. To achieve a delay of tens of microseconds or more, this structure usually requires tens or even hundreds of series-connected stages, which occupies a large chip area and is not suitable for scenarios with strict area requirements.
[0032] This scheme is a common circuit for generating delays in integrated circuits. It typically involves setting the MOS transistors of MP_1 and MN_1 to be inverted ratio transistors with a very small aspect ratio to reduce the current capability of the MOS transistors and decrease the charging current. Simultaneously, a large capacitor C_1 is connected at the NET_1 node. In this case, the delay is equal to... Where ΔV is the voltage level required for the next stage inverter to flip, and IM is the charging current of the NMOS or PMOS transistor. μ1 is the hole mobility of MP_1, C ox1 This refers to the gate oxide capacitance per unit area of MP_1, where W1 is the channel width of MP_1, L1 is the channel length of MP_1, and V... SGM1 It is the source voltage of MP_1 minus the gate voltage, V TH1 The threshold voltage of MP_1 is used. By increasing C_1 and decreasing IM, the charging time of node NET_1 can be increased, thereby increasing the delay. Inverter I_1 is used to invert and shape the output voltage of NET_1. MP_1, MN_1, C_1, and I_1 form a complete delay unit. A large delay is achieved through N-stage cascading. Using existing delay structures, achieving a 60-millisecond delay requires 40 to 50 stages and a large area.
[0033] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0034] Example 1
[0035] This invention provides a delay structure, see [link to relevant documentation]. Figure 2The schematic diagram shown in this embodiment of the invention illustrates a delay structure 1000, which includes: a first inverter, a first capacitor 410, a second capacitor 420, a first output module 100, and a second output module 200. The first output module 100 includes a first MOSFET 110, and the second output module 200 includes a second MOSFET 220. The first output module 100 is provided with a first port 101, a second port 102, a third port 103, and a fourth port 104. The second output module 200 is provided with a fifth port 201, a sixth port 202, a seventh port 203, and an eighth port 204. The first port 101 and the fifth port 204... Ports 01 and 202 are used to connect to the operating power supply; Ports 103 and 203 are used for grounding; Port 104 is connected to the input of the first inverter; Port 202 is connected to the output of the first inverter; The source of the first MOSFET 110 is connected to Port 101; The source of the second MOSFET 220 is connected to Port 201, and the drain of the second MOSFET 220 is connected to Port 204; One end of the first capacitor 410 is grounded, and the other end is connected to Port 104; One end of the second capacitor 420 is grounded, and the other end is connected to Port 204; Port 102 is used to receive external signals; Port 204 is used to output delayed signals.
[0036] Specifically, the first MOSFET 110 and the second MOSFET 220 are inverted ratio MOSFETs with a very small width-to-length ratio. An inverted ratio MOSFET is a type of MOSFET, with an exemplary width of 0.15µm and a length of 5µm. The first MOSFET 110 is connected as a diode, meaning that when the gate and drain of the MOSFET are shorted, the MOSFET functions as a diode.
[0037] Furthermore, when the VI N input is 0, the first MOSFET 110 is turned on, charging the fourth port 104 through the first MOSFET 110. The charging current is mainly limited by the first MOSFET 110, which charges the fourth port 104 from 0 to VDD-VGSM2. Where μ is the hole mobility of the first MOSFET 110, C_ox is the gate oxide capacitance per unit area of the first MOSFET 110, W is the channel width of the first MOSFET 110, L is the channel length of the first MOSFET 110, VSGM2 is the source voltage minus the gate voltage of the first MOSFET 110, and VTH is the threshold voltage of the first MOSFET 110.
[0038] As the voltage at port 104 increases from 0, the VSGM2 of the first MOSFET 110 decreases accordingly, and the charging current gradually decreases. When the voltage at port 104 exceeds the switching voltage ΔVI2 of the first inverter 300, the output of port 202 of the first inverter 300 flips from 1 to 0. At this time, the second MOSFET 220 turns on, charging port 203 through the second MOSFET 220. The charging current is mainly limited by the second MOSFET 220. Since the gate of the second MOSFET 220 is connected to the gate of the first MOSFET 110, VSGM5 = VSGM2. At this time, the voltage at port 104 has increased, and VSGM2 is small enough to cause the first MOSFET 110 and the second MOSFET 220 to enter a deep subthreshold state. Therefore, the second MOSFET 220 charges port 203 with a very weak deep subthreshold leakage current throughout the entire process. The delay of the entire delay unit is mainly generated by this stage.
[0039] Specifically, the deep subthreshold characteristic of a MOSFET refers to the fact that when the gate voltage Vgs of the MOSFET is less than the threshold voltage Vth, the MOSFET enters the deep subthreshold region. At this time, the relationship between the current Id and Vds of the MOSFET is not linear, but exponential, and the current capability of the MOSFET is very weak.
[0040] This invention provides a delay structure 1000, comprising: a first inverter, a first capacitor 410, a second capacitor 420, a first output module 100, and a second output module 200; wherein the first output module 100 includes a first MOSFET 110, and the second output module 200 includes a second MOSFET 220; the first output module 100 is provided with a first port 101, a second port 102, a third port 103, and a fourth port 104; the second output module 200 is provided with a fifth port 201, a sixth port 202, a seventh port 203, and an eighth port 204; the first port 101 and the fifth port 201 are both used to connect to a power supply; the third port 103 and the seventh port 203 are used for grounding; the fourth port 204... Port 104 is connected to the input of the first inverter; port 202 is connected to the output of the first inverter; the source of the first MOSFET 110 is connected to port 101; the gate of the second MOSFET 220 is connected to port 104, and the source of the second MOSFET 220 is connected to port 201; one end of the first capacitor 410 is grounded, and the other end is connected to port 104; one end of the second capacitor 420 is grounded, and the other end is connected to port 204; port 102 is used to receive external signals; port 204 is used to output delayed signals; by utilizing the deep subthreshold characteristic of MOSFETs, a delay of tens of microseconds can be achieved with a very small chip area, solving the problem that it is impossible to achieve a large delay with a small area in the absence of a clock.
[0041] Example 2
[0042] Based on the above embodiments, this invention provides another delay structure, see [link to previous embodiment]. Figure 3 The schematic diagram of another delay structure provided by the embodiment of the present invention shown shows that the first output module 100 further includes: a third MOS transistor 120 and a fourth MOS transistor 130; the gates of both the third MOS transistor 120 and the fourth MOS transistor 130 are connected to the second port 102; the source of the third MOS transistor 120 is connected to the first port 101; the drain of the third MOS transistor 120 is connected to the source of the first MOS transistor 110; the drain of the fourth MOS transistor 130 is connected to the fourth port 104; and the source of the fourth MOS transistor 130 is connected to the third port 103.
[0043] Furthermore, the second output module 200 also includes: a fifth MOSFET 210 and a sixth MOSFET 230; the gates of both the fifth MOSFET 210 and the sixth MOSFET 230 are connected to the sixth port 202; the source of the fifth MOSFET 210 is connected to the fifth port 201; the drain of the fifth MOSFET 210 is connected to the source of the second MOSFET 220; the drain of the sixth MOSFET 230 is connected to the eighth port 204; and the source of the sixth MOSFET 230 is connected to the seventh port 203.
[0044] Furthermore, the delay structure 1000 also includes: a signal inversion module 500; the input terminal of the signal inversion module 500 is connected to the eighth port 204; the output terminal of the signal inversion module 500 is used to output a delayed signal. The signal inversion module 500 includes: a second inverter 510 and a third inverter 520; the second inverter 510 and the third inverter 520 are connected in series; the input terminal of the second inverter 510 is connected to the input terminal of the signal inversion module 500; the output terminal of the second inverter 510 is connected to the output terminal of the signal inversion module 500.
[0045] Furthermore, the delay structure 1000 also includes: a fourth inverter 700; the output of the fourth inverter 700 is connected to the second port 102; the input of the fourth inverter 700 is used to receive external signals.
[0046] Furthermore, the delay structure 1000 also includes: a seventh MOSFET 610 and an eighth MOSFET 620; the gates of both the seventh MOSFET 610 and the eighth MOSFET 620 are connected to the output terminal of the second inverter 510; the drain of the seventh MOSFET 610 is connected to the fourth port 104; the drain of the eighth MOSFET 620 is connected to the eighth port 204; and the sources of both the seventh MOSFET 610 and the eighth MOSFET 620 are used to connect to the operating power supply.
[0047] Specifically, the first inverter, the second inverter 510, the third inverter 520, and the fourth inverter 700 are all standard inverters. The first capacitor 410 and the second capacitor 420 are active MOSFET capacitors. The first MOSFET 110 to the eighth MOSFET 620 are all ordinary MOSFETs. VDD is the power supply. The core of the delay generation is the first MOSFET 110 and the second MOSFET 220. The first MOSFET 110 and the second MOSFET 220 are inverted ratio MOSFETs with a very small aspect ratio. The first MOSFET 110 is connected as a diode, and the gate of the second MOSFET 220 is connected to the gate of the first MOSFET 110. The dimensions of the first MOSFET 110 and the second MOSFET 220 are proportional. By programming the control signal, the proportional relationship between the first MOSFET 110 and the second MOSFET 220 can be adjusted to adjust the delay of the delay unit. The gate of the seventh MOSFET 610 is connected to the output of the second inverter 510, and its drain is connected to the fourth port 104. The gate of the eighth MOSFET 620 is connected to the output of the second inverter 510, and its drain is connected to the eighth port 204. The main function of the seventh MOSFET 610 and the eighth MOSFET 620 is to promptly pull the fourth port 104 and the eighth port 204 high when the logic of the output of the second inverter 510 goes low.
[0048] See Figure 4 The diagram shown illustrates the signal potential change within a delay structure according to an embodiment of the present invention. Taking the flipping of V1N from 0 to 1 as an example, after the second port 102 is delayed by the fourth inverter, it changes from 1 to 0. At this time, the first MOSFET 110 and the third MOSFET 120 are turned on, while the fourth MOSFET 130 is turned off. The fourth port 104 is charged through the first MOSFET 110 and the third MOSFET 120. The charging current is mainly limited by the first MOSFET 110. Through the first MOSFET 110 and the third MOSFET 120, the fourth port 104 is charged from 0 to VDD-VGSM2. Where μ is the hole mobility of the first MOSFET 110, C_ox is the gate oxide capacitance per unit area of the first MOSFET 110, W is the channel width of the first MOSFET 110, L is the channel length of the first MOSFET 110, VSGM2 is the source voltage minus the gate voltage of the first MOSFET 110, and VTH is the threshold voltage of the first MOSFET 110.
[0049] Furthermore, as the voltage at the fourth port 104 increases from 0, the VSGM2 of the first MOSFET 110 decreases accordingly, and the charging current gradually decreases as well. When the voltage at the fourth port 104 exceeds the switching voltage ΔVI2 of the first inverter 300, the output of the sixth port 202 of the first inverter 300 flips from 1 to 0. At this time, the second MOSFET 220 and the fifth MOSFET 210 are turned on, and the sixth MOSFET 230 is turned off. The eighth port 204 is charged through the second MOSFET 220 and the fifth MOSFET 210. At this time, the charging current is mainly limited by the second MOSFET 220. Since the gate of the second MOSFET 220 is connected to the gate of the first MOSFET 110, VSGM5 = VSGM2. At this time, the voltage at the fourth port 104 has increased, and VSGM2 is small enough to cause the first MOSFET 110 and the second MOSFET 220 to enter a deep subthreshold state. Therefore, the second MOSFET 220 charges the eighth port 204 with a very weak deep subthreshold leakage current throughout the entire process. The delay of the entire delay unit is mainly generated by this stage. When the charging voltage at port 204 is increased from 0 to the flip voltage ΔVI3 of the second inverter, the output of the second inverter flips from 1 to 0. At this time, the gates of the seventh MOSFET 610 and the eighth MOSFET 620 are pulled low, and the seventh MOSFET 610 and the eighth MOSFET 620 are turned on. The seventh MOSFET 610 and the eighth MOSFET 620 quickly pull the fourth port 104 and the eighth port 204 to VDD, avoiding the fourth port 104 and the eighth port 204 being in a high-impedance state and susceptible to external interference; it also avoids leakage in the first inverter 300 and the second inverter 510 if the fourth port 104 and the eighth port 204 remain at the intermediate level. With the above structure, a delay of about sixty microseconds from the rising edge of VI N to VOUT is achieved.
[0050] Furthermore, the second output module 200 also includes a delay adjustment unit; the delay adjustment unit includes at least one MOSFET; the delay adjustment unit is connected in series or in parallel with the second MOSFET 220. The MOSFET in the delay adjustment unit is the same as the second MOSFET 220.
[0051] Specifically, the delay of the delay unit can be flexibly controlled by digital control bits. The control method is to adjust the width-to-length ratio of the second MOSFET 220 by adjusting the control word, that is, to adjust the number of MOSFETs connected in parallel in the delay adjustment unit.
[0052] When adjusting the delay, the size of the first MOSFET 110 generally remains unchanged. If the delay needs to be reduced, the width-to-length ratio of the second MOSFET 220 needs to be increased, that is, more units of the second MOSFET 220 need to be connected in parallel. If the delay needs to be increased, the width-to-length ratio of the second MOSFET 220 needs to be decreased, that is, fewer units of the second MOSFET 220 need to be connected in parallel, or it can be achieved by connecting units of the second MOSFET 220 in series.
[0053] In detail, by default, the second output module 200 is connected to two basic units. To reduce the delay, an additional basic unit can be connected in parallel, making it three basic units. To increase the delay, one less basic unit can be connected to the two basic units, making it one basic unit.
[0054] This invention provides a delay structure including multiple MOS transistors, of which the fourth and sixth MOS transistors are N-type MOS transistors and the rest are P-type MOS transistors.
[0055] This invention provides a delay structure with the following advantages: 1. Large delay unit in a small area; 2. Adjustable delay time; 3. Clock-free delay unit; 4. Applicable to power-on / off control and power-on reset signal generation of all integrated circuits; 5. Applicable to all scenarios requiring large delays; 6. Applicable to all CMOS processes; 7. Applicable to scenarios with strict area requirements.
[0056] Example 3
[0057] Based on the above embodiments, this invention provides another delay structure, which further includes: a fifth inverter 800; the input terminal of the fifth inverter 800 is connected to the eighth port 204; the output terminal of the fifth inverter 800 is used to output a delay signal.
[0058] For details, see Figure 5 The present invention provides another delay structure schematic diagram. The delay structure 1000 removes the fourth inverter 700 in embodiment 2 and adds a fifth inverter 800. The size and connection of other components remain unchanged. By adjusting the position of the inverter, a delay of about sixty microseconds on the falling edge can be achieved.
[0059] This invention addresses the problem of the lack of available small-area, high-delay cells in the absence of a clock signal. It meets the cost-effectiveness requirements of advanced processes for delay cells. While achieving the same delay, the cost-effectiveness is twenty times that of existing technologies.
[0060] Example 4
[0061] Based on the above embodiments, this invention provides a delay circuit, see [link to relevant documentation]. Figure 6 The diagram shown is a schematic of a delay circuit provided by an embodiment of the present invention. The delay circuit 2000 includes at least one of the aforementioned delay structures 1000. By combining the rising and falling edges in series, arbitrarily large delays for both the rising and falling edges can be achieved, which will not be described further in this embodiment.
[0062] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the delay circuit described above can be referred to the corresponding process in the aforementioned embodiments of the delay structure method, and will not be repeated here.
[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A time delay structure, characterized in that, include: The system comprises a first inverter, a first capacitor, a second capacitor, a first output module, and a second output module; wherein the first output module includes a first MOSFET, and the second output module includes a second MOSFET; the first output module is provided with a first port, a second port, a third port, and a fourth port; and the second output module is provided with a fifth port, a sixth port, a seventh port, and an eighth port. Both the first port and the fifth port are used to connect to the operating power supply; The third port and the seventh port are used for grounding; The fourth port is connected to the input terminal of the first inverter; The sixth port is connected to the output of the first inverter; The source of the first MOS transistor is connected to the first port; The gate of the second MOS transistor is connected to the fourth port, and the source of the second MOS transistor is connected to the fifth port; One end of the first capacitor is grounded, and the other end is connected to the fourth port; One end of the second capacitor is grounded, and the other end is connected to the eighth port; The second port is used to receive external signals; The eighth port is used to output a delayed signal.
2. The delay structure according to claim 1, characterized in that, The first output module further includes: a third MOS transistor and a fourth MOS transistor; the gates of the third MOS transistor and the fourth MOS transistor are both connected to the second port; the source of the third MOS transistor is connected to the first port; the drain of the third MOS transistor is connected to the source of the first MOS transistor; the drain of the fourth MOS transistor is connected to the fourth port; and the source of the fourth MOS transistor is connected to the third port.
3. The delay structure according to claim 1, characterized in that, The second output module further includes: a fifth MOS transistor and a sixth MOS transistor; the gates of the fifth MOS transistor and the sixth MOS transistor are both connected to the sixth port; the source of the fifth MOS transistor is connected to the fifth port; the drain of the fifth MOS transistor is connected to the source of the second MOS transistor; the drain of the sixth MOS transistor is connected to the eighth port; and the source of the sixth MOS transistor is connected to the seventh port.
4. The delay structure according to claim 1, characterized in that, The delay structure further includes: a signal inversion module; The input terminal of the signal inversion module is connected to the eighth port; The output of the signal inversion module is used to output the delayed signal.
5. The delay structure according to claim 4, characterized in that, The signal inversion module includes a second inverter and a third inverter; the second inverter and the third inverter are connected in series; the input terminal of the second inverter is connected to the input terminal of the signal inversion module; and the output terminal of the third inverter is connected to the output terminal of the signal inversion module.
6. The delay structure according to claim 1, characterized in that, The delay structure further includes: a fourth inverter; the output terminal of the fourth inverter is connected to the second port; The input terminal of the fourth inverter is used to receive the external signal.
7. The delay structure according to claim 1, characterized in that, The delay structure further includes: a fifth inverter; the input terminal of the fifth inverter is connected to the eighth port; The output of the fifth inverter is used to output the delayed signal.
8. A delay structure according to claim 5, characterized in that, The delay structure further includes a seventh MOS transistor and an eighth MOS transistor; the gates of both the seventh MOS transistor and the eighth MOS transistor are connected to the output terminal of the second inverter; the drain of the seventh MOS transistor is connected to the fourth port; and the drain of the eighth MOS transistor is connected to the eighth port. The sources of both the seventh and eighth MOS transistors are used to connect to the operating power supply.
9. The delay structure according to claim 1, characterized in that, The second output module further includes: a delay adjustment unit; the delay adjustment unit includes at least one MOS transistor; the delay adjustment unit is connected in series or in parallel with the second MOS transistor.
10. A delay circuit, characterized in that, The delay circuit includes at least one delay structure as described in any one of claims 1-9.