A PSE chip, a power receiving device detection method, and a driving method.

Abstract

This invention relates to the field of PSE chip technology, and discloses a PSE chip, a power receiving device detection method, and a driving method. The PSE chip includes a power receiving interface, a detection resistor, a switching transistor, an input sampling unit, a control unit, and an output control unit. The power receiving interface includes a positive interface and a negative interface. In actual use, the control unit can know the voltage across the two ends of the detection resistor and the voltage at one end of the detection resistor through the input sampling unit, thereby enabling characteristic resistance detection and power level detection based on the acquired voltage. In addition, the control unit can control the voltage at the control terminal of the switching transistor through the output control unit, thereby enabling switching transistor control based on the acquired voltage, realizing complete characteristic resistance detection, power level detection, and output control without the need for three separate functional modules, thus simplifying the circuit structure of the PSE chip.

Description

Technical Field

[0001] This invention relates to the field of PSE chip technology, specifically to a PSE chip, a power receiving device detection method, and a driving method. Background Technology

[0002] With the rise of the Industrial Internet of Things (IIoT), PoE (Power over Ethernet) technology, a technology that transmits power to network devices, is being applied in various fields because it can ensure the security of existing structured cabling while maintaining the normal operation of existing networks and minimizing costs.

[0003] A complete PoE system consists of two parts: the power supply equipment (PSE) and the power receiving equipment (PD). The PSE device supplies power to the Ethernet client devices and also manages the entire PoE Ethernet power supply process. The PSE device is managed through a PSE chip, while the PD device is the PoE load that receives power.

[0004] Currently in PoE systems, according to the IEEE 802.3 af / at standard, the PSE chip needs to detect the following three pieces of information from the PD device:

[0005] 1. Signature detection: Characteristic resistance detection. The PSE detects the impedance value of the connected PD device to determine whether the connected PD device is legitimate, thereby turning on the output power.

[0006] 2: PD device classification: The power supplied by the PSE is determined by the magnitude of the pull-down current of the PD device.

[0007] 3: PSE output management control, which controls a high-power MOSFET to power the PD device, detects the output current, and provides overvoltage, overcurrent, and short-circuit protection functions.

[0008] The structure of existing PSE chips is as follows Figure 1 As shown, because it achieves the detection of the three points of information of the above-mentioned PD device through a graded current detection unit, a characteristic resistance detection unit and an output control unit, the chip has more components, the chip area is larger and the cost is higher. Summary of the Invention

[0009] In view of the shortcomings of the prior art, the present invention provides a PSE chip, a powered device detection method and a driving method. The technical problem to be solved is that the existing PSE chip realizes the signature detection, device hierarchical detection and output control of PD device through three structural units, which has the problems of many components and large area.

[0010] To solve the above technical problems, in a first aspect, the present invention provides the following technical solution: a PSE chip, comprising a power receiving interface, a detection resistor, a switching transistor, an input sampling unit, a control unit, and an output control unit; the power receiving interface includes a positive interface and a negative interface;

[0011] One end of the detection resistor is electrically connected to the input terminal of the switching transistor, the output terminal of the switching transistor is grounded, and the other end of the detection resistor is electrically connected to the negative interface.

[0012] The input sampling unit is used to detect the voltage across the detection resistor and at one end of the detection resistor, and to input a voltage detection signal to the control unit;

[0013] The control unit is electrically connected to the output control unit. Based on the voltage detection signal, the control unit inputs a control signal to the output control unit. The output control unit responds to the control signal to control the magnitude of the voltage input to the switching transistor.

[0014] In one embodiment of the first aspect, the switching transistor is an NMOS transistor, the drain of the NMOS transistor is the input terminal of the switching transistor, the source of the NMOS transistor is the output terminal of the switching transistor, and the gate of the NMOS transistor is the control terminal of the switching transistor.

[0015] In one embodiment of the first aspect, the input sampling unit includes an analog-to-digital converter, a dual-channel selector, and a differential amplifier; the positive input terminal of the differential amplifier is electrically connected to the other end of the detection resistor, the negative input terminal of the differential amplifier is electrically connected to one end of the detection resistor, the output terminal of the differential amplifier and one end of the detection resistor are electrically connected to the two input terminals of the dual-channel selector, the output terminal of the dual-channel selector is electrically connected to the input terminal of the analog-to-digital converter, and the output terminal of the analog-to-digital converter is electrically connected to the control unit.

[0016] In one embodiment of the first aspect, the output control unit includes a digital-to-analog converter unit and a second differential amplifier unit. The digital-to-analog converter unit is electrically connected to the control unit and receives the control signal. The output terminal of the digital-to-analog converter unit is connected to the negative input terminal of the second differential amplifier unit. The positive input terminal of the second differential amplifier unit is electrically connected to one end of the detection resistor. The output terminal of the second differential amplifier unit is electrically connected to the control terminal of the switching transistor.

[0017] In one embodiment of the first aspect, the control terminal of the switching transistor is also electrically connected to the output terminal of the switching transistor via a resistor R2; the control terminal of the switching transistor is also electrically connected to the output terminal of the switching transistor via a capacitor C1.

[0018] Secondly, the present invention provides a power receiving device detection method, implemented using the aforementioned PSE chip, comprising the following steps:

[0019] S1: When the PSE chip is powered on, the control unit controls the switching transistor to turn off through the output control unit and connects to the powered device;

[0020] S2: Check whether the characteristic resistance of the powered device meets the requirements, as follows:

[0021] S21: When the control unit detects that a powered device is connected, the control unit first adjusts the control terminal voltage of the switching transistor through the output control unit. During this process, when the control unit detects through the input sampling unit that the voltage difference between the positive interface and the negative interface reaches a preset first threshold voltage, it stops adjusting the control terminal voltage of the switching transistor.

[0022] Next, the control unit first obtains the voltage across the detection resistor through the input sampling unit. The voltage across the detection resistor obtained at this time is recorded as the first detection voltage. The control unit calculates the detection current flowing through the detection resistor based on the first detection voltage and records the current flowing through the detection resistor as the first detection current.

[0023] Then the control unit calculates the resistance value of the externally connected characteristic resistor based on the first threshold voltage and the first detection current, and determines whether the resistance value of the characteristic resistor meets the requirements. If it meets the requirements, step S22 is executed; if it does not meet the requirements, step S21 is ended and the detection is terminated.

[0024] S22: The control unit first continues to adjust the control terminal voltage of the switching transistor through the output control unit until the voltage difference between the positive interface and the negative interface reaches the preset second threshold voltage;

[0025] Next, the control unit obtains the voltage across the detection resistor through the input sampling unit. The voltage across the detection resistor obtained at this time is recorded as the second detection voltage. The control unit calculates the current flowing through the detection resistor based on the second detection voltage and records the calculated current flowing through the detection resistor as the second detection current.

[0026] Then the control unit calculates the resistance value of the externally connected characteristic resistor based on the second threshold voltage and the second detection current; and determines whether the calculated characteristic resistor value meets the requirements. If it meets the requirements, step S3 is executed; if it does not meet the requirements, step S22 is ended and the detection is terminated.

[0027] S3: The control unit drives the switching transistor to turn off through the output control unit, and executes step S4;

[0028] S4: Determine the power level of the power receiving equipment, as follows:

[0029] The control unit first adjusts the voltage at the control terminal of the switching transistor through the output control unit until the voltage difference between the positive interface and the negative interface reaches a preset third threshold voltage;

[0030] Next, the control unit acquires the voltage across the detection resistor through the input sampling unit, calculates the current flowing through the detection resistor based on the voltage across the detection resistor at this time, and determines the power level of the powered device based on the current.

[0031] S5: After determining the power level of the powered device, the control unit again drives the switch to turn off through the output control unit.

[0032] In one embodiment of the second aspect, in steps S1, S3, and S5, the process by which the control unit controls the switching transistor to turn off via the output control unit is as follows:

[0033] The control unit drives the analog-to-digital conversion unit to input the maximum analog voltage to the negative input terminal of the second differential amplifier unit;

[0034] In step S2, the process by which the control unit adjusts the control terminal voltage of the switching transistor through the output control unit is as follows: the control unit drives the analog-to-digital conversion unit to adjust the magnitude of the analog voltage input to the negative input terminal of the second differential amplifier unit.

[0035] In one embodiment of the second aspect, when executing step S22, if the number of executions of step S21 is less than the preset number of cycles, when the characteristic resistor value is determined to meet the requirements in step S4, the control unit first adjusts the control terminal voltage of the switching transistor through the output control unit until the voltage difference between the positive and negative interfaces reaches the preset first threshold voltage, and then executes step S21; if the number of executions of step S21 is equal to the set number of cycles, when the characteristic resistor value is determined to meet the requirements in step S4, step S3 is executed.

[0036] In one embodiment of the second aspect, the power level includes level zero, level one, level two, level three and level four; the current corresponding to level zero to level four gradually increases. The power level is determined before step S4 is executed and before step S5 is executed. When the power level is level four, step S4 is executed again.

[0037] Thirdly, the present invention provides a method for driving a powered device. First, the power level of the powered device is determined by the aforementioned powered device detection method. Then, the control unit adjusts the control terminal voltage of the switching transistor according to the power level of the powered device through the output control unit, so that the power output by the power receiving interface reaches the power corresponding to the power level of the powered device.

[0038] The advantages of this invention compared to the prior art are as follows: The control unit of this invention can know the voltage across the two ends of the test resistor and the voltage at one end of the test resistor through the input sampling unit, thereby enabling characteristic resistance detection and power level detection based on the acquired voltage; in addition, the control unit can control the control terminal voltage of the switching transistor through the output control unit, thereby enabling switching transistor control based on the acquired voltage, realizing complete characteristic resistance detection, power level detection and output control, without the need for three separate functional modules to achieve characteristic resistance detection, power level detection and output control, thus simplifying the circuit structure of the PSE chip. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the structure of an existing PSE chip;

[0040] Figure 2 This is a schematic diagram of the PSE chip structure in the embodiment;

[0041] Figure 3 This is a diagram illustrating the power rating levels. Detailed Implementation

[0042] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0043] Example 1

[0044] like Figure 2 As shown, a PSE chip includes a power receiving interface, a sensing resistor R1, a switching transistor Q1, an input sampling unit 2, a control unit 1, and an output control unit 3; the power receiving interface includes a positive interface Vport+ and a negative interface Vport-, and the power receiving interface is used to provide operating voltage to the powered device;

[0045] One end of the sensing resistor R1 is electrically connected to the input terminal of the switching transistor Q1, the output terminal of the switching transistor Q1 is grounded, and the other end of the sensing resistor R1 is electrically connected to the negative interface Vport-.

[0046] The input sampling unit 2 is used to detect the voltage across the detection resistor R1 and at one end of the detection resistor R1, and inputs the voltage detection signal to the control unit 1;

[0047] Control unit 1 is electrically connected to output control unit 3. Based on the voltage detection signal, control unit 1 inputs a control signal to output control unit 3. Output control unit 3 responds to the control signal to control the voltage input to the control terminal of switch Q1.

[0048] In practical use, when a powered device is connected to the power receiving interface, the control unit 1 adjusts the voltage at the control terminal of the switching transistor Q1 through the output control unit 3, thereby adjusting the voltage at the negative interface Vport-. The control unit 1 can obtain the voltage across the detection resistor R1 through the input sampling unit 2. Therefore, the control unit 1 can realize characteristic resistance detection, power level detection and output power control through the input sampling unit 2 and the output control unit 3, simplifying the structure of the PSE chip.

[0049] Specifically in Figure 2 In this circuit, the switch Q1 is an NMOS transistor. The drain of the NMOS transistor is the input terminal of the switch Q1, the source of the NMOS transistor is the output terminal of the switch Q1, and the gate of the NMOS transistor is the control terminal of the switch Q1.

[0050] Specifically, in Figure 2 In the input sampling unit 2, there are an analog-to-digital converter 20, a dual-channel selector MUX, and a differential amplifier 21. The positive input terminal of the differential amplifier 21 is electrically connected to the other end of the detection resistor R1, the negative input terminal of the differential amplifier 21 is electrically connected to one end of the detection resistor R1, the output terminal of the differential amplifier 21 and one end of the detection resistor R1 are electrically connected to the two input terminals of the dual-channel selector MUX, the output terminal of the dual-channel selector MUX is electrically connected to the input terminal of the analog-to-digital converter 20, and the output terminal of the analog-to-digital converter 20 is electrically connected to the control unit.

[0051] In practical use, control unit 1 can control which input terminal and output terminal of the dual-channel selector MUX are electrically connected, thereby controlling whether the analog-to-digital conversion unit performs analog-to-digital conversion on the voltage across the sensing resistor R1 or detects the voltage at one end of the sensing resistor R1. When the voltage across the sensing resistor R1 is detected, the magnitude of the current flowing through the sensing resistor R1 can be obtained. When the voltage at one end of the sensing resistor R1 is detected, the voltage difference between the positive interface Vport+ and the negative interface Vport- can be obtained. The voltage at the positive interface Vport+ is the output voltage of the PSE chip, which is a known value.

[0052] Specifically, in Figure 2In the output control unit 3, there are digital-to-analog converter unit 30 and second differential amplifier unit 31. The digital-to-analog converter unit 30 is electrically connected to the control unit 1 and receives control signals. The output terminal of the digital-to-analog converter unit 30 is connected to the negative input terminal of the second differential amplifier unit 31. The positive input terminal of the second differential amplifier unit 31 is electrically connected to one end of the detection resistor R1. The output terminal of the second differential amplifier unit 31 is electrically connected to the control terminal of the switching transistor Q1.

[0053] In actual use, the control unit 1 controls the magnitude of the analog voltage input to the second differential amplifier unit 31 through the control signal, thereby changing the magnitude of the output voltage of the second differential amplifier unit 31, and thus realizing the switching control of the switching transistor Q1.

[0054] In addition, in this embodiment, the control terminal of switch Q1 is also electrically connected to the output terminal of switch Q1 through resistor R2. The control terminal of switch Q1 is also electrically connected to the output terminal of switch Q1 through capacitor C1.

[0055] Example 2

[0056] This embodiment provides a power receiving device detection method, implemented using the PSE chip in Embodiment 1, including the following steps:

[0057] Includes the following steps:

[0058] S1: When the PSE chip is powered on, the control unit 1 controls the switch Q1 to turn off through the output control unit 3 and connects to the powered device;

[0059] Specifically, the control unit 1 causes the digital-to-analog converter 30 to output the maximum analog voltage, thereby causing the drive signal output by the second differential amplifier unit 31 to turn off the switching transistor Q1.

[0060] S2: Check whether the characteristic resistance of the powered device meets the requirements, as follows:

[0061] S21: When the control unit 1 detects that a powered device is connected, the control unit 1 first adjusts the control terminal voltage of the switch Q1 through the output control unit 3. During this process, when the control unit 1 detects through the input sampling unit 2 that the voltage difference between the positive interface Vport+ and the negative interface Vport- reaches the preset first threshold voltage, it stops adjusting the control terminal voltage of the switch Q1.

[0062] Specifically, control unit 1 increases the control terminal voltage of switching transistor Q1 by reducing the analog voltage output of digital-to-analog converter unit 30; control unit 1 controls dual-channel selector MUX to electrically connect one end of detection resistor R1 to analog-to-digital converter unit 20, thereby detecting the voltage of negative interface Vport-. Since the voltage of positive interface Vport+ is known, the voltage difference between positive interface Vport+ and negative interface Vport- can be obtained by subtracting the voltage of negative interface Vport- from the voltage of positive interface Vport+; the first threshold voltage can be set according to actual needs, for example, the first threshold voltage is 8V;

[0063] Next, the control unit 1 first obtains the voltage across the detection resistor R1 through the input sampling unit 2. The voltage across the detection resistor R1 obtained at this time is recorded as the first detection voltage. The control unit 1 calculates the detection current flowing through the detection resistor R1 based on the first detection voltage and records the current flowing through the detection resistor R1 as the first detection current.

[0064] Specifically, the control unit 1 controls the dual-channel selector MUX to electrically connect the output of the differential amplifier unit 21 to the analog-to-digital converter unit 20, thereby realizing the voltage detection across the resistor R1 and dividing the first detection voltage by the resistance value of the detection resistor R1 to obtain the magnitude of the first detection current.

[0065] Then, the control unit 1 calculates the resistance value of the externally connected characteristic resistor based on the first threshold voltage and the first detection current, and determines whether the resistance value of the characteristic resistor meets the requirements. If it meets the requirements, step S22 is executed; if it does not meet the requirements, step S21 is ended and the detection is terminated.

[0066] S22: Control unit 1 first continues to adjust the control terminal voltage of switch Q1 through output control unit 3 until the voltage difference between positive interface Vport+ and negative interface Vport- reaches the preset second threshold voltage.

[0067] Specifically, in this embodiment, the second threshold voltage is less than the first threshold voltage, and its value can be set according to actual needs. For example, the second threshold voltage is 4V and the first threshold voltage is 8V. In addition, the voltage difference between the positive interface Vport+ and the negative interface Vport- can be calculated with reference to the above content.

[0068] Next, the control unit 1 obtains the voltage across the detection resistor R1 through the input sampling unit 2. The voltage across the detection resistor R1 obtained at this time is recorded as the second detection voltage. The control unit 1 calculates the current flowing through the detection resistor R1 based on the second detection voltage, and records the calculated current flowing through the detection resistor R1 as the second detection current. The voltage across the detection resistor R1 obtained by the control unit 1 through the input sampling unit 2 can refer to the content of obtaining the voltage across the detection resistor R1 in step S21.

[0069] Then, the control unit 1 calculates the resistance value of the externally connected characteristic resistor based on the second threshold voltage and the second detection current; and determines whether the calculated characteristic resistor value meets the requirements. If it meets the requirements, step S3 is executed; if it does not meet the requirements, step S22 is ended and the detection is terminated.

[0070] In practical applications, step S2 can be executed repeatedly to determine the resistance value of the characteristic resistor, as follows:

[0071] When executing step S22, if the number of executions of step S21 is less than the preset number of cycles, when the characteristic resistor value is determined to meet the requirements in step S4, the control unit 1 first adjusts the control terminal voltage of the switching transistor Q1 through the output control unit 3 until the voltage difference between the positive interface Vport+ and the negative interface Vport- reaches the preset first threshold voltage, and then executes step S21; if the number of executions of step S21 is equal to the set number of cycles, when the characteristic resistor value is determined to meet the requirements in step S4, step S3 is executed.

[0072] For example, the execution count starts from zero, and the execution count is incremented by 1 each time step S21 is executed; in addition, the number of loops can be set according to actual needs, for example, it can be 2;

[0073] S3: Control unit 1 drives switch Q1 to turn off through output control unit 3, and executes step S4; the specific turn-off process can be referred to step S1.

[0074] S4: Determine the power rating of the receiving equipment, as follows:

[0075] Control unit 1 first adjusts the voltage of the control terminal Q1 of the switching transistor through output control unit 3 until the voltage difference between the positive interface Vport+ and the negative interface Vport- reaches the preset third threshold voltage;

[0076] Specifically, the control unit 1 increases the voltage at the control terminal of the switching transistor Q1 by outputting the control unit 3, so that the voltage difference between the positive interface Vport+ and the negative interface Vport- reaches the preset third threshold voltage.

[0077] Specifically, the third threshold voltage is set according to actual needs; for example, the third threshold voltage is 20V.

[0078] Next, the control unit 1 collects the voltage across the detection resistor R1 through the input sampling unit 2, and calculates the current flowing through the detection resistor R1 based on the voltage across the detection resistor R1 at this time, and determines the power level of the powered device based on the current.

[0079] Specifically, power ratings include Class 0, Class 1, Class 2, Class 3, and Class 4; the relevant parameter classifications can be found in [reference needed]. Figure 3 The graded currents corresponding to grades zero to four gradually increase; when the power grade is grade zero, the graded current is greater than 0mA and less than or equal to 5mA; in addition, in this embodiment, the power grade can be judged before executing step S5 after executing step S4. When the power grade is grade four, step S4 is re-executed to perform a second power grade detection.

[0080] S5: After determining the power level of the powered equipment, the control unit 1 drives the switch Q1 to turn off again through the output control unit 3; the specific turn-off process can be referred to step S1.

[0081] In summary, the PSE chip of the present invention realizes the characteristic resistance detection and power level detection of the powered device through the control unit 1, the input sampling unit 2 and the output control unit 3, which simplifies the structure of the PSE chip and reduces the area of ​​the PSE chip.

[0082] Example 3

[0083] This embodiment provides a method for driving a powered device. First, the power level of the powered device is determined by the powered device detection method in Embodiment 2. Then, the control unit 1 adjusts the voltage at the control terminal of the switch Q1 through the output control unit 3 according to the power level of the powered device, so that the power output by the power receiving interface reaches the power corresponding to the power level of the powered device.

[0084] Based on the above description, those skilled in the art can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A PSE chip, characterized in that, It includes a power receiving interface, a detection resistor, a switching transistor, an input sampling unit, a control unit, and an output control unit; the power receiving interface includes a positive interface and a negative interface; One end of the detection resistor is electrically connected to the input terminal of the switching transistor, the output terminal of the switching transistor is grounded, and the other end of the detection resistor is electrically connected to the negative interface. The input sampling unit is used to detect the voltage across the detection resistor and at one end of the detection resistor, and to input a voltage detection signal to the control unit; The control unit is electrically connected to the output control unit, and inputs a control signal to the output control unit based on the voltage detection signal. The output control unit responds to the control signal to control the voltage input to the control terminal of the switching transistor. The input sampling unit includes an analog-to-digital converter, a dual-channel selector, and a differential amplifier. The positive input terminal of the differential amplifier is electrically connected to the other end of the detection resistor, the negative input terminal of the differential amplifier is electrically connected to one end of the detection resistor, the output terminal of the differential amplifier and one end of the detection resistor are electrically connected to the two input terminals of the dual-channel selector, the output terminal of the dual-channel selector is electrically connected to the input terminal of the analog-to-digital converter, and the output terminal of the analog-to-digital converter is electrically connected to the control unit. The output control unit includes a digital-to-analog converter (DAC) and a second differential amplifier. The DAC is electrically connected to the control unit and receives the control signal. The output terminal of the DAC is connected to the negative input terminal of the second differential amplifier. The positive input terminal of the second differential amplifier is electrically connected to one end of the detection resistor. The output terminal of the second differential amplifier is electrically connected to the control terminal of the switching transistor.

2. The PSE chip according to claim 1, characterized in that, The switching transistor is an NMOS transistor, with the drain of the NMOS transistor being the input terminal, the source of the NMOS transistor being the output terminal, and the gate of the NMOS transistor being the control terminal.

3. A PSE chip according to claim 1, characterized in that, The control terminal of the switching transistor is also electrically connected to the output terminal of the switching transistor through resistor R2; the control terminal of the switching transistor is also electrically connected to the output terminal of the switching transistor through capacitor C1.

4. A method for testing electrical receiving equipment, characterized in that, This is achieved using the PSE chip described in claim 1. Includes the following steps: S1: When the PSE chip is powered on, the control unit controls the switching transistor to turn off through the output control unit and connects to the powered device; S2: Check whether the characteristic resistance of the powered device meets the requirements, as follows: S21: When the control unit detects that a powered device is connected, the control unit first adjusts the control terminal voltage of the switching transistor through the output control unit. During this process, when the control unit detects through the input sampling unit that the voltage difference between the positive interface and the negative interface reaches a preset first threshold voltage, it stops adjusting the control terminal voltage of the switching transistor. Next, the control unit first obtains the voltage across the detection resistor through the input sampling unit. The voltage across the detection resistor obtained at this time is recorded as the first detection voltage. The control unit calculates the detection current flowing through the detection resistor based on the first detection voltage and records the current flowing through the detection resistor as the first detection current. Then the control unit calculates the resistance value of the externally connected characteristic resistor based on the first threshold voltage and the first detection current, and determines whether the resistance value of the characteristic resistor meets the requirements. If it meets the requirements, step S22 is executed; if it does not meet the requirements, step S21 is ended and the detection is terminated. S22: The control unit first continues to adjust the control terminal voltage of the switching transistor through the output control unit until the voltage difference between the positive interface and the negative interface reaches the preset second threshold voltage; Next, the control unit obtains the voltage across the detection resistor through the input sampling unit. The voltage across the detection resistor obtained at this time is recorded as the second detection voltage. The control unit calculates the current flowing through the detection resistor based on the second detection voltage and records the calculated current flowing through the detection resistor as the second detection current. The control unit then calculates the resistance value of the externally connected characteristic resistor based on the second threshold voltage and the second detection current. And determine whether the calculated characteristic resistance value meets the requirements. If it meets the requirements, proceed to step S3; otherwise, end step S22 and end the detection. S3: The control unit drives the switching transistor to turn off through the output control unit, and executes step S4; S4: Determine the power level of the power receiving equipment, as follows: The control unit first adjusts the voltage at the control terminal of the switching transistor through the output control unit until the voltage difference between the positive interface and the negative interface reaches a preset third threshold voltage; Next, the control unit acquires the voltage across the detection resistor through the input sampling unit, calculates the current flowing through the detection resistor based on the voltage across the detection resistor at this time, and determines the power level of the powered device based on the current. S5: After determining the power level of the powered device, the control unit again drives the switch to turn off through the output control unit.

5. The method for detecting electrical receiving equipment according to claim 4, characterized in that, In steps S1, S3, and S5, the process by which the control unit controls the switching transistor to turn off through the output control unit is as follows: The control unit drives the analog-to-digital conversion unit to input the maximum analog voltage to the negative input terminal of the second differential amplifier unit; In step S2, the process by which the control unit adjusts the control terminal voltage of the switching transistor through the output control unit is as follows: the control unit drives the analog-to-digital conversion unit to adjust the magnitude of the analog voltage input to the negative input terminal of the second differential amplifier unit.

6. The method for detecting electrical receiving equipment according to claim 5, characterized in that, When executing step S22, if the number of executions of step S21 is less than the preset number of cycles, when the characteristic resistor value is determined to meet the requirements in step S4, the control unit first adjusts the control terminal voltage of the switching transistor through the output control unit until the voltage difference between the positive and negative interfaces reaches the preset first threshold voltage, and then executes step S21; if the number of executions of step S21 is equal to the set number of cycles, when the characteristic resistor value is determined to meet the requirements in step S4, step S3 is executed.

7. The method for detecting electrical receiving equipment according to claim 5, characterized in that, The power levels include level zero, level one, level two, level three, and level four; the current corresponding to level zero to level four gradually increases. The power level is determined before step S5 is executed. When the power level is level four, step S4 is executed again.

8. A method for driving an electrical receiving device, characterized in that, First, the power level of the power receiving device is determined by the power receiving device detection method according to any one of claims 5-7. Then, the control unit adjusts the control terminal voltage of the switching transistor according to the power level of the power receiving device through the output control unit so that the power output of the power receiving interface reaches the power corresponding to the power level of the power receiving device.

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