A server mainboard interface test tool and test method

Abstract

The application belongs to the technical field of server mainboard production testing, and discloses a server mainboard interface testing tool and testing method, which comprises a testing tool, the testing tool comprises a tool core plate, a Riser adapter card and an OCP adapter card, the Riser adapter card and the OCP adapter card both comprise a golden finger interface and a SlimSAS connector, and the Riser adapter card and the OCP adapter card are respectively used for transmitting the signals of the Riser interface and the OCP interface on the mainboard to be tested to the tool core plate; the testing tool can realize the testing of the interfaces on the mainboard to be tested by connecting the tool core plate, the Riser adapter card and the OCP adapter card to the corresponding interfaces on the mainboard to be tested through cables, and has the advantages of low cost and strong versatility.

Description

Technical Field

[0001] This invention relates to the field of server motherboard production testing technology, and more specifically, to a server motherboard interface testing fixture and testing method. Background Technology

[0002] In the research and development and production of servers, the motherboard under test (TBT) is the core framework of the entire server, carrying the interconnection functions of the central processing unit, memory, hard drive, and PCIe standard expansion cards. The reliability and stability of the TTB determine the reliability and stability of the entire server. To ensure the stable and reliable function and performance of the server, comprehensive functional and correctness testing of the external interface signals of the TTB is required before production and assembly.

[0003] Typically, server motherboard interfaces can be tested by installing corresponding components. For example, standard CPU and memory interfaces can be tested by directly installing them on the motherboard. This method is flexible and convenient; once the test is passed, the components don't need to be disassembled and can be directly installed into the chassis for the next production step. However, for some non-standard interfaces defined by the manufacturer on the motherboard, such as the SlimSAS interface for connecting NVMe SSDs, the Riser card interface for installing network cards and RAID cards, the I2C bus interface for basic BMC management, and the power interface for powering expansion boards, connecting functional boards and installing NVMe SSD components or network cards via Riser cards to form a complete functional link and complete machine before testing and judging becomes very complex. This results in low testing efficiency and high labor costs. If the test fails, the fault signal point cannot be directly located, and further laboratory SIT analysis is required for judgment, further reducing production efficiency. Moreover, NVMe SSDs and network cards are expensive and prone to damage with repeated disassembly and reassembly, which also increases the production cost of the production line to some extent.

[0004] To address the aforementioned issues, how to ensure the correctness and integrity of the external interface signals of the motherboard under test during the production process of the server motherboard under test through testing methods, thereby improving production efficiency and ensuring that product quality meets requirements, is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] To overcome the aforementioned deficiencies of the prior art, this invention provides a server motherboard interface testing fixture, comprising a core board, a Riser adapter card, and an OCP adapter card. Both the Riser and OCP adapter cards include gold finger interfaces and SlimSAS connectors. The Riser and OCP adapter cards are respectively used to transfer signals from the Riser and OCP interfaces on the motherboard under test to the core board. The integrated circuits on the core board include:

[0006] A PCIe switch circuit used for testing PCIe Lanes link signals in the SlimSAS interface, Riser interface, and OCP interface on the motherboard under test.

[0007] A power and ground test circuit used for testing power and ground signals in the external interfaces of the motherboard under test.

[0008] CPLD circuit used for testing sideband signals and I2C interface signals in the external interfaces of the motherboard under test;

[0009] A clock test circuit used for testing the 100MHz differential clock in the external interfaces of the motherboard under test.

[0010] The firmware for connecting to an external PC serial port and configuring the PCIe Switch chip, and the UART serial port circuit for reading the test results of the PCIe link signal of the motherboard under test.

[0011] A power conversion circuit used to convert the 12V power supply voltage obtained from the motherboard under test to power the core board of the tooling.

[0012] Preferably, the PCIe Switch circuit includes two PCIe Switch chips, namely PCIe Switch1 and PCIe Switch2.

[0013] Preferably, the power supply and ground test circuit includes an I / O expander.

[0014] Preferably, the clock test circuit includes an 8:1 differential multiplexer with dual output buffers and a differential-to-single-ended output amplifier.

[0015] A method for testing the interface of a server motherboard under test, which is implemented based on the aforementioned testing fixture for the interface of a server motherboard under test, includes the following specific testing steps:

[0016] S1: Fix the core board of the tooling fixture on the tooling fixture, and at the same time install the Riser adapter card and OCP adapter card on the Riser interface and OCP interface of the motherboard under test.

[0017] S2: According to the topology for implementing the interface testing function of the motherboard under test, connect the motherboard under test, the Riser adapter card, and the OCP adapter card to the tooling core board with cables including: connecting the SlimSAS interface of the motherboard under test to the SlimSAS interface of the tooling core board, connecting the SlimSAS interface on the Riser adapter card to the SlimSAS interface of the tooling core board, connecting the SlimSAS interface on the OCP adapter card to the SlimSAS interface of the tooling core board, connecting the I2C interface cable of the motherboard under test to the terminal block on the tooling core board, connecting the power interface cable of the motherboard under test to the terminal block on the tooling core board, and connecting the power interface cable of the motherboard under test to the power interface on the tooling core board.

[0018] S3: Connect the power supply to the motherboard under test. The motherboard under test will start up and wait for the POST self-test and PCIe bifurcation of the motherboard under test to be completed.

[0019] S4: Connect the GbE network port of the motherboard under test to the network port of the local PC, and use IPMI Command to open the NCSI sideband interface between the BMC management controller and the GbE network controller of the motherboard under test.

[0020] S5: By continuously polling the PXE function of the GbE network port of the motherboard under test, the functional test script loaded from the local PC is loaded into the memory of the motherboard under test for execution. The functional test script uses Chiplink Tool Command and OS Command to determine the connectivity and correctness of the PCIe Lanes link signals of each interface under test. At the same time, the IMPItool tool is used in conjunction with IPMICommand to read and determine the connectivity and correctness of the signals of each interface on the motherboard under test through the I2C interface. After the test is completed, the overall test results are generated and compared with the expected results.

[0021] S6: Check the test results of all signals of each interface on each motherboard under test, and judge the test results of each interface test item. If all interfaces and all test items are PASS, it means that the test is passed and the signals of each interface on the motherboard under test are normal. If some test items of a certain interface on the motherboard under test are FAIL, it means that the test is failed and there is an abnormality in the signal of that interface on the motherboard under test.

[0022] S7: Determine the abnormality of the external interfaces on the motherboard under test based on the test content corresponding to the FAIL item. The external interfaces include SlimSAS interface, Riser interface, OCP interface, I2C interface and Power interface.

[0023] Preferably, if the PCIe B / D / F Number of a certain item is displayed incorrectly, the specific PCIe Lane link signal in the SlimSAS interface, Riser interface, and OCP interface of the motherboard under test can be determined to be abnormal based on the PCIe connection relationship corresponding to this B / D / F Number.

[0024] Preferably, if a power supply and ground test result is incorrect, the corresponding relationship between the pins of the I / O expander and the test signals can be used to determine which power connector and external interface power signal of the motherboard under test is abnormal.

[0025] Preferably, if the differential clock signal of a certain item is displayed incorrectly, the differential clock signal of the external interface of the motherboard under test can be determined by reading which differential signal the CPLD is currently detecting based on the I2C.

[0026] Preferably, if a certain sideband signal is displayed incorrectly, by reading the current sideband signal detected by the CPLD via I2C, it can be determined which external interface sideband signal of the motherboard under test is abnormal.

[0027] Preferably, the specific test method for the power supply and ground test circuit includes:

[0028] Connect the power and ground signals of the external interfaces on the motherboard under test, as well as the I2C interface signals, to the core board of the tooling via cables.

[0029] The 12V power signal and ground signal are isolated and converted before being connected to the I / O expander;

[0030] The voltage of each port of the I / O expander is read through the I2C bus to determine whether the power and ground signals in the external interfaces of the motherboard under test are normal.

[0031] Preferably, the specific testing method for the clock test circuit includes:

[0032] During testing, the CPLD controls the selection pin of the 8:1 differential multiplexer, and outputs each differential clock signal under test in a time sequence according to the correspondence of the multiplexer input truth table.

[0033] The output differential clock signal under test is then converted into a single-ended signal by a differential-to-single-ended output amplifier and input to the clock pin of the CPLD.

[0034] After frequency division, a synchronization clock is generated by synchronizing with the CPLD's master clock, and then it is determined whether the rising edge of the synchronization clock has changed.

[0035] If a jump occurs, the CPLD detects the clock as normal, indicating that the 100M differential clock is normal.

[0036] If no transition occurs, the CPLD detects a clock anomaly and determines that the 100M differential clock is faulty.

[0037] Preferably, the CPLD test measures the JATG, PERST, WAKE_N, PRSNT, and sideband signals in the SlimSAS, Riser, and OCP interfaces of the motherboard under test. The specific test method is as follows:

[0038] Read the level status of the sideband signal input to the CPLD pin, and compare the level status of the sideband signal input to the CPLD pin with the preset level threshold to determine whether it is normal;

[0039] If the level of the sideband signal input to the CPLD pin is within the preset level threshold, it is considered normal;

[0040] If the level of the sideband signal input to the CPLD pin exceeds or falls below the preset level threshold, it is judged as abnormal.

[0041] The technical effects and advantages of the server motherboard interface testing fixture and testing method of the present invention are as follows:

[0042] 1. By concentrating the signal testing of the external interfaces of the motherboard under test on the tooling core board, and using functional devices such as PCIe Switch, CPLD, and PCA9535 to test the signals of the SlimSAS interface, power interface, I2C interface, and OCP interface of the motherboard under test, the interface testing on the motherboard under test can be achieved by connecting the tooling core board, Riser adapter card, and OCP adapter card to the corresponding interfaces on the motherboard under test through cables. This method is low-cost and highly versatile.

[0043] 2. By using a simple, reliable, and efficient method to quickly and accurately determine the correctness and integrity of the external interface signals of the motherboard under test on the production line, this method solves the problems of complex operation procedures, low testing efficiency, and high labor costs caused by the use of expensive components after connecting functional boards to form a complete link in traditional external interface testing methods for motherboards under test.

[0044] 3. The testing method is low-cost and highly integrated, and can be quickly deployed on the production line and used repeatedly for testing, which greatly improves production efficiency and ensures that product quality meets factory requirements. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the overall structure of the test fixture of the present invention;

[0046] Figure 2 This is a schematic diagram showing the connection between the tooling core board, Riser adapter card, OCP adapter card, and external interface with the motherboard under test of this invention.

[0047] Figure 3 This is a functional schematic diagram of the tooling core board of the present invention;

[0048] Figure 4 This is a schematic diagram of the Riser adapter card structure of the present invention;

[0049] Figure 5 This is a schematic diagram of the OCP adapter card structure of the present invention;

[0050] Figure 6 This is a flowchart of the testing process for this invention;

[0051] Figure descriptions: 1. Tooling fixture; 2. Tooling core board; 3. Riser adapter card; 4. OCP adapter card. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] This invention provides, for example Figure 1-6 The diagram shows a server motherboard under test interface testing fixture, which is used to perform signal testing on the external interfaces of the server motherboard under test. The server motherboard under test is referred to as the motherboard under test below. The testing fixture includes a fixture core board 2, a Riser adapter card 3, and an OCP adapter card 4. The fixture core board 2 has integrated circuits including a PCIe Switch circuit, a power and ground test circuit, a CPLD circuit, a clock test circuit, a UART serial port circuit, and a power conversion circuit. The integrated circuits on the fixture core board 2 are electrically connected to a SlimSAS interface, an I2C interface, and a power interface. The fixture core board 2 is mounted on a fixture fixture 1. During testing, the motherboard under test can be placed on the fixture fixture 1.

[0054] Specifically, the external interfaces of the motherboard under test include SlimSAS interface, Riser card interface, OCP interface, I2C interface, and Power interface. Each type of interface has multiple signals. It is inconvenient to test the external interface signals of the motherboard under test directly. Therefore, different cables are needed to bring all the signals of the external interfaces of the motherboard under test to the test core board 2 to complete the test. Among them, the SlimSAS interface of the motherboard under test is a high-speed signal interface and can be directly brought to the SlimSAS interface of the test core board through the SlimSAS cable.

[0055] More specifically, such as Figure 3As shown, the PCIe Switch circuit is used to test the PCIe Lanes link signals in the SlimSAS interface, Riser interface, and OCP interface on the motherboard under test. The power and ground test circuit is used to test the power and ground signals in the external interfaces of the motherboard under test. The CPLD circuit is used to test the sideband signals and I2C interface signals in the external interfaces of the motherboard under test. The clock test circuit is used to test the 100MHz differential clock in the external interfaces of the motherboard under test. The UART serial port circuit is used to connect to the computer serial port to read the test results of the PCIe link signals of the motherboard under test. The power conversion circuit is used to convert the 12V power supply from the motherboard under test to 5V, 3V3, 1V8, and 0.9V voltages for use by other test circuits on the fixture board. The specific conversion voltage is set by those skilled in the art according to the actual application requirements.

[0056] Furthermore, the PCIe Switch circuit has two PCIe Switch chips, namely PCIe Switch1 and PCIe Switch2. In this embodiment, the PCIe Switch chip is PM8536B, and each chip has 96 PCIe Lanes and 48 Ports, corresponding to CPU1 and CPU2 in the test.

[0057] Furthermore, the x8 SlimSAS PCIe Lanes interface of CPU1 is connected to the x8 SlimSAS PCIe Lanes interface of PCIe Switch1. The x16 OCP PCIe Lanes interface of CPU1 is split into two x8 PCIe Lanes interfaces after passing through the OCP adapter card and connected to the x8 SlimSAS PCIe Lanes interface of PCIe Switch1. The x32 Riser PCIe Lanes interface of CPU1 is split into four x8 PCIe Lanes interfaces after passing through the Riser adapter card and connected to the x8 SlimSAS PCIe Lanes interface of PCIe Switch1. Similarly, the x8 SlimSAS PCIe Lanes interface of CPU2 is connected to the x8 SlimSAS PCIe Lanes interface of PCIe Switch2. The x32 Riser PCIe Lanes interface of CPU2 is split into four x8 PCIe Lanes interfaces after passing through the Riser adapter card and connected to the x8 SlimSAS PCIe Lanes interface of PCIe Switch2.

[0058] It should be noted that the SlimSAS interfaces on the core board 2 are all x8 PCIe. Therefore, the PCIe ports of the PCIeSwitch chips need to be allocated. Before testing, the firmware of the PCIe Switch chips was configured using a configuration tool via a serial port circuit. Based on the physical connection relationship, 64 PCIe Lanes of PCIe Switch1 and PCIe Switch2 chips were configured as 8 uplink ports, each port being an x8 PCIe Lane, connected to the x8 width SlimSAS interface. Since each uplink port of the PCIe Switch requires a corresponding downlink port, the remaining 32 PCIe Lanes of each chip of PCIe Switch1 and PCIe Switch2 also need to be configured as 8 downlink ports, each port being an x4 PCIe Lane. They are not physically connected and are used as the downlink ports corresponding to the uplink ports.

[0059] In this embodiment, the power and ground test circuit functions are implemented by multiple low-power I / O expanders with I2C bus. In this embodiment, the PCA9535 is used on the tooling core board 2 to complete the judgment of voltage and ground signals. The PCA9535 is a multi-functional chip with multiple functions and characteristics. Those skilled in the art can design a system based on the PCA9535 to complete the judgment of voltage and ground signals.

[0060] Specifically, the test method for the power and ground test circuit is as follows: First, the power signal, ground signal, and I2C interface signal of the motherboard under test are transmitted to the core board 2 of the test fixture via cables. Then, the 12V power signal and ground signal are isolated and converted before being connected to the I / O ports of each PCA9535. The normal 12V power signal becomes a low voltage after being isolated and converted by MOSFET, and the abnormal 12V power signal becomes a high voltage of 3.3V after being isolated and converted by MOSFET. The normal ground signal remains a low voltage after being converted by voltage divider, and the abnormal ground signal becomes a high voltage of 3.3V after being converted by voltage divider. Then, the voltage of each port of the PCA9535 is read through the I2C bus to determine whether the power and ground signals in the external interface of the motherboard are normal.

[0061] The clock test circuit consists of an 8:1 differential multiplexer with dual output buffers and a differential-to-single-ended output amplifier. Since each SlimSAS interface on the motherboard under test has a 100MHz differential clock, and a differential-to-single-ended output amplifier can only detect one differential clock signal at the same time, in order to reduce the number of differential-to-single-ended output amplifier chips, an 8:1 differential multiplexer is used on the tooling core board 2 to select the differential clock signal of the SlimSAS interface of the motherboard under test.

[0062] During testing, the CPLD controls the three selection pins of the 8:1 differential multiplexer. Each differential clock signal under test is output sequentially according to the truth table of the multiplexer inputs. The output differential clock signal is then converted to a single-ended signal by a differential-to-single-ended output amplifier before being input to the CPLD's clock pin. After frequency division, it is synchronized with the CPLD's master clock to generate a synchronous clock. The rising edge of the synchronous clock is then checked for a transition. If a transition occurs, the CPLD detects a normal clock, indicating that the 100M differential clock is normal. If no transition occurs, the CPLD detects an abnormal clock, indicating that the 100M differential clock is abnormal.

[0063] Furthermore, in this embodiment, the CPLD is the control core of the entire fixture core board 2, playing a crucial role. Besides providing power-on reset and selection control functions to the fixture core board 2, the CPLD test circuit is also used to test the sideband signals of the JATG, PERST, WAKE_N, and PRSNT signals in the SlimSAS, Riser card, and OCP interfaces on the motherboard under test. These sideband signals are introduced from the external interfaces of the motherboard under test to the fixture core board 2 via cables, and finally connected to the CPLD's GPIO port. During testing, the level of the sideband signals input to the CPLD pins is read via I2C to determine whether the currently tested signal is normal.

[0064] The specific testing method is as follows: Read the level of the sideband signal input to the CPLD pin, and compare the level of the sideband signal input to the CPLD pin with a preset level threshold to determine whether it is normal. The preset level threshold is obtained by those skilled in the art based on test data. If the level of the sideband signal input to the CPLD pin is within the preset level threshold, it is considered normal. If the level of the sideband signal input to the CPLD pin exceeds or falls below the preset level threshold, it is considered abnormal. Under normal circumstances, the sideband signal should vary within the expected level range, such as switching between high level (usually VCC voltage) and low level (usually GND voltage). Under abnormal circumstances, the sideband signal may exhibit unstable level, level exceeding the expected range, or remain at a certain level. Check the signal source: Ensure that the source of the sideband signal (e.g., sensor, external device, etc.) is working properly and providing the correct signal. If the signal source malfunctions or provides an incorrect signal, the sideband signal on the CPLD pin may be affected.

[0065] It is worth mentioning that since there are two PCIe Switch chips, there are also two UART serial port circuits, which are led out from the serial port interfaces of PCIe Switch1 and PCIe Switch2 chips respectively. After RS232 level conversion, they can be connected to the computer's serial port through a three-core serial cable. This is used to configure the firmware of the PCIe Switch chip and read the communication status of the PCIe Lanes signal. The configured firmware can be burned into the flash of the PCIe Switch through this serial port circuit, making firmware update operation relatively convenient. The current test PCIe Lanes connection status and communication information can also be obtained through this serial port circuit.

[0066] Additionally, it should be noted that in this embodiment, the core board 2 of the fixture does not have an additional power supply. All power is drawn from the motherboard under test, implemented using a power conversion circuit. The power conversion circuit is connected to the power connector on the motherboard under test via a power line to obtain 12V voltage. The voltage is then converted by the power conversion circuit to supply power to all test circuits on the core board 2. The power conversion circuit employs a step-down circuit based on Switch Mode Power Supply (SMPS) technology. Voltage conversion is achieved by controlling the switching state and duty cycle of the switching elements. This involves inductors, diodes, capacitors, switching elements, and control circuits (e.g., PWM controllers). The 12V input voltage is connected to the input terminal of the circuit. The inductor and diode are connected to form an inductor-diode (LC) filter to smooth the output voltage. The switching elements are connected to the circuit to control the current flow. The switching state and duty cycle of the switching elements can be controlled by the PWM controller. The capacitor is connected to the output terminal of the switching elements to further smooth the output voltage. The load is connected to the output terminal of the circuit. The specific circuit connections are known and publicly available technologies and will not be elaborated upon here.

[0067] like Figure 2 , Figure 3 and Figure 4 As shown, the Riser adapter card includes gold fingers and a SlimSAS connector. The gold fingers are used to connect to the Riser interface on the motherboard under test. The Riser card interface signal is output from the SlimSAS connector through the gold fingers and then connected to the SlimSAS interface on the core board 2 of the fixture through a cable, thus playing a signal conversion role. Specifically, in this embodiment, the gold fingers of the Riser adapter card adopt an x32 width gold finger interface and four x8 SlimSAS interfaces. The x32 width gold fingers are matched with the Riser card interface of the motherboard under test, which can introduce the Riser card interface signal into the x8 SlimSAS interface, and then be converted to the core board 2 of the fixture through the SlimSAS cable for testing.

[0068] like Figure 2 , Figure 3 and Figure 5 As shown, the OCP adapter card includes gold fingers and a SlimSAS connector. The gold fingers are used to connect to the OCP interface on the motherboard under test. The OCP card interface signal is output from the SlimSAS connector through the gold fingers and then connected to the SlimSAS interface on the core board 2 of the fixture through a cable, thus playing a signal conversion role. Specifically, in this embodiment, the gold fingers of the OCP adapter card adopt x16 width gold fingers and two x8 SlimSAS interfaces. The x16 width gold fingers are matched with the OCP card interface of the motherboard under test and are used to introduce the OCP card interface signal of the motherboard under test into the x8 SlimSAS interface, and then connect to the core board 2 of the fixture through the SlimSAS cable for testing.

[0069] It's worth noting that the SlimSAS connector is a high-density, small-size connector commonly used in high-speed data transmission and storage systems. Adhering to the SlimSAS standard, it features a 0.60 mm pitch, providing high-speed signal transmission and reliable connection performance.

[0070] like Figure 6 As shown, a test method for a server motherboard interface is implemented based on the aforementioned server motherboard interface test fixture. The specific test steps include:

[0071] S1: Fix the tooling core board (2) on the tooling fixture (1), and at the same time install the Riser adapter card (3) and OCP adapter card (4) on the Riser interface and OCP interface of the motherboard under test.

[0072] S2: According to the topology of the motherboard under test interface test function, connect the motherboard under test, Riser adapter card (3) and OCP adapter card (4) to the tooling core board (2) with the following cables: connecting the SlimSAS interface of the motherboard under test to the SlimSAS interface of the tooling core board (2), connecting the SlimSAS interface of the Riser adapter card (3) to the SlimSAS interface of the tooling core board (2), connecting the SlimSAS interface of the OCP adapter card (4) to the SlimSAS interface of the tooling core board (2), connecting the I2C interface cable of the motherboard under test to the terminal block of the tooling core board (2), connecting the power interface cable of the motherboard under test to the terminal block of the tooling core board (2), and connecting the power interface cable of the motherboard under test to the power interface of the tooling core board (2).

[0073] S3: Connect the power supply to the motherboard under test. The motherboard under test will start up and wait for the POST self-test and PCIe bifurcation of the motherboard under test to be completed.

[0074] S4: Connect the GbE network port of the motherboard under test to the network port of the local PC. Use IPMI Command to open the NCSI sideband interface between the BMC management controller and the GbE network controller of the motherboard under test. IPMI Command is a set of commands for remote management and control of server platforms. It allows users to remotely monitor system health, obtain information, and perform various management tasks. IPMI Command can be executed through IPMI tools (such as IPMItool). Using IPMI commands, servers can be easily managed and monitored.

[0075] S5: By continuously polling the PXE function of the GbE network port of the motherboard under test, the functional test script loaded from the local PC is loaded into the memory of the motherboard under test for execution. The functional test script uses Chiplink Tool Command and OS Command to determine the connectivity and correctness of the PCIe Lanes link signals of each interface under test. At the same time, the IMPItool tool is used in conjunction with IPMICommand to read and determine the connectivity and correctness of the signals of each interface on the motherboard under test through the I2C interface. After the test is completed, the overall test results are generated and compared with the expected results.

[0076] S6: Check the test results of all signals of each interface on each motherboard under test. Different interfaces have different signal types, such as PCIe, power, clock, sideband, I2C, etc. According to the output of the test script and test tool in step five, determine the test results of each interface test item. If all interfaces and all test items are PASS, it means that the test is passed and the signals of each interface on the motherboard under test are normal. If some test items of a certain interface on the motherboard under test are FAIL, it means that the test is failed and there is an abnormality in the signal of that interface on the motherboard under test.

[0077] S7: Determine the abnormality of the external interfaces on the motherboard under test based on the test content corresponding to the FAIL item. The external interfaces include SlimSAS interface, Riser interface, OCP interface, I2C interface and Power interface.

[0078] It should be noted that, in this embodiment, if the PCIe B / D / F Number is displayed incorrectly, the specific PCIe Lane link signal in the SlimSAS interface, Riser interface, and OCP interface of the motherboard under test can be determined based on the PCIe connection relationship corresponding to this B / D / F Number. If the power and ground test is displayed incorrectly, the power connector and external interface power signal of the motherboard under test can be determined based on the pin-to-test signal correspondence of the I / O expander. If the differential clock signal is displayed incorrectly, the differential signal detected by the CPLD at the time of I2C reading can be determined to be the differential clock signal of the external interface of the motherboard under test that is abnormal. If the sideband signal is displayed incorrectly, the sideband signal detected by the CPLD at the time of I2C reading can be determined to be the sideband signal of the external interface of the motherboard under test that is abnormal.

[0079] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0080] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for testing the interface of a server motherboard under test, which is based on a testing fixture for the interface of a server motherboard under test, characterized in that, The test fixture includes a fixture core board, a Riser adapter card, and an OCP adapter card. The Riser adapter card and the OCP adapter card are used to transfer the Riser interface and OCP interface signals on the motherboard under test to the fixture core board, respectively. The integrated circuits on the fixture core board include a PCIe Switch circuit, a power and ground test circuit, a CPLD circuit, a clock test circuit, a UART serial port circuit, and a power conversion circuit. The specific testing steps include: S1: Fix the core board of the tooling fixture on the tooling fixture, and at the same time install the Riser adapter card and OCP adapter card on the Riser interface and OCP interface of the motherboard under test. S2: According to the topology for implementing the interface testing function of the motherboard under test, connect the motherboard under test, the Riser adapter card, and the OCP adapter card to the core board of the fixture, including: connecting the SlimSAS interface of the motherboard under test, the SlimSAS interface on the Riser adapter card, and the SlimSAS interface on the OCP adapter card to the SlimSAS interface on the core board of the fixture; connecting the I2C interface cable of the motherboard under test and the Power interface cable of the motherboard under test to the terminal block on the core board of the fixture; and connecting the Power interface cable of the motherboard under test to the Power interface on the core board of the fixture. S3: Connect the power supply to the motherboard under test. The motherboard under test will start up and wait for the POST self-test and PCIefiurcation of the motherboard under test to be completed. S4: Connect the GbE network port of the motherboard under test to the network port of the local PC, and use IPMI Command to open the NCSI sideband interface between the BMC management controller and the GbE network controller of the motherboard under test. S5: By continuously polling the PXE function of the GbE network port of the motherboard under test, the functional test script loaded from the local PC is loaded into the memory of the motherboard under test for execution. The functional test script uses Chiplink Tool Command and OS Command to determine the connectivity and correctness of the PCIe Lanes link signals of each interface under test. At the same time, the IMPItool tool is used in conjunction with IPMICommand to read and determine the connectivity and correctness of the signals of each interface on the motherboard under test through the I2C interface. After the test is completed, the overall test results are generated and compared with the expected results. S6: Check the test results of all signals of each interface on each motherboard under test, and judge the test results of each interface test item. If all interfaces and all test items are PASS, it means that the test is passed and the signals of each interface on the motherboard under test are normal. If some test items of a certain interface on the motherboard under test are FAIL, it means that the test is failed and there is an abnormality in the signal of that interface on the motherboard under test. S7: Determine the abnormality of the external interfaces on the motherboard under test based on the test content corresponding to the FAIL item. The external interfaces include SlimSAS interface, Riser interface, OCP interface, I2C interface and Power interface.

2. The server motherboard interface testing method according to claim 1, characterized in that, If a PCIe B / D / F Number is displayed incorrectly, the specific PCIe Lane link signal in the SlimSAS interface, Riser interface, or OCP interface of the motherboard under test can be determined based on the PCIe connection relationship corresponding to this B / D / F Number.

3. The server motherboard interface testing method according to claim 1, characterized in that, Both the Riser adapter card and the OCP adapter card include a gold finger interface and a SlimSAS connector. The PCIe Switch circuit is used to test the PCIeLanes link signals in the SlimSAS interface, Riser interface, and OCP interface on the motherboard under test. The power and ground test circuit is used to test the power and ground signals in the external interfaces of the motherboard under test. The CPLD circuit is used to test the sideband signals and I2C interface signals in the external interfaces of the motherboard under test. The clock test circuit is used to test the 100MHz differential clock in the external interface of the motherboard under test; The UART serial port circuit is used to connect to an external PC serial port, configure the firmware of the PCIe Switch chip, and read the test results of the PCIe link signal of the motherboard under test. The power conversion circuit is used to convert the 12V power supply voltage obtained from the motherboard under test and to supply power to the tooling core board.

4. A method for testing the interface of a server motherboard under test according to claim 3, characterized in that, The PCIe Switch circuit includes two PCIe Switch chips, namely PCIe Switch1 and PCIe Switch2. The power and ground test circuit includes an I / O expander. The clock test circuit includes an 8:1 differential multiplexer with dual output buffers and a differential-to-single-ended output amplifier.

5. A method for testing the interface of a server motherboard under test according to claim 4, characterized in that, If a power and ground test result is incorrect, the pin correspondence between the I / O expander and the test signal can be used to determine which power connector and external interface power signal on the motherboard under test is abnormal.

6. A method for testing the interface of a server motherboard under test according to claim 3, characterized in that, If the differential clock signal of a certain item is displayed incorrectly, by reading which differential signal the CPLD is currently detecting through I2C, it can be determined which external interface differential clock signal of the motherboard under test is abnormal.

7. A method for testing the interface of a server motherboard under test according to claim 3, characterized in that, If a certain sideband signal is displayed incorrectly, by reading which sideband signal the CPLD is currently detecting through I2C, it can be determined which external interface sideband signal of the motherboard under test is abnormal.

8. A method for testing the interface of a server motherboard under test according to claim 3, characterized in that, The specific test methods for the power supply and ground test circuits include: Connect the power and ground signals of the external interfaces on the motherboard under test, as well as the I2C interface signals, to the core board of the tooling via cables. The 12V power signal and ground signal are isolated and converted before being connected to the I / O expander; The voltage of each port of the I / O expander is read through the I2C bus to determine whether the power and ground signals in the external interfaces of the motherboard under test are normal.

9. A method for testing the interface of a server motherboard under test according to claim 3, characterized in that, The specific testing methods for the clock test circuit include: During testing, the CPLD controls the selection pin of the 8:1 differential multiplexer, and outputs each differential clock signal under test in a time sequence according to the correspondence of the multiplexer input truth table. The output differential clock signal under test is then converted into a single-ended signal by a differential-to-single-ended output amplifier and input to the clock pin of the CPLD. After frequency division, a synchronization clock is generated by synchronizing with the CPLD's master clock, and then it is determined whether the rising edge of the synchronization clock has changed. If a jump occurs, the CPLD detects the clock as normal, indicating that the 100M differential clock is normal. If no transition occurs, the CPLD detects a clock anomaly and determines that the 100M differential clock is faulty.

10. A method for testing the interface of a server motherboard under test according to claim 3, characterized in that, The CPLD test measures the JATG, PERST, WAKE_N, PRSNT, and sideband signals in the SlimSAS, Riser, and OCP interfaces of the motherboard under test. The specific test method is as follows: Read the level status of the sideband signal input to the CPLD pin, and compare the level status of the sideband signal input to the CPLD pin with the preset level threshold to determine whether it is normal; If the level of the sideband signal input to the CPLD pin is within the preset level threshold, it is considered normal; If the level of the sideband signal input to the CPLD pin exceeds or falls below the preset level threshold, it is judged as abnormal.

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