Display panel and image display method

Abstract

An image display method includes: setting, by a driving circuit and a plurality of data buffers, a plurality of first driving voltages of a first row of a plurality of pixel units according to a first driving signal; and setting, by the driving circuit and the plurality of data buffers, a plurality of second driving voltages of a second row of the plurality of pixel units according to a second driving signal. The method of setting the plurality of second driving voltages of the second row of the plurality of pixel units includes: when one of the plurality of second driving voltages is the same as one of the plurality of first driving voltages, and both correspond to a same one of the plurality of data buffers, disabling an input end of the same one of the plurality of data buffers, so that the same one of the plurality of data buffers maintains the one of the plurality of first driving voltages as the one of the plurality of second driving voltages.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to image display technology, and in particular, to an image display method and a display panel. BACKGROUND

[0002] With the rapid development of electronic technology, display devices have been widely used in people's lives, such as smart phones or computers. The display device controls the brightness of each pixel on the display panel to present the corresponding image. The update method of the display device for the image screen will also affect its display quality. SUMMARY

[0003] The present disclosure relates to an image display method, comprising: setting, by a driving circuit and a plurality of data buffers, a plurality of first driving voltages of a first row of a plurality of pixel units according to a first driving signal, wherein the driving circuit is coupled to the plurality of pixel units through the plurality of data buffers; and setting, by the driving circuit and the plurality of data buffers, a plurality of second driving voltages of a second row of the plurality of pixel units according to a second driving signal, wherein the method of setting the plurality of second driving voltages of the second row of the plurality of pixel units comprises: when one of the plurality of second driving voltages and one of the plurality of first driving voltages are the same, and both correspond to the same one of the plurality of data buffers, disabling the input end of the same one of the plurality of data buffers to maintain the one of the plurality of first driving voltages as the one of the plurality of second driving voltages.

[0004] In an embodiment of the above-mentioned method of the present disclosure, the plurality of first driving voltages are used to control a plurality of first pixel values of the first row of the plurality of pixel units, the plurality of second driving voltages are used to control a plurality of second pixel values of the second row of the plurality of pixel units, and the method of providing the plurality of second driving voltages to the second row of the plurality of pixel units further comprises:

[0005] According to the second driving signal, outputting a part of the plurality of second driving voltages to a part of the plurality of data buffers, wherein at least one of the plurality of first pixel values corresponding to the part of the plurality of data buffers is different from at least one of the plurality of second pixel values corresponding to the part of the plurality of data buffers.

[0006] In an embodiment of the above-mentioned method of the present disclosure, the method of outputting the part of the plurality of second driving voltages to the part of the plurality of data buffers comprises:

[0007] According to a scan address in the second driving signal, driving a scan line corresponding to the second row of the plurality of pixel units;

[0008] identifying one of the plurality of data buffers as an update starting point according to an update starting address in the second driving signal;

[0009] outputting the portion of the plurality of second driving voltages to the portion of the plurality of data buffers according to an update data in the second driving signal; and

[0010] outputting the portion of the plurality of second driving voltages to the portion of the plurality of data buffers according to an update data in the second driving signal; and

[0011] In an embodiment of the above method of the present application, the method of outputting the portion of the plurality of second driving voltages to the portion of the plurality of data buffers comprises:

[0012] disabling the plurality of shift registers in the driving circuit when the outputting of the portion of the plurality of second driving voltages exceeds an update time in the second driving signal.

[0013] In an embodiment of the above method of the present application, the driving circuit comprises a plurality of shift registers, outputs of the plurality of shift registers are coupled to control terminals of the plurality of data buffers, and the method of outputting the portion of the plurality of second driving voltages to the portion of the plurality of data buffers comprises:

[0014] enabling one of a plurality of control logic components to identify the one of the plurality of data buffers as the update starting point, wherein the plurality of control logic components are coupled between the plurality of shift registers.

[0015] In an embodiment of the above method of the present application, the method of outputting the portion of the plurality of second driving voltages to the portion of the plurality of data buffers further comprises:

[0016] enabling one of a plurality of control logic components to identify the one of the plurality of data buffers as the update starting point, wherein the plurality of control logic components are coupled between the plurality of shift registers.

[0017] In an embodiment of the above method of the present application, the plurality of control logic components comprise a plurality of OR gates, and the plurality of switching logic components comprise a plurality of AND gates.

[0018] In an embodiment of the above method of the present application, the plurality of pixel units are divided into a plurality of rows according to a plurality of scan lines, and the image display method further comprises:

[0019] receiving an original image data by a processor, wherein the processor is communicatively connected to the driving circuit, and the original image data comprises a plurality of pixel values corresponding to the plurality of rows of the plurality of scan lines; and

[0020] comparing differences between the first pixel values corresponding to the first row of the first pixel units and the second pixel values corresponding to the second row of the first pixel units to generate the first driving signal and the second driving signal.

[0021] In an embodiment of the above-mentioned method of the present disclosure, the image display method further comprises:

[0022] comparing the pixel values corresponding to the multiple rows of the scan lines to set the first row and the second row of the first pixel units.

[0023] In an embodiment of the above-mentioned method of the present disclosure, the method of comparing the pixel values corresponding to the multiple rows of the scan lines comprises:

[0024] calculating a plurality of difference values between the pixel values corresponding to the multiple rows of the scan lines;

[0025] ranking each row of the pixel values according to the plurality of difference values; and

[0026] setting the first row and the second row of the first pixel units according to a ranking result of each row of the pixel values.

[0027] The present disclosure also relates to a display panel comprising a pixel circuit, a temporary storage circuit, and a driving circuit. The pixel circuit comprises a plurality of pixel units, wherein the plurality of pixel units are divided into multiple rows according to a plurality of scan lines. The temporary storage circuit comprises a plurality of data buffers, wherein the plurality of data buffers are coupled to the plurality of pixel units through a plurality of data lines. The driving circuit is coupled to the temporary storage circuit and the plurality of scan lines, to set a plurality of first driving voltages of a first row of the plurality of pixel units through the plurality of data buffers. The driving circuit is also to set a plurality of second driving voltages of a second row of the plurality of pixel units through the plurality of data buffers. When one of the plurality of second driving voltages is identical to one of the plurality of first driving voltages, and both correspond to a same one of the plurality of data buffers, the driving circuit does not output the one of the plurality of second driving voltages, and the same one of the plurality of data buffers maintains the one of the plurality of first driving voltages as the one of the plurality of second driving voltages.

[0028] In an embodiment of the above-mentioned display panel of the present disclosure, the plurality of first driving voltages are to control a plurality of first pixel values of the first row of the plurality of pixel units, and the plurality of second driving voltages are to control a plurality of second pixel values of the second row of the plurality of pixel units.

[0029] wherein the driving circuit is to receive a first driving signal and a second driving signal, and output a part of the plurality of second driving voltages to a part of the plurality of data buffers according to the second driving signal; and

[0030] wherein at least one of the plurality of first pixel values corresponding to the portion of the plurality of data buffers is different from at least one of the plurality of second pixel values corresponding to the portion of the plurality of data buffers.

[0031] In an embodiment of the above-mentioned display panel of the present application, the second driving signal further comprises:

[0032] a scan address, wherein the driving circuit is configured to drive one of the plurality of scan lines according to the scan address;

[0033] an update start address, wherein the driving circuit is configured to identify one of the plurality of data buffers according to the update start address; and

[0034] an update data, wherein the driving circuit is configured to output the portion of the plurality of second driving voltages according to the update data.

[0035] wherein the driving circuit is further configured to sequentially output the portion of the plurality of second driving voltages to the portion of the plurality of data buffers starting from the one of the plurality of data buffers as an update start point.

[0036] In an embodiment of the above-mentioned display panel of the present application, the second driving signal further comprises an update time, wherein the driving circuit is configured to disable the plurality of shift registers in the driving circuit when the update time is exceeded while the driving circuit sequentially outputs the portion of the plurality of second driving voltages to the portion of the plurality of data buffers.

[0037] In an embodiment of the above-mentioned display panel of the present application, the driving circuit comprises:

[0038] a shift register circuit comprising a plurality of shift registers, wherein a plurality of outputs of the plurality of shift registers are coupled to a plurality of control terminals of the plurality of data buffers, and the plurality of shift registers are connected through a plurality of control logic components;

[0039] a logic circuit comprising a plurality of switching logic components, wherein a plurality of outputs of the plurality of switching logic components are coupled to a plurality of inputs of the plurality of control logic components; and

[0040] a decoding circuit coupled to the plurality of switching logic components and configured to receive the first driving signal and the second driving signal.

[0041] In an embodiment of the above-mentioned display panel of the present application, the plurality of control logic components comprise a plurality of OR gates.

[0042] In an embodiment of the above-mentioned display panel of the present application, the plurality of switching logic components comprise a plurality of AND gates.

[0043] In an embodiment of the display panel according to the present disclosure, the second driving signal further comprises an update start address and an update data, the decoding circuit is configured to identify one of the plurality of control logic components according to the update start address, to take a corresponding one of the plurality of data buffers as an update start point, and to sequentially output the part of the plurality of second driving voltages to the part of the plurality of data buffers according to the update data.

[0044] In an embodiment of the display panel according to the present disclosure, the second driving signal further comprises an update time, when the driving circuit sequentially outputs the part of the plurality of second driving voltages to the part of the plurality of data buffers, the driving circuit is configured to provide a disable signal to the plurality of shift registers when the update time is exceeded.

[0045] In an embodiment of the display panel according to the present disclosure, the decoding circuit further comprises:

[0046] an address resolving circuit coupled to the logic circuit and configured to enable one of the plurality of switching logic components according to the update start address; and

[0047] a data generating circuit coupled to the temporary storage circuit and configured to output the part of the plurality of second driving voltages according to the second driving signal.

[0048] By selectively writing the driving voltages to be updated to the part of the data buffers, and using the original driving voltages corresponding to the same pixel values in the part of the data buffers, the update speed of the display panel can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 A schematic diagram of a display panel according to some embodiments of the present disclosure.

[0050] Figure 2 A schematic diagram of an image frame displayed by a display panel according to some embodiments of the present disclosure.

[0051] Figure 3 A schematic diagram of a driving signal applied to a display panel according to some embodiments of the present disclosure.

[0052] Figure 4 A partial schematic diagram of a display panel according to some embodiments of the present disclosure.

[0053] Figure 5 A flowchart of an image display method according to some embodiments of the present disclosure.

[0054] Figure 6 A schematic diagram of an operation state of a display panel according to some embodiments of the present disclosure.

[0055] Figure 7 A schematic diagram of an image frame presented by a display panel according to some embodiments of the present disclosure.

[0056] Wherein the reference numerals:

[0057] 100: display panel

[0058] 110: pixel circuit

[0059] 120: temporary storage circuit

[0060] 121-126: data buffer

[0061] 130: drive circuit

[0062] 131: shift register circuit

[0063] 132: logic circuit

[0064] 133: decoding circuit

[0065] 133A: address resolution circuit

[0066] 133B: data generation circuit

[0067] 133C: control circuit

[0068] 200: image frame

[0069] 301: mode selection data

[0070] 302: scan address

[0071] 303: update quantity

[0072] 304A-304B: update start address

[0073] 305A-305B: update time

[0074] 306A-306B: update data

[0075] 710-740: physical position

[0076] GL: scan line

[0077] DL: data line

[0078] PL: pixel unit

[0079] LA: data buffer

[0080] R1-R4: row

[0081] R71-R74: row

[0082] SHR1-SHR6: shift registers

[0083] OR2-OR6: control logic components

[0084] AND1-AND6: switching logic components

[0085] R11-R17: pixel values

[0086] R21-R27: pixel values

[0087] R31-R37: pixel values

[0088] R41-R47: pixel values

[0089] SI: driving signal

[0090] SCL: frequency signal

[0091] VST: start signal

[0092] PR: processor

[0093] GA: scanning circuit

[0094] GD: scanning line controller

[0095] S501-S505: steps DETAILED DESCRIPTION

[0096] Embodiments of the present application will be described herein below with reference to a number of drawings. Numerous specific details will be set forth in the following description in order to provide a thorough understanding of the present application. However, it will be appreciated that these specific details are not intended to limit the present application. In other words, in some embodiments of the present application, the specific details are not necessary for understanding the present application. In addition, for simplicity and clarity of illustration, the drawing figures will not necessarily show all of the components of the application.

[0097] In the present disclosure, when a component is referred to as being "connected" or "coupled" to another component, it can be "electrically connected" or "electrically coupled" to the other component. "Connected" or "coupled" can also be used to mean that two or more components are in operative or communicative connection or interaction with each other. In addition, although the terms "first", "second", and so on are used herein to describe various components, the terms are merely used to distinguish a component from another component with the same technical term. Unless the context clearly indicates otherwise, the terms do not specifically designate or imply an order or sequence, nor are they used to limit the present application.

[0098] Figure 1 A schematic diagram of a display panel 100 according to some embodiments of the present disclosure is shown. The display panel 100 is communicatively connected to a processor PR to receive display signals from the processor PR. The display panel 100 will present an image according to the received display signals.

[0099] The display panel 100 includes pixel circuits 110, a temporary storage circuit 120, and a driving circuit 130. The pixel circuits 110 include a plurality of pixel units PL, which are coupled to a plurality of scan lines GL and a plurality of data lines DL to sequentially receive driving voltages corresponding to display signals, thereby presenting different pixel values (e.g., gray scale values, brightness values). As shown, the pixel units PL are divided into a plurality of rows R1-R4 along a first direction (e.g., a vertical direction) according to the plurality of scan lines GL. Each row of the pixel units PL is coupled to a corresponding data line DL to correspond to different positions along a second direction (e.g., a horizontal direction), respectively. Since those skilled in the art can understand the principle of applying driving voltages to the pixel circuits 110 to display an image, further description is omitted herein. Figure 1 Figure 1 Figure 1

[0100] The temporary storage circuit 120 includes a plurality of data latches LA, which are coupled to the pixel units PL through the data lines DL. In an embodiment, the data latches LA can be D-type flip-flops, but the present disclosure is not limited thereto.

[0101] The driving circuit 130 is coupled to the temporary storage circuit 120 and the scan lines GL to set the driving voltages of the plurality of pixel units PL through the data latches LA. For example, a plurality of first driving voltages control first pixel values of the plurality of pixel units PL in the first row R1, or a plurality of second driving voltages control second pixel values of the pixel units PL in the second row R2. The "driving voltages" are used to control the pixel units PL to present corresponding pixel values (e.g., control the flipping angle and transmittance of liquid crystals). Taking the first driving voltages as an example, each first driving voltage corresponds to each pixel unit PL in the first row R1 of the pixel circuits 110. In other words, the "plurality of first driving voltages" is used to refer to voltages corresponding to the pixel units PL in the first row R1, and each first driving voltage is different according to the pixel value required to be presented by the image.

[0102] In an embodiment, the display panel 100 can be a liquid crystal display applying a Memory-In-Pixel (MIP) technology, in which each pixel unit PL is provided with an internal memory to record the state of liquid crystals, but the display panel of the present disclosure is not limited to the MIP display.

[0103] Figure 2 ​​​Fig. 1 shows a schematic diagram of an image frame 200 rendered by a display panel 100 according to some embodiments of the present disclosure. The image frame 200 is rendered by the pixel units PL of the pixel circuits 110. For ease of illustration, the pixel values rendered by the pixel units PL of each row are labeled as "R11~R17, R21~R27, R31~R37, R41~R47".

[0104] In some embodiments, the display panel 100 is configured to update the pixel values of the pixel units PL in a row-by-row manner. For example, the display panel 100 is configured to update the pixel values of the pixel units PL of the first row R1 first, and then update the pixel values of the pixel units PL of the second row R2, and so on. Figure 2 In the illustrated embodiment, the pixel values R11~R17 of the first row R1 are "black, white, black, white,... " from left to right, and the pixel values R21~R27 of the second row R1 are "white, black, white, white,... " from left to right. Generally, when the display panel 100 updates the image frame, the scan circuit GA and the scan line controller GD are configured to sequentially drive the scan lines GL (e.g., in the direction from top to bottom in Figs. 1 and 2) and sequentially turn on the data lines DL (e.g., in the direction from left to right in Figs. 1 and 2) to update the pixel units PL one by one. For example, the display panel 100 updates the pixel values of the pixel units PL of the first row R1 first, and the driving circuit 130 writes the driving voltages corresponding to the pixel values R11~R17 "black, white, black, white,... " of the first row R1 into the data buffers LA. Then, the display panel 100 updates the pixel values of the pixel units PL of the second row R2, and the driving circuit 130 writes the driving voltages corresponding to the pixel values R21~R27 "white, black, white, white,... " of the second row R2 into the data buffers LA. However, the aforementioned updating method will be difficult to improve the frame rate (or update rate) of the display panel, and the image file data will also be larger.

[0105] In some embodiments of the present disclosure, the format of the driving signals provided to the display panel is changed (to be described in the following paragraphs) so that the display panel 100 only needs to write the driving voltages of "different pixel values from the previous row" to improve the update speed. In other words, when the driving voltages required to be set for the pixel units PL of the second row R2 and the first row R1 corresponding to the same position (i.e., corresponding to the same data buffer LA) are the same (e.g., both need to be set to "white"), the driving circuit 130 will not need to output / write the second driving voltage to the data buffer LA again, and the driving voltage output by the data buffer LA will maintain the first driving voltage output previously, i.e., the data buffer LA can directly use / set the first driving voltage output previously as the second driving voltage. In some embodiments, the driving circuit 130 will transmit an enable signal to the corresponding data buffer LA (e.g., the "EN" terminal of the data buffer LA) so that the input terminal of the corresponding data buffer LA will not receive the input signal. Figure 4

[0106] ​For example, if the driving circuit 130 first sets the pixel values of the first row Rl, and then sets the pixel values of the second row R2, and the pixel values Rll-Rl7 of the first row Rl are "black, white, black, white,... ", and the pixel values R21-R27 of the second row R2 are "white, black, white, white,... ", when the driving circuit 130 sets the pixel values of the second row R2, the first three pixel values Rl "white, black, white" are updated first, but the fourth pixel value R24 does not need to be updated because it is the same as the pixel value Rl4 of the first row. The driving circuit 130 can skip the pixel value R24 and continue to set the last three pixel values R25-R27. In other words, the driving circuit 130 does not need to write data to the "data buffer LA corresponding to the pixel unit PL / pixel value R24", and accordingly, the update speed of the display panel 100 can be improved.

[0107] Please refer to FIGS. 1-3, which illustrate the format of the driving signal (serial data). Figure 3 FIG. 4 illustrates a schematic diagram of the driving signal SI according to some embodiments of the present disclosure. In an embodiment, the display panel 100 receives a plurality of driving signals, each of which corresponds to each row (e.g., Rl-R4) of the pixel unit PL. For example, the driving signal SI corresponding to the first row Rl is illustrated in FIG. 4. Figure 2 For example, as illustrated in the image frame 200, because the pixel value R24 of the second row R2 is the same as the pixel value Rl4 of the first row Rl, the driving circuit does not need to write the driving voltage again, but can use the driving voltage of the pixel value Rl4 to set the pixel value R24. The driving signal SI is transmitted to the driving circuit 130 along with the frequency signal SCL (serial clock) and includes the following information:

[0108] (1) Mode selection data 301: The mode selection data 301 is used to inform the driving circuit 130 to update the pixel circuit 110.

[0109] (2) Scan address 302: The scan address 302 is used to indicate which row (hereinafter referred to as the "current row") of the pixel unit PL is currently to be updated. If the pixel unit PL of the second row R2 is currently to be updated, the driving circuit 130 will drive the corresponding scan line GL according to the scan address.

[0110] (3) Update quantity 303: The update quantity 303 is used to indicate how many pieces the current row needs to be updated. For example, because the pixel values R21-R23 and R25-R26 of the second row R2 are different from the pixel values of the first row Rl, the second row R2 will be updated in two pieces.

[0111] (4) Update start address 304A-304B: The update start address 304A-304B is used to indicate the starting point of the update, corresponding to the "data buffer LA" of the pixel value to be updated. For example, the update start address 304A-304B of the second row R2 is "R21", which indicates that the update of the second row R2 starts from the pixel value R21. Figure 2For example, since the second row R2 is divided into two segments for updating, there are two update start addresses 304A-304B. The driving circuit 130 identifies / locates the corresponding data latches LA (e.g., corresponding to the pixel values R21 and R25) according to the update start addresses 304A-304B, and starts updating from the identified data latches LA as the starting point of updating.

[0112] (5) Update time 305A-305B: The update time 305A-305B is used to indicate the length (e.g., the number of frequency signals) of each segment of updating. For example, Figure 2 For example, the first segment of the second row R2 to be updated is the pixel values R21-R23, and thus the update time 305A can be the length of time required for sequentially writing data into three data latches LA.

[0113] (6) Update data 306A-306B: The update data 306A-306B is used to indicate the data (e.g., driving voltage) for setting the pixel unit PL. In other words, the driving circuit 130 is used to generate driving voltages according to the update data 306A-306B. For example, Figure 2 For example, after the driving circuit 130 identifies the corresponding data latches LA (e.g., corresponding to the pixel value R21) as the starting point of updating according to the update start address 304A, the driving circuit 130 starts timing, and sequentially outputs three driving voltages corresponding to the pixel values R21-R23 to the corresponding three data latches LA according to the update data 306A. After the driving voltages are input to the corresponding pixel units PL through the corresponding three data latches LA, the time counted by the driving circuit 130 will exactly exceed the update time 305A, at which time the driving circuit 130 will disable the internal shift register to complete the first segment of updating.

[0114] Figure 4 Fig. 1 shows a partial schematic view of a display panel 100 according to some embodiments of the present disclosure. In Figure 4 embodiments, similar components related to the embodiments of Figure 1 are denoted by the same reference numerals for ease of understanding, and the specific principles of the similar components have been described in detail in the previous paragraphs, and will not be described again herein unless necessary to introduce the components of Figure 4 in cooperative operation.

[0115] In an embodiment, the temporary storage circuit 120 includes a plurality of data latches 121-126 (same as Figure 1 the data latches LA shown in Fig. 1). The data latches 121-126 are connected to the data lines DL (e.g., the data lines DL1- DL6 shown in Fig. 1) through the data lines DL. Figure 1The driving circuit 130 includes a shift register circuit 131, a logic circuit 132 and a decoding circuit 133. The shift register circuit 131 includes a plurality of shift registers SHR1-SHR6, each of which corresponds to a data buffer 121-126, and the output of each shift register SHR1-SHR6 is coupled to the control terminal of the corresponding data buffer 121-126. When the control terminal of the data buffer 121-126 is input with a disable signal, the data buffer 121-126 will not receive a new input signal and will maintain the output signal. The shift registers SHR1-SHR6 are connected through a plurality of control logic components OR2-OR6. In one embodiment, the control logic components OR2-OR6 include "OR gates".

[0116] The logic circuit 132 includes a plurality of switching logic components AND1-AND6, the output of each switching logic component AND1-AND6 is coupled to the input of the corresponding control logic component OR2-OR6, except that the output of the first switching logic component AND1 is directly coupled to the input of the first shift register SHR1. In one embodiment, the switching logic components AND1-AND6 include "AND gates". One input of the switching logic components AND1-AND6 is used to receive a start signal VST.

[0117] Referring to FIGS. 1 and 4, the decoding circuit 133 is coupled to the other input of the switching logic components AND1-AND6 and is used to receive a driving signal provided by an external processor PR. In one embodiment, the decoding circuit 133 further includes an address resolving circuit 133A, a data generating circuit 133B and a control circuit 133C. The address resolving circuit 133A is coupled to the logic circuit 132 and is used to enable the switching logic component as the starting point of the update according to the update start address in the driving signal. The data generating circuit 133B is coupled to the shift register circuit 120 and is used to output the corresponding driving voltage according to the driving signal.

[0118] The control circuit 133C is used to output various control signals of the display panel 100, including a frequency signal CLK, a clear signal CLR and a start signal VST. The clear signal CLR is a kind of disable signal used to suspend the operation of the shift registers SHR1-SHR6.

[0119] Figure 5FIG. 1 shows a flowchart of an image display method according to some embodiments of the present disclosure. As shown in FIG. 1, in step S501, the driving circuit 130 sequentially receives a plurality of driving signals from the processor PR, each of which corresponds to a row of pixel values in the same frame of the image. The driving signals are generated by the processor PR according to the original image file data, and the generation method will be described in subsequent paragraphs.

[0120] For ease of illustration, only the process of updating the first row R1 and the second row R2 of the display panel 100 is described herein, and the display and update of other rows can be the same as the update of the first row R1 and / or the second row R2. In an embodiment, the driving circuit 130 first receives the first driving signal corresponding to the pixel units PL of the first row R1 from the processor PR, and sets a plurality of first driving voltages of the pixel units PL of the first row R1 according to the first driving signal through the data buffers 121-126 to present the pixel values R11-R16. Since the pixel units PL of the first row R1 are the first row to be updated, the driving circuit 130 writes the driving voltages corresponding to all the pixel units PL of the first row R1 through the data buffers 121-126 to set all the pixel values R11-R16 of the first row R1.

[0121] In step S502, the driving circuit 130 receives the second driving signal corresponding to the pixel units PL of the second row R2. As described above, since the display panel 100 does not need to update the pixel units PL with the same position (corresponding to the same data line DL) and the same pixel value in this embodiment, the second driving signal does not need to include the driving voltage of each pixel unit PL in the second row R2 (e.g., does not include the driving voltage of the pixel value R24), and the driving circuit 130 can still set each pixel unit PL in the second row R2 to the corresponding pixel value R21-R26 according to the second driving signal.

[0122] In step S503, the control circuit 133C of the decoding circuit 133 confirms the type of the second driving signal based on the mode selection data 301 in the second driving signal. The address resolution circuit 133A of the decoding circuit 133 confirms the position of the second row R2 of the pixel unit PL to be updated based on the scan address 302 of the second driving signal, and drives the scan line GL corresponding to the second row R2. It should be noted that although in this embodiment, the driving circuit 130 sets the pixel value of the first row R1 first and then sets the pixel value of the second row R2, in other embodiments, the order in which the display panel 100 updates the pixel units PL is not limited to "scanning sequentially from top to bottom". In other words, the "second row R2" indicated by the second driving signal may also be the fourth row arranged vertically on the display panel 100. The processor PR that generates the driving signal can adjust the update order based on the similarity between the pixel values ​​of multiple rows, an application that will be explained in later paragraphs.

[0123] In one embodiment, the decoding circuit 133 is further configured to determine how many segments the second row R2 needs to be updated based on the update quantity 303 in the second driving signal. For example, since the pixel values ​​of the second row R2 are different from those of the first row R1 (R21-R23 and R25-R26), they will be updated in two segments.

[0124] In step S504, the address resolution circuit 133A of the decoding circuit 133 identifies and enables the corresponding data buffer based on the update start address in the second driving signal. Figure 2 For example, since the pixel value R21 of the first pixel unit PL in the second row R2 needs to be updated, the update start address 304A corresponds to the data buffer 121. When both the start signal VST and the signal provided by the decoding circuit 133 to the switching logic component AND1 are "1" (enabled), the shift register SHR1 will be enabled, and the subsequent shift registers will also operate accordingly. Since those skilled in the art can understand the operating principle of shift registers, it will not be described in detail here.

[0125] Similarly, when setting the second pixel values ​​R25 to R27, the address resolution circuit 133A enables the corresponding control logic component OR5 according to the update start address 304B, thereby enabling the corresponding shift register SHR5, and the corresponding data buffer 125 will be used as the update start point. Other shift registers following shift register SHR5 will be enabled sequentially with the frequency signal CLK, but other shift registers SHR1 to SHR4 preceding shift register SHR5 will be disabled. In one embodiment, the decoding circuit 133 enables the corresponding switching logic component AND5 according to the update start address 304B and disables other switching logic components, thereby enabling the corresponding control logic component OR5.

[0126] In step S505, the data generating circuit 133B of the decoding circuit 133 outputs a portion of the second driving voltage corresponding to the pixel units PL of the second row R2 to a corresponding portion of the data buffer according to the update data in the second driving signal. In other words, the first pixel value and the second pixel value corresponding to the "corresponding portion of the data buffer" are different from each other, and thus the driving circuit 130 actively writes the second driving voltage to update the pixel value.

[0127] The aforementioned "a portion of the second driving voltage" means the driving voltage that needs to be actively written to the data buffer to update the corresponding pixel unit PL, such as the second driving voltage corresponding to the pixel values R21-R23 shown in FIG. 2. Figure 2 Since the pixel value R24 of the second row R2 is the same as the pixel value R14 at the corresponding position (i.e., corresponding to the same data line DL and data buffer 124) in the first row Rl, the driving circuit 130 does not actively write the second driving voltage, but directly uses the output voltage of the data buffer 124 as the second driving voltage for the pixel value R24.

[0128] In an embodiment, the driving circuit 130 uses the shift registers SHRl, SHR5 indicated by the update start addresses 304A, 304B as the update starting point, and sequentially outputs the second driving voltage to a corresponding portion of the data buffer. In addition, the driving circuit 130 can start timing when it starts outputting the second driving voltage, and output a clear signal CLR as a disable signal to interrupt all the shift registers when the timing time exceeds the update time in the second driving signal, to avoid continuous input of false signals.

[0129] The aforementioned steps S504-S505 can be repeatedly performed to complete the update of the pixel units PL of the same row. For example, after confirming in step S503 that the currently updated pixel units PL are of the second row R2, the display panel 100 first performs steps S504-S505 once to update the pixel values (e.g., R21-R23) of the pixel units in the first segment; then the display panel 100 performs steps S504-S505 again to update the pixel values (e.g., R25-R27) of the pixel units in the second segment.

[0130] To facilitate understanding of the operation of the driving circuit 130, FIGS. 2 and 6 are used as examples for illustration. Figure 6The signal state diagram shows that the display panel 100 is updating the second segment pixel values R25-R27 of the second row R2. When setting the second segment pixel values R25-R27, the decoding circuit 133 enables the switching logic component AND5 and disables other switching logic components. The switching logic component AND5 further inputs an enabling signal to the control logic component OR5. Since the control logic component OR5 is an OR gate, the output signal is also an enabling signal to enable the corresponding shift register SHR5.

[0131] As shown above, the control terminals (EN) of the data latches 121-124 receive a disabling signal, so that the input terminals of the shift registers SHR1-SHR4 are disabled and do not receive signals. Therefore, the second driving voltage outputted by the decoding circuit 133 is provided to the data latch 125 corresponding to the shift register SHR5 to update the pixel value R25. The data latch 125 serves as a starting point for updating, and the subsequent data latches 126 are sequentially enabled to update the pixel value R26, and so on.

[0132] In addition, since the pixel value R24 is the same as the pixel value R14, the data latch 124 corresponding to the pixel value R24 is disabled and does not receive an input signal when updating the pixel values of the second row R2. At this time, the data latch 124 maintains the output of the previously input first driving voltage.

[0133] Some embodiments of the present disclosure can also generate driving signals according to original image data. As shown in FIGS. 1-4, the processor PR receives original image data, wherein the original image data includes pixel values corresponding to the pixel units PL of each row. The processor PR compares the first pixel values R11-R17 corresponding to the pixel units PL of the first row R1 and the second pixel values R21-R27 corresponding to the pixel units PL of the second row R2, and generates a driving signal format as shown in FIG. 5 according to the comparison results. Figure 3

[0134] The processor PR does not need to sequentially generate driving signals in the same direction (e.g., from top to bottom). In an embodiment, the processor PR compares pixel values of different rows (corresponding to scanning lines GL) and sets the "first row R1" and the "second row R2" according to the comparison results. Specifically, the processor PR calculates difference values between pixel values of each row, and sets the order of each row of pixel values (i.e., the order of updating) according to the difference values. After confirming the order of the pixel values, the processor PR sets the "first row R1" and the "second row R2" accordingly.

[0135] Referring to FIGS. 1 and 7, Figure 7 ​Fig. 7 shows a schematic diagram of an image frame 700 rendered by the display panel 100 according to some embodiments of the present disclosure. The image frame 700 can be divided into a plurality of rows of physical locations 710-740 from top to bottom. The pixel values of the physical locations 710 and 730 are similar, and thus the processor PR sets the physical locations 710 and 730 as the "first row R71" and the "second row R72" to be updated. Accordingly, after updating the pixel values of the first row R71, the display panel 100 can directly update the pixel values of the second row R72 without writing any data to the data buffer LA, but using the driving voltage used to update the first row R71.

[0136] Similarly, the physical locations 720 and 740 are compared with the physical location 730. Since the physical location 720 has more similar pixel values with the physical location 730, the processor PR sets the physical location 720 as the "third row R73" to be updated, and sets the physical location 740 as the "fourth row R74" to be updated. Accordingly, the number of times of actively inputting the driving voltage is reduced, and thus the update speed of the display panel is improved.

[0137] The components, method steps, or technical features in the foregoing embodiments can be combined with each other without being limited by the order of the textual description or the order of the figures in the present disclosure.

[0138] Although the present disclosure has been disclosed with the above embodiments, it is not intended to limit the present disclosure. Any person skilled in the art can make various modifications and improvements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure is defined by the appended claims.

Claims

1. An image display method characterized by comprising: Comprising: setting, by a driving circuit and a plurality of data buffers, a plurality of first driving voltages of a first row of a plurality of pixel units according to a first driving signal, wherein the driving circuit is coupled to the plurality of pixel units through the plurality of data buffers; and setting, by the driving circuit and the plurality of data buffers, a plurality of second driving voltages of a second row of the plurality of pixel units according to a second driving signal, wherein the method of setting the plurality of second driving voltages of the second row of the plurality of pixel units comprises: when one of the plurality of second driving voltages is identical to one of the plurality of first driving voltages, and both correspond to a same one of the plurality of data buffers, disabling an input terminal of the same one of the plurality of data buffers to maintain the one of the plurality of first driving voltages as the one of the plurality of second driving voltages.

2. The image display method of claim 1, wherein, The plurality of first driving voltages are used to control a plurality of first pixel values of the first row of the plurality of pixel units, the plurality of second driving voltages are used to control a plurality of second pixel values of the second row of the plurality of pixel units, and the method of providing the plurality of second driving voltages to the second row of the plurality of pixel units further comprises: outputting, according to the second driving signal, a portion of the plurality of second driving voltages to a portion of the plurality of data buffers, wherein at least one of the plurality of first pixel values corresponding to the portion of the plurality of data buffers is different from at least one of the plurality of second pixel values corresponding to the portion of the plurality of data buffers.

3. The image display method of claim 2, wherein, The method of outputting the portion of the plurality of second driving voltages to the portion of the plurality of data buffers comprises: driving, according to a scan address in the second driving signal, a scan line corresponding to the second row of the plurality of pixel units; identifying, according to an update start address in the second driving signal, one of the plurality of data buffers; outputting, according to an update data in the second driving signal, the portion of the plurality of second driving voltages; and sequentially outputting, from the one of the plurality of data buffers as an update starting point, the portion of the plurality of second driving voltages to the portion of the plurality of data buffers. The method of sequentially outputting the portion of the plurality of second driving voltages to the portion of the plurality of data buffers comprises:

4. The image display method of claim 3, wherein, disabling a plurality of shift registers in the driving circuit when outputting the portion of the plurality of second driving voltages exceeds an update time in the second driving signal. The driving circuit comprises a plurality of shift registers, outputs of the plurality of shift registers are coupled to control terminals of the plurality of data buffers, and the method of sequentially outputting the portion of the plurality of second driving voltages to the portion of the plurality of data buffers comprises:

5. The image display method of claim 3, wherein, enabling one of a plurality of control logic components to set the one of the plurality of data buffers as the update starting point, wherein the plurality of control logic components are coupled between the plurality of shift registers. The method of sequentially outputting the portion of the plurality of second driving voltages to the portion of the plurality of data buffers further comprises:

6. The image display method of claim 5, wherein, ​ One of the plurality of switch logic components is enabled to enable the one of the plurality of control logic components, wherein outputs of the plurality of switch logic components are coupled to inputs of the plurality of control logic components.

7. The image display method of claim 6, wherein, The plurality of control logic components includes a plurality of OR gates and the plurality of switch logic components includes a plurality of AND gates.

8. The image display method of claim 1, wherein The plurality of pixel units is divided into a plurality of rows according to a plurality of scan lines, and the image display method further includes: receiving, by a processor, an original image data, wherein the processor is communicatively coupled to the driving circuit, and the original image data includes a plurality of pixel values corresponding to the plurality of rows of the plurality of scan lines; and comparing differences between a plurality of first pixel values corresponding to the first row of the plurality of pixel units and a plurality of second pixel values corresponding to the second row of the plurality of pixel units to generate the first driving signal and the second driving signal.

9. The image display method of claim 8, wherein, The image display method further includes: comparing the plurality of pixel values corresponding to the plurality of rows of the plurality of scan lines to set the first row and the second row of the plurality of pixel units.

10. The image display method of claim 9, wherein, The method of comparing the plurality of pixel values corresponding to the plurality of rows of the plurality of scan lines includes: calculating a plurality of difference values between the plurality of pixel values corresponding to the plurality of rows of the plurality of scan lines; ranking each row of the plurality of pixel values according to the plurality of difference values; and setting the first row and the second row of the plurality of pixel units according to a ranking result of each row of the plurality of pixel values.

11. A display panel, characterized by, includes: a pixel circuit including a plurality of pixel units, wherein the plurality of pixel units is divided into a plurality of rows according to a plurality of scan lines; a temporary storage circuit including a plurality of data buffers, wherein the plurality of data buffers is coupled to the plurality of pixel units through a plurality of data lines; and a driving circuit coupled to the temporary storage circuit and the plurality of scan lines to set a plurality of first driving voltages for a first row of the plurality of pixel units through the plurality of data buffers and to set a plurality of second driving voltages for a second row of the plurality of pixel units through the plurality of data buffers; wherein when one of the plurality of second driving voltages is the same as one of the plurality of first driving voltages and both correspond to a same one of the plurality of data buffers, the driving circuit does not output the one of the plurality of second driving voltages and the same one of the plurality of data buffers maintains the one of the plurality of first driving voltages as the one of the plurality of second driving voltages.

12. The display panel of claim 11, wherein, The plurality of first driving voltages are used to control a plurality of first pixel values of the first row of the plurality of pixel units, and the plurality of second driving voltages are used to control a plurality of second pixel values of the second row of the plurality of pixel units. wherein the driving circuit is used to receive a first driving signal and a second driving signal and output a portion of the plurality of second driving voltages to a portion of the plurality of data buffers according to the second driving signal; and wherein at least one of the plurality of first pixel values corresponding to the portion of the plurality of data buffers is different from at least one of the plurality of second pixel values corresponding to the portion of the plurality of data buffers.

13. The display panel of claim 12, wherein, The second driving signal at least includes: a scan address, wherein the driving circuit is configured to drive one of the plurality of scan lines according to the scan address; an update start address, wherein the driving circuit is configured to identify one of the plurality of data buffers according to the update start address; and an update data, wherein the driving circuit is configured to output the portion of the plurality of second driving voltages according to the update data. The driving circuit is further configured to sequentially output the portion of the plurality of second driving voltages to the portion of the plurality of data buffers starting from the one of the plurality of data buffers.

14. The display panel of claim 13, wherein, The second driving signal further comprises an update time, wherein the driving circuit is configured to disable the plurality of shift registers in the driving circuit when the update time is exceeded while the driving circuit sequentially outputs the portion of the plurality of second driving voltages to the portion of the plurality of data buffers.

15. The display panel of claim 12, wherein, The driving circuit comprises: a shift register circuit comprising a plurality of shift registers, wherein outputs of the plurality of shift registers are coupled to control terminals of the plurality of data buffers, and the plurality of shift registers are connected through a plurality of control logic components; a logic circuit comprising a plurality of switching logic components, wherein outputs of the plurality of switching logic components are coupled to inputs of the plurality of control logic components; and a decoding circuit coupled to the plurality of switching logic components and configured to receive the first driving signal and the second driving signal.

16. The display panel of claim 15, wherein, The plurality of control logic components comprise a plurality of OR gates.

17. The display panel of claim 15, wherein, The plurality of switching logic components comprise a plurality of AND gates.

18. The display panel of claim 15, wherein, The second driving signal comprises an update start address and an update data, wherein the decoding circuit is configured to identify one of the plurality of control logic components according to the update start address to start updating from a corresponding one of the plurality of data buffers, and sequentially output the portion of the plurality of second driving voltages to the portion of the plurality of data buffers according to the update data.

19. The display panel of claim 18, wherein, The second driving signal further comprises an update time, wherein the driving circuit is configured to provide a disable signal to the plurality of shift registers when the update time is exceeded while the driving circuit sequentially outputs the portion of the plurality of second driving voltages to the portion of the plurality of data buffers.

20. The display panel of claim 19, wherein, The decoding circuit further comprises: an address resolving circuit coupled to the logic circuit and configured to enable one of the plurality of switching logic components according to the update start address; and and a data generating circuit coupled to the shift register circuit and configured to output the portion of the plurality of second driving voltages according to the second driving signal.

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