Semiconductor memory device

Abstract

This application provides a semiconductor memory device capable of performing write operations at higher speeds. The control circuit performs a first pulse application operation, a pre-charge operation, and a second pulse application operation when performing a write operation on the memory cell transistor. In the first pulse application operation, the threshold voltage of the first memory cell transistor (sMT) is reduced. In the pre-charge operation, with the select transistors (ST1, T2, ST3) turned on, the bit line is charged by applying a third voltage (Vss) to the first word line (sWL) and a fourth voltage (Vdd) to the source line (SL). In the second pulse application operation, with the first select transistor (ST1) turned on and the second select transistors (ST2, ST3) turned off, a first voltage (Vpgm) is applied to the first word line (sWL).

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2022-150591 (filed on September 21, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor memory devices. Background Technology

[0004] In semiconductor memory devices, the writing operation of memory cell transistors is performed by repeatedly executing programming and verification operations. Summary of the Invention

[0005] According to the disclosed embodiments, a semiconductor memory device capable of performing write operations at a higher speed is provided.

[0006] The semiconductor memory device of the embodiment includes a memory string, multiple word lines, a sense amplifier unit, and a control circuit. The memory string has a first selection transistor connected to a bit line, a second selection transistor connected to a source line, and multiple memory cell transistors connected in series between the first and second selection transistors. The multiple word lines are each connected to the gate of a plurality of memory cell transistors. The sense amplifier unit is connected to the bit lines. The control circuit controls the voltages of the multiple word lines, the bit lines, and the source lines. The sense amplifier unit includes a latch circuit that holds data written to the memory cell transistors; and a sense amplifier section that can apply a voltage to the bit lines based on the data held in the latch circuit. When the control circuit performs a write operation on the first memory cell transistor, which is one of the memory cell transistors, it performs a first pulse application operation, a pre-charge operation, and a second pulse application operation. During the first pulse application operation, while the first selection transistor is turned on and the second selection transistor is turned off, a first voltage is applied to the first word line corresponding to the first memory cell transistor among the multiple word lines, and a second voltage lower than the first voltage is applied to the bit line, thereby lowering the threshold voltage of the first memory cell transistor. In the pre-charge operation, after the first pulse application operation is performed and the first and second selection transistors are turned on, the bit line is charged by applying a third voltage lower than the first voltage to the first word line and a fourth voltage higher than the third voltage to the source line. In the second pulse application operation, after the pre-charge operation is performed, the first voltage is applied to the first word line while the bit line is in a floating state by the sensing amplifier section, the first selection transistor is turned on, and the second selection transistor is turned off. Attached Figure Description

[0007] Figure 1 This is a block diagram showing the general configuration of the storage system according to the first embodiment.

[0008] Figure 2 This is a block diagram illustrating the schematic configuration of a semiconductor memory device according to the first embodiment.

[0009] Figure 3 This is a circuit diagram showing the equivalent circuit of the memory cell array of the first embodiment.

[0010] Figure 4 This is a cross-sectional view showing the cross-sectional structure of the memory cell array according to the first embodiment.

[0011] Figure 5 It shows along Figure 4 A cross-sectional view of the VV line.

[0012] Figure 6 This is a circuit diagram showing the circuit configuration of the sensing amplifier unit according to the first embodiment.

[0013] Figure 7 It is a graph showing the relationship between the applied voltage and polarization of the memory cell transistor in the first embodiment.

[0014] Figure 8 (A) and (B) are diagrams schematically illustrating the polarization states of the memory cell transistors in the first embodiment.

[0015] Figure 9 (A) and (B) are graphs showing the relationship between the threshold voltage and the probability of existence of the memory cell transistor in the first embodiment.

[0016] Figure 10 This is a diagram schematically illustrating an example of the operation of the storage cell array in the first programming operation of the first embodiment.

[0017] Figure 11 This is a diagram schematically illustrating an example of the operation of the storage cell array in the first programming operation of the first embodiment.

[0018] Figure 12 This is a diagram schematically illustrating an example of the operation of the memory cell array in the pre-charge operation of the second programming operation of the first embodiment.

[0019] Figure 13 This is a diagram schematically illustrating an example of the operation of the memory cell array in the pre-charge operation of the second programming operation of the first embodiment.

[0020] Figure 14 This is a diagram schematically illustrating an example of the operation of the memory cell array during the pulse application operation of the second programming action in the first embodiment.

[0021] Figure 15 This is a diagram schematically illustrating an example of the operation of the memory cell array during the pulse application operation of the second programming action in the first embodiment.

[0022] Figure 16 This is a diagram schematically illustrating an example of the operation of the memory cell array during the pulse application operation of the second programming action in the first embodiment.

[0023] Figure 17 (A) to (J) are timing diagrams showing the voltage shifts of each part of the memory cell array during the write operation of the first embodiment.

[0024] Figure 18 (A) to (E) are timing diagrams showing the shift of each signal of the sense amplifier unit during the write operation of the first embodiment.

[0025] Figure 19 This is a graph showing the relationship between the threshold voltage of the memory cell transistor and the charging voltage of the bit line in the semiconductor memory device of the first embodiment.

[0026] Figure 20 This is a flowchart illustrating the steps of the write operation performed by the sequencer of the first embodiment.

[0027] Figure 21 This is a flowchart illustrating the steps of the second programming action performed by the sequencer of the first embodiment.

[0028] Figure 22 This is a flowchart illustrating the steps of the second programming action performed by the sequencer of the second embodiment.

[0029] Figure 23 (A) to (J) are timing diagrams showing the voltage shifts of each part of the memory cell array during the write operation of the second embodiment.

[0030] Figure 24 (A) to (E) are timing diagrams showing the shift of each signal of the sensing amplifier unit during the write operation of the second embodiment.

[0031] Figure 25 This is a circuit diagram showing the circuit configuration of the sensing amplifier unit according to the third embodiment.

[0032] Figure 26 This is a flowchart illustrating the steps of the second programming action performed by the sequencer of the third embodiment.

[0033] Figure 27 (A) to (J) are timing diagrams showing the voltage shifts of each part of the memory cell array during the write operation of the third embodiment. Detailed Implementation

[0034] The embodiments will now be described with reference to the accompanying drawings. To facilitate understanding, the same reference numerals will be used as much as possible to refer to the same components in the drawings, and repeated descriptions will be omitted.

[0035] 1 First Implementation Method

[0036] The semiconductor memory device according to the first embodiment will be described. The semiconductor memory device according to this embodiment is a non-volatile memory device configured as a NAND flash memory.

[0037] 1.1 Composition of the storage system

[0038] Figure 1 An example configuration of a memory system including a semiconductor memory device 2 is shown. The memory system includes a memory controller 1 and a semiconductor memory device 2. Figure 1 The storage system can connect to a host device (not shown). The host device could be an electronic device such as a personal computer or a portable terminal.

[0039] The memory controller 1 controls the writing of data to the semiconductor memory device 2 based on write requests from the host. Additionally, the memory controller 1 controls the reading of data from the semiconductor memory device 2 based on read requests from the host.

[0040] Between the memory controller 1 and the semiconductor storage device 2, the following signals are transmitted and received: chip enable signal / CE, ready / busy signal / RB, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal / RE, RE, write protection signal / WP, data signal DQ<7:0>, data strobe signal DQS, and / DQS.

[0041] The chip enable signal / CE is used to activate the semiconductor memory device 2. The ready / busy signal / RB is used to indicate whether the semiconductor memory device 2 is in a ready or busy state. "Ready state" means accepting commands from the outside. "Busy state" means not accepting commands from the outside. The command latch enable signal CLE indicates that the signal DQ<7:0> contains a command. The address latch enable signal ALE indicates that the signal DQ<7:0> contains an address. The write enable signal / WE is used to fetch the received signal into the semiconductor memory device 2, and is activated whenever the memory controller 1 receives a command, address, or data. During the period when the signal / WE is at the "L (Low)" level, the memory controller 1 instructs the semiconductor memory device 2 to fetch the signal DQ<7:0>.

[0042] The read enable signals RE and / RE are used to enable the memory controller 1 to read data from the semiconductor memory device 2. For example, the read enable signals RE and / RE are used to control the timing of the operation of the semiconductor memory device 2 when the output signal DQ<7:0> is displayed. The write protect signal / WP is used to instruct the semiconductor memory device 2 to disable data writing and erasing. The signal DQ<7:0> represents the data transmitted and received between the semiconductor memory device 2 and the memory controller 1, including commands, addresses, and data. The data strobe signals DQS and / DQS are used to control the timing of the input and output of the signal DQ<7:0>.

[0043] The memory controller 1 includes RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15. RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are interconnected via an internal bus 16.

[0044] The host interface 13 outputs requests received from the host, user data (write data), etc., to the internal bus 16. Additionally, the host interface 13 sends user data read from the semiconductor storage device 2, responses from the processor 12, etc., back to the host.

[0045] The memory interface 15 controls, according to the instructions of the processor 12, processes such as writing user data to the semiconductor storage device 2 and reading user data from the semiconductor storage device 2.

[0046] Processor 12 performs comprehensive control over memory controller 1. Processor 12 may be, for example, a CPU or MPU. When processor 12 receives a request from the host via host interface 13, it performs control based on that request. For example, processor 12 instructs memory interface 15 to write user data and parity bits to semiconductor storage device 2 based on a request from the host. Additionally, processor 12 instructs memory interface 15 to read user data and parity bits from semiconductor storage device 2 based on a request from the host.

[0047] Processor 12 determines a memory region (memory area) on semiconductor memory device 2 for user data stored in RAM 11. User data is stored in RAM 11 via internal bus 16. Processor 12 determines the memory region for data in page units (page data) written as units. Hereinafter, user data stored in one page of semiconductor memory device 2 will also be referred to as "cell data". Cell data is typically encoded and stored as codewords in semiconductor memory device 2. In this embodiment, encoding is not necessary. Memory controller 1 may also store cell data in semiconductor memory device 2 without encoding, but... Figure 1The following example illustrates the encoding configuration. When the memory controller 1 does not perform encoding, the page data is identical to the cell data. Alternatively, a codeword can be generated based on a single cell data unit, or it can be generated based on segmented data obtained by dividing the cell data. Furthermore, a codeword can also be generated using multiple cell data units.

[0048] Processor 12 determines the memory region of semiconductor storage device 2 as the write destination for each unit of data. The memory region of semiconductor storage device 2 is assigned a physical address. Processor 12 uses the physical address to manage the memory region as the write destination for unit data. Processor 12 specifies the determined memory region (physical address) and instructs memory interface 15 to write user data to semiconductor storage device 2. Processor 12 manages the mapping between the logical address (the logical address managed by the host) of user data and the physical address. Upon receiving a read request containing a logical address from the host, processor 12 determines the physical address corresponding to the logical address, specifies the physical address, and instructs memory interface 15 to read the user data.

[0049] ECC circuit 14 encodes user data stored in RAM 11 to generate codewords. Additionally, ECC circuit 14 decodes codewords read from semiconductor memory device 2.

[0050] RAM 11 temporarily stores user data received from the host until this user data is stored in semiconductor memory device 2, or temporarily stores data read from semiconductor memory device 2 until this data is sent to the host. RAM 11 is, for example, general-purpose memory such as SRAM or DRAM.

[0051] exist Figure 1 The diagram shows an example configuration where the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 can also be integrated into the memory interface 15. Alternatively, the ECC circuit 14 can also be integrated into the semiconductor memory device 2. Figure 1 The specific composition and configuration of the elements shown are not particularly limited.

[0052] In the event that a write request is received from the host Figure 1 The storage system operates as follows: Processor 12 temporarily stores the data to be written in RAM 11. Processor 12 reads the data stored in RAM 11 and inputs it into ECC circuit 14. ECC circuit 14 encodes the input data and inputs the codeword into memory interface 15. Memory interface 15 writes the input codeword into semiconductor storage device 2.

[0053] When a read request is received from the host Figure 1The storage system operates as follows: Memory interface 15 inputs codewords read from semiconductor storage device 2 into ECC circuit 14. ECC circuit 14 decodes the input codewords and stores the decoded data in RAM 11. Processor 12 sends the data stored in RAM 11 to the host via host interface 13.

[0054] 1.2 Composition of Semiconductor Memory Devices

[0055] like Figure 2 As shown, the semiconductor memory device 2 includes two planes PL1 and PL2, an input / output circuit 21, a logic control circuit 22, a sequencer 41, a register 42, a voltage generation circuit 43, an input / output pad group 31, a logic control pad group 32, and a power input terminal group 33.

[0056] Plane PL1 includes a memory cell array 110, a sense amplifier 120, and a line decoder 130. Plane PL2 has the same configuration as plane PL1, including a memory cell array 210, a sense amplifier 220, and a line decoder 230. The number of planes provided in the semiconductor memory device 2 can be two, one, or three or more, as in this embodiment.

[0057] The sense amplifier 120 of the planar PL1 is a circuit used to adjust the voltage applied to the bit lines of the memory cell array 110, or to read the current or voltage of the bit lines and convert it into data. When reading data, the sense amplifier 120 acquires the read data from the memory cell transistors of the memory cell array 110 to the bit lines and transmits the acquired read data to the input / output circuit 21. When writing data, the sense amplifier 120 transmits the write data to the memory cell transistors of the memory cell array 110 via the bit lines.

[0058] The row decoder 130 of the plane PL1 is configured as a switch group (not shown) for applying voltage to each word line of the memory cell array 110. The row decoder 130 receives a block address and a row address from register 42, selects the corresponding block based on the block address, and selects the corresponding word line based on the row address. The row decoder 130 toggles the switch group on / off to apply voltage from the voltage generation circuit 43 to the selected word line.

[0059] The memory cell array 210 of plane PL2 has the same configuration as the memory cell array 110 of plane PL1, the sense amplifier 220 of plane PL2 has the same configuration as the sense amplifier 120 of plane PL1, and the line decoder 230 of plane PL2 has the same configuration as the line decoder 130 of plane PL1.

[0060] Memory cell arrays 110 and 210 are the data storage sections. Each of memory cell arrays 110 and 210 contains multiple memory cell transistors associated with word lines and bit lines.

[0061] Input / output circuit 21 transmits and receives signals DQ<7:0> and data strobe signals DQS and / DQS with memory controller 1. Input / output circuit 21 transmits the command and address contained in signal DQ<7:0> to register 42. In addition, input / output circuit 21 transmits and receives write data and read data with sense amplifiers 120 and 220.

[0062] The logic control circuit 22 receives, for example, a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, a read enable signal / RE, RE, and a write protect signal / WP from the memory controller 1. Additionally, the logic control circuit 22 transmits a ready / busy signal / RB to the memory controller 1, thereby notifying the external system of the status of the semiconductor memory device 2.

[0063] Both the input / output circuit 21 and the logic control circuit 22 are circuits configured as input / output signals between the input / output circuit and the memory controller 1. Hereinafter, the input / output circuit 21 and the logic control circuit 22 will also be referred to as "interface circuit 20". Interface circuit 20 can be described as the part that inputs and outputs signals containing control signals related to the operation of planes PL1 and PL2. Control signals include, for example, the command and address signals DQ<7:0> input to the input / output circuit 21, and the command latch enable signal CLE input to the logic control circuit 22.

[0064] The sequencer 41 controls the operation of various components such as the memory cell arrays 110 and 210 based on control signals input from the memory controller 1 to the interface circuit 20. In this embodiment, the sequencer 41 is equivalent to a control circuit. Alternatively, the sequencer 41 and the logic control circuit 22 can be used as the control circuit in this embodiment.

[0065] Register 42 is the part that temporarily holds commands and addresses. Commands that indicate write operations, erase operations, etc., of planes PL1 and PL2, and the addresses corresponding to those commands, are input from memory controller 1 to input / output circuit 21, and then transferred from input / output circuit 21 to register 42 and held thereafter.

[0066] Additionally, register 42 also stores status information indicating the state of the semiconductor memory device 2. The sequencer 41 updates the status information stored in register 42 each time. The status information is output as a status signal from input / output circuit 21 to memory controller 1 in response to a request from memory controller 1.

[0067] The voltage generation circuit 43 is a portion that generates the voltages required for the write, read, and erase operations of data in the memory cell arrays 110 and 210 according to the instructions from the sequencer 41. Such voltages include, for example, the voltages applied to the word lines and bit lines, which will be described later.

[0068] The input / output pad group 31 is a portion provided with multiple terminals (pads) for transmitting and receiving various signals between the memory controller 1 and the input / output circuit 21. Each terminal is individually configured corresponding to each of the signals DQ<7:0> and data strobe signals DQS and / DQS.

[0069] The logic control pad group 32 is a portion provided with multiple terminals (pads) for transmitting and receiving various signals between the memory controller 1 and the logic control circuit 22. Each terminal is individually configured corresponding to each of the following signals: chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal / RE, RE, write protect signal / WP, and ready / busy signal / RB.

[0070] The power input terminal block 33 is a portion provided with multiple terminals for receiving the applied voltages required for the operation of the semiconductor memory device 2. The voltages applied to each terminal include the power supply voltages Vcc, VccQ, Vpp, and the ground voltage Vss.

[0071] The power supply voltage Vcc is the circuit power supply voltage provided externally as the operating power source, for example, a voltage of approximately 3.3V. The power supply voltage VccQ is, for example, a voltage of 1.2V. The power supply voltage VccQ is the voltage used when transmitting and receiving signals between the memory controller 1 and the semiconductor memory device 2. The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, for example, a voltage of 12V.

[0072] 1.3 Composition of Storage Cell Array

[0073] Figure 3 The configuration of a memory cell array 110 disposed on plane PL1 is shown. The memory cell array 110 is composed of multiple blocks BLK, but... Figure 3 Only one block BLK is shown in the diagram. The composition of the other block BLKs in the storage cell array 110 is also similar. Figure 3 The same as shown.

[0074] like Figure 3As shown, block BLK, for example, contains four string units SU (SU0 to SU3). Furthermore, each string unit SU contains multiple storage strings MS. Thus, the storage unit array 110 has multiple storage strings MS, each storage string MS belonging to one of the multiple string units SU. The number of string units SU can also be different. Figure 3 Examples.

[0075] Each memory string (MS) includes, for example, eight memory cell transistors (MT0 to MT7), a drain-side selection transistor (ST1), and source-side selection transistors (ST2 and ST3), and they are connected in series. In this embodiment, the drain-side selection transistor (ST1) is equivalent to the first selection transistor, and the source-side selection transistors (ST2 and ST3) are equivalent to the second selection transistors.

[0076] Furthermore, the number of memory cell transistors MT in each memory string MS is not limited to 8; for example, it can also be 32, 48, 64, or 96. For instance, to improve cutoff characteristics, each or one of the drain-side selection transistor ST1, source-side selection transistors ST2, and ST3 may not be composed of a single transistor, but rather of multiple transistors. Alternatively, the source-side selection transistor ST3 can be omitted. Furthermore, dummy cell transistors can be placed between the memory cell transistor MT and the drain-side selection transistor ST1, and between the memory cell transistor MT and the source-side selection transistor ST2.

[0077] Each memory cell transistor MT is connected in series with the drain-side selection transistor ST1 and the source-side selection transistor ST2. The memory cell transistor MT7 on one end is connected to the source of the drain-side selection transistor ST1, and the memory cell transistor MT0 on the other end is connected to the drain of the source-side selection transistor ST2.

[0078] The memory cell array 110 has m bit lines BL (BL0, BL1, ..., BL(m-1)). “m” is an integer representing the number of memory strings MS contained in one string cell SU.

[0079] In multiple memory strings MS, memory strings belonging to the same string cell SU are connected to different bit lines BL via drain-side selection transistors ST1. Furthermore, the gates of each drain-side selection transistor ST1 belonging to the same string cell SU are commonly connected to gate lines SGD0 to SGD3, which are individually provided for each string cell SU. For example, the gates of each drain-side selection transistor ST1 belonging to the same string cell SU0 are commonly connected to the gate line SGD0 corresponding to string cell SU0.

[0080] The gates of the drain-side selection transistors ST1 belonging to other string units SU1, etc., are also commonly connected to the gate lines provided corresponding to the string unit SU. In addition, gate line SGD0 is the gate line provided corresponding to string unit SU0, gate line SGD1 is the gate line provided corresponding to string unit SU1, gate line SGD2 is the gate line provided corresponding to string unit SU2, and gate line SGD3 is the gate line provided corresponding to string unit SU3.

[0081] In each string cell SU, the source of source-side select transistor ST2 is connected to the drain of source-side select transistor ST3. The source of source-side select transistor ST3 is connected to the source line SL. The source line SL is commonly connected to the sources of the multiple source-side select transistors ST2 contained in block BLK. In this way, multiple memory strings MS are commonly connected to the same source line SL via their respective source-side select transistors ST2 and ST3.

[0082] The gates of all source-side selection transistors ST2 contained in block BLK are connected to the same gate line SGS. Similarly, the gates of all source-side selection transistors ST3 contained in block BLK are connected to the same gate line SGSB.

[0083] The gates of memory cell transistors MT0, located within the same block BLK, are all connected to word line WL0. Similarly, the gates of memory cell transistors MT1, also located within the same block BLK, are all connected to word line WL1. The other memory cell transistors MT are connected in the same way. That is, the gates of memory cell transistors MT0 through MT7 are all connected to their respective corresponding word lines WL (one of WL0 through WL7).

[0084] Within a single string cell SU, a collection of multiple memory cell transistors MT connected to a common word line WL is, for example, called a cell unit CU. The collection of one bit of data stored in each memory cell transistor MT within a single cell unit CU is called a "page". In this embodiment, one bit of data is stored in each memory cell transistor MT. Therefore, one page of data is stored in each cell unit CU. Alternatively, multiple pages of data can be stored in each cell unit CU.

[0085] 1.4 Construction of Storage Cell Array

[0086] Figure 4 This is an example of the cross-sectional structure of the storage cell array 110, and the structure corresponding to a block BLK is extracted and shown.

[0087] exist Figure 4In the cross-sectional diagram, for ease of observation, some components such as the insulating layer (interlayer insulating film), wiring, and contacts have been appropriately omitted. Additionally, Figure 4 The x-direction shown corresponds to the extension direction of the bit line BL. The y-direction corresponds to the extension direction of the word line WL. The z-direction corresponds to the direction perpendicular to the surface of the semiconductor substrate 300 on which the semiconductor memory device 2 is formed.

[0088] like Figure 4 As shown, the region on the semiconductor substrate 300 in which the memory cell array 110 is formed includes, for example, a P-type well region 320, an insulating layer 321, four conductive layers 322, eight conductive layers 323, four conductive layers 324, multiple memory pillars MP, conductive layers 325, 326, 328, and contacts 327 and 329. Additionally, an insulating layer (not shown) is formed between each conductive layer.

[0089] A P-type well region 320 is disposed near the surface of the semiconductor substrate 300. The P-type well region 320 serves as a source line SL. The P-type well region 320 includes mutually separated n+ impurity diffusion regions NP and p+ impurity diffusion regions PP. The n+ impurity diffusion regions NP and p+ impurity diffusion regions PP are respectively disposed near the surface of the P-type well region 320.

[0090] An insulating layer 321 is disposed on the P-type well region 320. Four conductive layers 322, stacked separately from each other, are disposed on the insulating layer 321. Eight conductive layers 323, stacked separately from each other, are disposed above the uppermost conductive layer 322. Four conductive layers 324, stacked separately from each other, are disposed above the conductive layers 323. A conductive layer 325 is disposed above the uppermost conductive layer 324.

[0091] Each conductive layer 322 has a structure extending along the xy plane. The conductive layer 322 located on the bottommost side serves as the gate line SGSB. The three conductive layers 322 located above it serve as the gate line SGS. Figure 4 In this configuration, three source-side selection transistors ST2 and one source-side selection transistor ST3 are provided. The number of conductor layers 322 is the same as the total number of source-side selection transistors ST2 and ST3.

[0092] The conductive layer 323 has a structure that extends along the xy plane. The eight conductive layers 323, from the bottom layer onwards, are used as word lines WL0, WL1, WL2, ..., WL7, respectively.

[0093] The conductive layer 324 has a structure extending along the y-direction. The conductive layer 324 serves as the select gate line (SGD). Figure 4In the example, it is configured with three drain-side selection transistors ST1. The number of conductor layers 324 is set to be the same as the total number of drain-side selection transistors ST1.

[0094] The conductive layer 325 has a structure extending along the x-direction. The conductive layer 325 serves as a bit line BL. Multiple conductive layers 325 are arranged in a manner that aligns along the y-direction.

[0095] Each storage column (MP) corresponds to one storage string (MS). The storage columns (MP) are arranged along the x and y directions. For example... Figure 4 As shown, the individual memory pillars MP arranged along the x-direction are connected to the same conductive layer 325 (i.e., bit line BL).

[0096] The memory pillars MP, arranged along the y-direction, are connected to different conductive layers 325 (i.e., bit lines BL). For example... Figure 4 As shown, a group of storage columns MP arranged along the y-direction belong to the same string of cells SU.

[0097] Each memory pillar MP connects the insulating layer 321, the four conductive layers 322, the eight conductive layers 323, and the four conductive layers 324. The portions of the memory pillar MP that intersect with each of these conductive layers constitute transistors. The transistor located at the intersection with conductive layer 322 functions as source-side selection transistors ST2 and ST3. The transistor located at the intersection with conductive layer 323 functions as memory cell transistors MT (MT0 to MT7). The transistor located at the intersection with conductive layer 324 functions as drain-side selection transistor ST1.

[0098] Each memory column MP includes a semiconductor film 330 and a ferroelectric film 331. The semiconductor film 330 is formed, for example, as a column extending along the z-direction. The ferroelectric film 331 is a film made of ferroelectric material, formed in such a way as to cover the outer peripheral surface of the semiconductor film 330.

[0099] Figure 5 It shows along Figure 4 The diagram shows a cross-sectional structure of the VV line, illustrating an example of the cross-sectional structure of the storage pillar MP in the layer containing the conductor layer 323.

[0100] like Figure 5 As shown, in the layer containing the conductive layer 323, the semiconductor film 330 is, for example, disposed in the central portion of the memory pillar MP. The ferroelectric film 331 covers the entire outer peripheral surface of the semiconductor film 330. The conductive layer 323, which functions as the word line WL, covers the entire outer peripheral surface of the ferroelectric film 331. Alternatively, an insulating film may be embedded inside the semiconductor film 330.

[0101] like Figure 4 As shown, the lower end of the semiconductor film 330 of the storage column MP is in contact with the P-type well region 320. The upper part of the semiconductor film 330 is in contact with the conductive layer 325. In addition, the upper part of the semiconductor film 330 and the conductive layer 325 can also be electrically connected via contacts, wiring, etc.

[0102] The semiconductor film 330 is formed, for example, from undoped polycrystalline silicon. The semiconductor film 330 functions as the channel of the memory string (MS). The ferroelectric film 331 is formed, for example, from a ferroelectric material such as hafnium (HfO2). The ferroelectric film 331 functions as a barrier insulating film for the transistor. The ferroelectric film 331 changes the direction and magnitude of its spontaneous polarization according to the voltage applied to the conductive layer 323 (i.e., the word line WL). Data is stored in the memory cell transistor MT by utilizing this polarization reversal.

[0103] Conductor layer 326 is disposed, for example, in the wiring layer between the uppermost conductor layer 324 and conductor layer 325, and serves as a CELSRC. The CELSRC serves as wiring for changing the potential of the P-type well region 320. Conductor layer 326 is electrically connected to the n+ impurity diffusion region NP via contact 327.

[0104] Conductor layer 328, for example, is disposed in a wiring layer between the uppermost conductor layer 324 and conductor layer 325, and serves as a CPWELL. The CPWELL serves as wiring for changing the potential of the P-type well region 320. Conductor layer 328 is electrically connected to the p+ impurity diffusion region PP via contact 329.

[0105] The bottommost conductive layer 322 and insulating layer 321 are formed in such a way that they extend to the vicinity of the n+ impurity diffusion region NP. Thus, when the source-side selection transistor ST3 is in the on state, the memory cell transistor MTO and the n+ impurity diffusion region NP are electrically connected through a channel formed near the surface of the P-type well region 320.

[0106] 1.5 Composition of the Sensing Amplifier

[0107] Figure 6 An example configuration of the sense amplifier 120 is shown. The sense amplifier 120 includes a plurality of sense amplifier units (SAUs) associated with a plurality of bit lines BL, respectively. Figure 6 The detailed circuit configuration of one of the sensing amplifier units, SAU, is shown.

[0108] like Figure 6 As shown, the sense amplifier unit SAU includes a sense amplifier section SA, a latch circuit SDL, and an XDL. The sense amplifier section SA and the latch circuits SDL and XDL are connected to each other via a bus LBUS in a manner that enables data transmission and reception.

[0109] For example, during a read operation, the sensing amplifier section SA senses the data read from the corresponding bit line BL and determines whether the read data is "0" or "1". The sensing amplifier section SA includes, for example, a p-channel MOS transistor, namely transistor TR1, n-channel MOS transistors, namely transistors TR2 to TR9, and a capacitor C10.

[0110] One end of transistor TR1 is connected to the power supply line, and the other end of transistor TR1 is connected to transistor TR2. The gate of transistor TR1 is connected to node INV within the latch circuit SDL. One end of transistor TR2 is connected to transistor TR1, and the other end of transistor TR2 is connected to node COM. The gate of transistor TR2 is fed by the input signal BLX. One end of transistor TR3 is connected to node COM, and the other end of transistor TR3 is connected to transistor TR4. The gate of transistor TR3 is fed by the input signal BLC. Transistor TR4 is a high-voltage MOS transistor. One end of transistor TR4 is connected to transistor TR3. The other end of transistor TR4 is connected to the corresponding bit line BL. The gate of transistor TR4 is fed by the input signal BLS.

[0111] Transistor TR5 is connected to node COM at one end and to node SRC at the other end. Its gate is connected to node INV. Transistor TR6 is connected between transistors TR1 and TR2 at one end and to node SEN at the other end. Its gate is connected to the input signal HLL. Transistor TR7 is connected to node SEN at one end and to node COM at the other end. Its gate is connected to the input signal XXL.

[0112] One end of transistor TR8 is grounded, and the other end is connected to transistor TR9. The gate of transistor TR8 is connected to node SEN. One end of transistor TR9 is connected to transistor TR8, and the other end is connected to the bus LBUS. The gate of transistor TR9 is fed by the input signal STB. One end of capacitor C10 is connected to node SEN. The other end of capacitor C10 is fed by the input clock CLK.

[0113] Signals BLX, BLC, BLS, HLL, XXL, and STB are generated, for example, by sequencer 41. Additionally, a power supply line connected to one end of transistor TR1 is applied, for example, as the internal power supply voltage Vdd of the semiconductor memory device 2, and node SRC is applied, for example, as the ground voltage Vss of the semiconductor memory device 2. The internal power supply voltage Vdd is, for example, 1.5V, and the ground voltage Vss is, for example, 0V.

[0114] The latch circuits SDL and XDL temporarily hold the read data. The latch circuit XDL is connected to the input / output circuit 21 and is used to sense the input and output of data between the amplifier unit SAU and the input / output circuit 21.

[0115] The latch circuit SDL includes, for example, inverters IV11 and IV12, and TR13 and TR14 as n-channel MOS transistors. The input node of inverter IV11 is connected to node LAT. The output node of inverter IV11 is connected to node INV. The input node of inverter IV12 is connected to node INV. The output node of inverter IV12 is connected to node LAT. One end of transistor TR13 is connected to node INV, and the other end is connected to the bus LBUS. The gate of transistor TR13 is connected to the input signal STI. One end of transistor TR14 is connected to node LAT, and the other end is connected to the bus LBUS. The gate of transistor TR14 is connected to the input signal STL. For example, the data held in node LAT is equivalent to the data held in the latch circuit SDL. Furthermore, the data held in node INV is equivalent to the inverted data of the data held in node LAT. The circuit configuration of the latch circuit XDL is, for example, the same as that of the latch circuit SDL, and therefore descriptions are omitted.

[0116] 1.6 Structure of a memory cell transistor

[0117] In the semiconductor memory device 2 according to this embodiment, the memory cell transistor MT is a so-called ferroelectric field-effect transistor (FeFET) that stores data through the spontaneous polarization of the ferroelectric film 331.

[0118] Reference Figure 7 and Figure 8 Explain the characteristics of the memory cell transistor MT. Figure 7 This is a graph showing the relationship between the applied voltage and polarization on the memory cell transistor MT. Figure 7 The horizontal axis VG represents the voltage applied between the channel (semiconductor film 330) of the memory cell transistor MT and the word line WL (conductor layer 323). Figure 7 The vertical axis represents the polarizability of the ferroelectric film 331. Figure 8 It is a cross-sectional view schematically showing the state of the memory cell transistor MT, and more specifically the spontaneous polarization state of the ferroelectric film 331.

[0119] exist Figure 7 In the state shown in P1, the applied voltage to the memory cell transistor MT is 0V, and the ferroelectric film 331 spontaneously polarizes in the positive direction. Figure 8Figure (A) shows the state of the memory cell transistor MT at point P1. In this state, a positive charge is induced on the surface of the ferroelectric film 331 on the side of the semiconductor film 330. At the surface of the semiconductor film 330 on the side of the ferroelectric film 331, a channel connection is achieved as indicated by reference numeral "330A" due to the electric field from the ferroelectric film 331. Thus, the memory cell transistor MT becomes conductive.

[0120] If the applied voltage is increased towards the negative side from the state shown in P1 (i.e., the potential of word line WL is decreased), the polarization of the ferroelectric film 331 will change along... Figure 7 The hysteresis loop changes in the direction of arrow AR11. When the applied voltage is V1, polarization reversal occurs, and the polarization of the ferroelectric film 331 reverses to the negative direction. After this, if the applied voltage is changed to the positive side (i.e., the potential of the word line WL is increased) after passing through the voltage value where the absolute value of the polarization is maximum, the absolute value of the polarization of the ferroelectric film 331 will change along... Figure 7 The hysteresis loop decreases slightly in the direction of arrow AR12. When the applied voltage is 0V, it becomes the state shown in P2, and the polarization state of P2 is maintained even when the external voltage is 0V.

[0121] In the state shown in P2, the applied voltage to the memory cell transistor MT is 0V, and the ferroelectric film 331 spontaneously polarizes in the negative direction. That is, as mentioned above, polarization reversal occurs from the state shown in P1. Figure 8 (B) shows the state of the memory cell transistor MT at P2. In this state, a negative charge is induced on the surface of the ferroelectric film 331 on the side of the semiconductor film 330. At the surface of the semiconductor film 330 on the side of the ferroelectric film 331, the channel is cut off due to the electric field from the ferroelectric film 331. Thus, the memory cell transistor MT is in the off state.

[0122] If the applied voltage is increased towards the positive side from the state shown in P2 (i.e., the potential of word line WL is further increased), the polarization of ferroelectric film 331 will increase along... Figure 7 The hysteresis loop changes in the direction of arrow AR21. When the applied voltage becomes V2, polarization reversal occurs again, and the polarization of the ferroelectric film 331 reverses to the positive direction. After this, if the applied voltage is changed to the negative side (i.e., the potential of the word line WL is reduced) after the voltage value that has passed the point where the absolute value of the polarization is maximum, the absolute value of the polarization of the ferroelectric film 331 will change along... Figure 7 The hysteresis loop decreases slightly in the direction of arrow AR22. When the applied voltage is 0V, it becomes the state shown in P1, and the polarization state of P1 is maintained even when the external voltage is 0V.

[0123] As described above, the memory cell transistor MT can alternately switch the ferroelectric film 331 as described above by varying the applied voltage via the word line WL. Figure 8 The state of spontaneous polarization in the positive direction, as in (A) and such Figure 8 (B) is a state that spontaneously polarizes in the negative direction.

[0124] In such Figure 8 As shown in (A), if the applied voltage is changed in the negative direction when the ferroelectric film 331 is spontaneously polarized in the positive direction (i.e., the potential of the word line WL is reduced), the channel will be cut off midway, causing the memory cell transistor MT to be turned off. That is, when the ferroelectric film 331 is spontaneously polarized in the positive direction, the threshold voltage Vth of the memory cell transistor MT is negative.

[0125] On the other hand, in such Figure 8 As shown in (B), when the ferroelectric film 331 is spontaneously polarized in the negative direction, if the applied voltage is changed in the positive direction (i.e., the potential of the word line WL is increased), it will become a channel connection state midway, making the memory cell transistor MT turn on. That is, when the ferroelectric film 331 is spontaneously polarized in the positive direction, the threshold voltage of the memory cell transistor MT is positive.

[0126] As described above, the memory cell transistor MT in this embodiment is configured such that the direction of spontaneous polarization changes according to the applied voltage between the word line WL and the channel, and the threshold voltage changes accordingly. Specifically, the memory cell transistor MT is configured such that if a voltage is applied that causes the potential of the word line WL to increase beyond the voltage that causes polarization reversal compared to the potential of its channel, the threshold voltage decreases; conversely, if a voltage is applied that causes the potential of the word line WL to decrease beyond the voltage that causes polarization reversal compared to the potential of its channel, the threshold voltage increases.

[0127] Figure 9 (A) represents the relationship between the threshold voltage Vth (horizontal axis) of the memory cell transistor MT and the probability of its existence (vertical axis). When using SLC (Single Level Cell) as the storage method for the memory cell transistor MT, the threshold voltages of multiple memory cell transistors MT are formed... Figure 9 The two distributions shown in (A) are referred to as Pr level and Er level, starting from the one with the lower threshold voltage.

[0128] The Pr level is the ferroelectric film 331, as shown. Figure 8 The distribution of the threshold voltage Vth in the state of spontaneous polarization in the positive direction, as in (A). The Pr level is the state in which data is written, such as data assigned "0".

[0129] Er level is the ferroelectric film 331, such as Figure 8 The threshold voltage Vth distribution in the state of spontaneous polarization in the negative direction, as shown in (B). The Er level represents the state where data has been erased, such as data assigned "1". When an erase operation is performed, the threshold voltage distribution of the memory cell transistor MT changes from the Pr level to the Er level.

[0130] 1.7 Write Action

[0131] In the semiconductor memory device 2 of this embodiment, if... Figure 3 If the bit lines BL0 to BL(m-1) shown are designated as even-numbered bit lines (BL0, BL2, BL4, ...) and BL1, BL3, BL5, ... are designated as odd-numbered bit lines, then read and write operations are performed separately on the even-numbered and odd-numbered bit lines. The following explanation uses the case of writing to the memory cell transistor MT corresponding to bit lines BL2 and BL4 as an example.

[0132] Figure 10 and Figures 12-16 The simplified diagram shows the memory strings MS11 and MS12 corresponding to bit line BL2. Figure 11 The simplified diagram shows the memory strings MS21 and MS22 corresponding to bit line BL4. Figures 10-16 In the diagram, transistors ST1, ST2, and ST3 that are in the off state are marked with a cross. Additionally, in... Figures 10-16 The text enclosed in rectangles, such as “Vss”, “Vsgd”, “Vpass”, and “Vpgm”, indicates the voltage of each part. Figures 10-16 The voltage of each component is shown during a write operation. For example... Figures 10-16 The voltage adjustment process shown is achieved by the sequencer 41 controlling the sensing amplifier 120, the line decoder 130, and the voltage generation circuit 43, etc.

[0133] In this implementation, the write operation is selectively performed on specific pages. Figures 10-16 In the image, the transistor MT, the memory cell to be written to, is shown enclosed by a single-dotted line. That is, in... Figures 10-16 The example illustrates the case where string cell SU0 is selected as the object of the write operation, and string cell SU1 is not selected as the object of the write operation.

[0134] Hereinafter, the string cell SU0 selected as the object of a write operation is referred to as the "selected string cell SU0," and the string cell SU1 not selected as the object of a write operation is referred to as the "non-selected string cell SU1." Furthermore, in the selected string cell SU0, the memory cell transistor MT that will be the object of a write operation is referred to as the "selected memory cell transistor sMT," and the word line WL connected to the selected memory cell transistor sMT is also referred to as the "selected word line sWL." In this embodiment, the selected word line sWL is equivalent to the first word line. Additionally, in the selected string cell SU0, memory cell transistors other than the selected memory cell transistor sMT are referred to as "non-selected memory cell transistor uMT," and the word line WL connected to the non-selected memory cell transistor uMT is also referred to as the "non-selected word line uWL." In this embodiment, the selected memory cell transistor sMT is equivalent to the first memory cell transistor.

[0135] In addition, in selecting memory cell transistors (sMT), besides Figures 10-16 In addition to the memory cell transistors shown, there are also memory cell transistors MT belonging to other memory strings MS of string unit SU0.

[0136] Figure 17 This is a timing diagram showing the voltage shifts of each part of the memory cell array 110 during such a write operation. Figure 17 In the diagram, "SGD0" indicates the voltage shift of gate line SGD0, and "SGD1" indicates the voltage shift of gate line SGD1. "sWL" indicates the voltage shift of select word line sWL, and "uWL" indicates the voltage shift of non-select word line uWL. "SGS, SGSB" indicates the voltage shift of gate lines SGS and SGSB, and "SEN" indicates the voltage shift of node SEN in the sense amplifier section SA. "BL2" indicates the voltage shift of bit line BL2, and "BL4" indicates the voltage shift of bit line BL4. "BL1, BL3, BL5" indicates the voltage shift of bit lines BL1, BL3, and BL5, and "SL" indicates the voltage shift of source line SL.

[0137] Figure 18 (A) to (E) are timing diagrams showing the shifts of each signal BLC, BLX, HLL, XXL, and STB of the sense amplifier 120 during the above-mentioned write operation.

[0138] like Figure 17 and Figure 18As shown, in the write operation of this embodiment, a first programming operation and a second programming operation are performed sequentially. The first programming operation is an operation for writing data to the storage cell array 110. In this embodiment, the first programming operation is equivalent to the application of a first pulse. The second programming operation is an operation for re-writing data if the first programming operation fails to fully write the data. The second programming operation can also be performed repeatedly.

[0139] 1.7.1 First Programming Action

[0140] exist Figure 17 and Figure 18 In the code, the start time of the write operation, or in other words, the start time of the first programming operation, is shown as "t10". For example... Figure 17 As shown, at time points before t10, each part of the memory cell array 110 is subjected to a ground voltage Vss. Additionally, as... Figure 18 As shown, all signals of the sensing amplifier 120 are set to low level.

[0141] After the first programming action begins at time t10, from Figure 2 The input / output circuit 21 shown transmits write data to the sense amplifier 120. Thus, in Figure 6 The latch circuit SDL of the shown sense amplifier 120 holds either "1" or "0" data. When "0" data is held in the latch circuit SDL, node LAT is set to low and node INV is set to high. Therefore, transistor TR1 is off and transistor TR5 is on. Conversely, when "1" data is held in the latch circuit SDL, node LAT is set to high and node INV is set to low. Therefore, transistor TR1 is on and transistor TR5 is off.

[0142] like Figure 18 As shown in (A) and (B), after the first programming action begins at time t10, signals BLC and BLX are set to high level. Therefore, Figure 6 Transistors TR2 and TR3 are turned on. At this time, with "0" data held in the latch circuit SDL, transistor TR1 is turned off as described above, and transistor TR5 is turned on. Therefore, by turning on transistor TR4, the voltage applied to node SRC, i.e., the ground voltage Vss, is applied to bit line BL. Thus, for example, when writing "0" data to the select memory cell transistor sMT corresponding to bit line BL2, as... Figure 10 and Figure 17As shown in (G), a ground voltage Vss is applied to bit line BL2. In this embodiment, the ground voltage Vss applied to bit line BL2 during the first programming operation is equivalent to the second voltage.

[0143] On the other hand, Figure 6 When the latch circuit SDL shows a "1" data value, transistor TR1 is turned on and transistor TR5 is turned off as described above. Therefore, by turning on transistor TR4, the internal power supply voltage Vdd is applied to bit line BL. Thus, for example, when writing a "1" data value to the select memory cell transistor sMT corresponding to bit line BL4, as... Figure 11 and Figure 17 As shown in (H), the bit line BL4 is supplied with the internal power supply voltage Vdd.

[0144] like Figure 17 As shown in (E), when the first programming operation begins at time t10, the gate lines SGS and SGSB are maintained in a state where a ground voltage Vss is applied. Therefore, as... Figure 10 and Figure 11 As shown, the source-side selection transistors ST2 and ST3 of each of the selected string unit SU0 and the non-selected string unit SU1 are kept off.

[0145] On the other hand, such as Figure 17 As shown in (A), after the first programming operation begins at time t10, the voltage of the gate line SGD0 of the selected serial cell SU0 rises to voltage Vsgd. Voltage Vsgd is a voltage that enables the drain-side selection transistor ST1 to turn on when a ground voltage Vss is applied to the bit line BL, and enables the drain-side selection transistor ST1 to turn off when an internal power supply voltage Vdd is applied to the bit line BL; for example, it is 1.5V. Therefore, as... Figure 10 As shown, the drain-side selection transistor ST1 of the selection string unit SU0 corresponding to bit line BL2 is turned on. In contrast, as... Figure 11 As shown, the drain-side selection transistor ST1 of the selection string unit SU0 corresponding to bit line BL4 is turned off. As a result, the channel of the memory string MS21 of the selection string unit SU0 is in a floating state.

[0146] In addition, such as Figure 17 As shown in (B), when the first programming operation begins at time t10, the gate line SGD1 of the non-selection string cell SU1 remains in a state where a ground voltage Vss is applied. Therefore, as Figure 10 and Figure 11As shown, since the drain-side selection transistor ST1 of the non-selection string unit SU1 remains in the off state, the channels of the memory strings MS12 and MS22 of the non-selection string unit SU1 become floating.

[0147] like Figure 17 As shown in (C) and (D), after the first programming action begins at time t10, the voltages of the select word line sWL and the non-select word line uWL rise to the pass voltage Vpass. The pass voltage Vpass is set to... Figure 9 The value shown in (A), specifically, is a voltage high enough to turn on the memory cell transistor MT and low enough to prevent writing, for example, set to 3V. Figure 9 As shown in (A), the pass voltage Vpass is set to a voltage higher than the maximum threshold voltage in the Er level of the memory cell transistor MT. Therefore, when the pass voltage Vpass is applied to the gate of the memory cell transistor MT, the memory cell transistor MT becomes in the on state regardless of the stored data.

[0148] If a pass voltage Vpass is applied to the select word line sWL and the non-select word line uWL, then in the memory string MS11 of the select string cell SU0, the select memory cell transistor sMT and the non-select memory cell transistor uMT become in an on state to the extent that no writing is performed. Therefore, as Figure 10 As shown, a ground voltage Vss is applied from bit line BL2 to the channel of memory string MS11 of selection string cell SU0 through drain-side selection transistor ST1, which is in the on state.

[0149] Next, as Figure 17 As shown in (C), at time t11, the voltage of the select word line sWL further rises to the programming voltage Vpgm. The programming voltage Vpgm is a high voltage, for example, set to 6V, to turn on the memory cell transistor MT and to write to the memory cell transistor MT. In this embodiment, the programming voltage Vpgm applied to the select word line sWL during the first programming operation is equivalent to the first voltage. When the programming voltage Vpgm is applied to the select word line sWL, the ferroelectric film 331 of the select memory cell transistor sMT provided in the memory string MS11 of the select string unit SU0 spontaneously polarizes according to the potential difference between the ground voltage Vss applied to the channel of the memory string MS11 and the programming voltage Vpgm applied to the select word line sWL. That is, the threshold voltage Vth of the select memory cell transistor sMT decreases to Figure 9 The Pr level shown in (A) represents the state in which data of "0" has been written into the select memory cell transistor sMT. In contrast, as... Figure 11As shown, since the channel of the memory string MS21 in the select string cell SU0 is in a floating state, even if a programming voltage Vpgm is applied to the select word line sWL, the ferroelectric film 331 of the select memory cell transistor sMT of the memory string MS21 will not spontaneously polarize. That is, the threshold voltage Vth of the select memory cell transistor sMT of the memory string MS21 remains unchanged. Figure 9 The Er level shown in (A) results in a state where data of "1" has been written. Additionally, as... Figure 10 and Figure 11 As shown, since the channels of the memory strings MS12 and MS22 of the non-selection string unit SU1 are in a floating state, even if the programming voltage Vpgm is applied to the select word line sWL, the memory cell transistor MT corresponding to the select word line sWL will not be written.

[0150] like Figure 17 As shown in (C), at time t12, the voltage of the select word line SWL drops from the programming voltage Vpgm to the ground voltage Vss. Additionally, as... Figure 18 As shown in (A) and (B), at time t12, signals BLC and BLX of the sensing amplifier 120 are set to low level. Thereafter, signals BLC, BLX, HLL, XXL, and STB of the sensing amplifier 120 are maintained at low level. Therefore, at... Figure 6 In the sense amplifier 120 shown, transistors TR2 and TR3 are maintained in a state where both are turned off. That is, bit line BL2 remains unconnected to node SRC and is not subjected to the internal power supply voltage Vdd. Additionally, as... Figure 17 As shown in (F), the voltage at node SEN is maintained at the ground voltage Vss.

[0151] In addition, such as Figure 17 As shown in (I), after the first programming operation begins at time t10, the voltage of the odd-numbered bit lines, including the bit lines BL1 and BL3 adjacent to each other on both sides of bit line BL2, still rises to the internal power supply voltage Vdd and remains in this state. This avoids the voltage fluctuations of the odd-numbered bit lines affecting the voltage of the even-numbered bit lines. In this embodiment, the internal power supply voltage Vdd applied to the odd-numbered bit lines is equivalent to a predetermined voltage.

[0152] However, if a "0" data is written to the selection memory cell transistor sMT in the memory string MS11 set in the selection string unit SU0, due to individual differences, a change will occur in the threshold voltage Vth of the selection memory cell transistor sMT after the write operation. Figure 9 The deviation shown in (B). In this embodiment, the threshold voltage Vth of the select memory cell transistor sMT after the write operation is less than Figure 9When the verification voltage Vpvfy is as shown in (B), the writing of the selected memory cell transistor sMT is determined to be complete. On the other hand, when the threshold voltage Vth of the selected memory cell transistor sMT is higher than or equal to the verification voltage Vpvfy, the writing of the selected memory cell transistor sMT is determined to be incomplete. In this embodiment, the verification voltage Vpvfy is equivalent to the write determination voltage.

[0153] Furthermore, in this embodiment, as described above, following the first programming operation, a second programming operation is performed to rewrite data onto the select memory cell transistor sMT that was not yet fully written. Specifically, the second programming operation is performed when the threshold voltage Vth of the select memory cell transistor sMT after the write operation is... Figure 9 When the verification voltage Vpvfy shown in (B) is above a certain value, the data writing operation is performed again on the selected memory cell transistor sMT. By performing one or more second programming operations, the distribution of the threshold voltage Vth of the selected memory cell transistor sMT can be transformed into... Figure 9 The distribution shown in (A) transforms into a distribution smaller than the verification voltage Vpvfy.

[0154] 1.7.2 Second Programming Action

[0155] like Figure 17 As shown, in the second programming operation, a pre-charge operation and a pulse application operation are performed sequentially. The pre-charge operation is used to apply the voltage required for writing data again to the bit line BL. The pulse application operation is used to write data to the select memory cell transistor sMT again using the voltage applied to the bit line BL. In this embodiment, the pulse application operation of the second programming operation is equivalent to the second pulse application operation.

[0156] 1.7.2.1 Pre-charge action of the second programmed action

[0157] exist Figure 17 and Figure 18 In the text, the start time of the second programming action, or in other words, the start time of the pre-charge action, is shown as "t13".

[0158] At the time point t13 when the pre-charging action begins, such as Figure 17 As shown in (C), a ground voltage Vss is applied to the select word line SWL. In this embodiment, the ground voltage Vss applied to the select word line SWL during the pre-charge operation is equivalent to a third voltage. Additionally, as... Figure 17 As shown in (D), the non-select word line uWL is subjected to a read pass voltage Vread. In this embodiment, the read pass voltage Vread is set to, for example, 3V, as... Figure 9As shown in (B), it is set to the same value as the voltage Vpass.

[0159] like Figure 17 As shown in (J), at time t13, the voltage of the source line SL rises to the internal power supply voltage Vdd. In this embodiment, the internal power supply voltage Vdd applied to the source line SL during the pre-charge operation is equivalent to the fourth voltage. Furthermore, as... Figure 17 As shown in (A), at time t14, the voltage of the gate line SGD0 of the selected serial cell SU0 rises to the read pass voltage Vread, and as... Figure 17 As shown in (E), at time t15, the voltages of the gate lines SGS and SGSB also rise to the read pass voltage Vread.

[0160] As mentioned above, such as Figure 12 As shown, in the memory string MS11 of the selected string cell SU0, the drain-side selection transistor ST1, the source-side selection transistors ST2 and ST3, and multiple non-selected memory cell transistors uMT are in the on state. At this time, the voltage corresponding to the write state of the selected memory cell transistor sMT is applied to the bit line BL2 for charging.

[0161] Specifically, when selecting the threshold voltage Vth of the memory cell transistor sMT, it is important to understand that... Figure 9 In the case of region A11 shown in (B), that is, when the threshold voltage Vth of the selected memory cell transistor sMT is less than the ground voltage Vss, the voltages of each part of the memory string MS11 become Figure 12 The situation is as shown. As... Figure 12 As shown, the internal power supply voltage Vdd is applied from the source line SL to the portion of the channel of the memory string MS11 located closer to the source line SL than the select memory cell transistor sMT, via source-side select transistors ST2 and ST3. Therefore, the source of the select memory cell transistor sMT is supplied with the internal power supply voltage Vdd. Since the select word line sWL is supplied with ground voltage Vss in this state, the select memory cell transistor sMT will be turned on as long as the threshold voltage Vth of the select memory cell transistor sMT is less than the ground voltage Vss. At this time, in the portion of the channel of the memory string MS11 located closer to the bit line BL2 than the select memory cell transistor sMT, a voltage is generated... Figure 7 The voltage corresponding to the polarization P1 shown is specifically a voltage equivalent to the absolute value |Vth| of the threshold voltage of the select cell transistor sMT. This voltage |Vth| is applied to bit line BL2 via the drain-side select transistor ST1. At this time, bit line BL2 is not connected to either node SRC or the internal power supply voltage Vdd. Therefore, voltage |Vth| is charged on bit line BL2.

[0162] Furthermore, when the write operation of the selected memory cell transistor sMT is complete, the threshold voltage Vth of the selected memory cell transistor sMT is less than... Figure 9 The verification voltage Vpvfy shown in (B) is therefore as follows Figure 17 As shown by the solid line in (G), bit line BL2 will be subjected to a voltage greater than the absolute value of the check voltage, |Vpvfy|. In contrast, when the write operation to the select cell transistor sMT is not complete, the threshold voltage Vth of the select cell transistor sMT satisfies "Vpvfy ≤ Vth < 0", therefore... Figure 17 As shown by the dashed line in (G), bit line BL2 will be subjected to a voltage with an absolute value of |Vpvfy| less than and greater than the ground voltage Vss.

[0163] On the other hand, when selecting the threshold voltage Vth of the memory cell transistor sMT, it belongs to Figure 9 In the case of region A12 shown in (B), that is, when the threshold voltage Vth of the selected memory cell transistor sMT is above the ground voltage Vss, the voltage of each part of the memory string MS11 becomes Figure 13 The situation is illustrated. In this case, when the source of the select cell transistor sMT is supplied with an internal power supply voltage Vdd and the select word line sWL is supplied with a ground voltage Vss, the select cell transistor sMT will be in a turned-off state. Therefore, the voltage of the portion of the channel of the memory string MS11 located closer to the bit line BL2 than the select cell transistor sMT, and the voltage of the bit line BL2 itself, are maintained. Specifically, as shown... Figure 17 As shown by the dashed line in (G), the voltage of bit line BL2 is maintained at the ground voltage Vss.

[0164] As described above, by performing a pre-charge operation, the charging voltage of bit line BL2 is as follows: Figure 19 As shown, it is set according to the threshold voltage Vth of the selected memory cell transistor sMT.

[0165] (a1) When the threshold voltage Vth of the selected memory cell transistor sMT satisfies "Vth < Vpvfy", that is, when the writing of the selected memory cell transistor sMT is completed, the charging voltage Vb of the bit line BL2 becomes the voltage |Vth|. At this time, the charging voltage Vb of the bit line BL2 satisfies "Vb > |Vpvfy|".

[0166] (a2) When the threshold voltage Vth of the selected memory cell transistor sMT satisfies "Vpvfy≦Vth<Vss", that is, when the writing of the selected memory cell transistor sMT is not completed, the charging voltage Vb of the bit line BL2 becomes the voltage |Vth|. At this time, the charging voltage Vb of the bit line BL2 satisfies "Vss<Vb≦|Vpvfy|".

[0167] (a3) When the threshold voltage Vth of the selected memory cell transistor sMT satisfies “Vss≦Vth”, that is, when the writing of the selected memory cell transistor sMT is not completed, the charging voltage Vb of the bit line BL2 becomes the ground voltage Vss.

[0168] like Figure 17 As shown in (E), at time t16, the voltages of gate lines SGS and SGSB drop from the read pass voltage Vread to the ground voltage Vss. Additionally, as... Figure 17 As shown in (A), (D), and (J), at time t17, the gate line SGD0, the non-select word line uWL, and the source line SL drop to the ground voltage Vss.

[0169] 1.7.2.2 Pulse application action of the second programmed action

[0170] exist Figure 17 and Figure 18 In the diagram, the moment when the pulse for the second programmed action begins is indicated as "t18".

[0171] like Figure 17 As shown in (E), at the start of the pulse application at time t18, the gate lines SGS and SGSB are subjected to a ground voltage Vss, therefore the source-side selection transistors ST2 and ST3 are both in the off state. Therefore, as... Figure 14 As shown, bit line BL2 remains in a floating state with a charging voltage Vb. The charging voltage Vb of bit line BL2 is applied to the channel of memory string MS11, thereby enabling a rewrite to the select memory cell transistor sMT.

[0172] Specifically, such as Figure 17 As shown in (C) and (D), after the pulse is applied at time t18, the voltages of the select word line sWL and the non-select word line uWL rise to the pass voltage Vpass. Therefore, as... Figure 14 As shown, the selection transistor sMT and the non-selection transistor uMT are turned on. Then, as... Figure 17 As shown in (C), at time t19, the voltage of the select word line SWL rises further to the programming voltage Vpgm.

[0173] On the other hand, such as Figure 17As shown in (A), when the pulse is applied at time t18, the gate line SGD0 voltage rises to “Vth_sgd+|Vpvfy|”. “Vth_sgd” is the threshold voltage of the drain-side selection transistor ST1. This “Vth_sgd+|Vpvfy|” is applied to the gate line SGD0, so that according to the states (a1) to (a3) ​​above, the drain-side selection transistor ST1 is either in the on state or the off state.

[0174] In addition, such as Figure 17 As shown in (C), at time t20, the voltage of the select word line SWL drops from the programming voltage Vpgm to the ground voltage Vss.

[0175] 1.7.2.2.1 Incomplete writing, i.e., the situation described in (a2) above.

[0176] In this case, the charging voltage Vb of bit line BL2 satisfies "Vss<Vb≦|Vpvfy|" as described above. Therefore, if the voltage of gate line SGD0 is set to "Vth_sgd+|Vpvfy|", the potential difference generated between the drain and gate in the drain-side selection transistor ST1 will be above the threshold voltage Vth_sgd. Therefore, if... Figure 14 As shown, the drain-side select transistor ST1 is turned on. As a result, the charging voltage Vb of bit line BL2, i.e., voltage |Vth|, is applied to the channel of memory string MS11 through the drain-side select transistor ST1. At this time, the select cell transistor sMT spontaneously polarizes according to the potential difference between the voltage |Vth| applied to the channel of memory string MS11 and the programming voltage Vpgm applied to the select word line sWL. By causing the select cell transistor sMT to spontaneously polarize in this way, the threshold voltage Vth of the incomplete write select cell transistor sMT will become less than the verification voltage Vpvfy, thus enabling the write operation of the select cell transistor sMT to be completed.

[0177] Additionally, because a voltage greater than the ground voltage Vss is applied to the channel of memory string MS11, therefore... Figure 10As shown, compared to the execution of the first programming operation when a ground voltage Vss is applied to the channel of memory string MS11, the potential difference generated in the select cell transistor sMT can be reduced. Therefore, the select cell transistor sMT can be spontaneously polarized in a less intense manner compared to the first programming operation. When the charging voltage Vb of bit line BL2 satisfies "Vss<Vb≦|Vpvfy|", the select cell transistor sMT is in a state where the write operation is incomplete, but it is in a state where some writing has been performed. Therefore, by spontaneously polarizing the select cell transistor sMT in a relatively weaker manner, the write operation of the select cell transistor sMT can be completed while avoiding excessive spontaneous polarization of the select cell transistor sMT in the second programming operation.

[0178] 1.7.2.2.2 Incomplete writing, i.e., the situation described in (a3) ​​above.

[0179] In this case, the charging voltage Vb of bit line BL2 is set to the ground voltage Vss. Therefore, if the voltage of gate line SGD0 is set to "Vth_sgd+|Vpvfy|", the potential difference generated between the drain and gate in the drain-side selection transistor ST1 will exceed the threshold voltage Vth_sgd. Therefore, if... Figure 15 As shown, the drain-side select transistor ST1 is turned on. As a result, the charging voltage Vb of bit line BL2, i.e., the ground voltage Vss, is applied to the channel of memory string MS11 via the drain-side select transistor ST1. At this time, the select memory cell transistor sMT spontaneously polarizes according to the potential difference between the ground voltage Vss applied to the channel of memory string MS11 and the programming voltage Vpgm applied to the select word line sWL. That is, the select memory cell transistor sMT undergoes the same write operation as the first programming operation.

[0180] When the charging voltage Vb of bit line BL2 satisfies "Vb=Vss", the selection memory cell transistor sMT is almost never written to. By performing the same writing operation as the first programming operation on such a selection memory cell transistor sMT, the writing of the selection memory cell transistor sMT can be completed.

[0181] 1.7.2.2.3 The case where the above (a1) is completed after writing.

[0182] In this case, the charging voltage Vb of bit line BL2 satisfies "Vb > |Vpvfy|". Therefore, if the voltage of gate line SGD0 is set to "Vth_sgd + |Vpvfy|", the potential difference between the drain and gate in the drain-side selection transistor ST1 will be less than the threshold voltage Vth_sgd. Therefore, if... Figure 16As shown, the drain-side select transistor ST1 is turned off. Therefore, the channel of memory string MS11 becomes floating. As a result, even if a programming voltage Vpgm is applied to the select word line sWL, the select memory cell transistor sMT will not spontaneously polarize further.

[0183] When the charging voltage Vb of bit line BL2 satisfies "Vb>|Vpvfy|", the select memory cell transistor sMT is in the write-complete state. Since the select memory cell transistor sMT will not spontaneously polarize further, excessive spontaneous polarization of the write-complete select memory cell transistor sMT during the second programming operation can be avoided.

[0184] 1.7.3 Sequencer Operation

[0185] Next, refer to Figure 20 and Figure 21 The processing steps for the write operation performed by the sequencer 41 are explained in detail. Furthermore, whenever data is written to a specified string cell SU and then to the selection memory cell transistor sMT corresponding to the selection word line sWL, the following steps are performed: Figure 20 The processing is shown. Additionally... Figure 20 The initial value of the counter C shown is set to "0".

[0186] like Figure 20 As shown, the sequencer 41 first performs the first programming action (step S10). Specifically, the sequencer 41 performs a write operation to the selection memory cell transistor sMT corresponding to the selection word line sWL of the selection string cell SU.

[0187] Next, sequencer 41 executes the second programming action described above (step S11). Sequencer 41 executes... Figure 21 The processing shown is the second programming action.

[0188] like Figure 21 As shown, the sequencer 41 first performs the pre-charge operation described above (step S110). Specifically, the sequencer 41 turns on the drain-side selection transistor ST1 and the source-side selection transistors ST2 and ST3 corresponding to the selection string cell SU, and applies the internal power supply voltage Vdd to the source line SL. In addition, the sequencer 41 applies the ground voltage Vss to the selection word line sWL and applies the read pass voltage Vread to the non-selection word line uWL. Thus, the bit line BL corresponding to the selection memory cell transistor sMT, which has been written with "0", can be charged with voltage |Vth| or ground voltage Vss.

[0189] Next, the sequencer 41 executes the pulse application operation (step S111) in the second programming operation described above. Specifically, the sequencer 41 turns off the source-side selection transistors ST2 and ST3, and applies "Vth_sgd+|Vpvfy|" to the gate line SGD0. Additionally, it applies the programming voltage Vpgm to the select word line sWL. Therefore, when the writing of "0" data to the select memory cell transistor sMT is complete, since the drain-side selection transistor ST1 is off, no further writing operation is performed on the select memory cell transistor sMT. Conversely, when the writing of "0" data to the select memory cell transistor sMT is incomplete, the drain-side selection transistor ST1 is turned on, and the channel of the memory string MS is supplied with the bit line BL charging voltage Vb. Therefore, in the select memory cell transistor sMT, the writing operation corresponding to the potential difference between the bit line BL charging voltage Vb and the programming voltage Vpgm is performed.

[0190] Thus, when Figure 21 After the second programming action shown is completed, as follows Figure 20 As shown, after incrementing the value of counter C (step S12), sequencer 41 determines whether the value of counter C is greater than or equal to the determination value Cth (step S13). The determination value Cth is set to an integer greater than or equal to 1. If the value of counter C is not greater than or equal to the determination value Cth (step S13: No), sequencer 41 returns to the processing of step S11 and executes the second programming action again. Each time the second programming action is executed, the value of counter C is incremented. Therefore, the value of counter C is equal to the number of times the second programming action is executed. When the value of counter C becomes greater than or equal to the determination value Cth (step S13: Yes), sequencer 41 initializes the value of counter C (step S14) and ends. Figure 20 The processing is shown.

[0191] 1.8 Functions and Effects

[0192] In the semiconductor memory device 2 of this embodiment, when the sequencer 41 performs a write operation on one of the memory cell transistors MT, namely the select memory cell transistor sMT, it performs a first programming operation and a second programming operation. In the first programming operation, with the drain-side select transistor ST1 turned on and the source-side select transistors ST2 and ST3 turned off, the sequencer 41 applies a programming voltage Vpgm to the select word line sWL corresponding to the select memory cell transistor sMT, and applies a ground voltage Vss lower than the programming voltage Vpgm to the bit line BL, thereby reducing the threshold voltage Vth of the select memory cell transistor sMT. The second programming operation includes a pre-charge operation and a pulse application operation. In the pre-charge operation, after performing the first programming operation, with the drain-side select transistor ST1 and the source-side select transistors ST2 and ST3 turned on, the sequencer 41 charges the bit line BL by applying the ground voltage Vss to the select word line sWL and applying an internal power supply voltage Vdd to the source line SL. During the pulse application operation, after performing the pre-charge operation, the sequencer 41 applies the programming voltage Vpgm to the select word line sWL while the bit line BL is still kept in a floating state by the sensing amplifier section SA, the drain-side select transistor ST1 is turned on and the source-side select transistors ST2 and ST3 are turned off.

[0193] According to this configuration, since the rewriting to the select memory cell transistor sMT is performed using the voltage charged by the bit line BL, the processing of reading the data written to the select memory cell transistor sMT through the sense amplifier 120 and the processing of setting the voltage applied to the bit line BL based on the data are unnecessary. Therefore, the writing operation can be performed at a higher speed.

[0194] In the semiconductor memory device 2 of this embodiment, during the pulse application operation of the second programming operation, the sequencer 41 applies "Vth_sgd+|Vpvfy|" to the gate line SGD0 of the drain-side selection transistor ST1. "Vth_sgd+|Vpvfy|" is a voltage that enables the drain-side selection transistor ST1 to be turned on when the charging voltage Vb of the bit line BL is below the absolute value of the verification voltage |Vpvfy|, and to be turned off when the charging voltage Vb of the bit line BL is above the absolute value of the verification voltage |Vpvfy|.

[0195] According to this configuration, when the charging voltage Vb of bit line BL is greater than the absolute value of the verification voltage |Vpvfy|, that is, when the write operation of the select cell transistor sMT is completed, the drain-side select transistor ST1 is turned off. Therefore, as Figure 16As shown, this avoids further writing to the selected memory cell transistor sMT when the programming voltage Vpgm is applied to the selected word line sWL.

[0196] Furthermore, when the charging voltage Vb of bit line BL is below the absolute value of the verification voltage |Vpvfy|, i.e., when the write operation of the select cell transistor sMT is not complete, the drain-side select transistor ST1 is turned on. Therefore, as Figure 14 and Figure 15 As shown, when the programming voltage Vpgm is applied to the select word line sWL, the incomplete write to the select memory cell transistor sMT is further written, thus enabling more reliable writing to the select memory cell transistor sMT.

[0197] Furthermore, in the pre-charge operation included in the second programming operation, when the threshold voltage Vth of the selected memory cell transistor sMT is "Vpvfy ≦ Vth < Vss", the charging voltage Vb of the bit line BL satisfies "Vss < Vb". When the threshold voltage Vth of the selected memory cell transistor sMT is "Vss ≦ Vth", the charging voltage Vb of the bit line BL becomes the ground voltage Vss. That is, in the pre-charge operation, the charging voltage Vb of the bit line BL is self-adjusted and set according to the difference between the threshold voltage Vth of the selected memory cell transistor sMT and the verification voltage Vpvfy. Therefore, in the pulse application operation included in the second programming operation, when the difference between the threshold voltage Vth of the selected memory cell transistor sMT and the verification voltage Vpvfy is large, the threshold voltage Vth of the selected memory cell transistor sMT changes significantly; when the difference between the threshold voltage Vth of the selected memory cell transistor sMT and the verification voltage Vpvfy is small, the threshold voltage Vth of the selected memory cell transistor sMT changes little. Therefore, the threshold voltage Vth of the memory cell transistor MT, which has been written with "0" data, can be distributed in a manner that is greater than that of the transistor MT. Figure 9 The lower limit of the Pr level shown in (B) is large and within the range of the verification voltage Vpvfy. That is, it can make the distribution of the threshold voltage Vth of the memory cell transistor MT narrower.

[0198] exist Figure 20 When the value of counter C is set to an integer greater than 2, sequencer 41 alternately executes the pre-charge action and pulse application action contained in the second programming action multiple times.

[0199] According to this configuration, when there is an incomplete write operation on the select memory cell transistor sMT, the pre-charge operation and pulse application operation are repeatedly performed until the write operation on the select memory cell transistor sMT is completed; in other words, until the threshold voltage Vth of the select memory cell transistor sMT is less than the verification voltage Vpvfy. Therefore, the write operation on the select memory cell transistor sMT can be performed more reliably.

[0200] When the sequencer 41 performs a write operation on the select memory cell transistor sMT, it maintains the voltage applied to the bit lines BL1 and BL3, which are arranged adjacent to the bit line BL2 connected to the select memory cell transistor sMT, at the internal power supply voltage Vdd. In this embodiment, bit line BL2 is equivalent to the first bit line, bit lines BL1 and BL3 are equivalent to the second bit lines, and the internal power supply voltage Vdd is equivalent to the fifth voltage.

[0201] According to this configuration, the voltage fluctuations of bit lines BL1 and BL3 can be prevented from affecting the charging voltage Vb of bit line BL2.

[0202] 2. Second Implementation Method

[0203] Next, a second embodiment of the semiconductor memory device 2 will be described. Hereinafter, the description will focus on the differences between the semiconductor memory device 2 and the first embodiment.

[0204] 2.1 Sequencer Operation

[0205] Figure 22 This is a flowchart illustrating the processing steps of the second programming operation performed by the sequencer 41 of this embodiment. Furthermore, the following explanation will use the case where data is held as "0" in the latch circuit SDL of the sense amplifier unit SAU corresponding to bit line BL2, and data is held as "1" in the latch circuit SDL of the sense amplifier unit SAU corresponding to bit line BL4 as an example.

[0206] After performing the pulse application action (step S111), sequencer 41 resets the voltage of the bit line BL of the selected string unit SU0 (step S112). Specifically, as Figure 23 As shown in (C), when the voltage of bit line BL2 drops to the ground voltage Vss at time t20, as Figure 24 As shown in (A) and (B), the signals BLC and BLX of the sensing amplifier 120 are set to high level. Therefore, when the latch circuit SDL of the sensing amplifier unit SAU holds data of "1", the bit line BL is supplied with the internal power supply voltage Vdd. Conversely, when the latch circuit SDL of the sensing amplifier unit SAU holds data of "0", the bit line BL is supplied with the voltage of node SRC, i.e., the ground voltage Vss. Thus, as... Figure 23 As shown in (G), at time t20, the voltage of bit line BL2 drops to ground voltage Vss and is reset. After this, the second programming action begins again at time t21.

[0207] 2.2 Functions and Effects

[0208] In the semiconductor memory device 2 of this embodiment, after the pulse application action for the second programming action and before the pre-charge action for the next second programming action, the sequencer 41 performs a reset action to reset the voltage of the bit line BL by means of the sense amplifier 120 based on the data held in the latch circuit SDL.

[0209] According to this configuration, for example, it is possible to avoid starting the next second programming operation while the bit line BL2 is still being charged with voltage |Vth|, i.e., while the bit line BL2 remains in a floating state. When the bit line BL2 is in a floating state, the voltage of the bit line BL2 is prone to instability. Therefore, by temporarily reducing the voltage of the bit line BL2 to the ground voltage Vss, the unstable state of the bit line BL2 can be eliminated, and the next second programming operation can begin. As a result, the second programming operation can be performed with higher accuracy.

[0210] 3. Third Implementation Method

[0211] Next, a third embodiment of the semiconductor memory device 2 will be described. Hereinafter, the description will focus on the differences between the semiconductor memory device 2 and the first embodiment.

[0212] 3.1 Composition of the sensing amplifier

[0213] Figure 25 An example configuration of the sensing amplifier 120 in this embodiment is shown. For example... Figure 25 As shown, a sense amplifier unit SAU and an amplifier circuit AC are connected in parallel on the bit line BL. The sense amplifier unit SAU has the same characteristics as... Figure 6 The sensor amplifier unit SAU shown has the same configuration. The amplifier circuit AC is a circuit used to amplify the charging voltage Vb of the bit line BL. In this embodiment, the amplifier circuit AC corresponds to the voltage adjustment unit.

[0214] 3.2 Sequencer Operation

[0215] Figure 26 This is a flowchart illustrating the processing steps of the second programming operation performed by the sequencer 41 of this embodiment. Furthermore, the following explanation will use the case where data is held as "0" in the latch circuit SDL of the sense amplifier unit SAU corresponding to bit line BL2, and data is held as "1" in the latch circuit SDL of the sense amplifier unit SAU corresponding to bit line BL4 as an example.

[0216] After performing the pre-charge operation (step S110), sequencer 41 performs the amplification operation of the charging voltage Vb of bit line BL (step S113). Specifically, as Figure 27 As shown in (E), after the voltages of gate lines SGS and SGSB drop from the read pass voltage Vread to the ground voltage Vss at time t16, i.e., after the source-side selection transistors ST2 and ST3 are turned off, the charging voltage Vb of bit line BL2 is... Figure 25 The amplifier circuit shown uses AC amplification. When the charging voltage Vb of bit line BL2 is greater than the absolute value of the verification voltage |Vpvfy|, the amplifier circuit AC performs as follows: Figure 27 As shown by the solid line in (E), the charging voltage Vb of bit line BL2 is raised to the internal power supply voltage Vdd. Therefore, when the write operation of the select memory cell transistor sMT is complete, the charging voltage Vb of bit line BL2 is set to the internal power supply voltage Vdd. On the other hand, when the charging voltage Vb of bit line BL2 is below the absolute value of the verification voltage |Vpvfy|, the amplifier circuit AC... Figure 27 As shown by the dashed line in (E), the charging voltage Vb of bit line BL2 is reduced to the ground voltage Vss. Therefore, when the write operation of the select memory cell transistor sMT is not complete, the charging voltage Vb of bit line BL2 is set to the ground voltage Vss.

[0217] like Figure 26 As shown, the sequencer 41 continues the processing of step S113 and executes the pulse application action (step S111). At this time, as... Figure 27 As shown in (A), when the pulse application operation begins at time t18, the gate line SGD0 of the select string cell SU0 is subjected to a voltage Vsgd. Therefore, when the write operation to the select memory cell transistor sMT is complete and the charging voltage Vb of the bit line BL4 is set to the internal power supply voltage Vdd, the drain-side select transistor ST1 becomes off. Consequently, the channel of the memory string MS11 becomes floating, and no write operation is performed to the select memory cell transistor sMT. On the other hand, when the write operation to the select memory cell transistor sMT is incomplete and the charging voltage Vb of the bit line BL4 is set to the ground voltage Vss, the drain-side select transistor ST1 becomes on. Therefore, the channel of the memory string MS11 is subjected to the ground voltage Vss, and the select memory cell transistor sMT spontaneously polarizes based on the potential difference between the ground voltage Vss applied to the channel of the memory string MS11 and the programming voltage Vpgm applied to the select word line sWL. Therefore, the write operation to the select memory cell transistor sMT is performed.

[0218] 3.3 Functions and Effects

[0219] The semiconductor memory device 2 also includes an amplifier circuit AC, which adjusts the voltage at which the bit line BL is charged by the pre-charge operation of the second programming operation.

[0220] According to this configuration, in the pulse application operation of the second programming operation, the voltage Vsgd used in the first programming operation can be directly used as the voltage applied to the gate line SGD0 of the select string unit SU0.

[0221] 4 Other Implementation Methods

[0222] This disclosure is not limited to the specific examples mentioned above.

[0223] For example, the magnitudes of various voltages, such as the programming voltage Vpgm and the internal power supply voltage Vdd, can be arbitrarily changed. Furthermore, during the pulse application operation of the second programming action, the voltage applied to the gate line SGD0 of the drain-side selection transistor ST1 can also be changed.

[0224] In the semiconductor memory device 2 of the third embodiment, the function of the built-in amplifier circuit AC can also be implemented in the sensing amplifier unit SAU.

[0225] While several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention equivalent to that described in the claims.

[0226] Explanation of reference numerals in the attached figures

[0227] AC: Amplifier circuit (voltage adjustment section), BL: Bit line, BL1, BL3: Second bit line, BL2: First bit line, MS: Memory string, MT: Memory cell transistor, SA: Sensing amplifier section, SAU: Sensing amplifier unit, SDL: Latch circuit, SL: Source line, ST1: Drain-side selection transistor (first selection transistor), ST2, ST3: Source-side selection transistor (second selection transistor), sWL: Select word line (first word line), WL: Word line, 2: Semiconductor memory device, 41: Sequencer (control circuit).

Claims

1. A semiconductor memory device comprising: A memory string having a first selection transistor connected to a bit line, a second selection transistor connected to a source line, and a plurality of memory cell transistors connected in series between the first selection transistor and the second selection transistor; Multiple word lines, each connected to the gate of one of the memory cell transistors; A sensing amplifier unit connected to the bit line; as well as A control circuit that controls the voltages of the multiple word lines, bit lines, and source lines. The sensing amplifier unit has: A latching circuit that holds data written to the memory cell transistor; and The sensing amplifier section is capable of applying a voltage to the bit line based on the data held in the latch circuit. When the control circuit performs a write operation on the first memory cell transistor, which is one of the memory cell transistors, A first pulse application action is performed. In this first pulse application action, while the first selection transistor is turned on and the second selection transistor is turned off, a first voltage is applied to the first word line corresponding to the first memory cell transistor among the plurality of word lines, and a second voltage lower than the first voltage is applied to the bit line, thereby reducing the threshold voltage of the first memory cell transistor. A pre-charge operation is performed. In this pre-charge operation, after the first pulse application operation is performed and the first selection transistor and the second selection transistor are turned on, the bit line is charged by applying a third voltage lower than the first voltage to the first word line and a fourth voltage higher than the third voltage to the source line. The second pulse application action is performed. In this second pulse application action, after the pre-charge action is performed, the first voltage is applied to the first word line while the bit line is made to float by the sensing amplifier section, the first selection transistor is turned on and the second selection transistor is turned off.

2. The semiconductor memory device according to claim 1, wherein, The third voltage is the same as the second voltage.

3. The semiconductor memory device according to claim 2, wherein, The second voltage and the third voltage are ground voltages.

4. The semiconductor memory device according to claim 3, wherein, During the pre-charge operation, the control circuit charges the bit line with a voltage corresponding to the threshold voltage of the first memory cell transistor.

5. The semiconductor memory device according to claim 4, wherein, The control circuit determines that the writing of the first memory cell transistor is complete based on the fact that the threshold voltage of the first memory cell transistor is less than the write determination voltage that is set to be negative. During the second pulse application operation, the control circuit applies a voltage to the gate line of the first selection transistor that enables the first selection transistor to turn on when the charging voltage of the bit line is below the absolute value of the write determination voltage, and to turn off when the charging voltage of the bit line is above the absolute value of the write determination voltage.

6. The semiconductor memory device according to claim 1, wherein, The control circuit alternately performs the pre-charging action and the second pulse application action multiple times.

7. The semiconductor memory device according to claim 6, wherein, After applying the second pulse and before performing the pre-charging operation, the control circuit performs a reset operation to reset the voltage of the bit line through the sensing amplifier section.

8. The semiconductor memory device according to claim 1, wherein, It also includes a voltage adjustment unit, which adjusts the voltage for charging the bit line through the pre-charging operation.

9. The semiconductor memory device according to claim 1, wherein, When the bit line connected to the first memory cell transistor is set as the first bit line. The semiconductor memory device further includes a second bit line, which is configured adjacent to the first bit line. When the control circuit performs a write operation on the first memory cell transistor, it maintains the voltage applied to the second bit line at the fifth voltage.

10. The semiconductor memory device according to claim 1, wherein, The memory cell transistor is a ferroelectric transistor.

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