System and method for sleep clock edge-based global counter synchronization in chiplet systems

Abstract

Various embodiments include methods and systems for providing global counter synchronization based on a sleep clock edge in a multi-chiplet system. A system on a chip (SoC) may include a first chiplet, the first chiplet including a first chiplet global counter subsystem; and a second chiplet, the second chiplet including a second chiplet global counter subsystem. The SoC may also include an interface bus that communicatively couples the first chiplet and the second chiplet, and a power management integrated circuit (PMIC) configured to provide a sleep clock to the first chiplet and the second chiplet. The first chiplet may be configured to transmit a global counter synchronization pulse trigger to the second chiplet across the interface bus. The second chiplet may be configured to load a global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. non-provisional patent application No. 17 / 402,884, filed on August 16, 2021; the entire contents of which are incorporated herein by reference. Background Art

[0003] To accommodate the increasing complexity and capabilities of integrated circuits used in various computing and communication devices, computing chips are increasingly implemented in a segmented manner. For example, processing devices and large-scale integrated circuits may include multiple "chiplets" that can be used together to perform joint tasks and processes. As processing speeds increase, synchronization of these processes becomes increasingly difficult. As processing speeds increase, the opportunity for errors to occur and create vulnerabilities for malicious attacks may also increase. Therefore, there is an increasing need to synchronize chiplets within a multi-chiplet system to better isolate and identify any such errors that may occur on one or all of the chiplets in the multi-chiplet system. Summary of the invention

[0004] Various aspects include methods and apparatus for providing global counter synchronization within a multi-chiplet system using a rising edge of a sleep clock. In various aspects, a master chiplet can be configured to transmit a global counter synchronization pulse trigger to a slave chiplet across an interface bus, and in response, the chiplet can be configured to load a global counter synchronization value into the slave chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock.

[0005] Some aspects may include: a first chiplet, the first chiplet including a first chiplet global counter subsystem; a second chiplet, the second chiplet including a second chiplet global counter subsystem; an interface bus, the interface bus communicatively coupling the first chiplet and the second chiplet; and a power management integrated circuit (PMIC), the PMIC configured to provide a sleep clock to the first chiplet and the second chiplet, wherein: the first chiplet is configured to transmit a global counter synchronization pulse trigger to the second chiplet across the interface bus; and the second chiplet is configured to load a global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.

[0006] In some aspects, the first chiplet may be further configured to: read the first chiplet global counter value from the first chiplet global counter subsystem; generate a global counter synchronization value based on the first chiplet global counter value; and transmit the global counter synchronization value to the second chiplet across an interface bus; and the second chiplet may be further configured to store the global counter synchronization value in a preload register, wherein the global counter synchronization value is loaded from the preload register into the second chiplet global counter subsystem.

[0007] In some aspects, the first chiplet global counter value may be read from the first chiplet global counter subsystem at a rising edge of the sleep clock. In some aspects, the first chiplet may be further configured to determine a sleep clock synchronization edge of the sleep clock, wherein the sleep clock synchronization edge is a rising edge of the sleep clock. In some aspects, the first chiplet may be further configured to transmit a global counter synchronization pulse trigger to the second chiplet one sleep clock cycle before the sleep clock synchronization edge of the sleep clock. In some aspects, the first chiplet may be further configured to transmit a global counter synchronization pulse trigger to the second chiplet at a delay time between the sleep clock synchronization edge and one sleep clock cycle before the sleep clock synchronization edge.

[0008] In some aspects, the first chiplet may be further configured to transmit a reset assertion to the second chiplet; and the second chiplet may be further configured to transmit a global counter synchronization request to the first chiplet across an interface bus in response to the reset assertion, wherein the first chiplet is configured to transmit a global counter synchronization pulse trigger to the second chiplet across the interface bus in response to the first chiplet receiving the global counter synchronization request from the second chiplet.

[0009] In some aspects, the second chiplet may be further configured to: disable a global counter pause within the second chiplet global counter subsystem, wherein disabling the global counter pause re-initiates counting of the second chiplet global counter within the second chiplet global counter subsystem; and enable a global counter synchronization path within the second chiplet global counter subsystem, wherein enabling the global counter synchronization path allows the first chiplet global counter subsystem to communicate with the second chiplet global counter subsystem.

[0010] In some aspects, the first chiplet may be further configured to disable global counter pauses within the first chiplet global counter subsystem and the second chiplet global counter subsystem, wherein disabling the global counter pause re-initiates counting of the first chiplet global counter within the first chiplet global counter subsystem, and re-initiates counting of the second chiplet global counter within the second chiplet global counter subsystem; and the second chiplet may be further configured to enable a global counter synchronization path within the second chiplet global counter subsystem, wherein enabling the global counter synchronization path allows the first chiplet global counter subsystem to communicate with the second chiplet global counter subsystem.

[0011] In some aspects, a sleep clock skew between the first chiplet and the second chiplet can be equal to or less than two crystal oscillator clock periods, wherein the sleep clock can be distributed to the first chiplet and the second chiplet in a star configuration. In some aspects, the interface bus can be a system power management interface (SPMI) bus.

[0012] Some aspects may also include a third chiplet, which includes a third chiplet global counter subsystem, wherein an interface bus communicatively couples the first chiplet and the third chiplet; and wherein: the first chiplet can be further configured to transmit a global counter synchronization pulse trigger to the third chiplet across the interface bus; and the third chiplet can be configured to load the global counter synchronization value into the third chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.

[0013] Additional aspects may also include a method for global counter synchronization within a multi-chiplet system. Such aspects may include: providing a sleep clock to a first chiplet and a second chiplet via a PMIC; transmitting a global counter synchronization pulse trigger from the first chiplet to the second chiplet; and loading a global counter synchronization value into a second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to the second chiplet receiving the global counter synchronization pulse trigger.

[0014] Some aspects may also include reading, by the first chiplet, a first chiplet global counter value from a first chiplet global counter subsystem; generating, by the first chiplet, a global counter synchronization value based on the first chiplet global counter value; transmitting the global counter synchronization value from the first chiplet to a second chiplet; and storing the global counter synchronization value in a preload register of the second chiplet, wherein the global counter synchronization value is loaded from the preload register into the second chiplet global counter subsystem. In some aspects, the first chiplet global counter value may be read from the first chiplet global counter subsystem at a rising edge of a sleep clock.

[0015] Some aspects may also include determining, by the first chiplet, a sleep clock synchronization edge of the sleep clock, wherein the sleep clock synchronization edge is a rising edge of the sleep clock. Some aspects may also include transmitting a global counter synchronization pulse trigger from the first chiplet to the second chiplet one sleep clock cycle before the sleep clock synchronization edge of the sleep clock. Some aspects may also include transmitting a global counter synchronization pulse trigger from the first chiplet to the second chiplet at a delay time between the sleep clock synchronization edge and one sleep clock cycle before the sleep clock synchronization edge.

[0016] Some aspects may also include transmitting a reset assertion from a first chiplet to a second chiplet; and transmitting a global counter synchronization request from the second chiplet to the first chiplet in response to the reset assertion, wherein transmitting the global counter synchronization pulse trigger from the first chiplet to the second chiplet is performed in response to the first chiplet receiving the global counter synchronization request from the second chiplet.

[0017] Some aspects may also include disabling a global counter pause within a second chiplet global counter subsystem by the second chiplet, wherein disabling the global counter pause re-initiates counting of the second chiplet global counter within the second chiplet global counter subsystem; and enabling a global counter synchronization path within the second chiplet global counter subsystem by the second chiplet, wherein enabling the global counter synchronization path allows the first chiplet global counter subsystem to communicate with the second chiplet global counter subsystem.

[0018] Some aspects may also include disabling, by the first chiplet, a global counter pause within a first chiplet global counter subsystem and a second chiplet global counter subsystem, wherein disabling the global counter pause re-initiates counting of the first chiplet global counter within the first chiplet global counter subsystem and re-initiates counting of the second chiplet global counter within the second chiplet global counter subsystem; and enabling, by the second chiplet, a global counter synchronization path within the second chiplet global counter subsystem, wherein enabling the global counter synchronization path allows the first chiplet global counter subsystem to communicate with the second chiplet global counter subsystem.

[0019] Additional aspects may include an SoC comprising: a first chiplet, the first chiplet comprising a first chiplet global counter subsystem; a second chiplet, the second chiplet comprising a second chiplet global counter subsystem; a component for providing a sleep clock to the first chiplet and the second chiplet; a component for transmitting a global counter synchronization pulse trigger from the first chiplet to the second chiplet; and a component for loading a global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to the second chiplet receiving a global counter synchronization pulse trigger.

[0020] Some aspects may also include a component for reading a first chiplet global counter value from a first chiplet global counter subsystem; a component for generating a global counter synchronization value based on the first chiplet global counter value; a component for transmitting the global counter synchronization value from the first chiplet to the second chiplet; and a component for storing the global counter synchronization value in a preload register of the second chiplet, wherein the global counter synchronization value is loaded from the preload register into the second chiplet global counter subsystem.

[0021] In some aspects, a first chiplet global counter value is read from a first chiplet global counter subsystem at a rising edge of a sleep clock. Some aspects may also include means for determining a sleep clock synchronization edge of the sleep clock, wherein the sleep clock synchronization edge is a rising edge of the sleep clock. Some aspects may also include means for transmitting a global counter synchronization pulse trigger from the first chiplet to the second chiplet one sleep clock cycle before the sleep clock synchronization edge of the sleep clock. Some aspects may also include means for transmitting a global counter synchronization pulse trigger from the first chiplet to the second chiplet at a delay time between the sleep clock synchronization edge and one sleep clock cycle before the sleep clock synchronization edge.

[0022] Some aspects may also include means for transmitting a reset assertion from the first chiplet to the second chiplet; and means for transmitting a global counter synchronization request from the second chiplet to the first chiplet in response to the reset assertion, wherein the means for transmitting the global counter synchronization pulse trigger from the first chiplet to the second chiplet is in response to the first chiplet receiving the global counter synchronization request from the second chiplet. Some aspects may also include means for disabling a global counter pause within a global counter subsystem of the second chiplet, wherein disabling the global counter pause re-initiates counting of a second chiplet global counter within the global counter subsystem of the second chiplet; and means for enabling a global counter synchronization path within the global counter subsystem of the second chiplet, wherein enabling the global counter synchronization path allows the first chiplet global counter subsystem to communicate with the second chiplet global counter subsystem.

[0023] Some aspects may also include components for disabling global counter pauses within a first chiplet global counter subsystem and a second chiplet global counter subsystem, wherein disabling the global counter pause re-initiates counting of the first chiplet global counter within the first chiplet global counter subsystem and re-initiates counting of the second chiplet global counter within the second chiplet global counter subsystem; and components for enabling a global counter synchronization path within the second chiplet global counter subsystem, wherein enabling the global counter synchronization path allows the first chiplet global counter subsystem to communicate with the second chiplet global counter subsystem.

[0024] Additional aspects include a method for global counter synchronization implemented by a first chiplet within a multi-chiplet system, comprising: receiving a sleep clock from a PMIC; and transmitting a global counter synchronization pulse trigger to a second chiplet; wherein the global counter synchronization pulse trigger is configured to cause the second chiplet to load a global counter synchronization value into a second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock. Some aspects may also include reading a first chiplet global counter value from a first chiplet global counter subsystem; generating a global counter synchronization value based on the first chiplet global counter value; and transmitting the global counter synchronization value to the second chiplet.

[0025] Additional aspects include a SOC comprising: a first chiplet, the first chiplet comprising a first chiplet global counter subsystem; a second chiplet, the second chiplet comprising a second chiplet global counter subsystem; an interface bus, the interface bus communicatively coupling the first chiplet and the second chiplet; and a PMIC, the PMIC configured to provide a sleep clock to the first chiplet and the second chiplet, wherein the first chiplet is configured to receive the sleep clock from the PMIC and transmit a global counter sync pulse trigger to the second chiplet, wherein the global counter sync pulse trigger is configured to cause the second chiplet to load a global counter sync value into the second chiplet global counter subsystem at a sleep clock sync edge of the sleep clock. In some aspects, the first chiplet may be further configured to: read the first chiplet global counter value from the first chiplet global counter subsystem; generate a global counter sync value based on the first chiplet global counter value; and transmit the global counter sync value to the second chiplet. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are incorporated herein and constitute a part of this specification, illustrate example embodiments, and together with the general description given above and the detailed description given below, serve to explain features of the various embodiments.

[0027] Figure 1 is a component block diagram illustrating an example of a multi-chiplet system circuit suitable for implementing various embodiments.

[0028] Figure 2 is a message flow diagram illustrating operations and chiplet-to-chiplet communication in a multi-chiplet system for sleep clock edge-based global counter synchronization in the multi-chiplet system during a boot sequence according to some embodiments.

[0029] Figure 3is a message flow diagram illustrating operations and chiplet-to-chiplet communications in a multi-chiplet system for sleep clock edge-based global counter synchronization in the multi-chiplet system when a chiplet global counter is paused according to some embodiments.

[0030] Figure 4 is a message flow diagram illustrating operations and chiplet-to-chiplet communications in a multi-chiplet system for sleep clock edge-based global counter synchronization in the multi-chiplet system when a master chiplet global counter is paused according to some embodiments.

[0031] Figure 5 is a timing diagram illustrating a timing flow for global counter synchronous pulse triggering in a multi-chiplet system according to some embodiments.

[0032] Figure 6 is a timing diagram illustrating a timing flow for sleep clock edge-based global counter synchronization in a multi-chiplet system according to some embodiments.

[0033] Figure 7 is a process flow diagram illustrating an embodiment method 700 for sleep clock edge-based global counter synchronization in a multi-chiplet system according to various embodiments.

[0034] Fig. 8A is a process flow diagram illustrating an embodiment method 800a for sleep clock edge-based global counter synchronization in a multi-chiplet system, which may be implemented as part of method 700 in some embodiments.

[0035] Figure 8B is a process flow diagram illustrating an embodiment method 800 b of sleep clock edge-based global counter synchronization in a multi-chiplet system, which may be implemented as part of method 700 in some embodiments.

[0036] Figure 8C is a process flow diagram illustrating an embodiment method 800c for sleep clock edge-based global counter synchronization in a multi-chiplet system, which may be implemented as part of method 700 in some embodiments.

[0037] Fig.8D is a process flow diagram illustrating an embodiment method 800d of sleep clock edge-based global counter synchronization in a multi-chiplet system, which may be implemented as part of method 700 in some embodiments.

[0038] Fig. 8Eis a process flow diagram illustrating an embodiment method 800e of sleep clock edge-based global counter synchronization in a multi-chiplet system, which may be implemented as part of method 700 in some embodiments.

[0039] Fig. 9 is a component block diagram of an example wireless device in the form of a smart phone 1100 suitable for implementing the various embodiments.

[0040] Fig.10 is a component block diagram illustrating an example computing device suitable for use with various embodiments.

[0041] Fig.11 is a component block diagram illustrating an example server suitable for use with the various embodiments. DETAILED DESCRIPTION

[0042] Various embodiments will be described in detail with reference to the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. References to specific examples and specific implementations are for illustrative purposes and are not intended to limit the scope of the claims.

[0043] Various embodiments provide a hardware-based global counter synchronization solution within a multi-chiplet system utilizing a sleep clock edge-based global counter synchronization method. Various embodiments may be implemented in a system-on-chip (SoC) or similar system including a plurality of chiplets, each chiplet including a chiplet global counter subsystem coupled to an interface bus and a power management integrated circuit (PMIC) configured to provide a sleep clock to a first chiplet and a second chiplet. The first chiplet may transmit a global counter synchronization pulse trigger to a second chiplet across the interface bus, and in response, the second chiplet may load a global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock.

[0044] The terms "system on chip" and SoC are used herein to refer to a single integrated circuit (IC) chip that contains multiple resources or processors integrated on a single substrate. A single SoC may contain circuits for digital, analog, mixed signal, and radio frequency functions. A single SoC may also include any number of general or special purpose processors (digital signal processors, modem processors, video processors, etc.), memory blocks (such as ROM, RAM, flash memory, etc.), and resources (such as timers, voltage regulators, oscillators, etc.). The SoC may also include software for controlling the integrated resources and processors, and for controlling peripheral devices.

[0045] The term "system-in-package" (SIP) is used herein to refer to a single module or package that contains multiple resources, computing units, cores, or processors on two or more IC chips, substrates, or SoCs. For example, a SIP may include a single substrate on which multiple IC chips or semiconductor dies are stacked in a vertical configuration. Similarly, a SIP may include one or more multi-chip modules (MCMs) on which multiple ICs or semiconductor dies are packaged into a unified substrate. A SIP may also include multiple independent SoCs that are coupled together via high-speed communication circuitry and packaged together in close proximity (such as on a single motherboard or in a single wireless device). The proximity of the SoCs facilitates high-speed communication and sharing of memory and resources.

[0046] The term "functional block" is used herein to refer to a grouping of one or more electronic circuit components that can be used to perform various functions. In various embodiments, a functional block may include components that can be used to perform functions related to the synchronization of a safety timer between the functional block and one or more external components. The functional block may include various hardware, software, and / or firmware to implement various embodiments. For example, a functional block may be or include a SoC, a SIP, a NOC, and various subsystems. The functional block may include various clock components, memory registers, logic gated bus interfaces, multiplexers, and other electronic components to implement various embodiments for synchronization of a safety timer.

[0047] As used herein, the term "chiplet" is used to refer to a sub-processing unit or sub-processing device within a processing system (such as an SoC). A chiplet can be an integrated circuit block designed to work with other similar chiplets within a processing system to perform various processes. A chiplet can be a separate die that operates independently of other die within a larger processing system (such as an SoC), or can be a separate die that operates in conjunction with other die within a larger processing system. A chiplet may include one or more processing cores to perform system processes in conjunction with other cores of an associated chiplet within the system. A chiplet may include input / output (IO) functionality to transmit system data to other chiplets and / or other system devices (such as memory, power controllers, IO controllers and / or interfaces, etc.). A chiplet can be used as and can be referred to as a functional block that performs processing operations within a system (such as an SoC).

[0048] Computing devices and systems are increasingly implemented in a segmented manner. As technology advances and processing speeds become faster, multi-chiplet systems continue to require improved yield and scalability. As processing speeds increase, synchronization of these processes becomes increasingly difficult. As processing speeds increase, the chances of errors occurring and creating vulnerabilities for malicious attacks may also increase. Therefore, there is an increasing need to synchronize chiplets. Reducing wait times during the synchronization process and when performing debug processes based on timestamps derived from the synchronization process within a multi-chiplet system can better isolate and identify any such errors that may occur on one or more chiplets working together within a multi-chiplet system.

[0049] In a multi-chiplet system, a master die or chiplet may be used to control, regulate, or otherwise instruct any number of associated slave die or chiplets in electrical communication with the master chiplet. The master chiplet may share at least one clock signal with the slave chiplets such that the shared clock signal may be derived from the same source (e.g., a PMIC crystal oscillator). For debugging purposes, it is helpful to correctly timestamp any errors that occur within any of the chiplets in a multi-chiplet system so that there is a minimal amount of deviation between timestamped events in one chiplet that can be associated with other timestamped events in another chiplet. If the clock synchronization between the chiplets is too skewed or out of sync, the timestamps used for any timestamped events (including recorded hardware and / or software errors) may not be able to be correctly associated with corresponding timestamped events recorded between other chiplets, and therefore may be useless in accurately identifying errors, malicious attacks, or for the purpose of initiating a correction process. Therefore, clock synchronization between chiplets within a multi-chiplet system is important for basic system operation.

[0050] Clock misalignment or desynchronization may be caused by a variety of reasons within a multi-chiplet system. At system startup, the master chiplet may be out of sync with any slave chiplet and may require clock or global counter synchronization. Specifically, the master chiplet may reset the slave chiplets in a staggered manner at system startup such that each chiplet clock and / or global counter is not aligned with each additional chiplet clock.

[0051] As another example, each chiplet uses its local global counter time base for functional and debug tracing. Whenever a chiplet is reset, the global counter of the master chiplet or the slave chiplet is reset. Therefore, the master chiplet may crash, and the PMIC may provide a reset signal, message, or assertion to the master chiplet. The master chiplet global counter that has been reset may therefore be out of sync with the slave chiplet global counter.

[0052] Similarly, a chiplet may crash and the master chiplet may provide a reset assertion to the chiplet. The chiplet global counter that has been reset may therefore be out of sync with the master chiplet global counter and other chiplet global counters.

[0053] As another example of when global counter desynchronization occurs, during cross trigger interface (CTI) operation and communication, the global counters of the master chiplet and any chiplets may be paused. A CTI trigger may pause the global counters from the chiplets, causing the chiplet global counters to freeze and be misaligned with the global counters still running in other chiplets. In the case where a CTI trigger pauses the master chiplet global counter, the same CTI pause trigger also stops the global counters in all chiplets. Therefore, all chiplets will need to be resynchronized again.

[0054] The lack of low latency global counter synchronization can lead to various system performance issues, such as during the debugging process. Multi-chiplet systems, such as those implementing CoreSight CTI, require a common time base to track timestamps collected and aggregated from all associated system chiplets. Global counter synchronization is also critical for the normal operation of multi-chiplet systems, such as chip-to-chip or device-to-device operations, and for communications that require accurate timestamped message transmission. Software-based synchronization solutions may also affect synchronization accuracy. Global counter synchronization faster than the microsecond (μs) scale may be desired in multi-chiplet systems to achieve accurate timelines across all associated chiplets, because microseconds are important periods when chiplet processors operate at GHz rates. Due to chip-to-chip latency and interrupt latency, software-based global counter synchronization is on the order of μs scale. Therefore, a hardware-based global counter synchronization solution can be used to improve global counter synchronization latency.

[0055] Various embodiments provide a hardware-based global counter synchronization solution within a multi-chiplet system. The multi-chiplet system may include a master chiplet and one or more slave chips. A sleep clock (e.g., 32kHz) derived from an active clock (e.g., 19.2MHz) may be assigned to each of the chiplets in the multi-chiplet system. The master chiplet may utilize the rising edge of the sleep clock to (i) read the master chiplet global counter, (ii) determine which future sleep clock rising edge should be utilized to synchronize with any slave chiplets, (iii) determine a global counter synchronization value based on the read master chiplet global counter value, (iv) transmit the global counter synchronization value to one or more slave chips, and (v) broadcast a global counter synchronization pulse trigger to cause any unsynchronized slave chips to latch the global counter synchronization value into each locally stored global counter subsystem within the chiplet.

[0056] In some embodiments, the master chiplet and the slave chiplets may be instantiated using a system power management interface (SPMI) slave interface or functional block to support chiplet to chiplet communication. The master chiplet may be configured with an SPMI slave interface or a CTI interface for transmitting a global counter synchronization pulse trigger to any unsynchronized chiplets. The slave chiplet global counter synchronization request and the master chiplet synchronization response may be transmitted via SPMI or any other physical interface.

[0057] In some embodiments, multi-chiplet global counter synchronization can be performed during the startup sequence using global counter synchronization based on the edge of the sleep clock. For example, at startup, the master chiplet can reset any connected chiplets to prepare the chiplets for synchronization, so that each chiplet in the chiplet is not synchronized at system startup. In some embodiments, when the chiplet global counter is paused, multi-chiplet global counter synchronization can be performed using global counter synchronization based on the edge of the sleep clock. For example, a chiplet alone can be paused and therefore not synchronized with the master chiplet, while other chiplets can still be synchronized with the master chiplet. The unsynchronized chiplets can disable the pause trigger and request global counter synchronization with the master chiplet, while other chiplets remain unaffected. In some embodiments, when the master chiplet global counter is paused, multi-chiplet global counter synchronization can be performed using global counter synchronization based on the edge of the sleep clock.

[0058] Figure 1 1 is a component block diagram illustrating an example multi-chiplet system circuit 100 suitable for implementing any of the various embodiments. The various embodiments may be implemented using any number of chiplets greater than or equal to two chiplets. The illustrated example multi-chiplet system 100 includes four chiplets 110a, 110b, 110c, and 110d within a single system package or system-in-package (SIP) 104, and a PMIC controller 102. The multi-chiplet system 100 may also include an interface bus 106 (e.g., SPMI, Inter-Integrated Circuit (IIC) bus). 2 C) bus). As another example, six chiplets may be implemented within the SIP 104, with one chiplet operating as a first (i.e., primary / master) chiplet and the remaining five chiplets operating as second (i.e., auxiliary / slave) chiplets. In some embodiments, the PMIC controller 102 may be located within the SIP 104.

[0059] In various embodiments, one of the chiplets 110a, 110b, 110c, and 110d may be configured as a master chiplet, and the remaining chiplets may be configured as slave chips. For example, chiplet 110a may be configured as a master chiplet, and chiplets 110b, 110c, and 110d may be configured as slave chips. Unless otherwise stated, the following examples and embodiments are described using the non-limiting examples of chiplet 110a configured as a master chiplet and chiplets 110b, 110c, 110d configured as slave chips. The master chiplet 110a is illustrated as having additional components (e.g., SPMI master interface 112, master timer 114, multiplexers 131, 133) compared to slave chips 110b, 110c, 110d. However, since each of the chiplets 110a, 110b, 110c, 110d can be configured as a master chiplet, each of the chiplets 110b, 110c, 110d can also include components instantiated within the master chiplet 110a.

[0060] For ease of description, the operation of various embodiments may be described herein using a non-limiting example of a dual chiplet system including a first chiplet (e.g., 110a) configured or used as a primary / master chiplet and a second chiplet (e.g., 110b) configured or used as an auxiliary / slave / slave chiplet. However, the description involving the first chiplet and the second chiplet without reference to another chiplet is not intended to be limiting, as the operation between the two chiplets represents the operation between any number of chiplets.

[0061] In some embodiments, one or more of the chiplets 110a, 110b, 110c, and 110d may collectively operate as a central processing unit (CPU) of the multi-chiplet system 100, which executes instructions of a software application by performing arithmetic, logic, control, and input / output (I / O) operations specified by the instructions. In some embodiments, one or more of the chiplets 110a, 110b, 110c, and 110d may operate as a dedicated processing unit. Each chiplet 110a, 110b, 110c, and 110d may include one or more cores, and each core may perform operations independently of other cores in the same chiplet and cores in other chiplets. In addition, any or all of the chiplets 110a, 110b, 110c, and 110d may be included as part of a processor cluster architecture (such as a synchronous processor cluster architecture, an asynchronous or heterogeneous processor cluster architecture, etc.).

[0062] The chiplets 110a, 110b, 110c, and 110d may include various additional system components, resources, and custom circuits for managing sensor data, analog-to-digital conversion, wireless data transmission, and for performing other specialized operations, such as decoding data packets and processing encoded audio and video signals for rendering in a web browser. For example, the system components and resources of the chiplets 110a, 110b, 110c, and 110d may include power amplifiers, voltage regulators, oscillators, phase-locked loops, peripheral bridges, data controllers, memory controllers, system controllers, access ports, timers, and other similar components for supporting processors and software clients that operate within the SIP 104 and that operate externally but in electrical communication with a SIP (e.g., PMIC controller 102) within the multi-chiplet system 100. The system components and resources and / or custom circuits may also include circuits for interfacing with peripheral devices (such as cameras, electronic displays, wireless communication devices, external memory chips, etc.). The chiplets 110a, 110b, 110c, and 110d may also each include an input / output module for communicating with resources external to the SIP, such as a clock source or the PMIC controller 102. Resources external to the SIP may be shared by two or more of the chiplets 110a, 110b, 110c, and 110d.

[0063] The chiplets 110a, 110b, 110c, and 110d may include memory devices 122a, 122b, 122c, and 122d (labeled "Memory"), which may be volatile or non-volatile memory configured to store data and processor executable code for access by one or more processing cores 120a, 120b, 120c, and 120d (labeled "Proc") of each respective chiplet 110a, 110b, 110c, and 110d. In addition to the memory devices 122a, 122b, 122c, and 122d, the multi-chiplet system 100 may also include one or more additional memory devices (not shown) located internally or externally to the SIP 104 that may be configured for various purposes. The one or more memory devices including the memory devices 122a, 122b, 122c, and 122d may include volatile memory, such as random access memory (RAM) or main memory, or cache memory. These memory devices may be configured to temporarily hold limited amounts of data received from data sensors or subsystems, data and / or processor executable code instructions requested from non-volatile memory, loaded into the memory devices from non-volatile memory in anticipation of future access based on various factors, and / or intermediate processed data and / or processor executable code instructions generated by chiplets 110a, 110b, 110c, and 110d and temporarily stored for future quick access without being stored in non-volatile memory. The memory devices 122a, 122b, 122c, and 122d of the multi-chiplet system 100 may be configured to at least temporarily store data and processor executable code that are loaded into the memory devices 122a, 122b, 122c, and 122d in each chiplet 110a, 110b, 110c, and 110d for access by one or more of the processing cores 120a, 120b, 120c, and 120d of the chiplets 110a, 110b, 110c, and 110d. The data or processor executable code loaded into the memory devices 122a, 122b, 122c, and 122d in each chiplet 110a, 110b, 110c, and 110d may be loaded in response to the processing cores 120a, 120b, 120c, and 120d performing a function.

[0064] In some embodiments, the processing cores 120a, 120b, 120c, and 120d may perform operations associated with various subsystems and / or functional blocks created as a virtual space within the chiplets 110a, 110b, 110c, 110d. For example, the processing cores 120a, 120b, 120c, and 120d may perform operations associated with the timer subsystems 124a, 124b, 124c, 124d, the global counter subsystems 126a, 126b, 126c, 126d, and the SPMI slave functional blocks 130a, 130b, 130c, 130d.

[0065] The chiplets 110a, 110b, 110c, 110d may include a timer subsystem 124a, 124b, 124c, 124d (labeled as timer SS), respectively. The timer subsystem 124a, 124b, 124c, 124d may be used to regulate, control, and maintain a local global counter for clock synchronization between the chiplets 110a, 110b, 110c, 110d. In some embodiments, the global counter may be a 56-bit global counter value. The timer subsystem 124a, 124b, 124c, 124d may include a global counter subsystem 126a, 126b, 126c, 126d (labeled as GC SS), which may be loaded with a global counter value for clock synchronization between the chiplets 110a, 110b, 110c, 110d. In some embodiments, the global counter may also be referred to as a system counter.

[0066] The PMIC controller 102 may control, distribute, or otherwise regulate clock signals used to synchronize the chiplets 110a, 110b, 110c, and 110d. The chiplets 110a, 110b, 110c, and 110d may receive various clock signals from the PMIC controller 102. For example, the PMIC controller 102 may store or otherwise receive reference clock signals for the chiplets 110a, 110b, 110c, and 110d from an external component (e.g., a crystal oscillator) for synchronization purposes. The reference clock signal may include a clock signal corresponding to an active mode, a sleep mode, or any other predefined mode with a preset frequency. For example, the PMIC controller 102 may transmit a 19.2 MHz clock corresponding to an active mode to the chiplets 110a, 110b, 110c, and 110d. Additionally, the PMIC controller 102 may transmit a 32 kHz clock or sleep clock 108 corresponding to the sleep mode / low power mode to the chiplets 110a, 110b, 110c, and 110d. Other clock frequencies may be used. The sleep clock 108 is always available to the chiplets 110a, 110b, 110b, 110d.

[0067] In various implementations, a crystal oscillator (CXO) (not shown) may generate an active clock signal (e.g., 19.2 MHz) distributed from a common clock source, the PMIC controller 102. A sleep clock 108 (e.g., 32 kHz) may be derived from the CXO active clock and may always be available to each of the chiplets 110a, 110b, 110c, 110d. For example, the sleep clock 108 may be distributed from the PMIC controller 102 to the timer subsystems 124a, 124b, 124c, 124d for synchronization purposes. A global counter of the multi-chiplet system 100 may be incremented by 1 when the CXO active clock is available and may be incremented by 586 when the clock source is switched to the sleep clock 108. The sleep clock 108 and the CXO active clock may have any integer or non-integer relationship as long as the clocks are derived from the same crystal.

[0068] In some embodiments, the sleep clock 108 deviation between the chiplets 110a, 110b, 110c, 110d can be less than one CXO clock period (e.g., 52.08ns for a 32kHz sleep clock). In some embodiments, the deviation can be less than or equal to two CXO clock periods. The sleep clock 108 can be provided to the chiplets 110a, 110b, 110c, 110d by the PMIC and can enter at a ball grid array (BGA) pin of a package (e.g., SIP 104) and then distributed to all chiplets 110a, 110b, 110c, 110d in the package (e.g., SIP 104). The sleep clock 108 routing can be connected between the chiplets 110a, 110b, 110c, 110d in a star configuration. In some embodiments, the sleep clock 108 insertion delays within each chiplet 110a, 110b, 110c, 110d may be balanced to keep process-to-process variations less than 52 nanoseconds (ns).

[0069] The interface bus 106 may be a broadcast interface, where data communication messages may be broadcast to multiple hardware components simultaneously. For example, the interface bus 106 may be an SPMI bus, which may allow the PMIC controller 102 and the chiplets 110a, 110b, 110c, 110d to communicate via a "telegraph" or broadcast messaging technique. For example, the PMIC controller 102 may broadcast a clock synchronization message across the interface bus 106 so that the chiplets 110a, 110b, 110c, 110d perform clock synchronization actions simultaneously or nearly simultaneously (i.e., subject to hardware communication path delay limitations). As another example, the master chiplet 110a may include an SPMI master interface 112 to broadcast clock synchronization messages to the PMIC controller 102 and the chiplets 110b, 110c, 110d. By implementing the interface bus 106 as an SPMI bus or other type of broadcast communication interface, the master chiplet 110a may be synchronized from the chiplets 110b, 110c, 110d simultaneously and in parallel. In some embodiments, the master chiplet 110a may synchronize individually from the chiplets 110b, 110c, 110d. In some embodiments, the master chiplet 110a may synchronize sequentially from the chiplets 110b, 110c, 110d if configured when a broadcast interface such as SPMI is implemented, or if limited by the interface bus 106 as a serial interface rather than a parallel broadcast interface. The synchronization requests from the chiplets 110b, 110c, 110d and the master chiplet 110a synchronization responses including the global counter 56-bit value may be transmitted over the interface bus 106 (e.g., SPMI) or any other physical interface.

[0070] Each of the chiplets 110a, 110b, 110c, 110d may be instantiated with a SPMI slave function block 130a, 130b, 130c, 130d, respectively. The SPMI slave function blocks 130a, 130b, 130c, 130d may support circuit-to-circuit (C2C) communications in the early stages of pre-boot loading. The master chiplet 110a software (i.e., primary boot loader (PBL) / secondary boot loader (SBL)) may configure the SPMI slave function blocks 130a, 130b, 130c, 130d for transmitting synchronization signals, pulses, or triggers. The synchronization trigger may be transmitted to each SPMI slave function block 130a, 130b, 130c, 130d within a sleep clock period (e.g., 30.5 μs (1 / 32 kHz)) to ensure that the correct synchronization clock edge is identified and used. The timer subsystem 124a of the master chiplet 110a may include a master timer 114. The master timer 114 may initiate a sync pulse trigger, which may be relayed by the SPMI slave function block 130a to the SPMI slave function blocks 130b, 130c, 130d.

[0071] One or more of the processing cores 120a, 120b, 120c, 120d may include general purpose input / output (GPIO) pins or internal hardwired communication interfaces that may be used to receive and transmit data messages from and to the PMIC controller 102 as well as to receive and transmit data messages between other chiplet communication interfaces and / or GPIO pins. For example, the CTI 130 may include one or more data paths connecting the GPIO pins of the chiplets 110a, 110b, 110c, 110d that may allow the chiplets 110a, 110b, 110c, 110d to transmit and receive data communications and / or synchronization messages between each of the chiplets 110a, 110b, 110c, 110d. The CTI 136 may be used to transmit a CTI trigger signal to the master chiplet 110a to pause the master chiplet global counter stored within the master chiplet global counter subsystem 126a. The CTI 136 may be used to transmit a CTI trigger signal to the chiplets 110b, 110c, 110d to pause the chiplet global counters stored in the global counter subsystems 126b, 126c, 126d, respectively.

[0072] The master chiplet 110a software (i.e., primary boot loader (PBL) / secondary boot loader (SBL)) can configure the CTI 136 for transmitting synchronization pulses. The synchronization pulses can be transmitted to each timer subsystem 124a, 124b, 124c, 124d within the sleep clock period (e.g., 30.5μs (1 / 32kHz)) to ensure that the correct synchronization clock edge is identified and used.

[0073] For example, the master chiplet 110a may activate a synchronization select signal (labeled "sync sel") to switch between synchronization methods. In some embodiments, the PMIC controller 102 may toggle the state of the synchronization select signal. Activating the synchronization select signal may allow the multi-chiplet system 100 to switch from an SPMI-based broadcast synchronization method implementing the interface bus 106 to a GPIO-based synchronization method implementing the CTI 136. In the SPMI-based broadcast synchronization method, various synchronization requests and responses may be communicated between the master chiplet SPMI slave functional block 130a and the slave chiplet SPMI slave functional blocks 130b, 130c, 130d across the interface bus 106. The SPMI slave function blocks 130a, 130b, 130c, 130d can relay the global counter value received from the interface bus 106 (i.e., at system startup or system resynchronization) through the corresponding multiplexers 134a, 134b, 134c, 134d to latch the global counter value into the corresponding global counter subsystems 126a, 126b, 126c, 126d. Activating the synchronization select signal can switch the data path of the illustrated multiplexers (e.g., multiplexers 131, 132a-d, 133, 134a-d). The master timer 114 can initiate a synchronization pulse trigger to the CTI 136 (i.e., through multiple GPIO pins) through multiplexers 133 and multiplexer 131 (i.e., as CTI trig out 0). The sync pulse trigger from the master timer 114 may be further propagated and latched into each global counter subsystem 126a, 126b, 126c, 126d through multiplexers 132a, 132b, 132c, 132d (i.e., as CTI trig in 0) and then through multiplexers 134a, 134b, 134c, 134d, respectively. When the global counter sync mode is not selected (i.e., the sync select signal (“sync sel”) is 0 or low), the multiplexers 134a, 134b, 134c, 134d may output CTI trig 0 for debugging purposes.

[0074] Figures 2 to 4 The message flow diagrams 200, 300, and 400 illustrate operation of sleep clock edge-based global counter synchronization and chiplet-to-chiplet and intra-chiplet communication for a multi-chiplet system according to some embodiments. The system may be implemented using at least two chiplets (e.g., chiplets 110a, 110b, 110c, 110d) and a PMIC (e.g., PMIC controller 102) communicatively connected via an interface bus (e.g., interface bus 106). Figures 2 to 4 Operation and communication for sleep clock edge-based global counter synchronization in a multi-chiplet system as illustrated in FIG. Figures 2 to 4Some operations or communications illustrated in the examples may not be performed in all embodiments, and operations and communications may be different from Figures 2 to 4 The examples shown in the example are executed in a different order.

[0075] refer to Figures 1 to 4 , a master chiplet 110a having a master chiplet processor 120a and a master chiplet global counter subsystem 126a can communicate with a chiplet 110b having a chiplet processor 120b and a chiplet global counter subsystem 126b. The master chiplet processor 120a can communicate locally with the master chiplet global counter subsystem 126a within the master chiplet 110a. The chiplet processor 120b can communicate locally with the chiplet global counter subsystem 126b within the chiplet 110b. The master chiplet processor 120a and the master chiplet global counter subsystem 126a can communicate with the chiplet processor 120b and the chiplet global counter subsystem 126b via an interface bus 106, which can be an SPMI bus. The interface bus 106 may be used to transmit and receive various global counter synchronization messages between the master chiplet processor 120 a , the master chiplet global counter subsystem 126 a , the slave chiplet processor 120 b and the slave chiplet global counter subsystem 126 b for synchronizing global counters based on the edges of the sleep clock 108 .

[0076] Figures 2 to 4 Various scenarios for resynchronization of global counters within any of the chiplets 110a, 110b, 110c, 110d are illustrated. For ease of illustration, the operation of two chiplets (e.g., chiplets 110a, 110b) and the communication therebetween are shown. However, the same operations performed by or in conjunction with chiplet 110b may be performed simultaneously by or in conjunction with additional chiplets (e.g., 110c, 110d) in electrical communication with the master chiplet 110a. For example, communications 214 may be transmitted simultaneously from the master chiplet global counter subsystem 126a to the slave chiplet global counter subsystems 126b, 126c, 126d. As another example, communications 220 may be transmitted simultaneously from the master chiplet processor 120a to the slave chiplet global counter subsystems 126b, 126c, 126d.

[0077] Figure 2 is a message flow diagram illustrating operation of sleep clock edge-based global counter synchronization in a multi-chiplet system during a boot sequence, as well as chiplet-to-chiplet and intra-chiplet communication, according to some embodiments.

[0078] During a cold start (i.e., system power-up) or warm start (i.e., system reset by software), the master chiplet 110a may not be synchronized with the chiplet 110b. For example, the master chiplet 110a may be reset before the chiplet 110b, and instructions may then be provided to the chiplet 110b to bring the chiplet 110b out of reset. The global counters maintained by the master chiplet global counter subsystem 126a may be out of synchronization with the global counters of the chiplet global counter subsystem 126b because the global counter values ​​of the master chiplet 110a and the chiplet 110b are independently enabled. The following flow provides for resynchronization of the global counters of the master chiplet 110a and the chiplet 110b.

[0079] At a cold start or warm start, the master chiplet 110 a comes out of reset and the master chiplet global counter subsystem 126 a begins incrementing based on a clock provided by the PMIC controller 102 (eg, a 19.2 MHz active clock).

[0080] In communication 202, the master chiplet processor 120a may generate a reset assertion and transmit the reset assertion to the chiplet processor 120b. The reset assertion may be transmitted by the master chiplet processor 120a to the chiplet processor 120b across a dedicated channel (such as a set of dedicated GPIO pins). The reset assertion may indicate that the chiplet 110b is out of reset (i.e., entering the PBL phase). The master chiplet processor 120a may transmit the reset assertion to the chiplet processor 120b after the master chiplet processor has entered the SBL phase. The SBL phase is an operating phase in which a process performed by a chiplet processor (e.g., the master chiplet processor 120a, the chiplet processor 120b) is executed using a dynamic random access memory (DRAM) that is physically separate from a chip or package including the chiplet processor (e.g., a DRAM located outside the SoC including the master chiplet processor 120a and the chiplet processor 120b). In some embodiments, the master chiplet processor 120a may transmit a reset assertion to the chiplet processor 120b while the master chiplet processor 120a is in the PBL phase and before entering the SBL phase. The PBL phase is an operational phase in which a process performed by a chiplet processor (e.g., the master chiplet processor 120a, the chiplet processor 120b) is executed using a read-only memory (ROM) that may be physically located in a chip or package including the chiplet processor (e.g., a ROM located inside a SoC including the master chiplet processor 120a and the chiplet processor 120b). The chiplet processor 120b may receive a reset assertion from the master chiplet processor 120a after the master chiplet processor 120a has entered the PBL phase. The reset assertion received from the master chiplet processor 120a by the chiplet processor 120b may trigger the chiplet processor 120b to enter the PBL phase. At this point, the global counter within the chiplet global counter subsystem 126b is not synchronized with the global counter within the master chiplet global counter subsystem 126a.

[0081] In communication 204, a global counter synchronization request may be generated from the chiplet processor 120b and transmitted to the master chiplet processor 120a. After entering the PBL phase, the chiplet processor 120b may transmit the global counter synchronization request to the master chiplet processor 120a. In some embodiments, the global counter synchronization request may be transmitted as an SPMI telegram or broadcast across the interface bus 106.

[0082] In some embodiments, the master chiplet processor 120a may continuously poll the interface bus 106 for any SPMI telegrams or broadcasts transmitted by the chiplet processor 120b. In some embodiments, communications 206 and / or 208 may be performed in response to the master chiplet processor 120a detecting an SPMI telegram or broadcast from the chiplet processor 120b requesting a global counter synchronization process.

[0083] In communication 206, the master chiplet processor 120a may transmit commands or instructions to the master chiplet global counter subsystem 126a, or otherwise configure the master chiplet global counter subsystem 126a to enable periodic reading of global counters by the master chiplet global counter subsystem 126a. In some embodiments, the master chiplet processor 120a may set bits or registers within the master chiplet global counter subsystem 126a (or within a memory associated with the master chiplet global counter subsystem 126a) to enable periodic reading of global counters by the master chiplet global counter subsystem 126a. Enabling periodic reading of local global counters within the master chiplet global counter subsystem 126a may allow the master chiplet global counter subsystem 126a to read its local global counter at each rising edge of the sleep clock 108 (e.g., 32kHz).

[0084] In communication 208, the master chiplet processor 120a may transmit a command or instruction to the master chiplet global counter subsystem 126a, or otherwise configure the master chiplet global counter subsystem 126a to read the most recent global counter value stored within the master chiplet global counter subsystem 126a. In some embodiments, the master chiplet processor 120a may set a bit or register within the master chiplet global counter subsystem 126a (or within a memory associated with the master chiplet global counter subsystem 126a) to read the most recent global counter value stored within the master chiplet global counter subsystem 126a. In response to receiving the command or instruction from the master chiplet processor 120a, the master chiplet global counter subsystem 126a may make the local global counter corresponding to the most recent rising edge of the sleep clock 108 available to the master chiplet processor 120a (e.g., within a register space or memory accessible by the master chiplet processor 120a). Thus, the master chiplet processor 120a may read or snapshot the latest local global counter determined by the periodic global counter read enabled in communication 206 .

[0085] In operation 209, the master chiplet processor 120a may determine a next sleep clock synchronization edge that may be used to synchronize with the chiplet global counter subsystem 126b. In some embodiments, the next sleep clock synchronization edge that may be used to synchronize with the chiplet global counter subsystem 126b may be the first sleep clock rising edge of the master chiplet sleep clock that occurs after the chiplet 110b completes the PBL phase and enters the SBL phase.

[0086] In communication 210, the master chiplet processor 120a may configure a time comparator (e.g., master timer 114) within the master chiplet global counter subsystem 126a. The time comparator may be configured to be ready to trigger a global counter sync pulse trigger at some future sleep clock rising edge determined by the sleep clock sync edge determined in operation 209.

[0087] In communication 212, the master chiplet processor 120a may transmit the global counter synchronization value to the slave chiplet global counter subsystem 126b (e.g., as an SPMI broadcast message) via the interface bus 106. The slave chiplet global counter subsystem 126b may store the global counter synchronization value in a preload register in preparation for loading the global counter synchronization value onto a local global counter stored and used by the slave chiplet global counter subsystem 126b.

[0088] The master chiplet global counter subsystem 126a may transmit a global counter synchronization pulse trigger (i.e., a synchronization message) to the slave chiplet global counter subsystem 126b in communication 214. The slave chiplet global counter subsystem 126b may then latch the global counter synchronization value stored in the preload register in communication 212 to synchronize the local global counter within the slave chiplet global counter subsystem 126b with the local global counter within the master chiplet global counter subsystem 126a.

[0089] In communication 216, the chiplet processor 120b may poll the chiplet global counter subsystem 126b to determine whether synchronization has been completed. For example, the chiplet processor 120b may poll the synchronization status register of the chiplet global counter subsystem 126b to determine whether a bit or register has been changed to indicate a state that the synchronization process has been completed.

[0090] Communications 218-224 may be used for global counter synchronization debugging.

[0091] In communication 218, the master chiplet processor 120a may configure a time comparator (e.g., master timer 114) within the master chiplet global counter subsystem 126a. The time comparator may be configured to prepare to trigger a global counter sync pulse trigger at some future sleep clock rising edge. The time comparator may be configured to trigger a global counter sync pulse trigger in a manner similar to communication 210 as described above.

[0092] In communication 220, the master chiplet processor 120a may transmit a message to or otherwise instruct (i.e., set a register value) the chiplet global counter subsystem 126b to disable the global counter synchronization path from the chiplet global counter subsystem 126b. Disabling the global counter synchronization path may include disabling the SPMI slave functional block 130b so that it may no longer be able to transmit and receive SPMI broadcast messages across the interface bus 106. In some embodiments, disabling the global counter synchronization path may also suspend the global counter of the chiplet 110b.

[0093] In communication 222, the master chiplet global counter subsystem 126a may transmit a global counter synchronization pulse trigger (i.e., a synchronization message) to the slave chiplet global counter subsystem 126b. The slave chiplet global counter subsystem 126b may then latch the global counter synchronization value stored in the preload register in communication 212 to synchronize the local global counter within the slave chiplet global counter subsystem 126b with the local global counter within the master chiplet global counter subsystem 126a. Communication 222 may be performed in a manner similar to communication 214 as described above.

[0094] In communication 224, the master chiplet processor 120a may read the global counter synchronization value stored within the slave chiplet global counter subsystem 126b. The master chiplet processor 120a may compare the global synchronization value determined in communication 218 with the global synchronization value stored by the preload register of the slave chiplet global counter subsystem 126b to determine whether the values ​​match. If the global synchronization value determined in communication 218 matches the global synchronization value stored by the preload register of the slave chiplet global counter subsystem 126b, the master chiplet processor 120a may determine that the synchronization process in communication 216 has been successfully completed.

[0095] refer to Figure 2The operations and communications described may also be used during a chiplet crash event. Any chiplet 110b, 110c, 110d may crash during the SBL or normal operation. When a chiplet crashes, the chiplet global counters enabled by the PBL stored by the chiplet global counter subsystem may become unsynchronized with the master chiplet global counters stored by the master chiplet global counter subsystem 126a. The master chiplet 110a may choose to individually reset any of the crashed chiplets 110b, 110c, 110d without resynchronizing any chiplets 110b, 110c, 110d that have not yet crashed.

[0096] refer to Figure 2 The operations and communications described may also be used during a master chiplet crash event.The multi-chiplet system 100 may be operated to perform global counter synchronization as if the master chiplet 110a and slave chiplets 110b, 110c, 110d were cold started.

[0097] Figure 3 is a message flow diagram illustrating operations for sleep clock edge-based global counter synchronization in a multi-chiplet system, and chiplet-to-chiplet and intra-chiplet communications when a chiplet global counter is paused, according to some embodiments.

[0098] A CTI trigger may pause a global counter stored locally by any of the chiplets 110b, 110c, 110d. A CTI trigger may be used to pause local storage (i.e., in the corresponding chiplet global counter subsystem 126b, 126c, 126d) for debugging purposes, such as determining a timestamp at a particular error event. When any locally stored global counter from a chiplet 110b, 110c, 110d is paused by a CTI trigger, the global counter value may become out of sync with the global counter of the master chiplet 110a stored locally within the master chiplet global counter subsystem 126a. The following flow provides a resynchronization of the global counters of the master chiplet 110a and the chiplet 110b after pausing the chiplet global counter.

[0099] In communication 301, the chiplet processor 120b may transmit a message to the chiplet global counter subsystem 126b or otherwise instruct (i.e., set a register value) to disable the global counter pause from the chiplet global counter subsystem 126b, which may be referred to as a CTI triggered pause. Disabling the global counter pause may allow the global counter stored in the chiplet global counter subsystem 126b to begin counting again. However, due to the duration of the CTI pause, the chiplet global counter may have become out of sync with the master chiplet global counter.

[0100] In communication 303, the chiplet processor 120b may transmit a message to the chiplet global counter subsystem 126b or otherwise instruct (i.e., set a register value) to enable a global counter synchronization path from the chiplet global counter subsystem 126b. Enabling the global counter synchronization path may include initiating an SPMI slave function block 130b, which may be capable of transmitting and receiving SPMI broadcast messages across the interface bus 106.

[0101] Once the chiplet 110b is reconfigured to start global counter synchronization and the locally stored global counter is running, it can be as described in reference Figure 2 Operations and communications 204 to 216 are performed as described to synchronize the slave chiplet global counter stored in the chiplet global counter subsystem 126 b with the master chiplet global counter stored in the master chiplet global counter subsystem 126 a. Figure 2 The described communications 218 to 224 are used to perform any debugging process.

[0102] Figure 4 is a message flow diagram illustrating operations for sleep clock edge-based global counter synchronization in a multi-chiplet system when a master chiplet global counter is paused, as well as chiplet-to-chiplet and intra-chiplet communications, according to some embodiments.

[0103] A CTI trigger may pause global counters stored locally by the master chiplet 110a. A CTI trigger may be used to pause local storage (i.e., in the master chiplet global counter subsystem 126a) for debugging purposes, such as determining a timestamp at a particular error event. When the locally stored global counters of the master chiplet 110a are paused by a CTI trigger, the global counter values ​​may become unsynchronized with all global counters from the chiplets 110b, 110c, 110d stored locally within the chiplet global counter subsystems 126b, 126c, 126d. For example, when the master chiplet global counter is paused by a CTI trigger, the same CTI trigger is transmitted to the chiplet global counters over the CTI network to simultaneously pause the chiplet global counters. The master chiplet may transmit a CTI non-pause trigger (interrupt request).

[0104] Therefore, in addition to chiplets 110b, 110c, 110d, the multi-chiplet system can also reinitialize the master chiplet 110a to resynchronize all locally stored global counter values. The following flow provides resynchronization of the global counters of the master chiplet 110a and slave chiplet 110b after the master chiplet global counter is paused.

[0105] In communication 401, the master chiplet processor 120a may transmit a message to the chiplet global counter subsystem 126b or otherwise instruct (i.e., set a register value) to disable the global counter pause from the chiplet global counter subsystem 126b, which may be referred to as a CTI triggered pause. Disabling the global counter pause may allow the global counter stored within the chiplet global counter subsystem 126b to begin counting again. However, due to the duration of the CTI pause, the chiplet global counter may have become out of sync with the master chiplet global counter.

[0106] In communication 402, the master chiplet processor 120a may transmit a message to the master chiplet global counter subsystem 126a or otherwise instruct (i.e., set a register value) the master chiplet global counter subsystem 126a to disable the global counter pause, which may be referred to as a CTI triggered pause. Disabling the global counter pause may allow the global counter stored within the master chiplet global counter subsystem 126a to begin counting again. However, due to the duration of the CTI pause, the master chiplet global counter may have become out of sync with the slave chiplet global counter.

[0107] In some embodiments, communications 401 and 402 may be a single interrupt request transmitted from the master chiplet processor 120 a. For example, a master chiplet CTI non-pause trigger may transmit an interrupt request to the master chiplet global counter subsystem 126 a, which may be the same interrupt request to slave A53, transmitted over the CTI network to the chiplet processor 120 b.

[0108] In communication 403, the chiplet processor 120b may transmit a message to the chiplet global counter subsystem 126b or otherwise instruct (i.e., set a register value) to enable a global counter synchronization path from the chiplet global counter subsystem 126b. Enabling the global counter synchronization path may include initiating an SPMI slave function block 130b, which may be capable of transmitting and receiving SPMI broadcast messages across the interface bus 106.

[0109] Once the master chiplet 110a and slave chiplet 110b are reconfigured to start global counter synchronization and the locally stored global counters are running, the Figure 2 Operations and communications 204 to 216 are performed as described to synchronize the slave chiplet global counter stored in the chiplet global counter subsystem 126 b with the master chiplet global counter stored in the master chiplet global counter subsystem 126 a. Figure 2 The described communications 218 to 224 are used to perform any debugging process.

[0110] Figure 5 is a timing diagram illustrating a timing flow 500 for global counter synchronization pulse triggering in a multi-chiplet system according to some embodiments. Figures 1 to 5 , exemplifies the reference Figures 2 to 4 The timing of some of the communications described.

[0111] At event 502, the time comparator of the master chiplet global counter subsystem 126a (e.g., the master timer 114) may initiate a global counter synchronization pulse trigger. If the interface bus 106 is capable of parallel communication, such as when the interface bus 106 is capable of being configured as an SPMI broadcast bus, the time comparator may trigger the global counter synchronization pulse trigger as a global counter synchronization enable telegram. If the interface bus 106 is not capable of parallel communication, the time comparator may trigger the global counter synchronization pulse trigger as a global counter synchronization enable message over a serial data path (such as a dedicated GPIO pin between the master chiplet 110a and the chiplet 110b). The global counter synchronization pulse trigger may instruct the chiplet 110b to transfer the global counter synchronization value (e.g., stored in a preload register from the chiplet 110b; as described below with reference to Figure 6 The "N" is loaded into the chiplet global counter.

[0112] At event 504, chiplet 110b may trigger a sleep clock from a rising edge of the sleep clock (eg, as described below with reference to Figure 6 The sleep clock synchronization edge "n") synchronizes the global counter value (for example, stored in the preload register of the chiplet 110b; as shown below Figure 6 The "N" described above) is loaded onto the chiplet global counter. After the global counter synchronization value is loaded from the chiplet 110b into the chiplet global counter subsystem 126b, the global counter synchronization pulse trigger can be de-asserted by the time comparator. For example, in the case of an SPMI-enabled interface bus 106, the global counter synchronization pulse trigger can be disabled after the rising edge identified at event 504 but before the next rising edge of the sleep clock, and the global counter synchronization pulse trigger can be a telegram or broadcast message that can be transmitted to all chiplets 110b, 110c, 110d at the same time.

[0113] In some embodiments where the interface bus is not capable of parallel communication (e.g., dedicated GPIO pins of master chiplet 110a are used to communicate with slave chips 110b, 110c, 110d, respectively), the sleep clock rising edge 505 (e.g., as described below with reference to Figure 6The sleep clock rising edge "n-1" described above can be aligned with the global counter sync pulse trigger at 502. If the sleep clock rising edge 505 is synchronized with the global counter sync pulse trigger, then at event 504, the time comparator can transmit the global counter sync pulse trigger one sleep clock cycle before the expected sleep clock cycle, thereby causing the chiplet global counter to be one sleep clock cycle ahead of the master chiplet global counter.

[0114] To avoid premature global counter sync pulse triggering caused by synchronization between the sleep clock and the global counter sync pulse triggering, the master chiplet 110a may introduce a delay after the sleep clock rising edge 505 to ensure that the global counter sync pulse triggering follows the sleep clock rising edge 505. The delay may be the number of CXO cycles starting from the sleep clock rising edge 505.

[0115] Figure 6 is a timing diagram illustrating a timing flow 600 for sleep clock edge-based global counter synchronization in multi-chiplets according to some embodiments. Figures 1 to 6 , illustrating various signals within the timing diagram, including signals observed from the perspective of the master chiplet 110a, such as chiplet RESIN_N (i.e., a reset assertion provided by the PMIC controller 102 to the master chiplet 110a and reallocated from the master chiplet 110a to the chiplet 110b across a set of dedicated GPIO pins), master chiplet processor operations, master chiplet global counters (i.e., stored within the master chiplet global counter subsystem 126a), a master chiplet sleep clock (e.g., 32kHz), chiplet SPMI messages (i.e., messages observed by the master chiplet 110a over the interface bus 106), and master chiplet SPMI messages (i.e., messages broadcast by the master chiplet 110a over the interface bus 106). Additional signals are illustrated from the perspective of the chiplet 110b, such as a chiplet preload register, VIO int (i.e., global synchronization pulse trigger), synchronization status, chiplet sleep clock (e.g., 32kHz), active clock (e.g., 19.2MHz), chiplet global counter (i.e., stored within chiplet global counter subsystem 126b), and chiplet processor operations.

[0116] At event 602, chiplet processor 120b may come out of reset in response to receiving a reset assertion from master chiplet processor 120a. Master chiplet processor 120a may generate a reset assertion and transmit the reset assertion to chiplet processor 120b. Master chiplet processor 120a may transmit the reset assertion to chiplet processor 120b after the master chiplet processor has entered the PBL phase. Chiplet processor 120b may receive a reset assertion from master chiplet processor 120a after the master chiplet processor 120a has entered the PBL phase. In some embodiments, master chiplet processor 120a may transmit the reset assertion to chiplet processor 120b after the master chiplet processor has entered the SBL phase. The reset assertion (e.g., RESIN_N) may be transmitted by master chiplet processor 120a to chiplet processor 120b across a dedicated channel (such as a set of dedicated GPIO pins). The reset assertion received by the chiplet processor 120b from the master chiplet processor 120a may trigger the chiplet processor 120b to enter the PBL phase. At this point, the global counter within the chiplet global counter subsystem 126b is not synchronized with the global counter within the master chiplet global counter subsystem 126a. The chiplet 110b may remain in the PBL phase at least until a sleep clock rising edge (e.g., designated as "n") of the master chiplet sleep clock has occurred, after which the chiplet global counter subsystem 126b may be synchronized with the master chiplet global counter subsystem 126a. Event 602 may be synchronized with reference Figure 2 The communication 202 described is performed in a similar manner.

[0117] At event 604a, a global counter synchronization request may be generated from chiplet processor 120b and transmitted to master chiplet processor 120a. After entering the PBL phase, chiplet processor 120b may transmit the global counter synchronization request to master chiplet processor 120a. In some embodiments, the global counter synchronization request may be transmitted as an SPMI telegram or broadcast across interface bus 106. The global counter synchronization request generated or otherwise configured by chiplet processor 120b may include a unique slave identifier (USID) and / or a group slave identifier (GSID).

[0118] At event 604b, the master chiplet processor 120a may detect or otherwise receive a global counter synchronization request transmitted by the slave chiplet processor 120b during event 604a. In some embodiments, the master chiplet processor 120a may continuously poll the interface bus 106 for any SPMI telegrams or broadcasts transmitted by the slave chiplet processor 120b. Events 604a and 604b may be synchronized with reference to Figure 2 The communication 204 described is performed in a similar manner.

[0119] In some embodiments, event 606 may be performed in response to master chiplet processor 120a detecting an SPMI telegram or broadcast from chiplet processor 120b requesting a global counter synchronization process.

[0120] At event 606, the master chiplet processor 120a may transmit a command or instruction to the master chiplet global counter subsystem 126a, or otherwise configure the master chiplet global counter subsystem 126a to enable periodic reading of global counters by the master chiplet global counter subsystem 126a. In some embodiments, the master chiplet processor 120a may set a bit or register within the master chiplet global counter subsystem 126a (or within a memory associated with the master chiplet global counter subsystem 126a) to enable periodic reading of global counters by the master chiplet global counter subsystem 126a. Enabling periodic reading of local global counters within the master chiplet global counter subsystem 126a may allow the master chiplet global counter subsystem 126a to read its local global counter at each rising edge of the master chiplet sleep clock (e.g., 32kHz).

[0121] The master chiplet processor 120a may further transmit a command or instruction to the master chiplet global counter subsystem 126a, or otherwise configure the master chiplet global counter subsystem 126a to read the most recent global counter value stored within the master chiplet global counter subsystem 126a. In some embodiments, the master chiplet processor 120a may set a bit or register within the master chiplet global counter subsystem 126a (or within a memory associated with the master chiplet global counter subsystem 126a) to read the most recent global counter value stored within the master chiplet global counter subsystem 126a. In response to receiving a command or instruction from the master chiplet processor 120a, the master chiplet global counter subsystem 126a may make available to the master chiplet processor 120a (e.g., within a register space or memory accessible by the master chiplet processor 120a) a local global counter corresponding to the most recent rising edge of the sleep clock 108 of the master chiplet processor 120a. Thus, the master chiplet processor 120a may read or snapshot the latest local global counter determined by the periodic global counter read enabled at event 606. Event 606 may be preceded by a reference Figure 2 The described communications 206 and 208 are performed in a similar manner.

[0122] At event 610, master chiplet processor 120a may determine a next sleep clock synchronization edge that may be used to synchronize with chiplet global counter subsystem 126b. In some embodiments, the next sleep clock synchronization edge (e.g., master chiplet sleep clock rising edge "n") that may be used to synchronize with chiplet global counter subsystem 126b may be the first sleep clock rising edge of the master chiplet sleep clock that occurs after chiplet 110b completes the PBL phase and enters the SBL phase (i.e., after the slave PBL wait time expires).

[0123] The master chiplet processor 120a may configure a time comparator (e.g., master timer 114) within the master chiplet global counter subsystem 126a. The time comparator may be configured to prepare to trigger a sync pulse trigger at the master chiplet sleep clock rising edge "n-1". The time comparator may be configured with the master chiplet sleep clock so that the time comparator may track the time at which the master chiplet sleep clock exhibits a rising edge (e.g., at each global counter read / snapshot).

[0124] In some embodiments, the sleep clock synchronization edge may be determined by the duration of the overall global counter synchronization mechanism. The duration of the overall global counter synchronization mechanism may be a duration determined in software (e.g., via the master chiplet 110a and / or PMIC controller 102) based at least on the interface bus 106 latency between the master chiplet 110a and the slave chiplets 110b, 110c, 110d (e.g., 8B global counter value and 2B sync message), and the master chiplet 110a software latency for (i) reading the current global counter value and transmitting it over the interface bus 106, and (ii) configuring a time comparator (e.g., master timer 114) for the global counter synchronization pulse triggering over the interface bus 106 (e.g., SPMI or CTI).

[0125] The master chiplet processor 120a may configure and / or generate an SPMI timestamp message including a global counter synchronization value and then transmit the SPMI timestamp message across the interface bus 106. The master chiplet processor may determine or otherwise generate a global counter synchronization value “N” based on the last read or most recent master chiplet global counter value “K”. The global counter synchronization value “N” may be equal to the last read master chiplet global counter “K” plus the next sleep clock synchronization edge “n” multiplied by the master chiplet sleep clock period. For example, N=K+(n*(1 / 32kHz)). Event 610 may be preceded by a time delay equal to the reference clock. Figure 2 The described communications 209, 210 and 218 are performed in a similar manner.

[0126] At event 612, the master chiplet processor 120a may transmit or broadcast a global counter synchronization value "N" to the slave chiplet global counter subsystem 126b as a master chiplet SPMI message via the interface bus 106. The slave chiplet global counter subsystem 126b may store the global counter synchronization value "N" in a preload register in preparation for loading the global counter synchronization value onto a local global counter stored and used by the slave chiplet global counter subsystem 126b. With the global counter synchronization value "N" preloaded into the slave chiplet global counter subsystem 126b, the slave chiplet global counter subsystem 126b may wait to synchronize with the master chiplet global counter subsystem 126a. Event 612 may be preceded by a reference to Figure 2 The communication 212 described is performed in a similar manner.

[0127] At event 614, the master chiplet global counter subsystem 126a may transmit or broadcast a global counter sync pulse trigger (i.e., an SPMI sync trigger message) to the slave chiplet global counter subsystem 126b. The global counter sync pulse trigger may be broadcast to the slave chiplet global counter subsystem 126b as a master chiplet SPMI message via the interface bus 106. The master chiplet processor 120a may broadcast the global counter sync pulse trigger at a time that is a master chiplet sleep clock cycle (i.e., n-1) that precedes the sleep clock sync edge "n" that was determined during event 610 for synchronization with the slave chiplet global counter subsystem 126b.

[0128] The master chiplet processor 120a may broadcast a global counter sync pulse trigger with a timer value equal to the master chiplet global counter value or the configured timer value K2. In some embodiments, the global counter sync pulse trigger may be initiated by a time comparator (e.g., master timer 114). Previously, in event 610, the time comparator may have been configured with the master chiplet sleep clock so that the time comparator can track the time when the master chiplet sleep clock exhibits a rising edge (e.g., at each global counter read / snapshot). Using the time comparator, the master chiplet processor 120a may read or snapshot the master chiplet global counter value at the rising edge “n-1” of the master chiplet sleep clock. When the time comparator value recorded at the rising edge “n-1” of the master chiplet sleep clock matches the configured value K2, the master chiplet processor 120a may broadcast a global counter sync pulse trigger. The master chiplet global counter value may be equal to (n-1) multiplied by the sleep clock period (e.g., K2=(n-1)(1 / 32kHz).

[0129] The global counter synchronization pulse trigger may arrive at the chiplet global counter subsystem 126b before the next rising edge "n" of the master chiplet sleep clock. The time between the rising edge "n-1" and the sleep clock synchronization edge "n" may be 586 crystal oscillator (XO) clocks, which may be referred to as the maximum SPMI message arrival delay, or the time the global counter synchronization pulse trigger must arrive at the chiplet global counter subsystem 126b. The time between the rising edge "n-1" when the global counter synchronization pulse trigger is broadcast and the time when the global counter synchronization pulse trigger is received from the chiplet global counter subsystem 126b (i.e., the rising edge of VIO int (sync trig)) may be referred to as the SPMI message arrival delay. The SPMI message arrival delay may be a time delay limited by a hardware communication path. The SPMI message arrival delay may be less than the maximum SPMI message arrival delay.

[0130] After receiving a global counter sync pulse trigger as indicated by the rising edge of VIO int (sync trig) from the chiplet global counter subsystem 126b, the chiplet global counter subsystem 126b can be ready to synchronize with the master chiplet global counter subsystem 126a at the sleep clock sync edge "n". At the sleep clock sync edge "n", the global counter sync value "N" stored in the chiplet preload register can be loaded or latched into the chiplet global counter stored by the chiplet global counter subsystem 126b. The global counter sync value "N" can be loaded into the chiplet global counter at the rising edge of the chiplet sleep clock, which is considered to be the same sleep clock sync edge "N" of the master chiplet sleep clock. The global counter sync value "N" can be loaded into the chiplet global counter at the rising edge of the chiplet sleep clock in the chiplet global counter subsystem 126b, which can be skewed from the sleep clock sync edge "n". The deviation between the master chiplet sleep clock and the chiplet sleep clock at the sleep clock sync edge "n" can be a time difference of 1 or 2 XO clock cycles. Event 614 can be used with reference Figure 2 The communication 214 described is performed in a similar manner.

[0131] At event 616, the chiplet processor 120b may poll the chiplet global counter subsystem 126b to determine whether synchronization has been completed. The chiplet processor 120b may poll the synchronization status register (e.g., "sync status") of the chiplet global counter subsystem 126b to determine whether a bit or register has been changed to indicate a state that the synchronization process has been completed. After the chiplet processor 120b determines that synchronization between the master chiplet global counter subsystem 126a and the chiplet global counter subsystem 126b is complete, the master chiplet processor 120a and the chiplet processor 120b may continue with normal processes, including debugging processes. Therefore, when global counter synchronization is completed, the chiplet processor 120b may transition from the PBL phase to the SBL phase. Once synchronization is complete, VIO int (sync trig) may be de-asserted before the next rising edge "n+1" of the sleep clock.

[0132] For ease of illustration and description, Figure 6 The timing signals between the two chiplets (e.g., chiplets 110a, 110b) are illustrated. Figure 1 As illustrated, additional chiplets (e.g., 110c, 110d) in electrical communication with master chiplet 110a may simultaneously execute the same timing signals and events occurring in, executed by, or in conjunction with chiplet 110b. For example, at event 612, a preload register of chiplet 110d may be loaded with a value of "N". As another example, at event 614, master chiplet 110a may broadcast a global synchronization pulse trigger across the SPMI bus to reach all three slave chiplets 110b, 110c, 110d simultaneously.

[0133] Figure 7 is a process flow diagram illustrating an embodiment method 700 for sleep clock edge-based global counter synchronization in a multi-chiplet system according to various embodiments. Figures 1 to 7 , method 700 may be implemented in a processor (e.g., processing cores 120a, 120b, 120c, 120d) configured to perform the operations of the method. In some embodiments, the processor (e.g., processing cores 120a, 120b, 120c, 120d) may be configured to perform operations via processor-executable instructions stored in a non-transitory processor-readable medium (e.g., memory devices 122a, 122b, 122c, and 122d). The means for performing each of the operations of method 700 may be a processor of multi-chiplet system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0134] In block 702, the PMIC may provide a sleep clock to a first chiplet and a second chiplet. The SoC (e.g., multi-chiplet system 100) may include a first chiplet (e.g., master chiplet 110a) that includes a first chiplet global counter subsystem (e.g., master chiplet global counter subsystem 126a). The SoC may include a second chiplet (e.g., from chiplet 110b) that includes a second chiplet global counter subsystem (e.g., from chiplet global counter subsystem 126b). The SoC may also include an interface bus (e.g., interface bus 106) that may communicatively couple the first chiplet and the second chiplet. The SoC may include a PMIC (e.g., PMIC controller 102) that may be configured to provide a sleep clock (e.g., sleep clock 108) to the first chiplet and the second chiplet in a star configuration. The first chiplet and the second chiplet may be configured to receive the sleep clock from the PMIC. In some embodiments, the sleep clock pulse deviation between the first chiplet and the second chiplet may be equal to or less than two crystal oscillator clock periods.

[0135] In some embodiments, the SoC may include a third chiplet (e.g., from chiplet 110c, 110d) that includes a third chiplet global counter subsystem (e.g., from chiplet global counter subsystem 126c, 126d). An interface bus may communicatively couple the first chiplet and the third chiplet. The first chiplet may be further configured to transmit a global counter sync pulse trigger to the third chiplet across the interface bus. The third chiplet may be configured to load a global counter sync value into the third chiplet global counter subsystem at a sleep clock sync edge of the sleep clock in response to receiving the global counter sync pulse trigger.

[0136] The process in block 702 may be as described with reference to Figure 1 The means for performing the operations in block 702 may include a processor of the multi-chiplet system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0137] In block 704, a global counter synchronization pulse trigger may be transmitted from a first chiplet to a second chiplet. The first chiplet may be configured to transmit the global counter synchronization pulse trigger to the second chiplet across an interface bus. For example, the first chiplet may transmit the global counter synchronization pulse trigger as a broadcast or telegram message across an interface bus that is an SPMI. As another example, the first chiplet may transmit the global counter synchronization pulse trigger by communicatively connecting the first chiplet to a series of dedicated GPIO pins of the second chiplet. The global counter synchronization pulse trigger may be configured by the first chiplet to cause the second chiplet to load a global counter synchronization value (e.g., "N") into the second chiplet global counter subsystem at a sleep clock synchronization edge (e.g., "n") of a sleep clock.

[0138] In some embodiments, the first chiplet can be configured to transmit the global counter sync pulse trigger to the second chiplet one sleep clock cycle before a sleep clock sync edge of the sleep clock. In some embodiments, the first chiplet can be configured to transmit the global counter sync pulse trigger to the second chiplet at a delay time between the sleep clock sync edge and one sleep clock cycle before the sleep clock sync edge.

[0139] The process in block 704 may be as described with reference to Figures 2 to 4 , Figure 5 Communications 214 and Figure 6 The operation may be performed as described in event 614 of block 704. The means for performing the operation in block 704 may include a processor of the multi-chiplet system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0140] In block 706, the global counter synchronization value may be loaded into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to the second chiplet receiving the global counter synchronization pulse trigger. In response to receiving the global counter synchronization pulse trigger as described with reference to block 704, the second chiplet may be configured to load the global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock (e.g.,

[0141] The process in block 706 may be as described with reference to Figures 2 to 4 , Figure 5 Communications 214 and Figure 6 The operation may be performed as described in event 614 of block 704. The means for performing the operation in block 704 may include a processor of the multi-chiplet system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0142] The order of operations performed in blocks 702-706 is merely illustrative, and the operations of blocks 702-706 may be performed in any order and partially simultaneously in some embodiments. In some embodiments, method 700 may be performed by a processor of a device independent of but in conjunction with an external memory device. For example, method 700 may be implemented as a software module executed within a processor of a SoC or in dedicated hardware within the SoC that issues commands for establishing a secure memory channel and accessing a memory of an external memory device and is otherwise configured to take actions and store data as described.

[0143] Fig. 8A is a process flow diagram illustrating an embodiment method 800a of global counter synchronization based on sleep clock edges in a multi-chiplet system in some embodiments, which can be implemented as part of method 700. Figures 1 to 8A , method 800a may be implemented in a processor (e.g., processing cores 120a, 120b, 120c, 120d) configured to perform the operations of the method. In some embodiments, the processor (e.g., processing cores 120a, 120b, 120c, 120d) may be configured to perform operations via processor-executable instructions stored in a non-transitory processor-readable medium (e.g., memory devices 122a, 122b, 122c, and 122d). The means for performing each of the operations of method 800a may be a processor of multi-chiplet system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0144] In block 802, a first chiplet may read a first chiplet global counter value from a first chiplet global counter subsystem. The first chiplet (e.g., master chiplet 110a) may be configured to read or otherwise receive the first chiplet global counter value from a first chiplet global counter subsystem (e.g., master chiplet global counter subsystem 126a). In some embodiments, the first chiplet global counter value may be read from the first chiplet global counter subsystem at a rising edge of a sleep clock. The process in block 802 may be described with reference to Figures 2 to 4 Communications 208 and Figure 6 The operation may be performed as described in event 606 of block 802. The means for performing the operation in block 802 may include a processor of the multi-chiplet system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0145] In block 804, a global counter synchronization value may be generated by the first chiplet based on the first chiplet global counter value. The first chiplet (e.g., master chiplet 110a) may be configured to generate a global counter synchronization value (e.g., "N") based on the first chiplet global counter value previously read as described with reference to block 802. The process in block 804 may be as described with reference to Figure 6 The operation may be performed as described in event 610 of block 804. The means for performing the operation in block 804 may include a processor of the multi-chiplet system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0146] In block 806, a global counter synchronization value may be transmitted from the first chiplet to the second chiplet. The first chiplet (e.g., master chiplet 110a) may be configured to transmit a global counter synchronization value (e.g., "N") to the second chiplet (e.g., from chiplet 110b). For example, the first chiplet may transmit the global counter synchronization value as a broadcast or telegram message across an interface bus such as SPMI. As another example, the first chiplet may transmit the global counter synchronization value by communicatively connecting the first chiplet to a series of dedicated GPIO pins of the second chiplet. The process in block 806 may be described with reference to Figures 2 to 4 Communications 212 and Figure 6 The operation may be performed as described in event 612 of block 806. The means for performing the operation in block 806 may include a processor of the multi-chiplet system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0147] In block 808, the global counter synchronization value may be stored in a preload register of the second chiplet. The second chiplet (e.g., from chiplet 110b) may be configured to store the global counter synchronization value (e.g., "N") in the preload register, where the global counter synchronization value may be loaded from the preload register into the second chiplet global counter subsystem (e.g., from chiplet global counter subsystem 126b). The process in block 808 may be described with reference to Figures 2 to 4 Communications 212 and Figure 6 The multi-chiplet system 100 may continue to execute block 702 ( Figure 7 The means for performing the operations in block 808 may include a processor of the multi-chiplet system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0148] The order of operations performed in blocks 802-808 is merely illustrative, and the operations of blocks 802-808 may be performed in any order and partially simultaneously in some embodiments. In some embodiments, method 800a may be performed by a processor of a device independent of but in conjunction with an external memory device. For example, method 800a may be implemented as a software module executed within a processor of a SoC or in dedicated hardware within the SoC that issues commands for establishing a secure memory channel and accessing a memory of an external memory device and is otherwise configured to take actions and store data as described.

[0149] Figure 8B is a process flow diagram illustrating an embodiment method 800b of global counter synchronization based on sleep clock edges in a multi-chiplet system in some embodiments, which can be implemented as part of method 700. Figures 1 to 8B , method 800b may be implemented in a processor (e.g., processing cores 120a, 120b, 120c, 120d) configured to perform the operations of the method. In some embodiments, the processor (e.g., processing cores 120a, 120b, 120c, 120d) may be configured to perform operations via processor-executable instructions stored in a non-transitory processor-readable medium (e.g., memory devices 122a, 122b, 122c, and 122d).

[0150] In block 810, the first chiplet may determine a sleep clock synchronization edge of a sleep clock. The first chiplet (e.g., master chiplet 110a) may be configured to determine a sleep clock synchronization edge (e.g., "n") of a sleep clock (e.g., sleep clock 108), where the sleep clock synchronization edge may be a rising edge of the sleep clock. The process in block 810 may be described with reference to Figures 2 to 4 Operation 209 and Figure 6 The means for performing the operations in block 810 may include a processor of the multi-chiplet system 100, such as processing cores 120a, 120b, 120c, 120d, etc. The multi-chiplet system 100 may continue to perform block 702 ( Figure 7 ) operation.

[0151] In some embodiments, the method 800b may be performed by a processor of a device independent of but in conjunction with the external memory device. For example, the method 800b may be implemented as a software module executed within a processor of the SoC or in dedicated hardware within the SoC that issues commands for establishing a secure memory channel and accessing the memory of the external memory device and is otherwise configured to take actions and store data as described.

[0152] Figure 8C is a process flow diagram illustrating an embodiment method 800c of global counter synchronization based on sleep clock edges in a multi-chiplet system in some embodiments, which can be implemented as part of method 700. Figures 1 to 8C , method 800c may be implemented in a processor (e.g., processing cores 120a, 120b, 120c, 120d) configured to perform the operations of the method. In some embodiments, the processor (e.g., processing cores 120a, 120b, 120c, 120d) may be configured to perform operations via processor-executable instructions stored in a non-transitory processor-readable medium (e.g., memory devices 122a, 122b, 122c, and 122d).

[0153] In block 812, the first chiplet may transmit a reset assertion to the second chiplet. The first chiplet (e.g., master chiplet 110a) may be configured to transmit the reset assertion to the second chiplet (e.g., from chiplet 110b) across a hardwired dedicated channel. For example, the first chiplet may transmit the reset assertion by communicatively connecting the first chiplet to a series of dedicated GPIO pins of the second chiplet. The reset assertion received by the chiplet may trigger the chiplet to enter the PBL phase. The process in block 812 may be as described with reference to Figure 2 Communications 202 and Figure 6 The operation may be performed as described in event 602 of block 812. The means for performing the operation in block 812 may include a processor of the multi-chiplet system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0154] In block 814, in response to the reset assertion, the second chiplet may transmit a global counter synchronization request to the first chiplet. The second chiplet (e.g., from chiplet 110b) may be configured to transmit the global counter synchronization request to the first chiplet in response to receiving the reset assertion from the first chiplet (e.g., master chiplet 110a), as described with reference to block 812. For example, the second chiplet may transmit the global counter synchronization request as a broadcast or telegram message across an interface bus that is SPMI. As another example, the second chiplet may transmit the global counter synchronization request by communicatively connecting the first chiplet to a series of dedicated GPIO pins of the second chiplet. The multi-chiplet system 100 may continue to execute block 702 of method 700 as described ( Figure 7 ). For example, the first chiplet may be configured to transmit a global counter synchronization pulse trigger to the second chiplet across the interface bus in response to the first chiplet receiving a global counter synchronization request from the second chiplet. The process in block 814 may be as described with reference to Figure 2 Communications 204 and Figure 6Means for performing the operations in block 814 may include a processor of the multi-chiplet system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0155] In some embodiments, the method 800c may be performed by a processor of a device independent of but in conjunction with the external memory device. For example, the method 800c may be implemented as a software module executed within a processor of the SoC or in dedicated hardware within the SoC that issues commands for establishing a secure memory channel and accessing the memory of the external memory device and is otherwise configured to take actions and store data as described.

[0156] Fig.8D is a process flow diagram illustrating an embodiment method 800d of sleep clock edge-based global counter synchronization in a multi-chiplet system in some embodiments, which may be implemented as part of method 700. Figures 1 to 8D , method 800d may be implemented in a processor (e.g., processing cores 120a, 120b, 120c, 120d) configured to perform the operations of the method. In some embodiments, the processor (e.g., processing cores 120a, 120b, 120c, 120d) may be configured to perform operations via processor-executable instructions stored in a non-transitory processor-readable medium (e.g., memory devices 122a, 122b, 122c, and 122d).

[0157] In block 816, the second chiplet may disable a global counter pause within the second chiplet global counter subsystem. The second chiplet (e.g., from chiplet 110b) may be configured to disable a global counter pause within the second chiplet global counter subsystem (e.g., from chiplet global counter subsystem 126b). The global counter pause may be a CTI pause trigger. Disabling the global counter pause may re-initiate counting of the second chiplet global counter within the second chiplet global counter subsystem. The process in block 816 may be as described with reference to Figure 3 The communication 301 is performed as described. The means for performing the operation in block 816 may include a processor of the multi-chiplet system 100, such as the processing cores 120a, 120b, 120c, 120d, etc.

[0158] In block 818, the second chiplet may enable a global counter synchronization path within the second chiplet global counter subsystem. The second chiplet (e.g., from chiplet 110b) may be configured to enable a global counter synchronization path within the second chiplet global counter subsystem (e.g., from chiplet global counter subsystem 126b). Enabling the global counter synchronization path may allow the first chiplet global counter subsystem (e.g., master chiplet global counter subsystem 126a) to communicate with the second chiplet global counter subsystem. The multi-chiplet system 100 may continue to execute block 702 of method 700 as described ( Figure 7 ) operation. The process in block 818 can be as described in reference Figure 3 The communication 303 may be performed as described. The means for performing the operations in block 818 may include a processor of the multi-chiplet system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0159] The order of operations performed in blocks 816 and 818 is merely illustrative, and the operations of blocks 816-818 may be performed in any order and partially simultaneously in some embodiments. In some embodiments, method 800d may be performed by a processor of a device independent of but in conjunction with an external memory device. For example, method 800d may be implemented as a software module executed within a processor of a SoC or in dedicated hardware within the SoC that issues commands for establishing a secure memory channel and accessing a memory of an external memory device and is otherwise configured to take actions and store data as described.

[0160] Fig. 8E is a process flow diagram illustrating an embodiment method 800e of global counter synchronization based on sleep clock edges in a multi-chiplet system in some embodiments, which can be implemented as part of method 700. Figures 1 to 8E , method 800e may be implemented in a processor (e.g., processing cores 120a, 120b, 120c, 120d) configured to perform the operations of the method. In some embodiments, the processor (e.g., processing cores 120a, 120b, 120c, 120d) may be configured to perform operations via processor-executable instructions stored in a non-transitory processor-readable medium (e.g., memory devices 122a, 122b, 122c, and 122d).

[0161] In block 820, the first chiplet may disable global counter pauses within the first chiplet global counter subsystem and the second chiplet global counter subsystem. The first chiplet (e.g., master chiplet 110a) may disable global counter pauses within the first chiplet global counter subsystem (e.g., master chiplet global counter subsystem 126a) and the second chiplet global counter subsystem (e.g., from chiplet global counter subsystem 126b). The global counter pause may be a CTI pause trigger. Disabling the global counter pause may re-initiate counting of the first chiplet global counter within the first chiplet global counter subsystem, and may re-initiate counting of the second chiplet global counter within the second chiplet global counter subsystem. The process in block 820 may be described with reference to Figure 4 The communication 401 and 402 are performed as described. The means for performing the operation in block 820 may include a processor of the multi-chiplet system 100, such as the processing cores 120a, 120b, 120c, 120d, etc.

[0162] In block 822, the second chiplet may enable a global counter synchronization path within the second chiplet global counter subsystem. The second chiplet (e.g., from chiplet 110b) may be configured to enable a global counter synchronization path within the second chiplet global counter subsystem (e.g., from chiplet global counter subsystem 126b). Enabling the global counter synchronization path may allow the first chiplet global counter subsystem (e.g., master chiplet global counter subsystem 126a) to communicate with the second chiplet global counter subsystem. The multi-chiplet system 100 may continue to execute block 702 of method 700 as described ( Figure 7 ) operation. The process in block 822 may be as described with reference to Figure 4 The communication 403 is performed as described. The means for performing the operation in block 822 may include a processor of the multi-chiplet system 100, such as processing cores 120a, 120b, 120c, 120d, etc.

[0163] The order of operations performed in blocks 820 and 822 is merely illustrative, and the operations of blocks 820-822 may be performed in any order and partially simultaneously in some embodiments. In some embodiments, method 800e may be performed by a processor of a device independent of but in conjunction with an external memory device. For example, method 800e may be implemented as a software module executed within a processor of a SoC or in dedicated hardware within the SoC that issues commands for establishing a secure memory channel and accessing a memory of an external memory device and is otherwise configured to take actions and store data as described.

[0164] Fig. 9900 is a component block diagram of an example wireless device in the form of a smart phone 900 suitable for implementing some embodiments. The smart phone 900 may include a first processing device (such as the multi-chiplet system 100) coupled to a second processing device (such as the SoC 918). The multi-chiplet system 100 and the SoC 918 may be 5G-enabled SoCs. The multi-chiplet system 100 and the SoC 918 may be coupled to internal memory 906, 916, a display 912, and to a speaker 914. Additionally, the smart phone 900 may include an antenna 904 that may be connected to a wireless data link for sending and receiving electromagnetic radiation, or a cellular telephone transceiver 908 coupled to one or more processors in the multi-chiplet system 100 and the SoC 918. The smart phone 900 also typically includes a menu selection button or rocker switch 920 for receiving user input.

[0165] The typical smart phone 900 also includes a sound coding / decoding (CODEC) circuit 910 that digitizes the sound received from the microphone into data packets suitable for wireless transmission and decodes the received sound data packets to generate analog signals provided to the speaker to produce sound. In addition, one or more of the processor, wireless transceiver 908, and CODEC 910 in the multi-chiplet system 100 and SoC 918 may include a digital signal processor (DSP) circuit (not shown separately).

[0166] The processor of the smart phone 900 can be any programmable microprocessor, microcomputer, or one or more multi-processor chips that can be configured by processor-executable instructions to perform various functions, including the functions of the various specific implementations described herein. In some mobile devices, multiple processors may be provided (such as one processor dedicated to wireless communication functions within the multi-chiplet system 100 and one processor dedicated to running other applications within the SoC 918). Typically, software applications can be stored in the memory 906, 916, which are then accessed and loaded into the processor. The processor may include internal memory sufficient to store application software instructions.

[0167] Various embodiments (including but not limited to the above reference Figures 1 to 8E The described embodiments may be implemented in a variety of computing systems including a laptop computer 1000, an example of which is shown in FIG. Fig.10 Example in. refer to Figures 1 to 10, the laptop computer may include a trackpad touch surface 1017 that serves as a pointing device for the computer and, therefore, may receive drag, scroll, and tap gestures similar to those implemented on computing devices equipped with a touch screen display and as described above. The laptop computer 1000 will typically include a processor 1002 coupled to a volatile memory 1012 and a large capacity non-volatile memory, such as a hard drive 1013 of flash memory. Additionally, the computer 1000 may have one or more antennas 1008 for sending and receiving electromagnetic radiation, which may be connected to a wireless data link, and / or a cellular telephone transceiver 1016 coupled to the processor 1002. The computer 1000 may also include a floppy disk drive 1014 and a compact disk (CD) drive 1015 coupled to the processor 1002. The laptop computer 1000 may include a trackpad 1017, a keyboard 1018, and a display 1019 all coupled to the processor 1002. Other configurations of computing devices may include a computer mouse or trackball coupled to a processor (eg, via a universal serial bus (USB) input) as is well known, which may also be used in conjunction with various embodiments.

[0168] Various embodiments (including but not limited to the above reference Figures 1 to 8E The described embodiments may also be implemented in a fixed computing system, such as any of a variety of commercially available servers. Figures 1 to 11 ,exist Fig.11 An example server 1100 is illustrated in FIG. Such a server 1100 typically includes one or more multi-core processor assemblies 1101 coupled to a volatile memory 1102 and a large capacity non-volatile memory (such as a disk drive 1104). Fig.11 As illustrated, multi-core processor assemblies 1101 may be added to the server 1100 by inserting them into the assembly's chassis. The server 1100 may also include a floppy disk drive, compact disk (CD), or digital versatile disk (DVD) disk drive 1106 coupled to the processor 1101. The server 1100 may also include a network access port 1103 coupled to the multi-core processor assembly 1101 for establishing a network interface connection with a network 1105, such as a local area network coupled to other broadcast system computers and servers, the Internet, a public switched telephone network, and / or a cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, LTE, or any other type of cellular data network).

[0169] Specific implementation examples are described in the following paragraphs. Specific implementation examples described according to the example method also include: example methods implemented in circuits and processors configured with processor-executable instructions to perform the operations of the example method; example methods implemented in components for performing the functions of the method; and example methods implemented in non-transitory processor-readable storage media having processor-executable instructions stored thereon, the processor-executable instructions being configured to cause a chiplet processor to perform the operations of the example method.

[0170] Embodiment 1. A system on chip (SoC), comprising: a first chiplet, the first chiplet including a first chiplet global counter subsystem; a second chiplet, the second chiplet including a second chiplet global counter subsystem; an interface bus, the interface bus communicatively coupling the first chiplet and the second chiplet; and a power management integrated circuit (PMIC), the PMIC being configured to provide a sleep clock to the first chiplet and the second chiplet, wherein: the first chiplet is configured to transmit a global counter synchronization pulse trigger to the second chiplet across the interface bus; and the second chiplet is configured to load a global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.

[0171] Embodiment 2. An SoC according to embodiment 1, wherein: the first chiplet is further configured to: read the first chiplet global counter value from the first chiplet global counter subsystem; generate the global counter synchronization value based on the first chiplet global counter value; transmit the global counter synchronization value to the second chiplet across the interface bus; and the second chiplet is further configured to store the global counter synchronization value in a preload register, wherein the global counter synchronization value is loaded from the preload register into the second chiplet global counter subsystem.

[0172] Embodiment 3. The SoC of Embodiment 2, wherein the first chiplet global counter value is read from the first chiplet global counter subsystem at a rising edge of the sleep clock.

[0173] Embodiment 4. A SoC according to any one of embodiments 1 to 3, wherein the first chiplet is further configured to determine the sleep clock synchronization edge of the sleep clock, wherein the sleep clock synchronization edge is a rising edge of the sleep clock.

[0174] Embodiment 5. A SoC according to any one of embodiments 1 to 4, wherein the first chiplet is further configured to trigger the transmission of the global counter synchronization pulse to the second chiplet one sleep clock cycle before the sleep clock synchronization edge of the sleep clock.

[0175] Embodiment 6. A SoC according to any one of embodiments 1 to 5, wherein the first chiplet is further configured to trigger the transmission of the global counter synchronization pulse to the second chiplet at a delay time between the sleep clock synchronization edge and a sleep clock cycle before the sleep clock synchronization edge.

[0176] Embodiment 7. A SoC according to any one of embodiments 1 to 6, wherein: the first chiplet is further configured to transmit a reset assertion to the second chiplet; and the second chiplet is further configured to transmit a global counter synchronization request to the first chiplet across the interface bus in response to the reset assertion, wherein the first chiplet is configured to transmit the global counter synchronization pulse trigger to the second chiplet across the interface bus in response to the first chiplet receiving the global counter synchronization request from the second chiplet.

[0177] Embodiment 8. A SoC according to any one of embodiments 1 to 7, wherein the second chiplet is further configured to: disable a global counter pause within the global counter subsystem of the second chiplet, wherein disabling the global counter pause re-initiates counting of the second chiplet global counter within the global counter subsystem of the second chiplet; and enable a global counter synchronization path within the global counter subsystem of the second chiplet, wherein enabling the global counter synchronization path allows the first chiplet global counter subsystem to communicate with the second chiplet global counter subsystem.

[0178] Embodiment 9. An SoC according to any one of embodiments 1 to 8, wherein: the first chiplet is further configured to disable global counter pauses within the first chiplet global counter subsystem and the second chiplet global counter subsystem, wherein disabling the global counter pause re-initiates counting of the first chiplet global counter within the first chiplet global counter subsystem, and re-initiates counting of the second chiplet global counter within the second chiplet global counter subsystem; and the second chiplet is further configured to enable a global counter synchronization path within the second chiplet global counter subsystem, wherein enabling the global counter synchronization path allows the first chiplet global counter subsystem to communicate with the second chiplet global counter subsystem.

[0179] Embodiment 10. A SoC according to any one of embodiments 1 to 9, wherein the sleep clock deviation between the first chiplet and the second chiplet is equal to or less than two crystal oscillator clock cycles, and wherein the sleep clock is distributed to the first chiplet and the second chiplet in a star configuration.

[0180] Embodiment 11. The SoC according to any one of embodiments 1 to 10 further includes: a third chiplet, the third chiplet including a third chiplet global counter subsystem, wherein the interface bus communicatively couples the first chiplet and the third chiplet; and wherein: the first chiplet is further configured to transmit the global counter synchronization pulse trigger to the third chiplet across the interface bus; and the third chiplet is configured to load the global counter synchronization value into the third chiplet global counter subsystem at the sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.

[0181] Embodiment 12. The SoC according to any one of embodiments 1 to 11, wherein the interface bus is an SPMI bus.

[0182] Embodiment 13. A method for global counter synchronization within a multi-chiplet system, comprising: providing a sleep clock to a first chiplet and a second chiplet via a power management integrated circuit (PMIC); transmitting a global counter synchronization pulse trigger from the first chiplet to the second chiplet; and loading a global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to the second chiplet receiving the global counter synchronization pulse trigger.

[0183] Embodiment 14. The method according to embodiment 13 also includes: reading the first chiplet global counter value from the first chiplet global counter subsystem by the first chiplet; generating the global counter synchronization value based on the first chiplet global counter value by the first chiplet; transmitting the global counter synchronization value from the first chiplet to the second chiplet; and storing the global counter synchronization value in a preload register of the second chiplet, wherein the global counter synchronization value is loaded from the preload register into the second chiplet global counter subsystem.

[0184] Embodiment 15. The method of Embodiment 14, wherein the first chiplet global counter value is read from the first chiplet global counter subsystem at a rising edge of the sleep clock.

[0185] Embodiment 16. The method according to any one of embodiments 13 to 15 further includes: determining the sleep clock synchronization edge of the sleep clock by the first chiplet, wherein the sleep clock synchronization edge is a rising edge of the sleep clock.

[0186] Embodiment 17. The method according to any one of embodiments 13 to 16 also includes: transmitting the global counter synchronization pulse trigger from the first chiplet to the second chiplet one sleep clock cycle before the sleep clock synchronization edge of the sleep clock.

[0187] Embodiment 18. The method according to any one of Embodiments 13 to 17 further includes: triggering the transmission of the global counter synchronization pulse from the first chiplet to the second chiplet at a delay time between the sleep clock synchronization edge and a sleep clock cycle before the sleep clock synchronization edge.

[0188] Embodiment 19. The method according to any one of embodiments 13 to 18 further includes: transmitting a reset assertion from the first chiplet to the second chiplet; and transmitting a global counter synchronization request from the second chiplet to the first chiplet in response to the reset assertion, wherein the global counter synchronization pulse trigger is transmitted from the first chiplet to the second chiplet in response to the first chiplet receiving the global counter synchronization request from the second chiplet.

[0189] Embodiment 20. The method according to any one of embodiments 13 to 19 further includes: disabling, by the second chiplet, a global counter pause within the global counter subsystem of the second chiplet, wherein disabling the global counter pause re-initiates counting of the second chiplet global counter within the global counter subsystem of the second chiplet; and enabling, by the second chiplet, a global counter synchronization path within the global counter subsystem of the second chiplet, wherein enabling the global counter synchronization path allows the first chiplet global counter subsystem to communicate with the second chiplet global counter subsystem.

[0190] Embodiment 21. The method according to any one of embodiments 13 to 20 further includes: disabling the global counter pause within the first chiplet global counter subsystem and the second chiplet global counter subsystem by the first chiplet, wherein disabling the global counter pause re-initiates the counting of the first chiplet global counter within the first chiplet global counter subsystem, and re-initiates the counting of the second chiplet global counter within the second chiplet global counter subsystem; and enabling the global counter synchronization path within the second chiplet global counter subsystem by the second chiplet, wherein enabling the global counter synchronization path allows the first chiplet global counter subsystem to communicate with the second chiplet global counter subsystem.

[0191] Embodiment 22. A method for global counter synchronization implemented by a first chiplet within a multi-chiplet system, comprising: receiving a sleep clock from a power management integrated circuit (PMIC); and transmitting a global counter synchronization pulse trigger to a second chiplet; wherein the global counter synchronization pulse trigger is configured to cause the second chiplet to load a global counter synchronization value into a second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock.

[0192] Embodiment 32. The method according to embodiment 22 also includes: reading a first chiplet global counter value from a first chiplet global counter subsystem; generating the global counter synchronization value based on the first chiplet global counter value; and transmitting the global counter synchronization value to the second chiplet.

[0193] The various embodiments illustrated and described are provided merely as examples of the various features described in the claims. However, the features shown and described for any given embodiment are not necessarily limited to the associated embodiment and may be used or combined with other embodiments shown and described. Furthermore, the claims are not intended to be limited to any one exemplary embodiment.

[0194] As used in this application, the terms "component", "module", "system", etc. are intended to include computer-related entities, such as but not limited to hardware, firmware, a combination of hardware and software, software, or software being executed, which are configured to perform specific operations or functions. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, or a computer. As an example, both an application running on a wireless device and a wireless device can be referred to as a component. One or more components may reside within a process or a thread of execution, and the component may be localized on a processor or core or distributed between two or more processors or cores. In addition, these components may be executed from various non-transient computer-readable media having various instructions or data structures stored thereon. Each component may communicate via local and / or remote processes, function or procedure calls, electronic signals, data packets, memory read / write, and other known network, computer, processor, or process-related communication methodologies.

[0195] Several different cellular and mobile communication services and standards are available and contemplated in the future, all of which may be implemented and benefit from various specific implementations. Such services and standards include, for example, the 3rd Generation Partnership Project (3GPP), Long Term Evolution (LTE) system, 3rd Generation wireless mobile communication technology (3G), 4th Generation wireless mobile communication technology (4G), 5th Generation wireless mobile communication technology (5G), Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), 3GSM, General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA) systems (such as cdmaOne, CDMA1020TM), Enhanced Data Rates for GSM Evolution (EDGE), Advanced Mobile Phone System (AMPS), Digital AMPS (IS-136 / TDMA), Evolution Data Optimized (EV-DO), Digital Enhanced Cordless Telecommunications (DECT), Worldwide Interoperability for Microwave Access (WiMAX), Wireless Local Area Network (WLAN), Wi-Fi Protected Access I and II (WPA, WPA2), and Integrated Digital Enhanced Network (iDEN). Each of these technologies involves, for example, the transmission and reception of voice, data, signaling, or content messages. It should be understood that any reference to terminology or technical details related to individual telecommunication standards or technologies is for illustrative purposes only and is not intended to limit the scope of the claims to a particular communication system or technology unless expressly stated in the claim language.

[0196] The various implementations illustrated and described are provided merely as examples of the various features described in the claims. However, the features shown and described for any given implementation are not necessarily limited to the associated implementation, and may be used or combined with other implementations shown and described. Furthermore, the claims are not intended to be limited to any one example implementation. For example, one or more operations of the methods disclosed herein may replace or be combined with one or more operations of the methods disclosed herein.

[0197] The above method descriptions and process flow diagrams are provided only as illustrative examples and are not intended to require or imply that the blocks of the various embodiments must be executed in the order given. As will be appreciated by those skilled in the art, the order of the blocks in the aforementioned embodiments may be executed in any order. Words such as "thereafter", "then", "next", etc. are not intended to limit the order of the blocks; these words are only used to guide the reader to read the description of the method. In addition, any reference to a claim element in singular form (e.g., a reference using the article "a", "an", or "the") should not be interpreted as limiting the element to the singular.

[0198] The various exemplary logic blocks, modules, circuits, and algorithm blocks described in conjunction with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or a combination of the two. To clearly illustrate this interchangeability of hardware and software, various exemplary components, blocks, modules, circuits, and blocks are generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. The technician may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as departing from the scope of the various embodiments.

[0199] The hardware for implementing the various illustrative logics, logic blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed using a general purpose single-chip or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration. In some specific implementations, specific processes and methods may be performed by circuits specific to a given function.

[0200] In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents, or in any combination thereof. Specific implementations of the subject matter described in this specification may also be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on computer storage media for execution by data processing apparatus or for controlling the operation of data processing apparatus.

[0201] Computer program code or "program code" for execution on a programmable processor to perform the operations of the various embodiments may be written in a high-level programming language (such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic), a structured query language (e.g., Transact-SQL), Perl, or in various other programming languages. Program code or program stored on a computer-readable storage medium as used in this application may refer to machine language code (such as object code) in a format that can be understood by a processor.

[0202] In various embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, these functions may be stored as one or more instructions or codes on a non-transient computer-readable medium or a non-transient processor-readable medium. The operation of the method or algorithm disclosed herein may be embodied in a processor-executable software module, which may reside on a non-transient computer-readable or processor-readable storage medium. A non-transient computer-readable or processor-readable storage medium may be any storage medium accessible by a computer or processor. By way of example and not limitation, such a non-transient computer-readable or processor-readable medium may include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disk storage device, disk storage device or other magnetic storage device, or any other medium that may be used to store a desired program code in the form of an instruction or data structure and accessible by a computer. Disks and optical disks as used herein include compact discs (CDs), laser discs, optical disks, digital versatile discs (DVDs), floppy disks, and blue discs, wherein disks generally magnetically replicate data, and optical disks optically replicate data with lasers. The above combination is also included within the scope of non-transient computer-readable and processor-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and / or instructions on a non-transitory processor-readable medium and / or computer-readable medium, which may be incorporated into a computer program product.

[0203] Various modifications to the specific implementations described in this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other specific implementations without departing from the spirit or scope of the disclosure. Therefore, the claims are not intended to be limited to the specific implementations shown herein, but should be given the widest scope consistent with the disclosure, the principles and novel features disclosed herein.

[0204] Certain features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, individual features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable subcombination. Furthermore, while some features are described above as working in a particular combination and even initially claimed as such, in some cases one or more features from a claimed combination may be cut out of the combination, and a claimed combination may be directed to a subcombination or a variation of a subcombination.

[0205] Similarly, although the operations are depicted in a specific order in the figure, this should not be understood as requiring such operations to be performed in the specific order shown or in a sequential order, or to perform all illustrated operations to achieve the desired result. In addition, the accompanying drawings may schematically depict one or more example processes in the form of a flow chart. However, other operations not depicted can be incorporated into the example processes schematically illustrated. For example, one or more additional operations can be performed before, after, at the same time, or between any operations in the illustrated operations. In some cases, multitasking and parallel processing are advantageous. In addition, the separation of each system component in the specific implementation described above should not be understood as requiring such separation in all specific implementations, but it should be understood that the described program components and systems can usually be integrated together in a single software product, or be packaged in multiple software products. Additionally, other specific implementations are within the scope of the following claims. In some cases, the actions recorded in the claims can be performed in different orders and still achieve the desired result.

[0206] The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the embodiments of the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the scope of the embodiments. Thus, the various embodiments are not intended to be limited to the embodiments shown herein, but should be given the widest scope consistent with the following claims and the principles and novel features disclosed herein.

Claims

1. A system on chip SoC, comprising: a first chiplet, the first chiplet comprising a first chiplet global counter subsystem; a second chiplet, the second chiplet comprising a second chiplet global counter subsystem; an interface bus communicatively coupling the first chiplet and the second chiplet; and a power management integrated circuit (PMIC) configured to provide a sleep clock to the first chiplet and the second chiplet, wherein: the first chiplet being configured to transmit a global counter sync pulse trigger to the second chiplet across the interface bus one sleep clock cycle prior to a sleep clock sync edge of the sleep clock; and The second chiplet is configured to load a global counter synchronization value into the second chiplet global counter subsystem at the sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.

2. The SoC according to claim 1, wherein: The first chiplet is further configured as: reading a first chiplet global counter value from said first chiplet global counter subsystem; generating the global counter synchronization value based on the first chiplet global counter value; transmitting the global counter synchronization value to the second chiplet across the interface bus; and The second chiplet is further configured to store the global counter synchronization value in a preload register, wherein the global counter synchronization value is loaded from the preload register into the second chiplet global counter subsystem.

3. The SoC of claim 2, wherein the first chiplet global counter value is read from the first chiplet global counter subsystem at a rising edge of the sleep clock.

4. The SoC of claim 1 , wherein the first chiplet is further configured to determine the sleep clock synchronization edge of the sleep clock, wherein the sleep clock synchronization edge is a rising edge of the sleep clock.

5. The SoC of claim 1 , wherein the first chiplet is further configured to trigger transmission of the global counter synchronization pulse to the second chiplet at a delay time between the sleep clock synchronization edge and one sleep clock cycle before the sleep clock synchronization edge.

6. The SoC according to claim 1, wherein: The first chiplet is further configured to transmit a reset assertion to the second chiplet; and The second chiplet is further configured to transmit a global counter synchronization request to the first chiplet across the interface bus in response to the reset assertion, Wherein the first chiplet is configured to transmit the global counter synchronization pulse trigger to the second chiplet across the interface bus in response to the first chiplet receiving the global counter synchronization request from the second chiplet.

7. The SoC of claim 1 , wherein the second chiplet is further configured to: disabling a global counter pause within the second chiplet global counter subsystem, wherein disabling the global counter pause re-initiates counting of a second chiplet global counter within the second chiplet global counter subsystem; and A global counter synchronization path within the second chiplet global counter subsystem is enabled, wherein enabling the global counter synchronization path allows the first chiplet global counter subsystem to communicate with the second chiplet global counter subsystem.

8. The SoC according to claim 1, wherein: The first chiplet is further configured to disable global counter pauses within the first chiplet global counter subsystem and the second chiplet global counter subsystem, wherein disabling the global counter pause re-initiates counting of the first chiplet global counter within the first chiplet global counter subsystem and re-initiates counting of the second chiplet global counter within the second chiplet global counter subsystem; and The second chiplet is further configured to enable a global counter synchronization path within the second chiplet global counter subsystem, wherein enabling the global counter synchronization path allows the first chiplet global counter subsystem to communicate with the second chiplet global counter subsystem.

9. The SoC of claim 1 , wherein a sleep clock deviation between the first chiplet and the second chiplet is equal to or less than two crystal oscillator clock periods, and wherein the sleep clock is distributed to the first chiplet and the second chiplet in a star configuration.

10. The SoC according to claim 1, further comprising: a third chiplet, the third chiplet comprising a third chiplet global counter subsystem, wherein the interface bus communicatively couples the first chiplet and the third chiplet, in: The first chiplet is further configured to transmit the global counter synchronization pulse trigger to the third chiplet across the interface bus; and The third chiplet is configured to load the global counter sync value into the third chiplet global counter subsystem at the sleep clock sync edge of the sleep clock in response to receiving the global counter sync pulse trigger. 11 . The SoC according to claim 1 , wherein the interface bus is a System Power Management Interface (SPMI) bus.

12. A method for global counter synchronization in a multi-chiplet system, comprising: providing a sleep clock to the first chiplet and the second chiplet via a power management integrated circuit PMIC; transmitting a global counter sync pulse trigger from the first chiplet to the second chiplet at a delay time between a sleep clock sync edge and one sleep clock cycle before the sleep clock sync edge; as well as A global counter synchronization value is loaded into a second chiplet global counter subsystem at the sleep clock synchronization edge of the sleep clock in response to the second chiplet receiving the global counter synchronization pulse trigger.

13. The method according to claim 12, further comprising: reading, by the first chiplet, a first chiplet global counter value from a first chiplet global counter subsystem; generating, by the first chiplet, the global counter synchronization value based on the first chiplet global counter value; transferring the global counter synchronization value from the first chiplet to the second chiplet; as well as The global counter synchronization value is stored in a preload register of the second chiplet, wherein the global counter synchronization value is loaded from the preload register into the second chiplet global counter subsystem.

14. The method of claim 13, wherein the first chiplet global counter value is read from the first chiplet global counter subsystem at a rising edge of the sleep clock.

15. The method according to claim 12, further comprising: The sleep clock synchronization edge of the sleep clock is determined by the first chiplet, wherein the sleep clock synchronization edge is a rising edge of the sleep clock.

16. The method according to claim 12, further comprising: The global counter sync pulse trigger is transmitted from the first chiplet to the second chiplet one sleep clock cycle before the sleep clock sync edge of the sleep clock.

17. The method according to claim 12, further comprising: transmitting a reset assertion from the first chiplet to the second chiplet; as well as transmitting a global counter synchronization request from the second chiplet to the first chiplet in response to the reset assertion, wherein transmitting the global counter synchronization pulse trigger from the first chiplet to the second chiplet is in response to the first chiplet receiving the global counter synchronization request from the second chiplet.

18. The method according to claim 12, further comprising: disabling, by the second chiplet, a global counter pause within the second chiplet global counter subsystem, wherein disabling the global counter pause re-initiates counting of a second chiplet global counter within the second chiplet global counter subsystem; as well as A global counter synchronization path within the second chiplet global counter subsystem is enabled by the second chiplet, wherein enabling the global counter synchronization path allows the first chiplet global counter subsystem to communicate with the second chiplet global counter subsystem.

19. The method according to claim 12, further comprising: disabling, by the first chiplet, a global counter pause within a first chiplet global counter subsystem and a second chiplet global counter subsystem, wherein disabling the global counter pause re-initiates counting of a first chiplet global counter within the first chiplet global counter subsystem and re-initiates counting of a second chiplet global counter within the second chiplet global counter subsystem; as well as A global counter synchronization path within the second chiplet global counter subsystem is enabled by the second chiplet, wherein enabling the global counter synchronization path allows the first chiplet global counter subsystem to communicate with the second chiplet global counter subsystem.

20. A system on chip (SoC), comprising: a first chiplet, the first chiplet comprising a first chiplet global counter subsystem; a second chiplet, the second chiplet comprising a second chiplet global counter subsystem; means for providing a sleep clock to the first chiplet and the second chiplet; means for transmitting a global counter sync pulse trigger from the first chiplet to the second chiplet one sleep clock cycle prior to a sleep clock sync edge of the sleep clock; and means for loading a global counter synchronization value into the second chiplet global counter subsystem at the sleep clock synchronization edge of the sleep clock in response to the second chiplet receiving the global counter synchronization pulse trigger.

21. The SoC according to claim 20, further comprising: means for reading a first chiplet global counter value from said first chiplet global counter subsystem; means for generating the global counter synchronization value based on the first chiplet global counter value; means for transmitting the global counter synchronization value from the first chiplet to the second chiplet; and means for storing the global counter synchronization value in a preload register of the second chiplet, wherein the global counter synchronization value is loaded from the preload register into the second chiplet global counter subsystem.

22. The SoC of claim 21 , wherein the first chiplet global counter value is read from the first chiplet global counter subsystem at a rising edge of the sleep clock.

23. The SoC according to claim 20, further comprising: Means for determining the sleep clock synchronization edge of the sleep clock, wherein the sleep clock synchronization edge is a rising edge of the sleep clock.

24. The SoC according to claim 20, further comprising: means for transmitting the global counter sync pulse trigger from the first chiplet to the second chiplet at a delay time between the sleep clock sync edge and one sleep clock cycle before the sleep clock sync edge.

25. The SoC according to claim 20, further comprising: means for transmitting a reset assertion from the first chiplet to the second chiplet; as well as means for transmitting a global counter synchronization request from the second chiplet to the first chiplet in response to the reset assertion, Wherein the means for transmitting the global counter synchronization pulse trigger from the first chiplet to the second chiplet is responsive to the first chiplet receiving the global counter synchronization request from the second chiplet.

26. The SoC according to claim 20, further comprising: means for disabling a global counter pause within the second chiplet global counter subsystem, wherein disabling the global counter pause re-initiates counting of a second chiplet global counter within the second chiplet global counter subsystem; as well as means for enabling a global counter synchronization path within the second chiplet global counter subsystem, wherein enabling the global counter synchronization path allows the first chiplet global counter subsystem to communicate with the second chiplet global counter subsystem.

27. The SoC according to claim 20, further comprising: means for disabling global counter pauses within the first chiplet global counter subsystem and the second chiplet global counter subsystem, wherein disabling the global counter pause re-initiates counting of a first chiplet global counter within the first chiplet global counter subsystem and re-initiates counting of a second chiplet global counter within the second chiplet global counter subsystem; as well as means for enabling a global counter synchronization path within the second chiplet global counter subsystem, wherein enabling the global counter synchronization path allows the first chiplet global counter subsystem to communicate with the second chiplet global counter subsystem.

28. A method for global counter synchronization implemented by a first chiplet in a multi-chiplet system, comprising: receiving a sleep clock from a power management integrated circuit PMIC; as well as transmitting a global counter sync pulse trigger to a second chiplet one sleep clock cycle before a sleep clock sync edge of the sleep clock, wherein the second chiplet receives the sleep clock from the PMIC; Wherein the global counter sync pulse trigger is configured to cause the second chiplet to load a global counter sync value into a second chiplet global counter subsystem at the sleep clock sync edge of the sleep clock.

29. The method according to claim 28, further comprising: reading a first chiplet global counter value from a first chiplet global counter subsystem; generating the global counter synchronization value based on the first chiplet global counter value; as well as The global counter synchronization value is transmitted to the second chiplet.

30. A system on chip (SoC), comprising: a first chiplet, the first chiplet comprising a first chiplet global counter subsystem; a second chiplet, the second chiplet comprising a second chiplet global counter subsystem; an interface bus communicatively coupling the first chiplet and the second chiplet; and a power management integrated circuit (PMIC) configured to provide a sleep clock to the first chiplet and the second chiplet, The first chiplet is configured as: receiving a sleep clock from the PMIC; and A global counter sync pulse trigger is transmitted to the second chiplet one sleep clock cycle before a sleep clock sync edge of the sleep clock, and the global counter sync pulse trigger is configured to cause the second chiplet to load a global counter sync value into a second chiplet global counter subsystem at the sleep clock sync edge of the sleep clock.

31. The SoC of claim 30, wherein the first chiplet is further configured to: reading a first chiplet global counter value from a first chiplet global counter subsystem; generating the global counter synchronization value based on the first chiplet global counter value; and The global counter synchronization value is transmitted to the second chiplet.

Images