Display panel, display screen and electronic device

Abstract

The present disclosure relates to a display panel, a display area of the display panel has a middle area and an edge area located outside the middle area, the display panel comprises a plurality of data lines, a plurality of first power signal lines and a plurality of second power signal lines located in the display area, wherein each data line located in the edge area is led to the middle area through a signal trace, at least part of the signal trace corresponds to the position of the first power signal line, the conductive layer where the signal trace is located further comprises a dummy pattern, the dummy pattern is arranged separately from the signal trace, and at least part of the dummy pattern is electrically connected with the second power signal line.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel, display screen, and electronic device. Background Technology

[0002] With the development of technology, terminal devices have become an indispensable part of people's daily lives. While users are pursuing better display effects for terminal devices, their requirements for screen-to-body ratio are also increasing. Currently, narrow bezels on the left and right sides of display panels have been achieved, but the bottom bezel is still relatively wide due to the influence of data cable windings and the area where control chips are bonded. Summary of the Invention

[0003] To overcome the problems existing in the related technologies, this disclosure provides a display panel, a display screen, and an electronic device.

[0004] According to a first aspect of this disclosure, a display panel is provided. The display panel has a central region and an edge region located outside the central region. The display panel includes multiple data lines, multiple first power signal lines, and multiple second power signal lines located in the display region. Each data line located in the edge region is connected to the central region via a signal trace. At least a portion of the signal traces correspond to the positions of the first power signal lines. The conductive layer containing the signal traces further includes a dummy pattern, which is spaced apart from the signal traces.

[0005] At least a portion of the dummy pattern is electrically connected to the second power signal line.

[0006] In some embodiments of this disclosure, the display panel includes a first conductive layer, a second conductive layer, and a third conductive layer stacked together.

[0007] The data lines are located in the first conductive layer and extend along the first direction. The multiple data lines are arranged at intervals along the second direction, and the first direction and the second direction are set at an angle.

[0008] Each of the signal traces includes a first signal trace extending along the second direction and a second signal trace extending along the first direction. The first signal trace is located in the second conductive layer, and the second signal trace is located in the third conductive layer. The first end of the first signal trace is located in the edge region and is connected to the corresponding data line through a first connection hole. The second end of both the first and second signal traces is located in the central region. The second end of the first signal trace is connected to the second signal trace through a second connection hole.

[0009] In some embodiments of this disclosure, the dummy pattern includes multiple first dummy electrode lines and multiple second dummy electrode lines, wherein,

[0010] The plurality of first dummy electrode lines are located in the second conductive layer and form a first pattern evenly distributed in the display area together with the first signal traces;

[0011] The plurality of second dummy electrode lines are located on the third conductive layer and together with the second signal traces form a second pattern evenly distributed in the display area.

[0012] In some embodiments of this disclosure, the plurality of second power signal lines are all connected to a second power signal bus, the second power signal bus is located in the second conductive layer, and at least a portion of the first dummy electrode lines are connected to the second power signal bus.

[0013] In some embodiments of this disclosure, the second power signal bus extends along the first direction, and in the second direction, the second power signal bus is located in a non-display area outside the display area, and the plurality of first dummy electrode lines include:

[0014] The first dummy sub-electrode line is collinear with the first signal trace and located between the first signal trace and the second power signal bus.

[0015] The second dummy sub-electrode line is collinear with the first signal trace and located on the side of the first signal trace away from the second power signal bus;

[0016] The third dummy sub-electrode line is parallel to the first signal trace;

[0017] Both the first dummy sub-electrode line and the third dummy sub-electrode line are connected to the second power signal bus, and the second dummy sub-electrode line is connected to the first dummy sub-electrode line, the third dummy sub-electrode line, or the second dummy sub-electrode line through a connection structure.

[0018] In some embodiments of this disclosure, the plurality of first power signal lines are located in the first conductive layer, and the first power signal lines and the data lines are arranged alternately along the second direction;

[0019] A portion of the second dummy electrode lines and a portion of the second signal traces correspond to the data line positions in the central region, while another portion of the second dummy electrode lines and another portion of the second signal traces correspond to the first power signal line positions in the central region.

[0020] In some embodiments of this disclosure, each of the second dummy electrode lines is connected to the intersecting first dummy electrode lines via a third connecting hole; or,

[0021] A portion of the second dummy electrode line is connected to the intersecting first dummy electrode line through a third connection hole, and another portion of the second dummy electrode line is connected to the first power signal line through a fourth connection hole.

[0022] In some embodiments of this disclosure, the second dummy electrode lines connected to the first dummy electrode line and the second dummy electrode lines connected to the first power signal line are alternately arranged along the second direction.

[0023] In some embodiments of this disclosure, the plurality of second dummy electrode lines include a fourth dummy sub-electrode line collinear with the second signal trace and a fifth dummy sub-electrode line parallel to the second signal trace, and the second dummy sub-electrode line in the first dummy electrode line is connected to the fourth dummy sub-electrode line through a connection structure.

[0024] In some embodiments of this disclosure, the second dummy sub-electrode line is provided with the connection structure near the endpoint of the collinear first signal trace.

[0025] According to a second aspect of this disclosure, a display screen is provided, including a display panel as described in the first aspect.

[0026] According to a third aspect of this disclosure, an electronic device is provided, including a display screen as described in the second aspect.

[0027] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: by electrically connecting at least a portion of the dummy pattern to the second power signal line, the at least portion of the dummy pattern is equivalent to the second power signal line, thereby reducing the coupling capacitance between the data line and the first power signal line, reducing the voltage fluctuation amplitude of the first power signal line when the data line signal jumps, thereby improving signal crosstalk and improving the display effect of the display panel.

[0028] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0030] Figure 1 This is a schematic diagram of the structure of a display panel.

[0031] Figure 2 It is a voltage change graph of a display panel.

[0032] Figure 3 This is a schematic diagram of the structure of a display panel according to an exemplary embodiment.

[0033] Figure 4 This is a partial cross-sectional view of a display panel along the AA direction, according to an exemplary embodiment.

[0034] Figure 5 This is a top view of the second conductive layer according to an exemplary embodiment.

[0035] Figure 6 This is a top view of the third conductive layer according to an exemplary embodiment.

[0036] Figure 7 This is a partial cross-sectional view of a display panel along the BB direction, according to an exemplary embodiment.

[0037] Figure 8 This is a top view of the first conductive layer according to an exemplary embodiment.

[0038] Figure 9 This is a partial cross-sectional view of a display panel along the CC direction, according to an exemplary embodiment.

[0039] Figure 10 This is a schematic diagram of the layout of a display panel according to an exemplary embodiment.

[0040] Figure 11 This is a partial cross-sectional view of a display panel along the CC direction, according to an exemplary embodiment.

[0041] Figure 12 This is a schematic diagram of the layout of a display panel according to an exemplary embodiment.

[0042] Figure 13 This is a partial cross-sectional view of a display panel along the DD direction, according to an exemplary embodiment. Detailed Implementation

[0043] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0044] Currently, narrow bezels on the left and right sides of display panels have been achieved, but the bottom bezel remains relatively wide due to the data cable routing and the area where the control chip is bonded. To reduce the width of the bottom edge of the display area, flexible panels are typically used, and the area on the flexible panel where the chip and control chip are bonded is bent to the back of the display panel, reducing some of the bottom bezel space. However, the bottom bezel is still relatively wide.

[0045] To further reduce the width of the bottom edge of the display area and achieve a design with equal width on all four sides, related technologies involve routing the data cable within the display area, reducing the height of the fanout area, and thus decreasing the width of the bottom edge of the display area. See [link to related technology]. Figure 1 As shown, in the display panel 100, the data line 3 (Data) of the edge area 2 of the display area is routed to the central area 1 of the display area via a connected first signal trace 61 and a second signal trace 62. The first signal trace 61 is connected to the data line 3, and the second signal trace 62 is bonded to the driver IC in the Bending Area of ​​the edge of the display panel 100, thereby reducing the width of the lower edge of the display area. Simultaneously, to avoid differences in reflectivity of the display panel 100 when the screen is off due to differences in metal density, a dummy pattern 7 is provided in the conductive layer where the first signal trace 61 and the second signal trace 62 are located. The dummy pattern 7 is connected to the VDD line.

[0046] However, since the second signal trace 62, which is partially connected to data line 3, is located above the VDD line, there is a coupling capacitance between signal trace 6 and the VDD line. This results in a coupling capacitance between data line 3 and the VDD line. Furthermore, the dummy pattern 7 is also connected to the VDD line, thus acting as a VDD line. This further increases the coupling capacitance between the dummy pattern 7 and the second signal trace 62, thus increasing the coupling capacitance between the VDD line and data line 3. (See also...) Figure 2As shown, when the signal on data line 3 changes, the signal trace 6 connected to data line 3 also changes. The voltage of the VDD line fluctuates synchronously due to the influence of the coupling capacitor. Because the power IC is farther away from the display panel 100, the voltage fluctuation is more severe at the far end than at the near end, resulting in severe signal crosstalk. This manifests on the display panel 100 as a bright or dark line appearing at the junction of black and white blocks, affecting the display effect.

[0047] Based on this, the present disclosure provides a display panel with a display area having a central region and an edge region located outside the central region. The display panel includes multiple data lines, multiple first power signal lines, and multiple second power signal lines located in the display area. Each data line located in the edge region is led to the central region through a signal trace. At least a portion of the signal trace corresponds to the position of the first power signal line. The conductive layer containing the signal trace also includes a dummy pattern, which is separated from the signal trace. At least a portion of the dummy pattern is electrically connected to the second power signal lines. By electrically connecting at least a portion of the dummy pattern to the second power signal lines, the coupling capacitance between the data lines and the first power signal lines is reduced, thereby weakening signal crosstalk.

[0048] Figure 3 This is a schematic diagram illustrating the structure of a display panel according to an exemplary embodiment, such as... Figure 3 As shown, an exemplary embodiment of this disclosure provides a display panel 100. The display area of ​​the display panel 100 has a central region 1 and an edge region 2 located outside the central region 1. The display panel 100 includes multiple data lines 3, multiple first power signal lines 4, and multiple second power signal lines 5 located in the display area. Each data line 3 located in the edge region 2 is led to the central region 1 through a signal trace 6. At least a portion of the signal trace 6 corresponds to the position of the first power signal line 4. The conductive layer where the signal trace 6 is located also includes a dummy pattern 7. The dummy pattern 7 is separated from the signal trace 6. At least a portion of the dummy pattern 7 is electrically connected to the second power signal line 5.

[0049] In this embodiment, the display area refers to the image display area of ​​the display panel 100, and the Bending Area is a region of the non-display area of ​​the display panel 100. Multiple data lines 3 in the display area form a bending connection with the driver IC in the Bending Area. The driver IC inputs control signals to the data lines 3 to control the array of pixels in the display area, thereby achieving image formation on the display panel 100. The display panel 100 can be a flexible display panel, which can be bent and folded, allowing the non-display area to be bent to the back of the display area.

[0050] The display panel 100 includes multiple data lines 3, multiple first power signal lines 4, and multiple second power signal lines 5 located in the display area. The data lines 3 transmit data signals. The multiple data lines 3 intersect and are insulated from multiple scan lines (not shown in the figure). Each intersection of a data line 3 and a scan line defines a sub-pixel, thus forming a pixel array. Various control signals related to the Bending Area scan drive are transmitted to the data lines 3 and the scan lines. The data lines 3 drive transistors to emit light according to the data signals, causing the display area of ​​the display panel 100 to display a target image. The first power signal lines 4 can be VDD power signal lines, i.e., power signal lines connected to the drain of transistors, providing drain voltage to the transistors. The second power signal lines 5 can be VSS power signal lines, i.e., power signal lines connected to the source of transistors, providing source voltage to the transistors.

[0051] The display panel 100 has a central region 1 and an edge region 2 located outside the central region 1. The Bending Area is located in the central region 1 near the display area to facilitate the transmission of control signals to the data lines 3 and scan lines. Since multiple data lines 3 are arranged in a certain pattern in the display area of ​​the display panel 100, and the wiring area of ​​the data lines 3 in the display area is larger than the area where the Bending Area is located, when the data lines 3 are connected from the display area to the Bending Area, it is necessary to concentrate the relatively dispersed data lines 3. Therefore, the data lines 3 in the central region 1 can form a connection with the driver IC in the Bending Area, and each data line 3 located in the edge region 2 is led to the central region 1 through a signal trace 6 and connected to the driver IC in the Bending Area, thereby realizing the transmission of data signals of the data lines 3 in the edge region 2.

[0052] In some embodiments, a portion of the signal traces 6 corresponds to the position of the first power signal line 4. That is, the projection of a portion of the signal traces 6 coincides with the first power signal line 4, and the routing direction and line shape of the portion of the signal traces 6 corresponding to the position of the first power signal line 4 are consistent with the first power signal line 4, so as to improve the uniformity of the structural performance and display performance of the display panel 100 and reduce the reflectivity difference.

[0053] In other embodiments, the signal traces 6 may also correspond entirely to the positions of the first power signal line 4, in order to further improve the structural performance and display performance uniformity of the display panel 100 and reduce reflectivity differences.

[0054] To ensure the structural and electrical performance of the display panel 100 and avoid differences in screen-off reflectivity caused by variations in metal density and film thickness, a dummy pattern 7 is provided in the conductive layer where the signal trace 6 is located in the display panel 100 provided in this embodiment. The dummy pattern 7 is separated from the signal trace 6 and is insulated from it, and is not used to transmit electrical signals to the signal trace 6. The dummy pattern 7 improves the reflectivity differences caused by variations in metal density and film thickness in certain areas of the display area where the signal trace 6 is located, thereby improving the screen color uniformity of the display panel 100 in the screen-off state.

[0055] In some embodiments, at least a portion of the dummy pattern 7 is electrically connected to the second power signal line 5. The portion of the dummy pattern 7 is equivalent to a VSS line. Compared with the prior art, the coupling capacitance between the data line 3 and the first power signal line 4 is reduced, thereby reducing the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal jumps, thus improving signal crosstalk and achieving a good display effect of the display panel 100.

[0056] In other embodiments, all dummy patterns 7 may be electrically connected to the second power signal line 5. All dummy patterns 7 are VSS lines to further reduce the coupling capacitance between the data line 3 and the first power signal line 4, further reduce the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal changes, weaken signal crosstalk, and improve the display effect of the display panel 100.

[0057] It should be noted that, due to the large number of signal lines, in order to Figure 3 The signal lines can be clearly shown in the image. Figure 3 Only the lower part of the display panel 100 is shown; the data cable 3 is... Figure 3 The data lines 3 in the central area 1 are shown in solid lines, with only two data lines 3 shown as an example, and four data lines 3 shown in each of the edge areas 2 on both sides of the display area; only two first power signal lines 4 are shown as an example; only two second power signal lines 5 are shown as an example; and only four signal traces 6 are shown as an example. In actual design and production, the data lines 3, first power signal lines 4, and second power signal lines 5 are distributed throughout the display panel 100 according to a preset rule, and the signal traces 6 are also set in multiples according to the number of data lines 3 in the edge areas 2. In addition, the data lines 3 are shown in solid lines, and the dummy pattern 7 is shown in dashed lines. The solid and dashed lines are not the actual form of the signal lines, but are only for the purpose of differentiation. The actual form of the multiple data lines 3, multiple first power signal lines 4, multiple second power signal lines 5, multiple signal traces 6, and the dummy pattern 7 are strip-shaped metal lines, which serve to transmit data and electrical signals.

[0058] For example, data line 3 can be a data line in the circuit design, first power signal line 4 can be a VDD line in the circuit design, second power signal line 5 can be a VSS line in the circuit design, signal trace 6 can be an SD line (Source & Drain line) in the circuit design, and dummy pattern 7 can be a dummy pattern in the circuit design.

[0059] In this embodiment, multiple data lines 3, multiple first power signal lines 4, multiple second power signal lines 5, multiple signal traces 6, and a dummy pattern 7 are mutually insulated in the display area of ​​the display panel 100. The arrangement of these multiple data lines 3, multiple first power signal lines 4, multiple second power signal lines 5, multiple signal traces 6, and the dummy pattern 7 can be patterned on the initial substrate of the display panel 100 according to a specific application layout. Then, the multiple lines are formed on the initial substrate according to the pattern design. For example, material forming techniques can be used to form them on the initial substrate, such as chemical vapor deposition, electroless plating, electrolytic plating, printing, spin coating, spraying, sputtering, or vacuum deposition. The materials for these multiple lines can be conductive materials such as copper, aluminum, or tungsten. The materials for these multiple lines can be the same or different; this disclosure does not impose any limitations on this.

[0060] In one exemplary embodiment, combined with Figure 3 and Figure 4 As shown, the display panel 100 includes a first conductive layer 10, a second conductive layer 20, and a third conductive layer 30 stacked together. Data lines 3 are located on the first conductive layer 10 and extend along a first direction. Multiple data lines 3 are arranged at intervals along a second direction, with the first direction and the second direction forming an angle. Each signal trace 6 includes a first signal trace 61 extending along the second direction and a second signal trace 62 extending along the first direction. The first signal trace 61 is located on the second conductive layer 20, and the second signal trace 62 is located on the third conductive layer 30. The first end of the first signal trace 61 is located in the edge region 2 and is connected to the corresponding data line 3 through a first connection hole 91. The second end of the first signal trace 61 and the second signal trace 62 are both located in the central region 1, and the second end of the first signal trace 61 is connected to the second signal trace 62 through a second connection hole 92.

[0061] In this embodiment, the first conductive layer 10, the second conductive layer 20, and the third conductive layer 30 can be separated by an insulating layer, which is an insulating material. Data lines 3 are located on the first conductive layer 10. Data lines 3 can be formed on the first conductive layer 10 using a material forming technique. The data lines 3 extend along a first direction on the first conductive layer 10, and multiple data lines 3 are spaced apart along a second direction, such that the multiple data lines 3 are mutually insulated. The first direction can be... Figure 3 The Y direction in the middle, the second direction can be Figure 3 In the X direction, the first direction and the second direction are set at an angle, and the angle between the first direction and the second direction can be 90°, so that the multiple data lines 3 do not intersect each other, and the multiple data lines 3 transmit different display content data to realize the display imaging of the display panel 100.

[0062] Each signal trace 6 includes a first signal trace 61 extending along the X direction and a second signal trace 62 extending along the Y direction. The first signal trace 61 is located on the second conductive layer 20, and the second signal trace 62 is located on the third conductive layer 30. The first signal trace 61 and the second signal trace 62 can be formed on the second conductive layer 20 and the third conductive layer 30 respectively by material forming technology. The first signal trace 61 and the second signal trace 62 are located on different conductive layers, which makes the wiring of the display panel 100 reasonable and compact, improving production efficiency while enhancing the uniformity of the display performance of the display panel 100. For example, the first signal trace 61 can be SD1 line in the circuit design, and the second signal trace 62 can be SD2 line in the circuit design.

[0063] Because multiple data lines 3 are provided in the edge area 2 of the display area, each data line 3 is led to the central area 1 through a corresponding first signal trace 61 and second signal trace 62. See also Figure 4 , Figure 4 An exemplary illustration shows a display panel 100 along... Figure 3A partial cross-sectional view of a data line 3 located in the edge region 2, and the first signal trace 61 and the second signal trace 62 connected to it, cut along the AA direction. The first end of the first signal trace 61 is located in the edge region 2 and is connected to the corresponding data line 3 through a first connection hole 91. The first connection hole 91 can be formed by etching an insulating layer between the first conductive layer 10 and the second conductive layer 20 to form a via, and then filling the via with conductive material by deposition to form a conductive via, so that electrical signals can be transmitted between the data line 3 and the first signal trace 61. The second end of the first signal trace 61 and the second signal trace 62 are both located in the middle region 1. The second end of the first signal trace 61 is connected to the second signal trace 62 through the second connection hole 92. The second connection hole 92 is formed in the insulating layer between the second conductive layer 20 and the third conductive layer 30, and its formation method can be the same as the formation method of the first connection hole 91, so that electrical signals can be transmitted between the first signal trace 61 and the second signal trace 62. The data line 3 located in the edge area 2 is connected to the first signal line 61 through the first connection hole 91. The first signal line 61 is then connected to the second signal line 62 located in the middle area 1 through the second connection hole 92, so that the data line 3 in the edge area 2 can be connected to the Bending Area, realizing the transmission of electrical signals between the data line 3 and the driver IC, so that the display panel 100 has a good imaging effect.

[0064] For example, the first direction can also be Figure 3 The X direction in the equation, the second direction can be... Figure 3 The Y direction, or the first direction, can also be Figure 3 The first signal trace 61 can be a direction between the X and Y directions, and the second signal trace 62 can be a direction that forms a 90° angle with the first signal trace 62. This disclosure does not impose any restrictions on this, as long as the multiple data lines 3 do not intersect each other and are mutually insulated, and the first signal trace 61 and the second signal trace 62 are set accordingly.

[0065] In an exemplary embodiment, the dummy pattern 7 includes a plurality of first dummy electrode lines 71 and a plurality of second dummy electrode lines 72, wherein the plurality of first dummy electrode lines 71 are located in the second conductive layer 20 and form a first pattern evenly distributed in the display area with the first signal trace 61; the plurality of second dummy electrode lines 72 are located in the third conductive layer 30 and form a second pattern evenly distributed in the display area with the second signal trace 62.

[0066] In this embodiment, the dummy pattern 7 includes multiple first dummy electrode lines 71 and multiple second dummy electrode lines 72. The first dummy electrode lines 71 and the second dummy electrode lines 72 are distinguished according to the different positions, extension directions, and arrangement directions of the conductive layer in the dummy pattern 7. See also Figure 5 As shown, Figure 5 An exemplary top view of the second conductive layer 20 is shown. Multiple first dummy electrode lines 71 and first signal traces 61 are located in the second conductive layer 20, and the first dummy electrode lines 71 and first signal traces 61 extend in the same direction, and are insulated from each other. The multiple first dummy electrode lines 71 and first signal traces 61 form a first pattern evenly distributed in the display area. For example, the first pattern is the first dummy electrode lines 71 and first signal traces 61 uniformly arranged along the Y direction. This improves the reflectivity differences caused by the metal density and film thickness differences resulting from the presence of first signal traces 61 in certain areas of the second conductive layer 20, thereby enhancing the uniformity of the structural and display performance of the display panel 100. For example, the first dummy electrode line 71 can be an SD1 dummy line in the circuit design, which is disposed on the same SD metal layer (Source & Drain Electrode) as the first signal line 61 (SD1 line), i.e., the second conductive layer 20; the second dummy electrode line 72 can be an SD2 dummy line in the circuit design, which is disposed on the same SD metal layer as the second signal line 62 (SD2 line), i.e., the third conductive layer 30.

[0067] See Figure 6 As shown, Figure 6 An exemplary top view of the third conductive layer 30 is shown. Both the second dummy electrode line 72 and the second signal trace 62 are located within the third conductive layer 30, and the second dummy electrode line 72 and the second signal trace 62 extend in the same direction. The second dummy electrode line 72 is not used to transmit electrical signals to the second signal trace 62. The second dummy electrode line 72 and the second signal trace 62 form a second pattern evenly distributed in the display area. For example, the second pattern is a uniform arrangement of the second dummy electrode line 72 and the second signal trace 62 along the X direction. This improves the reflectivity differences caused by the metal density and film thickness differences resulting from the placement of the second signal trace 62 in certain areas of the third conductive layer 30, thereby enhancing the uniformity of the structural and display performance of the display panel 100.

[0068] In one exemplary embodiment, such as Figure 5 As shown, multiple second power signal lines 5 are connected to the second power signal bus 8, which is located in the second conductive layer 20. At least some of the first dummy electrode lines 71 are connected to the second power signal bus 8.

[0069] In this embodiment, the second power signal bus 8 can be located in the non-display area of ​​the second conductive layer 20. The second power signal bus 8 can be connected to the Bending Area, and multiple second power signal lines 5 are connected to the second power signal bus 8. To make the wiring of the second conductive layer 20 reasonable and compact and reduce unnecessary winding, multiple second power signal lines 5 are set in the second conductive layer 20, and at least some of the first dummy electrode lines 71 are connected to the second power signal bus 8. Compared with the prior art, where the first dummy electrode line 71 is connected to the first power signal line 4, the first dummy electrode line 71 is equivalent to the first power signal line 4, which increases the coupling capacitance between the data line 3 and the first power signal line 4 due to the coupling capacitance between the first power signal line 4 and the second signal trace 62. In this embodiment, some of the first dummy electrode lines 71 are connected to the second power signal bus 8, which makes some of the first dummy electrode lines 71 equivalent to the second power signal bus 8. This reduces the coupling capacitance between the data line 3 and the first power signal line 4, reduces the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal jumps, thereby improving signal crosstalk and achieving a good display effect for the display panel 100.

[0070] In some embodiments, all of the first dummy electrode lines 71 may be connected to the second power signal bus 8. All the first dummy electrode lines 71 are equivalent to the second power signal bus 8, so as to further reduce the coupling capacitance between the data line 3 and the first power signal line 4, further reduce the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal jumps, weaken signal crosstalk, and improve the display effect of the display panel 100.

[0071] In some possible implementations, combined Figure 3 and Figure 5 The second power signal bus 8 extends along a first direction, and in a second direction, the second power signal bus 8 is located on at least one side of the display area. Multiple first dummy electrode lines 71 include a first dummy sub-electrode line 711, a second dummy sub-electrode line 712, and a third dummy sub-electrode line 713. The first dummy sub-electrode line 711 is collinear with the first signal trace 61 and located between the first signal trace 61 and the second power signal bus 8. The second dummy sub-electrode line 712 is collinear with the first signal trace 61 and located on the side of the first signal trace 61 away from the second power signal bus 8. The third dummy sub-electrode line 713 is parallel to the first signal trace 61. Both the first dummy sub-electrode line 711 and the third dummy sub-electrode line 713 are connected to the second power signal bus 8. The second dummy sub-electrode line 712 is connected to the first dummy sub-electrode line 711, the third dummy sub-electrode line 713, or the second dummy electrode line 72 via a connection structure.

[0072] In this embodiment, the second power signal bus 8 extends along a first direction, which is the Y direction. Since multiple second power signal lines 5 are connected to the second power signal bus 8, and the first dummy electrode line 71 is connected to the second power signal bus 8, and both the first dummy electrode line 71 and the second power signal line 5 are disposed on the second conductive layer 20, in order to make the wiring of the second conductive layer 20 reasonable and compact and reduce unnecessary winding, multiple second power signal lines 5 extend along a second direction, which is the X direction. That is, the extension direction of the second power signal line 5 and the first dummy electrode line 71 is the same, and the second power signal line 5 and the first dummy electrode line 71 are alternately arranged along the first direction and are mutually insulated. The second power signal bus 8 can be located on one side of the display area or on both sides of the display area, so as to facilitate the connection of the first dummy electrode line 71 to the second power signal bus 8.

[0073] The multiple first dummy electrode lines 71 include multiple first dummy sub-electrode lines 711, multiple second dummy sub-electrode lines 712, and multiple third dummy sub-electrode lines 713. The first dummy sub-electrode lines 711, second dummy sub-electrode lines 712, and third dummy sub-electrode lines 713 are distinguished by their different positions and types on the second conductive layer 20 where the first dummy electrode lines 71 are located. See also... Figure 5 The multiple first dummy electrode lines 71 include multiple first dummy sub-electrode lines 711. Each first dummy sub-electrode line 711 is collinear with and insulated from its corresponding first signal trace 61, and does not receive electrical signals. The first dummy sub-electrode line 711 is located between the first signal trace 61 and the second power signal bus 8, reducing the metal density difference between the areas of the first signal trace 61 and the second power signal bus 8 in the second conductive layer 20, thereby improving the uniformity of the film thickness and reflectivity of the display panel 100. The first dummy sub-electrode line 711 can be connected to the second power signal bus 8, making it equivalent to the second power signal bus 8. This reduces the coupling capacitance between the data line 3 and the first power signal line 4, reduces the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal changes, thereby improving signal crosstalk and achieving a good display effect for the display panel 100. It should be noted that the first dummy sub-electrode line 711 is a series of short lines between the first signal trace 61 and the second power signal bus 8 in the display area. Each first dummy sub-electrode line 711 is collinear with and insulated from the corresponding first signal trace 61, and is connected to the second power signal bus 8.

[0074] The multiple first dummy electrode lines 71 also include multiple second dummy sub-electrode lines 712. The second dummy sub-electrode lines 712 are collinear with and insulated from the corresponding first signal traces 61, and do not receive electrical signals. Combined with... Figure 3 and Figure 5The data lines 3 of the display area are evenly arranged on both sides in the X direction. Multiple first signal lines 61 extend along the X direction, with one end of the first signal line 61 located in the edge region 2 and connected to the corresponding data line 3, and the other end located in the middle region 1 and connected to the corresponding second signal line 62. Therefore, the first signal lines 61 can also be evenly arranged in the X direction. For example, the first signal lines 61 of the display area on both sides in the X direction are collinear, and the second dummy sub-electrode line 712 is located on the side of the first signal line 61 away from the second power signal bus 8. That is, the second dummy sub-electrode line 712 is located between the first signal lines 61 of the display area on both sides in the X direction, which reduces the metal density difference of the second conductive layer 20 in the area between the first signal lines 61 on both sides in the X direction, thereby improving the uniformity of the film thickness and reflectivity of the display panel 100.

[0075] The multiple first dummy electrode lines 71 also include multiple third dummy sub-electrode lines 713. The third dummy sub-electrode lines 713 are parallel to the first signal traces 61. When the second power signal bus 8 is located on one side of the display area, one end of the third dummy sub-electrode line 713 is connected to the second power signal bus 8. When the second power signal bus 8 is located on both sides of the display area, both ends of the third dummy sub-electrode line 713 are connected to the second power signal bus 8, making the third dummy sub-electrode line 713 equivalent to the second power signal bus 8. This reduces the coupling capacitance between the data line 3 and the first power signal line 4, reduces the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal changes, thereby improving signal crosstalk and achieving a good display effect for the display panel 100. Simultaneously, the multiple third dummy sub-electrode lines 713 parallel to the first signal traces 61 improve the difference in film thickness and reflectivity caused by the placement of the first signal traces 61 in certain areas of the second conductive layer 20, thereby improving the uniformity of the display performance of the display panel 100.

[0076] See Figure 5 As shown, because the second dummy sub-electrode line 712 is collinear with the first signal trace 61 and located on the side of the first signal trace 61 furthest from the second power signal bus 8, the second dummy sub-electrode line 712 is not directly connected to the second power signal bus 8. See also... Figure 7 As shown, Figure 7 It is along Figure 3A partial cross-sectional view of the first dummy sub-electrode line 711 and the second dummy sub-electrode line 712 connected thereto, cut along the BB direction. In this embodiment, only a partial cross-sectional view of the second conductive layer 20 is shown. In this embodiment, the second dummy sub-electrode line 712 can be connected to the first dummy sub-electrode line 711 through a connecting structure 11. The connecting structure 11 is disposed in the isolation layer between the first conductive layer 10 and the second conductive layer 20. Since the first signal trace 61 and the data line 3 are connected through the first connecting hole 91, the connecting structure 11 bypasses the position of the first connecting hole 91, i.e., the connecting structure... The projections of 11 and the first connection hole 91 on a plane parallel to the display panel 100 do not intersect, so that the first signal trace 61 transmits data content, and the second dummy sub-electrode line 712 can be indirectly connected to the second power signal bus 8 through the first dummy sub-electrode line 711, so that all the first dummy electrode lines 71 are equivalent to the second power signal bus 8, thereby reducing the coupling capacitance between the data line 3 and the first power signal line 4, reducing the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal jumps, improving signal crosstalk, and achieving a good display effect of the display panel 100.

[0077] In another embodiment, the second dummy sub-electrode line 712 can also be connected to the third dummy sub-electrode line 713 (not shown in the figure) via a connection structure 11. The connection structure 11 is disposed in the isolation layer between the first conductive layer 10 and the second conductive layer 20, and the connection structure 11 extends along... Figure 3 The Y-direction extension in the middle allows the second dummy sub-electrode line 712 to be indirectly connected to the second power signal bus 8 through the third dummy sub-electrode line 713, thereby reducing the coupling capacitance between the data line 3 and the first power signal line 4, improving signal crosstalk, and achieving a good display effect for the display panel 100.

[0078] In another embodiment, the second dummy sub-electrode line 712 can also be connected to the second dummy electrode line 72 through the connection structure 11 (described in detail below). The connection structure 11 is disposed in the isolation layer between the second conductive layer 20 and the third conductive layer 30, so that the second dummy sub-electrode line 712 can be indirectly connected to the second power signal bus 8 or the first power signal line 4 through the second dummy electrode line 72, thereby reducing the coupling capacitance generated between the data line 3 and the first power signal line 4, improving the crosstalk of the lines, and achieving a good display effect of the display panel 100.

[0079] For example, the connection structure 11 can be formed by first etching the isolation layer between the first conductive layer 10 and the second conductive layer 20 or the isolation layer between the second conductive layer 20 and the third conductive layer 30 to form a via, and then filling the via with conductive material by deposition to form a through hole, so that the second dummy sub-electrode line 712 can be indirectly connected to the second power signal bus 8 or the first power signal line 4, thereby reducing the coupling capacitance between the data line 3 and the first power signal line 4, improving signal crosstalk, and achieving a good display effect of the display panel 100.

[0080] In one exemplary embodiment, combined with Figure 6 and Figure 8 As shown, multiple first power signal lines 4 are located in the first conductive layer 10, and the first power signal lines 4 and data lines 3 are arranged alternately along the second direction; some second dummy electrode lines 72 and some second signal traces 62 correspond to the positions of data lines 3 in the central region 1, and other parts of the second dummy electrode lines 72 and other parts of the second signal traces 62 correspond to the positions of the first power signal lines 4 in the central region 1.

[0081] In this embodiment, see Figure 6 As shown, the first power signal line 4 and the data line 3 are both disposed on the first conductive layer 10. In order to make the wiring of the first conductive layer 10 reasonable and compact and reduce unnecessary winding, multiple first power signal lines 4 extend along the first direction, which is the Y direction. That is, the extension direction of the first power signal line 4 and the data line 3 is the same, and the first power signal line 4 and the data line 3 are arranged alternately along the second direction, so that the film thickness and metal density of the first conductive layer 10 are uniform and the reflectivity difference is reduced.

[0082] Combination Figure 3 , Figure 6 and Figure 8As shown, the second dummy electrode line 72 and the second signal trace 62 are located in the third conductive layer 30, while the first power signal line 4 and the data line 3 are located in the first conductive layer 10. The second dummy electrode line 72 and the second signal trace 62 extend in the same direction as the first power signal line 4 and the data line 3, and the second signal trace 62 is located in the central region 1. When the first conductive layer 10 and the third conductive layer 30 are stacked, a portion of the second dummy electrode line 72 and a portion of the second signal trace 62 on the third conductive layer 30 correspond to the position of the data line 3 in the central region 1, while another portion of the second dummy electrode line 72 and another portion of the second signal trace 62 correspond to the position of the first power signal line 4 in the central region 1. In other words, the projection of a portion of the second dummy electrode line 72 and a portion of the second signal trace 62 onto the first conductive layer 10 coincides with the data line 3 in the central region 1, and the projection of another portion of the second dummy electrode line 72 and another portion of the second signal trace 62 onto the first conductive layer 10 coincides with the first power signal line 4 in the central region 1. The routing direction and line shape of a portion of the second dummy electrode line 72 and a portion of the second signal line 62 corresponding to the position of data line 3 are consistent with those of data line 3. The routing direction and line shape of another portion of the second dummy electrode line 72 and another portion of the second signal line 62 corresponding to the position of the first power signal line 4 are consistent with those of the first power signal line 4, so as to improve the uniformity of the structural performance and display performance of the display panel 100 and reduce the difference in reflectivity.

[0083] In some possible implementations, combined Figure 9 and Figure 10 As shown, Figure 9 It is shown according to an exemplary embodiment along Figure 3 A partial sectional view of the connection between the first dummy electrode line 71 and the second dummy electrode line 72, cut along the CC direction. Figure 10 This is a schematic diagram of a display panel layout according to an exemplary embodiment. This embodiment shows a partial cross-sectional view of the second conductive layer 20 and the third conductive layer 30, wherein each second dummy electrode line 72 is connected to the intersecting first dummy electrode line 71 through a third connecting hole 93.

[0084] In this embodiment, combined with Figure 3 , Figure 9 and Figure 10As shown, since the second dummy electrode line 72 is located on the third conductive layer 30 and extends along the first direction, and the first dummy electrode line 71 is located on the second conductive layer 20 and extends along the second direction, when the second conductive layer 20 and the third conductive layer 30 are stacked, the projection of each second dummy electrode line 72 on the second conductive layer 20 intersects with multiple first dummy electrode lines 71. Each second dummy electrode line 72 is connected to the intersecting first dummy electrode lines 71 through a third connecting hole 93. The third connecting hole 93 is located in the isolation layer between the second conductive layer 20 and the third conductive layer 30. Since the first dummy electrode line 71 is connected to the second power signal bus 8, the second dummy electrode line 72 can be indirectly connected to the second power signal bus 8 through the first dummy electrode line 71. This makes all second dummy electrode lines 72 equivalent to the second power signal bus 8, thereby reducing the coupling capacitance between the data line 3 and the first power signal line 4, reducing the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal changes, improving signal crosstalk, and achieving a good display effect for the display panel 100. Furthermore, when all the first dummy electrode lines 71 and the second dummy electrode lines 72 are connected to the second power signal bus 8, multiple first dummy electrode lines 71 and multiple second dummy electrode lines 72 are connected in parallel with the second power signal bus 8, thereby reducing the resistance of the second power signal bus 8, thereby reducing the voltage drop, and thus reducing the power consumption of the display panel 100.

[0085] In some possible implementations, combined Figure 11 and Figure 12 As shown, Figure 11 It is shown according to an exemplary embodiment along Figure 3 A partial cross-sectional view showing the second dummy electrode line 72, cut along the CC direction, connecting the first dummy electrode line 72 and the first power signal line 4. Figure 12 This is a schematic diagram of a display panel layout according to an exemplary embodiment. A portion of the second dummy electrode line 72 is connected to the intersecting first dummy electrode line 71 through a third connection hole 93, and another portion of the second dummy electrode line 72 is connected to the first power signal line 4 through a fourth connection hole 94.

[0086] In this embodiment, the portion of the second dummy electrode line 72 connected to the intersecting first dummy electrode line 71 via the third connecting hole 93 corresponds to the position of the data line 3, and the other portion of the second dummy electrode line 72 connected to the first power signal line 4 via the fourth connecting hole 94 corresponds to the position of the first power signal line 4. This makes the wiring layout inside the display panel 100 reasonable and facilitates production. The fourth connecting hole 94 is disposed in the isolation layer between the first conductive layer 10 and the third conductive layer 30, allowing the second dummy electrode line 72 to be connected to the first power signal line 4. By connecting a portion of the second dummy electrode line 72 in parallel to the second power signal bus 8 via the first dummy electrode line 71, and another portion of the second dummy electrode line 72 in parallel to the first power signal line 4, the resistance of the first power signal line 4 and the second power signal bus 8 is reduced, thereby reducing the power consumption of the display panel 100. Meanwhile, since some of the second dummy electrode lines 72 are connected to the second power signal bus 8, some of the second dummy electrode lines 72 are equivalent to the second power signal bus 8, thereby reducing the coupling capacitance between the data line 3 and the first power signal line 4, reducing the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal jumps, thereby improving signal crosstalk and achieving a good display effect of the display panel 100.

[0087] For example, such as Figure 11 As shown, since the second dummy electrode line 72 connected to the first dummy electrode line 71 corresponds to the position of the data line 3, and the second dummy electrode line 72 connected to the first power signal line 4 corresponds to the position of the first power signal line 4, and since the data line 3 and the first power signal line 4 are alternately arranged on the first conductive layer 10 along the second direction, the second dummy electrode line 72 connected to the first dummy electrode line 71 and the second dummy electrode line 72 connected to the first power signal line 4 are alternately arranged on the third conductive layer 30 along the second direction, making the film thickness and metal density of the third conductive layer 30 uniform, reducing the reflectivity difference of the display panel 100.

[0088] In one exemplary embodiment, combined with Figure 3 , Figure 6 and Figure 13 As shown, the multiple second dummy electrode lines 72 include a fourth dummy sub-electrode line 721 that is collinear with the second signal line 62 and a fifth dummy sub-electrode line 722 that is parallel to the second signal line 62. The second dummy sub-electrode line 712 in the first dummy electrode line 71 is connected to the fourth dummy sub-electrode line 721 through the connection structure 11.

[0089] In this embodiment, multiple fourth dummy sub-electrode lines 721 collinear with the second signal trace 62, multiple fifth dummy sub-electrode lines 722 parallel to the second signal trace 62, and multiple second signal traces 61 together form a second pattern evenly distributed on the third conductive layer 30. This improves the differences in metal density and film thickness caused by the second signal traces 62 in some areas of the third conductive layer 30, reduces the differences in reflectivity, and thus improves the uniformity of the structural performance and display performance of the display panel 100.

[0090] The fourth dummy sub-electrode line 721 can be connected to the crossing third dummy sub-electrode line 713 or the second dummy sub-electrode line 712. When the fourth dummy sub-electrode line 721 is connected to the crossing third dummy sub-electrode line 713, it combines... Figure 9 The fourth dummy sub-electrode line 721 and the third dummy sub-electrode line 713 can be connected through the third connection hole 93, thereby allowing the fourth dummy sub-electrode line 721 to be indirectly connected to the second power signal bus 8.

[0091] See Figure 3 and Figure 4 Since the fourth dummy sub-electrode line 721 is collinear with and insulated from the second signal line 62, and the second dummy sub-electrode line 712 is collinear with and insulated from the first signal line 61, and the first signal line 61 and the second signal line 62 are connected through the second connection hole 92. When the fourth dummy sub-electrode line 721 is connected to the second dummy sub-electrode line 712, see [reference needed]. Figure 13 , Figure 13 It is along Figure 3 A partial cross-sectional view showing the fourth dummy sub-electrode line 721 connected to the second dummy sub-electrode line 712 in the DD direction. In this embodiment, only a partial cross-sectional view of the second conductive layer 20 and the third conductive layer 30 is shown. The second dummy sub-electrode line 712 has a connection structure 11 near the end of the collinear first signal trace 61. That is, the projection of the connection structure 11 and the second connection hole 92 on a plane parallel to the display panel 100 does not coincide or intersect. This allows the fourth dummy sub-electrode line 721 to be connected to the second dummy sub-electrode line 712 through the connection structure 11. The second dummy sub-electrode line 712 is then connected to the second power signal bus 8 through the first dummy sub-electrode line 711. Thus, the fourth dummy sub-electrode line 721 is indirectly connected to the second power signal bus 8, making the fourth dummy sub-electrode line 721 equivalent to the second power signal bus 8. This reduces the coupling capacitance between the data line 3 and the first power signal line 4, reduces the voltage fluctuation amplitude of the first power signal line 4 when the data line 3 signal changes, improves signal crosstalk, and enhances the display performance of the display panel 100.

[0092] In one exemplary embodiment, this disclosure provides a display screen including the display panel 100 described above, which improves signal crosstalk in the display screen and enhances the display effect. The display screen may also include a touch layer, which can be attached to the display panel 100 to enable touch functionality. Exemplarily, the display screen may be an LCD (Liquid Crystal Display) or an OLED (Organic Light-Emitting Diode) display screen.

[0093] In one exemplary embodiment, this disclosure also provides an electronic device including the aforementioned display screen, which improves signal crosstalk and enhances the display effect of the electronic device. The electronic device may be a terminal device requiring narrow bezels, such as a smartphone, a full-screen phone, a tablet computer, etc.

[0094] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0095] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A display panel, characterized by, The display area of the display panel has a middle area and an edge area outside the middle area, the display panel comprises a plurality of data lines, a plurality of first power signal lines and a plurality of second power signal lines in the display area, wherein each data line in the edge area is connected to the middle area through a signal trace, at least part of the signal trace corresponds to the position of the first power signal line, the conductive layer where the signal trace is located further comprises a dummy pattern, the dummy pattern is arranged separately from the signal trace, wherein at least part of the dummy pattern is electrically connected to the second power signal line; the plurality of second power signal lines are connected to a second power signal bus and are used to provide a source voltage; the dummy pattern comprises a plurality of first dummy electrode lines in the same conductive layer as the second power signal bus, and at least part of the first dummy electrode lines are connected to the second power signal bus.

2. The display panel of claim 1, wherein, The display panel comprises a first conductive layer, a second conductive layer and a third conductive layer arranged in layers, wherein the data lines are located in the first conductive layer and extend along a first direction, the plurality of data lines are arranged in a second direction at intervals, and the first direction and the second direction are arranged at an included angle; each signal trace comprises a first signal trace extending along the second direction and a second signal trace extending along the first direction, the first signal trace is located in the second conductive layer, the second signal trace is located in the third conductive layer, the first end of the first signal trace is located in the edge area and connected to the corresponding data line through a first connection hole, and the second end of the first signal trace and the second signal trace are located in the middle area, and the second end of the first signal trace is connected to the second signal trace through a second connection hole.

3. The display panel of claim 2, wherein, The dummy pattern further comprises a plurality of second dummy electrode lines, wherein the plurality of first dummy electrode lines are located in the second conductive layer and form a first pattern uniformly distributed in the display area with the first signal trace; the plurality of second dummy electrode lines are located in the third conductive layer and form a second pattern uniformly distributed in the display area with the second signal trace.

4. The display panel of claim 3, wherein, The second power signal bus is located in the second conductive layer.

5. The display panel of claim 4, wherein, The second power signal bus extends along the first direction, and in the second direction, the second power signal bus is located in a non-display area outside the display area, and the plurality of first dummy electrode lines comprise: a first dummy sub-electrode line which is collinear with the first signal trace and located between the first signal trace and the second power signal bus; a second dummy sub-electrode line which is collinear with the first signal trace and located on the side of the first signal trace away from the second power signal bus; a third dummy sub-electrode line which is parallel to the first signal trace; the first dummy sub-electrode line and the third dummy sub-electrode line are both connected to the second power signal bus, and the second dummy sub-electrode line is connected to the first dummy sub-electrode line, the third dummy sub-electrode line or the second dummy electrode line through a connection structure.

6. The display panel of any one of claims 3 to 5, wherein, The first power signal lines are located in the first conductive layer, and the first power signal lines and the data lines are arranged alternately along the second direction; Part of the second dummy electrode lines and part of the second signal lines correspond to the data lines in the middle region, and another part of the second dummy electrode lines and another part of the second signal lines correspond to the first power signal lines in the middle region.

7. The display panel of claim 6, wherein, Each of the second dummy electrode lines is connected to the intersecting first dummy electrode line through a third connection hole; or, Part of the second dummy electrode lines are connected to the intersecting first dummy electrode line through a third connection hole, and another part of the second dummy electrode lines are connected to the first power signal line through a fourth connection hole.

8. The display panel of claim 7, wherein, The second dummy electrode lines connected to the first dummy electrode lines and the second dummy electrode lines connected to the first power signal lines are arranged alternately along the second direction.

9. The display panel of claim 6, wherein, The second dummy electrode lines include fourth dummy sub-electrode lines co-linear with the second signal lines and fifth dummy sub-electrode lines parallel to the second signal lines, and the second dummy sub-electrode lines in the first dummy electrode lines are connected to the fourth dummy sub-electrode lines through a connection structure.

10. The display panel of claim 9, wherein, The second dummy sub-electrode lines are provided with the connection structure at the end point close to the co-linear first signal line.

11. A display screen, characterized by The display panel comprises the display panel as claimed in any one of claims 1 to 10.

12. An electronic device, comprising: The display screen comprises the display panel as claimed in claim 11.

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