Built-in self-test method and apparatus

Abstract

This disclosure provides a built-in self-testing method and device, comprising: obtaining a first initial address of a storage area containing data to be written; masking at least one bit of the first initial address to activate multiple storage areas; writing test data into the corresponding storage area according to a first compressed write address; obtaining a second initial address of a storage area containing data to be read; masking at least one bit of the second initial address to activate multiple storage areas; reading the test data corresponding to the multiple storage areas according to the first compressed read address, and compressing the test data during the reading process; calculating ideal read data based on the test data and a preset compression rule; comparing the read data from the memory with the ideal read data to obtain a test result. This setup improves testing efficiency.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a built-in self-testing method and apparatus. Background Technology

[0002] Semiconductor memory is one of the most important components of electronic devices, playing a crucial role in their performance and stability. Therefore, ensuring the reliability of the memory used in these electronic devices is essential, making memory testing a necessary requirement.

[0003] However, existing testing methods require accessing different addresses and performing read and write operations on each address, which leads to longer testing times and reduced testing efficiency. Summary of the Invention

[0004] This disclosure provides a built-in self-test method, wherein the memory includes multiple storage areas, and the method includes:

[0005] Obtain the first initial address of the storage area where the data to be written is to be obtained;

[0006] At least one bit of the first initial address is masked to activate multiple storage regions, and the addresses of the activated multiple storage regions are recorded as the first compressed write address;

[0007] Write test data to the corresponding storage area according to the first compressed write address;

[0008] Obtain the second initial address of the storage area from which the data to be read is to be retrieved;

[0009] At least one bit of the second initial address is masked to activate multiple storage regions, and the addresses of the activated multiple storage regions are recorded as the first compressed read address;

[0010] The test data corresponding to the multiple storage areas is read according to the first compressed read address, and the test data is compressed during the reading process so that the number of bits of compressed data read by the memory is equal to the number of bits of uncompressed data read by one of the storage areas.

[0011] The ideal read data is calculated based on the test data and the preset compression processing rules. The read data of the memory and the ideal read data are compared to obtain the test result.

[0012] In some embodiments, at least one bit of the first initial address is masked, specifically including:

[0013] Obtain a compressed write instruction, and based on the compressed write instruction, force at least one bit of the address itself and its inverted signal in the first initial address to the same specific value, so as to activate the corresponding plurality of storage regions.

[0014] In some embodiments, at least one bit of the second initial address is masked, specifically including:

[0015] Obtain a compressed read instruction, and based on the compressed read instruction, force at least one bit of the address itself and its inverted signal in the second initial address to the same specific value to activate the corresponding plurality of storage regions.

[0016] In some embodiments, each storage region includes multiple storage arrays;

[0017] Write test data to the corresponding storage area according to the first compressed write address, specifically including:

[0018] Within the storage area corresponding to each first compressed write address, the current word line is enabled based on the current row address, and the current column selection line in the storage array on the current word line is enabled to write test data to the target number of storage cells. The next column selection line is then updated until test data is written to all storage cells on the current word line.

[0019] In some embodiments, each storage region includes multiple storage arrays;

[0020] The test data corresponding to multiple storage areas is read according to the first compressed read address, specifically including:

[0021] Within the storage area corresponding to each first compressed read address, the current word line is enabled according to the current row address, and the current column selection line in the storage array on the current word line is enabled to read test data into the target value storage cells. The next column selection line is then updated until test data is read from all storage cells on the current word line.

[0022] In some embodiments, the number of storage regions that are activated simultaneously when writing data is greater than the number of storage regions that are activated simultaneously when reading data.

[0023] In some embodiments, before calculating ideal read data based on the test data and the rules of the compression process, comparing the read data of the memory with the ideal read data, and obtaining the test result, the method further includes:

[0024] Obtain the third initial address of the storage area where the data to be written is to be retrieved;

[0025] At least one bit of the third initial address is masked to activate multiple storage regions, and the addresses of the activated multiple storage regions are recorded as the second compressed write address;

[0026] Write test data to the corresponding storage area according to the second compressed write address;

[0027] Obtain the fourth initial address of the storage area from which the data to be read is to be retrieved;

[0028] At least one bit of the fourth initial address is masked to activate multiple storage regions, and the addresses of the activated multiple storage regions are recorded as the second compressed read address;

[0029] The test data corresponding to the multiple storage areas is read according to the second compressed read address, and the test data is compressed during the reading process so that the number of bits of compressed data read from the memory is equal to the number of bits of uncompressed data read from one of the storage areas.

[0030] Another embodiment of this disclosure provides a built-in self-test device, the memory including multiple storage areas, the device comprising:

[0031] The writing module is used to obtain the first initial address of the storage area of ​​the data to be written; mask at least one bit of the first initial address to activate multiple storage areas, and record the addresses of the multiple activated storage areas as the first compressed write address; and write test data into the corresponding storage area according to the first compressed write address.

[0032] The read module is configured to obtain a second initial address of the storage area containing the data to be read; mask at least one bit of the second initial address to activate multiple storage areas, and record the addresses of the activated multiple storage areas as a first compressed read address; read the test data corresponding to the multiple storage areas according to the first compressed read address, and compress the test data during the read process so that the number of bits of compressed data read from the memory is equal to the number of bits of uncompressed data read from one of the storage areas;

[0033] The output module is used to calculate the ideal read data based on the test data and preset compression processing rules, compare the read data of the memory with the ideal read data, and obtain the test result.

[0034] In some embodiments, the write module is configured to obtain a compressed write instruction and, based on the compressed write instruction, force at least one bit of the address itself and its inverted signal in the first initial address to the same specific value, so as to activate the corresponding plurality of storage regions.

[0035] Another embodiment of this disclosure provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the built-in self-test method involved in the above embodiments.

[0036] The built-in self-test method and apparatus disclosed herein mask at least one bit of a first initial address to activate multiple storage regions, and write test data into the activated storage regions to achieve data write compression and shorten data write time. At least one bit of a second initial address is also masked to activate multiple storage regions, and test data is read from the activated storage regions to achieve data read compression and shorten data read time. The read test data is further compressed to adapt to the data read bit width of the memory without altering the existing memory structure. By shortening data write and read times, test time can be reduced, and test efficiency improved. Attached Figure Description

[0037] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0038] Figure 1 This is a schematic diagram of a memory.

[0039] Figure 2 for Figure 1 The diagram shows a storage area in the memory.

[0040] Figure 3 A flowchart of a built-in self-test method provided in an embodiment of this disclosure;

[0041] Figure 4 A flowchart illustrating data writing in a built-in self-test method provided in another embodiment of this disclosure;

[0042] Figure 5 A flowchart of data reading in a built-in self-test method provided in yet another embodiment of this disclosure;

[0043] Figure 6 A schematic diagram of a built-in self-test device provided for yet another embodiment of this disclosure.

[0044] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0045] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0046] Memory built in self-test (Mbist) is a testing method in which test vectors are automatically generated by the built-in memory test logic, rather than by an external test instrument.

[0047] When Mbist's controller receives the command to start testing, it controls the memory's test module to operate. The test vectors of the test module are automatically generated internally, and it also calculates the expected output value of the memory. When the memory receives the test vectors, it performs read and write operations at equal intervals, traversing all addresses in the memory, accessing all memory cells, and finally reading through the mode register. It compares the data read from the memory with the expected output value of the memory, records the addresses of errors, and then corrects the errors.

[0048] Because Mbist needs to access different addresses and perform read and write operations on each address, the testing time is relatively long and the testing efficiency is reduced.

[0049] One embodiment of this disclosure provides a built-in self-test method and device, which shortens test time and improves test efficiency by simultaneously reading and writing to multiple storage areas and performing compressed reading and writing within each storage area.

[0050] like Figure 1 As shown, a memory 100 includes multiple storage areas 110, an Mbist controller 120, an address bus 150, an XOR gate circuit 130, and a DQ circuit 140. After receiving a command to start testing, the Mbist controller 120 controls a test module (not shown) to perform the test.

[0051] DQ circuit 140 is used to receive test data from the mode register (not shown) and write the test data into each memory area 110 via the address bus. Data is read from each memory area 110, output to XOR gate circuit 130 via address bus 150, compressed by XOR gate circuit 130, and then output to another mode register.

[0052] like Figure 2As shown, a storage region 110 includes multiple memory arrays (MATs) 230. Memory arrays in the same row share the same set of word lines 210, and memory arrays in the same column share the same set of column select lines 220 and the same set of bit lines (not shown in the figure). A column select line 220 controls a unit number of bit lines, enabling reading and writing data to a unit number of memory cells when a column select line is enabled.

[0053] In some embodiments, data is read from and written to eight storage units when one column selection line is enabled.

[0054] like Figure 3 As shown, one embodiment of this disclosure provides a built-in self-test method, which includes the following steps:

[0055] S101. Obtain the first initial address of the storage area where the data to be written is to be stored, and mask at least one bit of the first initial address to activate multiple storage areas.

[0056] Specifically, the first initial address of the storage area where the data to be written is obtained by parsing the test vector. For example, if the address of the storage area is 4 bits and is marked with BA<3:0>, the first initial address BA<3:0> is 0000 obtained by parsing the test vector.

[0057] In some embodiments, the first initial address includes multiple address bits. By masking at least one address bit of the first initial address, multiple storage regions are activated based on the masked address.

[0058] In some embodiments, a compression write instruction is obtained, and based on the compression write instruction, at least one address bit in the first initial address and its inverted signal are forced to the same specific value, thereby masking at least one address bit in the first initial address to activate the corresponding multiple storage regions.

[0059] In some embodiments, a compressed write instruction is obtained, and based on the compressed write instruction, at least one high-order address bit in the first initial address and its inverted signal are forced to the same specific value to activate the corresponding multiple memory regions.

[0060] For example: The fourth address BA in the first initial address BA<3:0> <3> Set to high level, the inverted signal BA of the fourth address bit. <3> B is set to high level. By decoding the forced first initial address, the first memory area BA0 and the ninth memory area BA8 are activated simultaneously, thus activating two memory areas at the same time.

[0061] For example: the fourth address BA in the first initial address BA<3:0> <3> and the third address BA <2> Set to high level, the inverted signal BA of the fourth address bit. <3> B and the inverted signal BA of the third address <2> B is set to high level. By decoding the forced first initial address, the first storage area BA0, the fifth storage area BA4, the ninth storage area BA8, and the thirteenth storage area BA12 are activated, thus simultaneously activating four storage areas.

[0062] For example: the fourth address BA in the first initial address BA<3:0> <3> The third address BA <2> Second address BA <1> Set to high level, the inverted signal BA of the fourth address bit. <3> B. The inverted signal BA of the third address <2> B and the inverted signal BA of the second address <1> B is set to high level. By decoding the forced first initial address, the first storage area BA0, the third storage area BA2, the fifth storage area BA4, the seventh storage area BA6, the ninth storage area BA8, the eleventh storage area BA10, the thirteenth storage area BA12, and the fifteenth storage area BA14 are activated, thus simultaneously activating 8 storage areas.

[0063] S102. Write test data to the corresponding storage area according to the first compressed write address.

[0064] The addresses of the multiple activated storage regions are designated as the first compressed write addresses, and test data is written to the corresponding storage regions according to the first compressed write addresses.

[0065] In some embodiments, the same test data is written to the corresponding storage area according to the first compressed write address.

[0066] S103. Obtain the second initial address of the storage area of ​​the data to be read, and mask at least one bit of the second initial address to activate multiple storage areas.

[0067] Specifically, the second initial address of the storage area where the data to be read is obtained by parsing the test vector. For example, if the address of the storage area is 4 bits and is marked with BA<3:0>, the second initial address BA<3:0> is 0000 obtained by parsing the test vector.

[0068] In some embodiments, the second initial address includes multiple address bits, and multiple storage regions are activated based on the masked address by masking at least one address bit of the second initial address.

[0069] In some embodiments, a compressed read instruction is obtained, and based on the compressed read instruction, at least one address bit in the second initial address and its inverted signal are forced to the same specific value, thereby masking at least one address bit in the second initial address to activate the corresponding multiple storage regions.

[0070] In some embodiments, a compressed read instruction is obtained, and based on the compressed read instruction, at least one high-order address bit in the second initial address and its inverted signal are forced to the same specific value to activate the corresponding multiple memory regions.

[0071] S104. Read test data corresponding to multiple storage areas according to the first compressed read address, and compress the test data during the reading process so that the number of bits of compressed data read from the memory is equal to the number of bits of uncompressed data read from a storage area.

[0072] The addresses of the multiple activated storage regions are designated as the first compressed read addresses, and the test data corresponding to the multiple storage regions is read based on the first compressed read addresses.

[0073] In some embodiments, the number of bits of uncompressed data read from a storage area is M bits, and the number of bits of data read from the memory is M bits when data is read from only one storage area.

[0074] If data is read from N storage areas simultaneously, when compressing the test data during the reading process, a preset compression rule is used to compress the number of bits read from each storage area to M / N bits, so that the number of bits of compressed data read from the memory is equal to the number of bits of uncompressed data read from one storage area.

[0075] In some embodiments, the preset compression processing rule is as follows: for each storage array, select one data from multiple test data read from the current column selection line of the storage array, group the selected data, perform XOR processing on the grouped data, and then select the next data from multiple test data read from each storage array, until the compression of all test data read from the current column selection line of the storage array is completed.

[0076] For example, in a storage region, 16 storage arrays share a set of word lines. When one column select line is enabled, data is read and written to 8 storage cells. For each of the 16 storage arrays, 8 test data points are read when the current column select line is enabled, and 1 test data point is selected from these 8. Therefore, 16 test data points can be selected from the 16 storage arrays. These 16 test data points are divided into two groups: the 8 test data points from the first 8 storage arrays are grouped together, and XORed with each group to output one bit; the 8 test data points from the last 8 storage arrays are grouped together, and XORed with each group to output one bit, thus completing the compression of the 16 test data points.

[0077] Then, select the next test data from the 8 test data read from each storage array, and process it according to the same rules as above until the compression of 16×8 test data is completed, and finally output 16 test data.

[0078] In some embodiments, the number of storage regions activated simultaneously during data writing is greater than the number of storage regions activated simultaneously during data reading. Reducing the number of storage regions activated simultaneously during data reading can ensure the quality of read data and improve the accuracy of testing.

[0079] S105. Calculate the ideal read data based on the test data and preset compression processing rules, compare the read data of the memory with the ideal read data, and obtain the test results.

[0080] The test data is processed using compression rules to output ideal read data. The data read from memory is compared with the ideal read data. If the data read from memory and the ideal read data are the same, it indicates that the storage function of the tested storage area is normal. If the data read from memory and the ideal read data differ by at least one bit, it indicates that the storage function of the tested storage area is faulty.

[0081] In the above technical solution, at least one bit of the first initial address is masked to activate multiple storage regions, and test data is written to the activated storage regions to achieve data write compression and shorten data write time. At least one bit of the second initial address is masked to activate multiple storage regions, and test data is read from the activated storage regions to achieve data read compression and shorten data read time. The read test data is also compressed to adapt to the data read bit width of the memory without changing the existing memory structure. By shortening the data write time and data read time, the testing time can be shortened and testing efficiency improved.

[0082] In some embodiments, writing test data to the corresponding storage area according to the first compressed write address specifically includes:

[0083] S201. In the storage area corresponding to each first compressed write address, the current word line is enabled according to the current row address, and the current column selection line in the storage array on the current word line is enabled to write test data to the target value storage cells. The next column selection line is updated until test data is written to all storage cells on the current word line.

[0084] Within each storage area corresponding to the first compressed write address, the current row address is decoded, and the current word line is activated based on the decoding result. Each word line has M storage arrays. The current column selection line is activated from each of the M storage arrays, writing test data to the target value of storage cells on the current word line, completing one loop. The next column selection line is updated, and the next column selection line is activated from each of the M storage arrays, writing test data to the target value of storage cells on the next column selection line, completing another loop. These steps are repeated until test data has been written to all storage cells on the current word line.

[0085] After writing test data to all memory cells on the current word line, update the address of the next row and start the next word line based on the address of the next row. Start the current column selection line in the memory array on the current word line to write test data to the target number of memory cells on the next word line, update the next column selection line, and so on until all memory cells on the next word line are written with test data.

[0086] For example, in a storage region, each word line has 16 memory arrays, and one column select line controls 8 bit lines. Enable the current word line, enable the first column select line of the first memory array, and write test data to the 8 memory cells on the current word line. Enable the first column select line of the second memory array and write test data to the 8 memory cells on the current word line, and so on, until the first column select line of the 16th memory array is enabled and test data is written to the 8 memory cells on the current word line, thus writing test data to all 128 memory cells on the current word line, completing one loop. Update the next column select line and repeat the above steps until test data has been written to all memory cells on the current word line.

[0087] In the above technical solution, when writing test data from each activated storage area, a fast write method is used, and data is written to multiple storage units each time a column selection line is opened, thereby shortening the data write time.

[0088] In some embodiments, reading test data corresponding to multiple storage regions according to a first compressed read address specifically includes:

[0089] S301. In the storage area corresponding to each first compressed read address, the current word line is enabled according to the current row address, and the current column selection line in the storage array on the current word line is enabled to read test data from the target value storage cells on the current word line. The next column selection line is updated until test data is read from all storage cells on the current word line.

[0090] Within each storage area corresponding to the first compressed read address, the current row address is decoded, and the current word line is activated based on the decoding result. Each word line has M storage arrays. The current column selection line is activated from each of the M storage arrays, enabling the reading of test data from the target value storage units on the current word line, completing one loop.

[0091] After completing one loop, the ideal read data is calculated based on the test data and preset compression processing rules. The data read in one loop is compared with the ideal read data to obtain the test result.

[0092] Next, update the next selection line, selecting the next selection line from each of the M storage arrays to enable it. This allows the test data to be read from the target number of storage cells on the current word line. Then, complete another loop, comparing the data read in one loop with the ideal read data to obtain the test result. Repeat the above steps until test data has been read from all storage cells on the current word line.

[0093] After reading test data from all memory cells on the current word line, update the address of the next row and start the next word line based on the address of the next row. Start the current column selection line in the memory array on the current word line to read test data from the target number of memory cells on the next word line, update the next column selection line, and continue until test data has been read from all memory cells on the next word line.

[0094] In the above technical solution, when reading test data from each activated storage area, a fast write method is used to read the data. Data is read from multiple storage units each time a column selection line is opened, thus shortening the data read time.

[0095] One embodiment of this disclosure provides a built-in self-testing method, which includes the following steps:

[0096] S401. Repeatedly execute the process of writing test data to multiple storage areas simultaneously to complete the data writing to the memory.

[0097] S402, refresh the data in each storage area.

[0098] S403. Repeatedly read test data from multiple storage areas to complete the writing of data to the memory.

[0099] S404. Compare the read test data with the written test data to obtain the test results.

[0100] Among them, such as Figure 4 As shown, S401 specifically includes the following sub-steps:

[0101] S501. Obtain the first initial address of the storage area where the data to be written is to be stored, and mask at least one bit of the first initial address to activate multiple storage areas.

[0102] Where the first initial address BA<3:0> is 0000, the fourth bit of the first initial address BA<3:0> is BA <3> and the third address BA <2> Set to high level, the inverted signal BA of the fourth address bit. <3> B and the inverted signal BA of the third address <2> B is set to high level. Decoding is performed using the forced first initial address to activate the first storage area BA0, the fifth storage area BA4, the ninth storage area BA8, and the thirteenth storage area BA12, thus activating four storage areas simultaneously.

[0103] S502. Write test data to the corresponding storage area according to the first compressed write address.

[0104] Among them, the first activated storage area BA0, the fifth storage area BA4, the ninth storage area BA8, and the thirteenth storage area BA12 are designated as the first compressed write address, and test data is written to the first storage area BA0, the fifth storage area BA4, the ninth storage area BA8, and the thirteenth storage area BA12 according to the first compressed write address.

[0105] S503. Determine whether the data writing of all storage areas has been completed. If yes, proceed to S504; otherwise, proceed to S505.

[0106] S504, refresh the data in each storage area.

[0107] S505. Obtain the next initial address and return to S501.

[0108] In some embodiments, the next initial address is marked as the third initial address. At least one bit of the third initial address is masked to activate multiple storage regions. The activated multiple storage regions are denoted as the second compressed write address, and test data is written to the corresponding storage region according to the second compressed write address.

[0109] For example: If the third initial address BA<3:0> is 0001, then the fourth bit of the third initial address BA<3:0> will be... <3> and the third address BA <2> Set to high level, the inverted signal BA of the fourth address bit. <3> B and the inverted signal BA of the third address <2> B is set to high level. Decoding is performed using the forced third initial address to activate the second storage area BA1, the sixth storage area BA5, the tenth storage area BA9, and the fourteenth storage area BA13, thus activating four storage areas simultaneously.

[0110] The activated second storage area BA1, sixth storage area BA5, tenth storage area BA9, and fourteenth storage area BA13 are designated as the second compressed write address. The second compressed write address is used to write to the second storage area BA1, sixth storage area BA5, tenth storage area BA9, and fourteenth storage area BA13.

[0111] Among them, such as Figure 5 As shown, S403 specifically includes the following sub-steps:

[0112] S601. Obtain the second initial address of the storage area of ​​the data to be read, and mask at least one bit of the second initial address to activate multiple storage areas.

[0113] Where the second initial address BA<3:0> is 0000, the fourth bit of the second initial address BA<3:0> is BA <3> Set to high level, the inverted signal BA of the fourth address bit. <3> B is set to high. Decoding is performed using the forced first initial address to activate the first memory area BA0 and the ninth memory area BA8, thus activating two memory areas simultaneously.

[0114] S602. Read test data corresponding to multiple storage areas according to the first compressed read address, and compress the test data during the reading process so that the number of bits of compressed data read from the memory is equal to the number of bits of uncompressed data read from a storage area.

[0115] The first activated storage area BA0 and the ninth storage area BA8 are designated as the first compressed read address, and test data is read from the first storage area BA0 and the ninth storage area BA8 according to the first compressed read address.

[0116] In some embodiments, in the first compressed read address from the first storage area BA0 and the ninth storage area BA8, the current word line is enabled according to the current row address, and the current column selection line in the storage array on the current word line is enabled, so as to read test data into the target value storage cells on the current word line, and to compress the test data read from the target value storage cells.

[0117] When reading uncompressed data from a memory region, the read data is 128 bits. The 128-bit data read from the first memory region BA0 is compressed to 64 bits according to a preset compression rule, and the 128-bit data read from the ninth memory region BA8 is compressed to 64 bits according to the preset compression rule, so that the compressed data read from the memory is 128 bits.

[0118] In some embodiments, the preset compression processing rule includes an XOR logical operation.

[0119] S603. After each data read from the storage area, the read test data is compared with the written test data to obtain the test result.

[0120] S604. Determine whether the first compressed read address has been used to read the test data corresponding to multiple storage areas. If not, proceed to S605; if yes, proceed to S606.

[0121] S605. After updating the row address or column address, return to S602.

[0122] If all data cells on the current word line have been read, the row address is updated, and test data for the next word line's memory cell is read. If no data has been read from all memory cells on the current word line, the column address is updated, which means updating the next column select line, and test data for the memory cell on the bit line controlled by the next column select line is read.

[0123] S606. Determine whether all data readings from all storage areas have been completed. If not, proceed to S607. If yes, end the process.

[0124] S607. Obtain the next initial address and return to S601.

[0125] In some embodiments, the next initial address is marked as the fourth initial address, and at least one bit of the fourth initial address is masked to activate multiple storage regions. The addresses of the activated multiple storage regions are denoted as the second compressed read address. Test data corresponding to the multiple storage regions is read according to the second compressed read address, and the test data is compressed during the read process so that the number of bits of compressed data read from the memory is equal to the number of bits of uncompressed data read from one storage region.

[0126] like Figure 6 As shown, one embodiment of this disclosure provides a built-in self-test device 700. The memory includes multiple storage areas, and the built-in self-test device 700 includes:

[0127] The writing module 701 is used to obtain the first initial address of the storage area of ​​the data to be written; mask at least one bit of the first initial address to activate multiple storage areas, and record the addresses of the activated multiple storage areas as the first compressed write address; and write test data into the corresponding storage area according to the first compressed write address.

[0128] The read module 702 is used to obtain the second initial address of the storage area of ​​the data to be read; to mask at least one bit of the second initial address to activate multiple storage areas, and to record the addresses of the activated multiple storage areas as the first compressed read address; to read the test data corresponding to the multiple storage areas according to the first compressed read address, and to compress the test data during the read process so that the number of bits of compressed data read from the memory is equal to the number of bits of uncompressed data read from a storage area;

[0129] The output module 703 is used to calculate the ideal read data based on the test data and preset compression processing rules, compare the read data of the memory with the ideal read data, and obtain the test results.

[0130] In some embodiments, the writing module 701 is specifically used for:

[0131] Obtain a compressed write instruction, and based on the compressed write instruction, force at least one bit of the address itself and its inverted signal in the first initial address to the same specific value to activate the corresponding multiple memory regions.

[0132] In some embodiments, the readout module 702 is specifically used for:

[0133] Obtain a compressed read instruction, and based on the compressed read instruction, force at least one bit of the address itself and its inverted signal in the second initial address to the same specific value to activate the corresponding multiple memory regions.

[0134] In some embodiments, each storage region includes multiple storage arrays, and the write module 701 is specifically used for:

[0135] Within the storage area corresponding to each first compressed write address, the current word line is enabled based on the current row address, and the current column selection line in the storage array on the current word line is enabled to write test data to the target number of storage cells. The next column selection line is then updated until test data is written to all storage cells on the current word line.

[0136] In some embodiments, each storage region includes multiple storage arrays, and the read module 702 is specifically used for:

[0137] Within the storage area corresponding to each first compressed read address, the current word line is enabled according to the current row address, and the current column selection line in the storage array on the current word line is enabled to read test data into the target value storage cells. The next column selection line is then updated until test data is read from all storage cells on the current word line.

[0138] In some embodiments, the number of storage regions that are activated simultaneously when writing data is greater than the number of storage regions that are activated simultaneously when reading data.

[0139] In some embodiments, the writing module 701 is specifically used for:

[0140] Obtain the third initial address of the storage area where the data to be written is to be retrieved;

[0141] At least one bit of the third initial address is masked to activate multiple storage regions, and the addresses of the activated multiple storage regions are recorded as the second compressed write address;

[0142] Write test data to the corresponding storage area according to the second compressed write address;

[0143] The read module 702 is specifically used for:

[0144] Obtain the fourth initial address of the storage area containing the data to be read;

[0145] At least one bit of the fourth initial address is masked to activate multiple storage regions, and the addresses of the activated multiple storage regions are recorded as the second compressed read address;

[0146] Test data corresponding to multiple storage areas are read according to the second compressed read address, and the test data is compressed during the reading process so that the number of bits of compressed data read from the memory is equal to the number of bits of uncompressed data read from a storage area.

[0147] This disclosure also provides a computer-readable storage medium storing computer instructions, which, when executed by a processor, implement the steps of the methods described above.

[0148] This disclosure also provides a computer program product, including computer instructions that, when executed by a processor, implement the steps of the methods described above.

[0149] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0150] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A built-in self-test method, characterized in that, The memory includes multiple storage areas, and the method includes: Obtain the first initial address of the storage area where the data to be written is to be obtained; At least one bit of the first initial address is masked to activate multiple storage regions, and the addresses of the activated multiple storage regions are recorded as the first compressed write address; Write test data to the corresponding storage area according to the first compressed write address; Obtain the second initial address of the storage area from which the data to be read is to be retrieved; At least one bit of the second initial address is masked to activate multiple storage regions, and the addresses of the activated multiple storage regions are recorded as the first compressed read address; The test data corresponding to the multiple storage areas is read according to the first compressed read address, and the test data is compressed during the reading process so that the number of bits of compressed data read by the memory is equal to the number of bits of uncompressed data read by one of the storage areas. The ideal read data is calculated based on the test data and the preset compression processing rules. The read data of the memory and the ideal read data are compared to obtain the test result.

2. The built-in self-test method according to claim 1, characterized in that, Masking at least one bit of the first initial address specifically includes: Obtain a compressed write instruction, and based on the compressed write instruction, force at least one bit of the address itself and its inverted signal in the first initial address to the same specific value, so as to activate the corresponding plurality of storage regions.

3. The built-in self-test method according to claim 2, characterized in that, At least one bit of the second initial address is masked, specifically including: Obtain a compressed read instruction, and based on the compressed read instruction, force at least one bit of the address itself and its inverted signal in the second initial address to the same specific value to activate the corresponding plurality of storage regions.

4. The built-in self-test method according to any one of claims 1 to 3, characterized in that, Each storage region comprises multiple storage arrays; Writing test data to the corresponding storage area according to the first compressed write address specifically includes: Within the storage area corresponding to each first compressed write address, the current word line is enabled according to the current row address, and the current column selection line in the storage array on the current word line is enabled to write the test data into the target number of storage units. The next column selection line is then updated until test data is written to all storage units on the current word line.

5. The built-in self-test method according to any one of claims 1 to 3, characterized in that, Each storage region comprises multiple storage arrays; Reading the test data corresponding to the multiple storage areas according to the first compressed read address specifically includes: Within the storage area corresponding to each first compressed read address, the current word line is enabled according to the current row address, and the current column selection line in the storage array on the current word line is enabled to read the test data into the target number of storage cells. The next column selection line is then updated until the test data is read from all storage cells on the current word line.

6. The built-in self-test method according to any one of claims 1 to 3, characterized in that, The number of storage regions activated simultaneously when writing data is greater than the number of storage regions activated simultaneously when reading data.

7. The built-in self-test method according to any one of claims 1 to 3, characterized in that, Before obtaining the second initial address of the storage area from which the data to be read is to be retrieved, the method further includes: Obtain the third initial address of the storage area where the data to be written is to be retrieved; At least one bit of the third initial address is masked to activate multiple storage regions, and the addresses of the activated multiple storage regions are recorded as the second compressed write address; Write test data to the corresponding storage area according to the second compressed write address; Accordingly, before calculating the ideal read data based on the test data and preset compression processing rules, comparing the read data of the memory with the ideal read data, and obtaining the test result, the method further includes: Obtain the fourth initial address of the storage area from which the data to be read is to be retrieved; At least one bit of the fourth initial address is masked to activate multiple storage regions, and the addresses of the activated multiple storage regions are recorded as the second compressed read address; The test data corresponding to the multiple storage areas is read according to the second compressed read address, and the test data is compressed during the reading process so that the number of bits of compressed data read from the memory is equal to the number of bits of uncompressed data read from one of the storage areas.

8. A built-in self-test device, characterized in that, The memory includes multiple storage areas, and the device includes: The writing module is used to obtain the first initial address of the storage area of ​​the data to be written; mask at least one bit of the first initial address to activate multiple storage areas, and record the addresses of the multiple activated storage areas as the first compressed write address; and write test data into the corresponding storage area according to the first compressed write address. The read module is configured to obtain a second initial address of the storage area containing the data to be read; mask at least one bit of the second initial address to activate multiple storage areas, and record the addresses of the activated multiple storage areas as a first compressed read address; read the test data corresponding to the multiple storage areas according to the first compressed read address, and compress the test data during the read process so that the number of bits of compressed data read from the memory is equal to the number of bits of uncompressed data read from one of the storage areas; The output module is used to calculate the ideal read data based on the test data and preset compression processing rules, compare the read data of the memory with the ideal read data, and obtain the test result.

9. The built-in self-test device according to claim 8, characterized in that, The writing module is specifically used for: Obtain a compressed write instruction, and based on the compressed write instruction, force at least one bit of the address itself and its inverted signal in the first initial address to the same specific value, so as to activate the corresponding plurality of storage regions.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the built-in self-test method as described in any one of claims 1 to 7.

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