Indium gallium arsenide wafer and manufacturing method thereof, radio frequency array chip and manufacturing method thereof

Abstract

The present application provides an InGaAs wafer and a method for manufacturing the same, as well as a radio frequency array chip and a method for manufacturing the same. The method includes: forming a donor substrate, the donor substrate including a first substrate, an absorption layer, a first doping layer, and a bonding layer stacked in sequence, the absorption layer being made of InGaAs, the first doping layer being made of InGaAs or InP, and the first substrate including at least a target layer being made of InP. Forming an acceptor substrate, the acceptor substrate including a first silicon substrate, a trap-rich layer, and an insulating layer stacked in sequence, the trap-rich layer being an amorphous material composed of Group IV elements. Bonding the donor substrate and the acceptor substrate with the bonding layer facing the insulating layer, removing a portion of the first substrate, retaining the target layer, and doping the target layer to obtain a second doping layer, thereby forming an InGaAs wafer. The trap-rich layer can capture free parasitic charges, reduce parasitic capacitance, and thereby improve the performance of the radio frequency array chip manufactured using the InGaAs wafer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to an indium gallium arsenide wafer and a method for manufacturing the same, and a radio frequency array chip and a method for manufacturing the same. Background Art

[0002] With the advancement of semiconductor-related technologies, ultra-high-speed short-wave infrared imaging technology is also developing rapidly. This technology can be used to construct an ultra-high-speed short-wave infrared imaging system. This system primarily consists of a high-speed short-wave infrared imaging chip, ultra-high-speed storage, and real-time vision modules. This system can capture images of high-speed moving objects, record and transmit massive amounts of images in real time, and measure target position, posture, trajectory, and velocity. It has widespread application in various fields.

[0003] The high-speed short-wave infrared imaging chip can be an indium gallium arsenide (InGaAs) short-wave infrared imaging chip. The indium gallium arsenide short-wave infrared imaging chip uses indium gallium arsenide as the intrinsic layer and indium phosphide (InP) as the N-type doping layer or the P-type doping layer. The InGaAs short-wave infrared photoelectric imaging chip is usually directly formed by epitaxial growth on an InP substrate.

[0004] However, the current InGaAs short-wave infrared imaging chip has the problem of slow operating speed. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide an InGaAs wafer and a manufacturing method thereof, a radio frequency array chip and a manufacturing method thereof, which can manufacture high-performance InGaAs wafers, thereby improving the performance of the radio frequency array chip manufactured using the InGaAs wafer, thereby achieving a higher chip operating speed.

[0006] The present application provides a method for manufacturing an InGaAs wafer, the method comprising:

[0007] forming a donor substrate, the donor substrate comprising a first substrate, an absorption layer, a first doping layer, and a bonding layer stacked in sequence, the absorption layer comprising at least indium gallium arsenide, the first doping layer being of a first doping type or a second doping type, the first doping type being one of P-type doping and N-type doping, the second doping type being the other of P-type doping and N-type doping, the first doping layer being of indium gallium arsenide or indium phosphide, and the first substrate comprising at least a target layer being of indium phosphide;

[0008] forming an acceptor substrate, the acceptor substrate comprising a first silicon substrate, a trap-rich layer, and an insulating layer stacked in sequence, wherein the trap-rich layer is an amorphous material composed of Group IV elements;

[0009] bonding the donor substrate and the acceptor substrate in a direction where the bonding layer faces the insulating layer;

[0010] removing a portion of the thickness of the first substrate and retaining the target layer;

[0011] The target layer is doped to obtain a second doping layer, where the doping type of the second doping layer is different from the doping type of the first doping layer.

[0012] Optionally, the material of the trap-rich layer is one or more of amorphous silicon, amorphous silicon tin, amorphous silicon germanium, amorphous germanium and amorphous germanium tin.

[0013] Optionally, the absorption layer is a stacked layer, which is formed by alternating a first target layer and a second target layer, the material of the first target layer is indium gallium arsenide, gallium arsenic phosphide or gallium arsenic antimony, and the material of the second target layer is indium phosphide, indium aluminum arsenic, aluminum gallium arsenic, indium aluminum gallium arsenic or indium gallium arsenic phosphide.

[0014] Optionally, the first substrate includes a second silicon substrate, a first buffer layer, a second buffer layer, a third buffer layer and the target layer stacked in sequence, the material of the first buffer layer is germanium, the material of the second buffer layer is gallium arsenide, the material of the third buffer layer is indium phosphide, and the second silicon substrate is a beveled silicon substrate.

[0015] Optionally, the material of the first substrate is indium phosphide.

[0016] Optionally, a resistance value of the first silicon substrate is greater than a target threshold value.

[0017] Optionally, the bonding layer and the insulating layer constitute a distributed Bragg reflector, and the distributed Bragg reflector includes a silicon oxide layer, a silicon oxide layer and an aluminum oxide layer stacked in sequence, or the distributed Bragg reflector includes a stacked silicon oxide layer and a polysilicon layer, or the distributed Bragg reflector includes a silicon oxide layer, a silicon nitride layer and a silicon oxide layer stacked in sequence, or the distributed Bragg reflector includes a stacked silicon oxide layer and a silicon layer.

[0018] The present application provides an indium gallium arsenide wafer, comprising a first silicon substrate, a trap-rich layer, an insulating layer, a bonding layer, a first doping layer, an absorption layer, and a second doping layer stacked in sequence; the absorption layer is made of indium gallium arsenide, the doping type of the first doping layer is a first doping type or a second doping type, the first doping type is one of P-type doping and N-type doping, and the second doping type is the other of P-type doping and N-type doping, the material of the first doping layer is indium gallium arsenide or indium phosphide, the material of the second doping layer is indium phosphide, the doping type of the second doping layer is different from the doping type of the first doping layer, and the trap-rich layer is an amorphous material composed of Group IV elements.

[0019] The present application provides a radio frequency array chip, comprising: a bonded indium gallium arsenide wafer and a readout circuit wafer;

[0020] The InGaAs wafer comprises a first silicon substrate, a trap-rich layer, an insulating layer, a bonding layer, a first doping layer, an absorption layer, and a second doping layer stacked in sequence; the absorption layer is made of InGaAs, the doping type of the first doping layer is a first doping type or a second doping type, the first doping type is one of P-type doping and N-type doping, and the second doping type is the other of P-type doping and N-type doping, the first doping layer is made of InGaAs or InP, the second doping layer is made of InP, the doping type of the second doping layer is different from the doping type of the first doping layer, and the trap-rich layer is an amorphous material composed of Group IV elements; the stacked structure composed of the first doping layer, the absorption layer, and the third doping layer comprises a plurality of pixels and a plurality of trenches, the pixels and the trenches being covered by a surface passivation layer, the surface passivation layer at the bottom of the trench having a first opening, the first opening having a first metal layer therein, the first metal layer being in contact with the first doping layer, the surface passivation layer at the top of the pixel having a second opening, the second opening having a second metal layer therein, the second metal layer being in contact with the second doping layer;

[0021] The readout circuit wafer has a third metal layer and a fourth metal layer. The third metal layer contacts the first metal layer, and the fourth metal layer contacts the second metal layer.

[0022] The present application provides a method for manufacturing a radio frequency array chip, the method comprising:

[0023] An indium gallium arsenide wafer and a readout circuit wafer are provided. The indium gallium arsenide wafer includes a first silicon substrate, a trap-rich layer, an insulating layer, a bonding layer, a first doped layer, an absorption layer, and a second doped layer stacked in sequence. The absorption layer is made of at least indium gallium arsenide. The first doped layer has a first doping type or a second doping type, the first doping type is one of P-type doping and N-type doping, and the second doping type is the other of P-type doping and N-type doping. The first doped layer is made of indium gallium arsenide or indium phosphide, the second doped layer is made of indium phosphide, the doping type of the second doped layer is different from the doping type of the first doped layer, and the trap-rich layer is made of an amorphous material composed of Group IV elements.

[0024] Etching the first doping layer, the absorption layer, and the second doping layer to obtain a plurality of grooves, wherein the grooves do not penetrate the first doping layer, and protrusions between adjacent grooves constitute picture elements;

[0025] forming a surface passivation layer, wherein the surface passivation layer covers the surface of the groove and the surface of the pixel;

[0026] Etching the surface passivation layer at the bottom of the trench to form a first opening, and forming a first metal layer in the first opening, wherein the first metal layer is in contact with the first doping layer;

[0027] Etching the surface passivation layer on the top of the pixel to form a second opening, forming a second metal layer in the second opening, wherein the second metal layer is in contact with the second doping layer;

[0028] The InGaAs wafer and the readout circuit wafer are bonded in a direction where the first metal layer and the second metal layer are toward the readout circuit wafer. The readout circuit wafer has a third metal layer and a fourth metal layer. The third metal layer is in contact with the first metal layer, and the fourth metal layer is in contact with the second metal layer.

[0029] The present application provides a method for manufacturing an InGaAs wafer, the method comprising: forming a donor substrate, the donor substrate comprising a first substrate, an absorber layer, a first doping layer, and a bonding layer stacked in sequence, the absorber layer being made of InGaAs; the first doping layer being doped with a first doping type or a second doping type, the first doping type being one of P-type and N-type doping, and the second doping type being the other of P-type and N-type doping, the first doping layer being made of InGaAs or InP; the first substrate comprising at least a target layer, the target layer being made of InP; forming an acceptor substrate, the acceptor substrate comprising a first silicon substrate, a trap-rich layer, and an insulating layer stacked in sequence, the trap-rich layer being an amorphous material composed of Group IV elements; bonding the donor substrate and acceptor substrate with the bonding layer facing the insulating layer; removing a portion of the first substrate, retaining the target layer; and doping the target layer to obtain a second doping layer, the doping type of the second doping layer being different from that of the first doping layer. This forms InP of different doping types on both sides of the absorber layer, thereby ultimately forming an InGaAs wafer. The trap-rich layer in the InGaAs wafer can capture free parasitic charges in the insulating layer, bonding layer, first doping layer, absorption layer and second doping layer, thereby reducing parasitic capacitance. The RF array chip subsequently manufactured using the InGaAs wafer can have a higher imaging speed, thereby improving the performance of the RF array chip manufactured using the InGaAs wafer and achieving a higher chip operating speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0031] Figure 1 A schematic diagram of a process for manufacturing an InGaAs wafer provided in an embodiment of the present application is shown;

[0032] Figure 2-Figure 7 A schematic structural diagram of a method for manufacturing an InGaAs wafer according to an embodiment of the present application is shown;

[0033] Figure 8 A schematic structural diagram of a radio frequency array chip provided in an embodiment of the present application is shown;

[0034] Figure 9 A schematic diagram showing a process of manufacturing a radio frequency array chip provided in an embodiment of the present application is shown;

[0035] Figure 10-14 A structural schematic diagram of a radio frequency array chip manufactured by a method for manufacturing a radio frequency array chip provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0036] In order to help those skilled in the art better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0038] This application is described in detail with reference to schematic diagrams. When describing the embodiments of this application, for ease of explanation, cross-sectional views of device structures may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0039] High-speed short-wave infrared imaging chips can be indium gallium arsenide (InGaAs) short-wave infrared imaging chips. InGaAs short-wave infrared imaging chips use InGaAs as the intrinsic layer and indium phosphide (InP) as the N-type or P-type doping layer. The band gap of the InGaAs intrinsic layer can be adjusted by varying the In and Ga content, making it well-suited for imaging applications in the 0.9-3μm short-wave infrared band. Given the lattice matching between InP and InGaAs (with In and Ga content of 53% and 47%, respectively), InGaAs short-wave infrared photoelectric imaging chips are typically formed by direct epitaxial growth on InP substrates. Their spectral response range is 0.9-1.7μm, and InGaAs short-wave infrared photoelectric imaging chips have extremely low dark current at room temperature.

[0040] However, current InGaAs short-wave infrared imaging chips have problems such as slow operating speed, expensive InP substrate cost, small InP wafer size and low yield.

[0041] To address these issues, InGaAs material can be grown heteroepitaxially on silicon substrates. However, the quality of heteroepitaxial InGaAs crystals is extremely poor, making it unsuitable for high-performance short-wave infrared imaging chips. Alternatively, a smart-cut process can be used to intelligently peel an InP substrate to form an indium phosphide-on-insulator (InPOI) substrate. However, current InPOI substrates contain a large amount of free parasitic charge, which introduces parasitic capacitance into short-wave infrared imaging chips fabricated using these substrates, severely impacting the imaging speed of InGaAs short-wave infrared imaging chips. Therefore, developing new short-wave infrared wafers is essential for developing ultra-high-speed InGaAs short-wave infrared imaging chips.

[0042] Based on this, the present application provides a method for manufacturing an InGaAs wafer. The method includes: forming a donor substrate, the donor substrate comprising a first substrate, an absorber layer, a first doping layer, and a bonding layer stacked in sequence, the absorber layer being made of InGaAs; the first doping layer having a first doping type or a second doping type, the first doping type being one of P-type and N-type doping, and the second doping type being the other of P-type and N-type doping, the first doping layer being made of InGaAs or InP; and the first substrate comprising at least a target layer, the target layer being made of InP. Forming an acceptor substrate, the acceptor substrate comprising a first silicon substrate, a trap-rich layer, and an insulating layer stacked in sequence, the trap-rich layer being an amorphous material composed of Group IV elements. Bonding the donor and acceptor substrates with the bonding layer facing the insulating layer, removing a portion of the first substrate, retaining the target layer, and doping the target layer to obtain a second doping layer. The doping type of the second doping layer is different from that of the first doping layer. This forms InP of different doping types on both sides of the absorber layer, ultimately forming an InGaAs wafer. The trap-rich layer in the InGaAs wafer can capture free parasitic charges in the insulating layer, bonding layer, first doping layer, absorption layer and second doping layer, thereby reducing parasitic capacitance. The RF array chip subsequently manufactured using the InGaAs wafer can have a higher imaging speed, thereby improving the performance of the RF array chip manufactured using the InGaAs wafer and achieving a higher chip operating speed.

[0043] In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0044] See also Figure 1 , which is a flow chart of a method for manufacturing an InGaAs wafer provided in an embodiment of the present application.

[0045] The method for manufacturing an InGaAs wafer provided in this embodiment includes the following steps:

[0046] S101 , forming a donor substrate 100 .

[0047] In the embodiment of the present application, the donor substrate 100 may include a first substrate 110, an absorption layer 120, a first doping layer 130 and a bonding layer 150 stacked in sequence. Figure 2 shown.

[0048] Specifically, the first substrate 110 includes at least a target layer 111, and the material of the target layer 111 is indium phosphide. The first substrate 110 can be a single layer or a stacked layer.

[0049] When the first substrate 110 is a single layer, the first substrate 110 may include only the target layer 111 , that is, the first substrate 110 is an InP substrate.

[0050] When the first substrate 110 is a stacked layer, the first substrate 110 may include a second silicon substrate 112, a first buffer layer 113, a second buffer layer 114, a third buffer layer 115, and a target layer 111 stacked in sequence. The second silicon substrate 112 may be a beveled silicon substrate, for example, a 6° beveled silicon substrate. The material of the first buffer layer is germanium 113, the material of the second buffer layer 114 is gallium arsenide, the material of the third buffer layer 115 is indium phosphide, and the target layer 111 is intrinsic indium phosphide. The first buffer layer 113, the second buffer layer 114, and the third buffer layer 115 may serve as buffer film layers between the second silicon substrate 112 and the target layer 111 to form a target layer 111 with higher crystal quality. When the first substrate 110 is a stacked layer, the cost is reduced compared to an InP substrate.

[0051] As an example, the thickness of the first buffer layer 113 may be 100-1400 nm, the thickness of the second buffer layer 114 may be 100-1400 nm, the thickness of the third buffer layer 115 may be 100-2000 nm, and the thickness of the target layer 111 may be 100-500 nm.

[0052] In the embodiment of the present application, the absorption layer 120 is used to respond to light in the short-wave infrared band. The material of the absorption layer 120 includes at least indium gallium arsenide, wherein the In and Ga contents are 53% and 47% respectively.

[0053] As an example, the thickness of the absorption layer 120 may be 500-3000 nm.

[0054] The absorption layer 120 may be composed of a single film layer or a stack of multiple film layers. In other words, the absorption layer 120 may be an intrinsic layer or a stacked layer. The details are described below.

[0055] In some embodiments, the absorption layer 120 may be an intrinsic layer, and the material of the intrinsic layer is InGaAs.

[0056] In some embodiments, the absorption layer 120 may be a stacked layer formed by alternately stacking the first target layer 121 and the second target layer 122. Figure 3 As shown. Thus, the first target layer 121 and the second target layer 122 are alternately stacked to form a quantum well structure, thereby improving the photosensitivity of the absorption layer 120. The material of the first target layer 121 is indium gallium arsenide, gallium arsenic phosphide, or gallium arsenic antimony, and the material of the second target layer 122 is indium phosphide, indium aluminum arsenide, aluminum gallium arsenide, indium aluminum gallium arsenide, or indium gallium arsenic phosphide.

[0057] As an example, the first target layer 121 is made of indium gallium arsenide, and the second target layer 122 is made of indium phosphide.

[0058] As another example, the first target layer 121 is made of InGaAs, and the second target layer 122 is made of InAlAs.

[0059] As another example, the first target layer 121 is made of InGaAs, and the second target layer 122 is made of AlGaAs.

[0060] As another example, the first target layer 121 is made of InGaAs, and the second target layer 122 is made of InAlGaAs.

[0061] As another example, the first target layer 121 is made of InGaAs, and the second target layer 122 is made of InGaAsP.

[0062] As another example, the first target layer 121 is GaAsP, and the second target layer 122 is InGaAs.

[0063] As another example, the first target layer 121 is made of gallium arsenide antimony, and the second target layer 122 is made of indium gallium arsenide.

[0064] In the embodiments of the present application, the doping type of the first doping layer 130 is the first doping type or the second doping type, and the material of the first doping layer 130 is indium gallium arsenide or indium phosphide. That is, the first doping layer 130 is doped indium gallium arsenide or indium phosphide and can function as an electron transport layer or a hole transport layer for charge response. When the material of the first doping layer 130 is indium gallium arsenide, the In and Ga contents are 53% and 47%, respectively. The first doping type is either P-type doping or N-type doping, and the second doping type is the other of P-type doping and N-type doping.

[0065] As an example, the first doping type is P-type doping, and the second doping type is N-type doping, and the first doping layer is P-type doping or N-type doping.

[0066] As another example, the first doping type is N-type doping and the second doping type is P-type doping, and the first doping layer is P-type doping or N-type doping.

[0067] The first doping layer 130 may be formed by an ion implantation process, an ion diffusion process, or an in-situ growth process.

[0068] As an example, the thickness of the first doping layer 130 may be 100-500 nm.

[0069] When the material of the first doped layer 130 is InGaAs, the resulting InGaAs wafer can be an InGaAs-on-Insulator (InGaAsOI) wafer. When the material of the first doped layer 130 is InP, the resulting InGaAs wafer can be an InP-on-Insulator (InPOI) wafer. In this case, regardless of whether the material of the first doped layer 130 is InGaAs or InP, both are derived from a large silicon substrate. The first doped layer 130 on the silicon substrate is formed using heteroepitaxial growth, which offers the advantage of low cost.

[0070] The bonding layer 150 is used to achieve bonding with the acceptor substrate 200. The bonding layer 150 may be made of aluminum oxide.

[0071] In practical applications, the target layer 111 , the absorption layer 120 and the first doping layer 130 may form a diode structure, and the diode structure is a vertical structure, realizing a vertical diode structure on an InGaAs wafer.

[0072] S102 , forming an acceptor substrate 200 .

[0073] In an embodiment of the present application, an acceptor substrate 200 may be formed. The acceptor substrate 200 includes a first silicon substrate 210, a trap-rich layer 220, and an insulating layer 230 stacked in sequence. Figure 4 shown.

[0074] Specifically, the resistance of the first silicon substrate 210 is greater than the target threshold, that is, the first silicon substrate 210 is a high-resistance substrate. The target threshold may be 0.5 kΩ.cm, for example, the resistance range of the first silicon substrate 210 is 0.5-1 kΩ.cm.

[0075] The trap-rich layer 220 can capture free parasitic charges in the insulating layer 230, bonding layer 150, first doped layer 130, absorption layer 120, second doped layer 140 formed using the target layer 111, and first silicon substrate 210, thereby reducing parasitic capacitance. This allows the RF array chip subsequently manufactured using the InGaAs wafer to achieve high imaging speeds and enable ultra-high-speed infrared imaging. The InGaAs wafer also maintains a very high resistivity, resulting in extremely high linearity and signal integrity for ultra-high-speed InGaAs short-wave infrared imaging chips.

[0076] The material of the trap-rich layer 220 is an amorphous material composed of Group IV elements. For example, the material of the trap-rich layer 220 is one or more of amorphous silicon, amorphous silicon tin, amorphous silicon germanium, amorphous germanium, and amorphous germanium tin. That is, the trap-rich layer 220 can be a single layer or a stacked layer. The thickness of the trap-rich layer 220 can be 200-500 nm. A thinner trap-rich layer 220 cannot effectively capture parasitic charges, while a thicker trap-rich layer 220 may affect the absorption of infrared light by the absorption layer 120.

[0077] The insulating layer 230 can be a single layer or a stacked layer. When the insulating layer 230 is a single layer, it can be a silicon oxide layer, specifically formed using a thermal oxidation process. When the insulating layer 220 is a stacked layer, it can include a first insulating layer and a second insulating layer, wherein the second insulating layer is located on the side of the first insulating layer away from the first silicon substrate 210, that is, the first insulating layer covers the first silicon substrate 210, and the second insulating layer covers the first insulating layer. The first insulating layer can be a silicon oxide layer, and the second insulating layer can be silicon oxide formed using tetraethyl orthosilicate (TEOS). Silicon oxide formed using tetraethyl orthosilicate (TEOS) has excellent film quality.

[0078] In practical applications, the insulating layer 230 and the bonding layer 150 form a distributed Bragg reflector, which is beneficial for improving the light response in a specific wavelength band.

[0079] As an example, the distributed Bragg reflector may include a silicon oxide layer, a silicon oxide layer formed using tetraethyl orthosilicate (TEOS), and an aluminum oxide layer stacked in sequence.

[0080] As another example, the distributed Bragg reflector includes a stacked silicon oxide layer and a polysilicon layer, that is, the bonding layer 150 may not be provided in the donor substrate 100, and the insulating layer 230 in the acceptor substrate 200 is a stacked silicon oxide layer and a polysilicon layer.

[0081] As another example, the distributed Bragg reflector includes a silicon oxide layer, a silicon nitride layer and a silicon oxide layer stacked in sequence, that is, the bonding layer 150 may not be provided in the donor substrate 100, and the insulating layer 230 in the acceptor substrate 200 is a silicon oxide layer, a silicon nitride layer and a silicon oxide layer stacked in sequence.

[0082] As another example, the distributed Bragg reflector includes stacked silicon oxide layers and silicon layers. That is, the bonding layer 150 may not be provided in the donor substrate 100, and the insulating layer 230 in the acceptor substrate 200 is a stacked silicon oxide layer and silicon layer.

[0083] S103 , the donor substrate 100 and the acceptor substrate 200 are bonded together with the bonding layer 150 facing the insulating layer 230 .

[0084] In the embodiment of the present application, after forming the donor substrate 100 and the acceptor substrate 200, the donor substrate 100 and the acceptor substrate 200 may be subjected to direct wafer bonding (Direct Wafer-bonding), referring to Figure 5 Specifically, during bonding, the donor substrate 100 and the acceptor substrate 200 are bonded in a direction in which the bonding layer 150 faces the insulating layer 230 , so that after bonding, the bonding layer 150 and the insulating layer 230 are in contact.

[0085] S104 , removing a portion of the first substrate 110 , and retaining the target layer 111 .

[0086] In an embodiment of the present application, after the donor substrate 100 and the acceptor substrate 200 are bonded, a portion of the thickness of the first substrate 110 may be removed.

[0087] When the first substrate 110 is a single layer, removing a portion of the thickness of the first substrate 110 is referred to as thinning the first substrate 110 , and the thinned first substrate 110 is the target layer 111 .

[0088] When the first substrate 110 is a stacked layer, the first substrate 110 may include a second silicon substrate 112, a first buffer layer 113, a second buffer layer 114, a third buffer layer 115, and a target layer 111 stacked in sequence. Therefore, after removing part of the first substrate 110, the second silicon substrate 112, the first buffer layer 113, the second buffer layer 114, and the third buffer layer 115 are removed, and the target layer 111 is retained. Figure 6 shown.

[0089] Specifically, the second silicon substrate 112 , the first buffer layer 113 , the second buffer layer 114 and the third buffer layer 115 may be removed by using a backside thinning process, a chemical mechanical polishing (CMP) process, a dry etching process or a wet etching process.

[0090] S105 , doping the target layer 111 to obtain a second doping layer 140 .

[0091] In the embodiment of the present application, after removing a portion of the thickness of the first substrate 110 and retaining the target layer 111, the target layer 111 can be doped to obtain a second doping layer 140. The doping type of the second doping layer 140 is different from the doping type of the first doping layer 130. Figure 7 shown.

[0092] Specifically, the target layer 111 may be doped using an ion implantation process or an ion diffusion process.

[0093] The first doping layer 130 and the second doping layer 140 are located on both sides of the absorption layer 120 and are of different doping types.

[0094] As an example, the first doping type is P-type doping and the second doping type is N-type doping, then the first doping layer 130 is a P-type doped germanium layer and the second doping layer 140 is an N-type doped germanium layer.

[0095] As another example, the first doping type is N-type doping and the second doping type is P-type doping, then the first doping layer 130 is an N-type doped germanium layer and the second doping layer 140 is a P-type doped germanium layer.

[0096] In summary, InGaAs wafers capable of ultra-high-speed infrared imaging offer the advantages of large wafer size and low mass production costs, making them considered a key technological approach to disrupting conventional InGaAs short-wave infrared imaging technology. The InGaAs wafer manufacturing method provided in the embodiments of this application can significantly advance the widespread application of short-wave infrared focal plane array chips in a variety of fields, possessing significant research significance and application value.

[0097] Based on the method for manufacturing an InGaAs wafer provided in the above embodiment, the embodiment of the present application further provides an InGaAs wafer, and its working principle is described in detail below with reference to the accompanying drawings.

[0098] See also Figure 7 , which is a schematic structural diagram of an InGaAs wafer provided in an embodiment of the present application.

[0099] The InGaAs wafer 1000 provided in this embodiment includes a first silicon substrate 210, a trap-rich layer 220, an insulating layer 230, a bonding layer 150, a first doping layer 130, an absorption layer 120, and a second doping layer 140, which are stacked in sequence. The absorption layer 120 is made of at least InGaAs, the first doping layer 130 is doped with a first doping type or a second doping type, the first doping type being one of P-type doping and N-type doping, and the second doping type being the other of P-type doping and N-type doping. The first doping layer 130 is made of InGaAs or InP, the second doping layer 140 is made of InP, and the doping type of the second doping layer 140 is different from that of the first doping layer 130. The trap-rich layer 220 is an amorphous material composed of Group IV elements.

[0100] Based on the method for manufacturing an InGaAs wafer provided in the above embodiment, the embodiment of the present application further provides a radio frequency array chip, and its working principle is described in detail below with reference to the accompanying drawings.

[0101] See also Figure 8 , which is a structural schematic diagram of a radio frequency array chip provided in an embodiment of the present application.

[0102] The radio frequency array chip provided in this embodiment includes a bonded InGaAs wafer 1000 and a readout circuit wafer 2000 .

[0103] InGaAs wafer 1000 includes a first silicon substrate 210, a trap-rich layer 220, an insulating layer 230, a bonding layer 150, a first doping layer 130, an absorption layer 120, and a second doping layer 140, which are stacked in sequence. The absorption layer 120 is made of at least InGaAs. The first doping layer 130 has a first doping type or a second doping type, where the first doping type is either P-type or N-type, and the second doping type is the other of P-type and N-type. The first doping layer 130 is made of InGaAs or InP, and the second doping layer 140 is made of InP. The doping type of the second doping layer 140 is different from that of the first doping layer 130. The trap-rich layer 220 is an amorphous material composed of Group IV elements.

[0104] The readout circuit wafer 2000 may include a circuit layer 2100 and a metal layer, wherein the metal layer includes a third metal layer 2200 and a fourth metal layer 2300 .

[0105] In an embodiment of the present application, a stacked structure consisting of a first doping layer 130, an absorption layer 120 and a third doping layer 140 includes a plurality of pixels 1200 and a plurality of grooves 1100, the pixels 1200 and the grooves 1100 are covered by a surface passivation layer 1300, the surface passivation layer 1300 located at the bottom of the groove 1100 has a first opening 1400, the first opening 1400 has a first metal layer 1600, the first metal layer 1600 is in contact with the first doping layer 130, the surface passivation layer 1300 located at the top of the pixel 1200 has a second opening 1500, the second opening 1500 has a second metal layer 1700, the second metal layer 1700 is in contact with the second doping layer 140, the third metal layer 2200 is in contact with the first metal layer 1600, and the fourth metal layer 2300 is in contact with the second metal layer 1700.

[0106] Based on the RF array chip provided in the above embodiment, the present application also provides a method for manufacturing the RF array chip, and its working principle is described in detail below with reference to the accompanying drawings.

[0107] See also Figure 9 , which is a flow chart of a method for manufacturing a radio frequency array chip provided in an embodiment of the present application.

[0108] The manufacturing method of the radio frequency array chip provided in this embodiment includes the following steps:

[0109] S201 , provide an InGaAs wafer 1000 and a readout circuit wafer 2000 .

[0110] In an embodiment of the present application, an InGaAs wafer 1000 includes a first silicon substrate 210, a trap-rich layer 220, an insulating layer 230, a bonding layer 150, a first doping layer 130, an absorption layer 120, and a second doping layer 140, which are stacked in sequence. The absorption layer 120 is made of at least InGaAs, the first doping layer 130 has a first doping type or a second doping type, the first doping type being one of P-type doping and N-type doping, and the second doping type being the other of P-type doping and N-type doping. The first doping layer 130 is made of InGaAs or InP, the second doping layer 140 is made of InP, and the doping type of the second doping layer 140 is different from that of the first doping layer 130. The trap-rich layer 220 is an amorphous material composed of Group IV elements.

[0111] The readout circuit wafer 2000 may include a circuit layer 2100 and a metal layer, wherein the metal layer includes a third metal layer 2200 and a fourth metal layer 2300 .

[0112] S202 , etching the first doping layer 130 , the absorption layer 120 and the second doping layer 140 to obtain a plurality of trenches 1100 .

[0113] In the embodiment of the present application, the first doping layer 130, the absorption layer 120 and the second doping layer 140 can be etched to obtain a plurality of grooves 1100. The depth of the grooves 1100 is less than the thickness of the diode structure formed by the first doping layer 130, the absorption layer 120 and the second doping layer 140. Specifically, the grooves 1100 penetrate the absorption layer 120 and the second doping layer 140, but do not penetrate the first doping layer 130. Figure 10 shown.

[0114] There are protrusions between adjacent grooves 1100, and the protrusions constitute picture elements 1200. Picture elements 1200 are the light response parts of the radio frequency array chip.

[0115] S203 , forming a surface passivation layer 1300 .

[0116] In the embodiment of the present application, a surface passivation layer 1300 may be formed, and the surface passivation layer 1300 covers the surface of the groove 1100 and the surface of the pixel 1200. Figure 11 As shown, it specifically covers the sidewalls and bottom of the trench 1100 and the top of the pixel 1200, wherein the bottom of the trench 1100 is determined by the direction of the first silicon substrate 210 toward the absorption layer 120, and the top of the pixel 1200 is also determined by the direction of the first silicon substrate 210 toward the absorption layer 120.

[0117] S204 , etching the surface passivation layer 1300 at the bottom of the trench 1100 to form a first opening 1400 , and forming a first metal layer 1600 in the first opening 1400 .

[0118] S205 , etching the surface passivation layer 1300 on the top of the pixel 1200 to form a second opening 1500 , and forming a second metal layer 1700 in the second opening 1500 .

[0119] In the embodiment of the present application, the surface passivation layer 1300 at the bottom of the trench 1100 and the top of the pixel 1200 can be etched separately to obtain a first opening 1400 and a second opening 1500. Figure 12 As shown, the first opening 1400 and the second opening 1500 penetrate the surface passivation layer 1300, respectively exposing the surfaces of the first doping layer 130 and the second doping layer 140. Then, a first metal layer 1600 and a second metal layer 1700 are formed in the first opening 1400 and the second opening 1500, respectively. The first metal layer 1600 contacts the first doping layer 130, and the second metal layer 1700 contacts the second doping layer 140. That is, the first metal layer 1600 can electrically lead the first doping layer 130, and the second metal layer 1600 can electrically lead the second doping layer 140. Figure 13 shown.

[0120] In actual applications, the process sequence for forming the first opening 1400 and the second opening 1500 can be determined according to actual conditions. Accordingly, the process sequence for forming the first metal layer 1600 and the second metal layer 1700 can also be determined according to actual conditions, and is not limited to the situation described in the embodiments of this application.

[0121] S206 , bonding the InGaAs wafer 1000 and the readout circuit wafer 2000 with the first metal layer 1600 and the second metal layer 1700 facing the readout circuit wafer 2000 .

[0122] In an embodiment of the present application, the InGaAs wafer 1000 and the readout circuit wafer 2000 can be bonded in a direction where the first metal layer 1600 and the second metal layer 1700 are directed toward the readout circuit wafer 2000. Specifically, bump bonding is performed on the InGaAs wafer 1000 and the readout circuit wafer 2000, so that the third metal layer 2200 contacts the first metal layer 1600 and the fourth metal layer 2300 contacts the second metal layer 1700. Figure 7 shown.

[0123] In practical applications, a portion of the first silicon substrate 210 or the entire first silicon substrate 210 may be removed. Figure 14 As shown, light can pass through the insulating layer 230, the trap-rich layer 220 and the bonding layer 150 to reach the pixel 1200, thereby achieving a photoresponse.

[0124] In summary, compared to ordinary InGaAs wafers, this application forms an RF InGaAs wafer by providing a trap-rich layer, which can achieve ultra-high-speed short-wave infrared imaging. In addition, the materials of the first doping layer, the absorption layer, and the second doping layer are all derived from a large-scale silicon substrate. The InGaAs or InP on the silicon substrate is formed by heteroepitaxial growth, which has the advantage of low cost. In addition, the RF array chip formed by the InGaAs wafer has a certain resonant cavity effect. Specifically, the stacked layer composed of the bonding layer and the insulating layer is conducive to the improvement of the photoresponsivity and quantum efficiency of the RF array chip formed by the InGaAs wafer.

[0125] Each embodiment in this specification is described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the structural embodiments are described briefly because they are generally similar to the method embodiments. For relevant parts, refer to the description of the method embodiments. Those skilled in the art can understand and implement the present invention without inventive effort.

[0126] The above is only a preferred embodiment of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above-disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of protection of the technical solution of the present application.

Claims

1. A method for manufacturing an InGaAs wafer, characterized in that: The method comprises: forming a donor substrate, the donor substrate comprising a first substrate, an absorption layer, a first doping layer, and a bonding layer stacked in sequence, the absorption layer comprising at least indium gallium arsenide, the first doping layer being of a first doping type or a second doping type, the first doping type being one of P-type doping and N-type doping, the second doping type being the other of P-type doping and N-type doping, the first doping layer being of indium gallium arsenide or indium phosphide, and the first substrate comprising at least a target layer being of indium phosphide; forming an acceptor substrate, the acceptor substrate comprising a first silicon substrate, a trap-rich layer, and an insulating layer stacked in sequence, wherein the trap-rich layer is an amorphous material composed of Group IV elements; bonding the donor substrate and the acceptor substrate in a direction where the bonding layer faces the insulating layer; removing a portion of the thickness of the first substrate and retaining the target layer; doping the target layer to obtain a second doping layer, wherein the doping type of the second doping layer is different from the doping type of the first doping layer; The material of the trap-rich layer is one or more of amorphous silicon tin, amorphous germanium, and amorphous germanium tin; The first substrate includes a second silicon substrate, a first buffer layer, a second buffer layer, a third buffer layer, and the target layer stacked in sequence, the first buffer layer is made of germanium, the second buffer layer is made of gallium arsenide, the third buffer layer is made of indium phosphide, and the second silicon substrate is a bevel-cut silicon substrate; The bonding layer and the insulating layer constitute a distributed Bragg reflector, which includes a silicon oxide layer, a silicon oxide layer formed using tetraethyl orthosilicate (TEOS), and an aluminum oxide layer stacked in sequence, or the distributed Bragg reflector includes a stacked silicon oxide layer and a polysilicon layer, or the distributed Bragg reflector includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence, or the distributed Bragg reflector includes a stacked silicon oxide layer and a silicon layer.

2. The method according to claim 1, characterized in that The absorption layer is a stacked layer, which is formed by alternating a first target layer and a second target layer. The material of the first target layer is indium gallium arsenide, gallium arsenic phosphide or gallium arsenic antimony, and the material of the second target layer is indium phosphide, indium aluminum arsenic, aluminum gallium arsenic, indium aluminum gallium arsenic or indium gallium arsenic phosphide.

3. The method according to claim 1, characterized in that The resistance of the first silicon substrate is greater than a target threshold.

4. An InGaAs wafer, characterized in that: Prepared by the method of any one of claims 1 to 3, comprising a first silicon substrate, a trap-rich layer, an insulating layer, a bonding layer, a first doping layer, an absorption layer, and a second doping layer stacked in sequence; the material of the absorption layer comprises at least indium gallium arsenide, the doping type of the first doping layer is a first doping type or a second doping type, the first doping type is one of P-type doping and N-type doping, the second doping type is the other of P-type doping and N-type doping, the material of the first doping layer is indium gallium arsenide or indium phosphide, the material of the second doping layer is indium phosphide, the doping type of the second doping layer is different from the doping type of the first doping layer, and the trap-rich layer is an amorphous material composed of Group IV elements.

5. A radio frequency array chip, characterized in that: include: The bonded InGaAs wafer and readout circuit wafer as claimed in claim 4; The InGaAs wafer comprises a first silicon substrate, a trap-rich layer, an insulating layer, a bonding layer, a first doping layer, an absorption layer, and a second doping layer stacked in sequence; the absorption layer is made of at least InGaAs, the first doping layer has a first doping type or a second doping type, the first doping type being one of P-type doping and N-type doping, and the second doping type being the other of P-type doping and N-type doping; the first doping layer is made of InGaAs or InP, the second doping layer is made of InP, the doping type of the second doping layer is different from the doping type of the first doping layer, and the trap-rich layer is an amorphous material composed of Group IV elements; the stacked structure formed by the first doping layer, the absorption layer, and the second doping layer comprises a plurality of pixels and a plurality of trenches, the pixels and the trenches being covered by a surface passivation layer, the surface passivation layer at the bottom of the trench having a first opening, the first opening having a first metal layer therein, the first metal layer being in contact with the first doping layer, the surface passivation layer at the top of the pixel having a second opening, the second opening having a second metal layer therein, the second metal layer being in contact with the second doping layer; The readout circuit wafer has a third metal layer and a fourth metal layer. The third metal layer contacts the first metal layer, and the fourth metal layer contacts the second metal layer.

6. A method for manufacturing a radio frequency array chip, characterized in that: The method comprises: Provided are an InGaAs wafer and a readout circuit wafer according to claim 4, wherein the InGaAs wafer comprises a first silicon substrate, a trap-rich layer, an insulating layer, a bonding layer, a first doped layer, an absorption layer, and a second doped layer stacked in sequence; the absorption layer comprises at least InGaAs, the first doped layer has a first doping type or a second doping type, the first doping type being one of P-type doping and N-type doping, and the second doping type being the other of P-type doping and N-type doping, the first doped layer is made of InGaAs or InP, the second doped layer is made of InP, the doping type of the second doped layer is different from the doping type of the first doped layer, and the trap-rich layer is an amorphous material composed of Group IV elements; Etching the first doping layer, the absorption layer, and the second doping layer to obtain a plurality of grooves, wherein the grooves do not penetrate the first doping layer, and protrusions between adjacent grooves constitute picture elements; forming a surface passivation layer, wherein the surface passivation layer covers the surface of the groove and the surface of the pixel; Etching the surface passivation layer at the bottom of the trench to form a first opening, and forming a first metal layer in the first opening, wherein the first metal layer is in contact with the first doping layer; Etching the surface passivation layer on the top of the pixel to form a second opening, forming a second metal layer in the second opening, wherein the second metal layer is in contact with the second doping layer; The InGaAs wafer and the readout circuit wafer are bonded in a direction where the first metal layer and the second metal layer are toward the readout circuit wafer. The readout circuit wafer has a third metal layer and a fourth metal layer. The third metal layer is in contact with the first metal layer, and the fourth metal layer is in contact with the second metal layer.

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