Backplane and method for pulse width modulation

Abstract

A backplane for driving a display includes a two-dimensional array of pixel drive circuits organized into a plurality of rows and a plurality of columns. The backplane has at least one shift register addressing component that includes a shift register chain formed from a plurality of control shift registers connected in series with and separated by equal-sized groups of non-control shift registers. Each control shift register controls a different one of a plurality of word lines, each word line connected with a row of pixel drive circuits. The backplane also includes a plurality of bit lines, each bit line connected with a column of pixel drive circuits. A shift register data sequence is input to a first one of the plurality of control shift registers and propagates through the shift register chain to control the plurality of word lines to load display values from the bit lines into the pixel drive circuits.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 221,536, filed July 14, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to a backplane for driving a pixel driving circuit array. Background Technology

[0004] Backplanes for display devices have been manufactured using various processes for many years. The market for such devices is highly competitive with other established companies that have established products in the market. Manufacturing display devices in monocrystalline silicon is relatively expensive. Summary of the Invention

[0005] In one embodiment, a backplane configured to drive a display includes: a pixel driving circuit array organized into multiple rows and columns, each pixel driving circuit including memory circuitry operable to receive and store a display value; a plurality of word lines, each word line connected to a pixel driving circuitry in a corresponding row of the rows; a plurality of bit lines, each bit line operable to present the display value to all pixel driving circuitry along a corresponding column of the columns; and at least one shift register addressing component. The shift register addressing component includes: a plurality of control shift registers, each of which has an output operable to control different word lines among the plurality of word lines; a plurality of non-control shift registers connected in series with the plurality of control shift registers to form a shift register chain, wherein a group of at least one of the plurality of non-control shift registers is logically located among the sequential control shift registers among the plurality of control shift registers; and a sequence input of a first control shift register among the plurality of control shift registers for receiving a shift register data sequence that controls the selection of the plurality of word lines during operation.

[0006] In another embodiment, a method of operating a two-dimensional display of display elements, the method comprising: providing a backplane for driving the two-dimensional display, the backplane including: a two-dimensional pixel driving circuit array organized into multiple rows and columns, wherein each pixel driving circuit includes: a corresponding memory circuit operable to receive and store a display value, and in operation, to generate an output based on the display value stored in the corresponding memory circuit, the output driving a display element of the two-dimensional display; a plurality of word lines, wherein each word line is connected to a pixel driving circuit of a corresponding row in the rows; a plurality of bit lines, wherein each bit line is operable to present the display value to all pixel driving circuits along a corresponding column in the columns; and a shift register addressing component including: a plurality of control shift registers, each of the control shift registers operable to... The system controls different word lines among the plurality of word lines based on data values ​​in the control shift register, wherein, in operation, by the action of one of the word lines, a memory circuit in the pixel driving circuit corresponding to at least a portion of a row in the row is selectively activated to receive a display value from the display value presented by the corresponding bit line in the memory circuit; and a plurality of non-control shift registers, which are not operable to control any word line among the word lines, wherein the control shift register and the non-control shift registers are connected in series in a shift register chain, wherein a group of one or more non-control shift registers among the non-control shift registers is logically arranged within the shift register chain, between consecutive shift registers in the control shift register, such that the data value propagates through both the control shift register and the non-control shift register in response to consecutive periods of a clock signal. The method further includes: in each cycle of the clock signal, inputting a data value from a shift register data sequence into a first control shift register among the plurality of control shift registers, wherein the shift register data sequence is arranged such that a maximum value of one of the control shift registers operates its corresponding word line during any period of the clock signal; and providing continuous cycles of the clock signal to the control shift registers and the non-control shift registers to propagate the data value through the shift register chain. Attached Figure Description

[0007] Figure 1A A schematic block diagram of a backplane suitable for driving an array of pixel driving circuits according to one or more embodiments is presented.

[0008] Figure 1B A schematic block diagram of a backplane having a shift register row addressing component according to one or more embodiments is presented.

[0009] Figure 1C A schematic block diagram of the shift register addressing component is presented, showing connections to rows on the backplane.

[0010] Figure 1D A schematic diagram and timing diagram of an OLED pixel driving circuit with pulse width modulation are presented.

[0011] Figure 2A A schematic block diagram of a modified shift register addressing component, including both a control shift register and a non-control shift register, is presented according to one or more embodiments.

[0012] Figure 2B A schematic block diagram of a row addressing implementation according to one or more embodiments is presented, wherein a first modified shift register addresses odd rows of the backplane, and a second modified shift register addresses even rows of the backplane.

[0013] Figure 2C A schematic block diagram of a modified shift register addressing component according to one or more embodiments is presented, wherein the selection device can select between a first number of uncontrolled shift registers and a second number of uncontrolled shift registers.

[0014] Figure 3A Presented are similar to one or more embodiments Figure 2A A schematic block diagram of the modified shift register addressing component.

[0015] Figure 3B The identifiers presented according to one or more embodiments include Figure 3A A description table of the types of components in the modified shift register addressing component.

[0016] Figure 3C Presented are methods that can be derived from one or more embodiments. Figure 3A A diagram of the write pointer implemented by the modified shift register addressing component.

[0017] Figure 3D Presented according to one or more embodiments by Figure 3C The write pointer generates a table of shift register data states for sequential time intervals.

[0018] Figure 3E , Figure 3F and Figure 3G Presented are descriptions of the application of one or more embodiments to the application of ... Figure 3C A table showing the data status of each shift register for the selected time interval.

[0019] Figure 3HAn unfavorable shift register data sequence was presented.

[0020] Figure 4A A graph of write pointer sequences according to one or more embodiments is presented, wherein the row span of the write pointer sequence exceeds... Figure 3A The number of rows on the back panel.

[0021] Figure 4B Presented according to one or more embodiments by Figure 4A The shift register data state generated by the write pointer sequence is a table of sequential time intervals.

[0022] Figure 4C , Figure 4D and Figure 4E Presented are descriptions of the application of one or more embodiments to the application of ... Figure 4A A table showing the data status of each shift register for the selected time interval.

[0023] Figure 5A , 5B And 5C presents a design according to one or more embodiments for Figure 3D A table showing the data status of each shift register during the first twenty-seven time intervals.

[0024] Figure 6 Depicting according to one or more embodiments Figure 3A A detailed schematic diagram of the shift register addressing component. Detailed Implementation

[0025] This disclosure relates to the design and use of a shift register assembly operable to control the writing of data to rows of a pixel drive circuitry array during a continuous time period. Advantageously, the data writing during the continuous time period can occur on non-adjacent rows and according to a predetermined pattern repeating downwards along the display, and optionally has a fixed row number offset between each instance of the pattern.

[0026] In some technologies, the cost of manufacturing display devices may be high enough to limit their use to applications where the high cost is offset by performance factors. Furthermore, the use of monocrystalline silicon can impose size limitations on display devices due to the constraints of one or more reticles used in the chosen manufacturing process. Therefore, it is desirable to find ways to extend the range of manufacturing technologies for display applications to other lower-cost materials.

[0027] One such material is low-temperature polycrystalline silicon, hereinafter referred to as LTPS. Another is indium gallium zinc oxide (IGZO). Other technologies are also known, such as amorphous silicon. Each can be used as part of a backplane with different degrees of charge mobility and therefore different degrees of operating bandwidth. Such materials are commonly used to form thin-film transistors (TFTs) on suitable glass or other types of substrates. The backplane described herein can be implemented in monocrystalline silicon, although other implementations using line decoders can be readily achieved.

[0028] One feature of some backplanes disclosed herein using any of the above techniques is that row write operations are triggered by using a shift register data sequence, which is input to a first shift register in a plurality of cascaded shift registers (e.g., a shift register chain) and passed clockwise through the shift register chain such that a different shift register in the chain triggers a row in a fixed sequence. For example, the input value may be a high state, operable to place the word line of the row in a state that allows the cell in the row to receive image data, while other values ​​in the shift register data sequence are placed low states that are inoperable to place the word lines of those rows in a state that allows the cell in the row to receive image data. This results in the display being written from top to bottom or from bottom to top as data values ​​move through the shift register chain. The image data of the pixels written to the row may include analog voltages varying among individual pixels or may include a relatively fixed voltage driving each pixel to the same level. In the latter case, the display may be pulse-width modulated to achieve intermediate values ​​along the grayscale. Pulse Width Modulation (PWM) is a method of driving a part of a display (e.g., pixel driver circuitry) to produce grayscale. In one type of PWM, varying grayscale levels are represented by multi-bit words (e.g., binary numbers). These multi-bit words are converted into a series of pulses. The time-averaged RMS voltage corresponds to the specific voltage necessary to maintain the desired grayscale level. A high state indicates that the word line is putting the associated pixel driver circuitry into a state of receiving image data, and a low state indicates that the word line is not putting the associated pixel driver circuitry into a state of receiving image data.

[0029] While this method works, it imposes some bandwidth limitations on the displayed image because once written, a row on the display cannot be changed until all other rows below it have been written, then the shift register turn-on state value starts at the top again and descends to that row. This limits the minimum duration of the least significant bit to the time required to write the entire array.

[0030] One constraint for many displays is size and power consumption. In known systems using PWM, a higher image write frequency improves modulation efficiency because the data for each pixel can be updated more frequently. However, the timing of displaying each bit of data also needs to be controlled, so higher frequencies don't always solve the control problem. Furthermore, high-speed drive circuitry is inevitably more expensive and draws more power from the system, factors that are undesirable in such circuit designs. Another way to improve modulation efficiency is to reduce the system's frame rate. However, a lower frame rate can significantly exacerbate flickering issues in the display, another undesirable effect. Therefore, it is desirable to increase the image write frequency in the display without increasing the frequency of the drive circuitry and without increasing system power consumption.

[0031] This document discloses a system and method for overcoming this limitation by using a line decoder component to select the lines to be written, such that the individual lines written sequentially in time do not need to be spatially adjacent, and can actually be operated in a predetermined arrangement forming a pattern. In most embodiments, the pattern is selected such that the interval between lines in the pattern is approximately proportional to the duration of the bit plane modulated on the line initiated by the passage of a first write pointer, which is subsequently rewritten by the passage of other write pointers of the pattern as they propagate down the line during subsequent time intervals.

[0032] Note that in a shift register-based backplane, the sequence of word lines being written can be moved from the last line to be written back to the first line originally intended to be written, such as non-adjacent lines. This is sometimes a result of the physical layout of the lines.

[0033] One aspect of this disclosure is a modified shift register assembly driven by a shift register data sequence that defines a row addressing pattern across time, resulting in non-contiguous row write operations at various intervals, wherein the duration of a series of bit planes is approximately determined by the intervals between rows. The bit planes can be determined by flattening an input signal (e.g., a video signal and / or an image stream). See U.S. Patent No. 6,144,356, entitled “System and Method for Data Planarization,” which is incorporated herein by reference in its entirety for all purposes.

[0034] Advantageously, compared to prior art backplanes that do not include shift register addressing components, by using flattening and PWM with modified shift register addressing components having multiple write pointers, lower voltages and / or lower clock speeds can be used on the backplane and display, simplifying the design, resulting in improved display quality, and using less power.

[0035] The applicant's prior patents relate to bit-plane architectures similar to the bit-plane architectures mentioned above. These patents include U.S. Patent Application No. 10 / 435,427, now U.S. Patent 8,421,828, a continuation of which is U.S. Patent Application No. 13 / 790,120, now U.S. Patent 9,583,031, and a continuation of which is U.S. Patent Application No. 15 / 408,869, now U.S. Patent 9,824,619, the contents of which are incorporated herein by reference for all purposes. Figures 7A, 7B, 8A, and 8B, and the associated specification texts in all these patents, are particularly illustrative. These patents are collectively referred to herein as the "MegaMod Patents." One objective of this embodiment is to implement modulation schemes similar to the modulation schemes of the MegaMod Patents in the backplane using previously described techniques—such as LTPS—without requiring the development of line decoder circuitry capable of implementing the line selection schemes of those techniques.

[0036] The modulation scheme discussed in the preceding paragraphs is characterized by the use of a row-addressing circuitry system capable of writing data to non-contiguous rows. The row to be written responds to a pattern of row write actions that can be repeatedly applied to rows of the array, wherein there is an offset between successive applications of the same pattern. The offset is typically one or two rows, depending on the details of the backplane, as explained below, but other offsets are conceivable and can be implemented by those skilled in the art upon reading and understanding this disclosure.

[0037] As the pattern of the row write operation advances through the rows of the display, a row having image data written to it in response to a first write pointer can then have different image data written to it in response to a second write pointer. Write pointer sequences comprising twenty or more write pointers have been designed. Simple examples are given in this application to aid understanding, but these examples should be understood not to limit the range of possible patterns and / or values ​​in the embodiments.

[0038] Using pulse width modulation (PWM) to modulate LTPS backplanes or similar devices provides the opportunity to use such backplanes with emitting devices such as organic light-emitting diode displays (OLEDs) or small conventional light-emitting diodes (LEDs)—sometimes called microLEDs or μLEDs. Using pulse width modulation at a constant voltage reduces the color shift in the emitted light that can occur when these devices are modulated with varying voltages.

[0039] It is conceivable that circuits may require DC balancing of the liquid crystal layer (e.g., liquid crystal display circuits) and circuits may not require DC balancing (e.g., micro light-emitting diode (μLED) circuits). These are collectively referred to as display elements. Typically, in these display applications, image data is written to a row of pixel driving circuits in response to the word line of that row being pulled high, enabling the memory circuitry of that row's pixel driving circuits to receive the image data served on the bit line.

[0040] These and other objects and advantages of the embodiments of this disclosure, as well as modifications and equivalents to those embodiments, will become clear to those skilled in the art after reading and understanding this detailed description and the accompanying drawings.

[0041] Figure 1A A block diagram of the data transmission portion and some external interfaces of an example backplane 100 is presented. Backplane 100 includes a pixel driver circuit array 101, a left shift register addressing component 105L for odd rows, a right shift register addressing component 105R for even rows, a column data register array 104L (bottom) for even rows, a column data register array 104U (top) for odd rows, a control block 103, and lead bonding pads 102L (bottom) and 102U (top). It should be understood that designating the shift register addressing component as "right" or "left" and the column data register array and lead bonding pad as "top" and "bottom" is for clarity of reference. Figure 1A This does not imply any limitation on the spatial layout or physical organization in the actual backplane. The wire bonding pad 102L provides contact with a flexible printed circuit assembly (FPCA) or other suitable connection device to receive data and control signals from the display controller circuitry via input, and may include one or more clock lines 111, one or more opcode lines 112, one or more signal lines 113, one or more temperature signal lines 114, and / or parallel data signal lines 115. Selected interfaces for the higher wire bonding pad 102U include circuit voltages V_H 116 and V_L 117, a temperature sensor digital interface 118, and a rail voltage V DD and V SS 119 and return voltage 120. As will be apparent to those skilled in the art, the function and polarity of these voltages depend on a number of factors that vary across different types of pixel drive circuits and / or process technologies.

[0042] The physical layout of the backplane components may differ from that depicted and remain within the scope of this disclosure. For example, only one shift register addressing component may be required, or all external connections may be along a single side of the backplane. In some embodiments, only one row data register is used to provide data to the pixel driving circuitry for both even and odd rows.

[0043] Lead bonding pad 102L receives image data and control signals and connects these signals to control block 103. Control block 103 receives image data and routes it to column data register array 104L (lower) or column data register array 104U (upper). In one embodiment, the value of operation code line 112 can determine which of the two shift register addressing components 105L or 105R is active.

[0044] Left shift register addressing component 105L (e.g., odd-numbered rows) and right shift register addressing component 105R (e.g., even-numbered rows) are configured to operate word lines. In operation, the data value in the shift register causes the row driver to place the corresponding word line in a state where image data for the corresponding row can be transferred from column data register array 104L and / or from column data register array 104U to the memory circuitry of the pixel cells in that row of the pixel driver circuitry array 101. In one embodiment, only one column data register array exists on the backplane.

[0045] Clock line 111 may include multiple lines carrying various clock signals. For example, a shift register addressing component may receive a clock signal HCLK from clock line 111 to advance the shift register data value. Additionally, the column data register may receive a clock signal CLK from the controller via clock line 111 as part of the process of transferring image data to the column data register.

[0046] Signal line 113 may include various signal lines, including reset functions for shift register addressing components 105L and 105R and separate reset functions for column data register arrays 104U and 104L. Signal line 113 may also include a separate line supplying data to one or both of the shift register addressing components 105L, 105R, while the other keeps the shift register addressing component synchronized with the image data on the row to be loaded onto the corresponding word line of the shift register addressing components 105L, 105R. Enable signals for activating components such as column data register arrays 104U, 104L, which might otherwise be in a standby state, are conceivable.

[0047] Figure 1B A block diagram of a backplane assembly 150 is shown, which has, in addition to Figure 1A Additional details beyond those shown. The backplane assembly 150 includes a substrate 155 (e.g., formed of glass or an alternative material), a pixel drive circuit array 151, a shift register addressing assembly 152, column drivers 154a, 154b, 154c and 154d, and a controller 153.

[0048] In some embodiments, a pixel drive circuit array 151 and a shift register addressing component 152 are formed in thin-film transistors (TFTs) on substrate 155 using techniques known in the art. Other components, such as controller 153 and column drivers 154a-154d, may be formed from small integrated circuits fabricated in monocrystalline silicon (or other material systems) surface-mounted to substrate 155.

[0049] Controller 153 delivers various signals and data to shift register addressing component 152 and column driver 154 of backplane assembly 150. For example, controller 153 may deliver HCLK to shift register addressing component 152 via line 156a, and / or deliver a shift register data sequence (e.g., R data or register data) via line 156b and / or deliver an RST (reset) signal via line 156c to shift register addressing component 152. Advantageously, the shift register data sequence is a single bit, and therefore uses less space and less power than prior art row decoder components that require multiple input bits. In some embodiments, HCLK advances data within shift register addressing component 152, R data provides a logic 1 or 0 to shift register addressing component 152, and RST can reset shift register addressing component 152. Controller 153 may route at least CLK, data (pixel data), and RST (reset) to column drivers 154a-154d via lines. Column drivers 154a-154d then deliver pixel data to the pixels of the row that is pulled up on the column drive line (not indicated). Figure 1C A simplified block diagram of a prior art backplane 170, including shift registers and shift register assembly 176 and row assembly 171, is presented. Row assembly 171 includes rows 172a-172e. Each of row drivers 174a-174e is connected to a corresponding one of rows 172a-172e. Shift register / row driver assembly 176 includes a set of shift registers 173a-173e coupled to row drivers 174a-174e, wherein for each row 172, there is one shift register 173 and one row driver 174. Each shift register 173 drives one row driver 174 when high. Each shift register 173 and its associated row driver 174 are formed in a single circuit. In this prior art backplane 170 (which uses shift registers to determine which row is activated to receive data from column registers), the number of shift registers is the same as the number of rows. Data from column registers (not shown) is delivered to all rows 172 via bit lines. Depending on the type of memory circuitry used in row 172, each column may require one or two bit lines.

[0050] The shift register data sequence is received via input 175. In the prior art, the shift register data sequence is typically a high data state, also known as a 1 state or 1 value for the first clock cycle of the HCLK clock signal at the start of a refresh cycle, followed by a low state for each remaining clock cycle of the refresh cycle. As the HCLK clock signal operates, the high data state propagates through shift register components 176, pulling the word lines of each consecutive row of 172a-172e high, as previously described.

[0051] In this disclosure, a high shift register data point enables the pixel driving circuitry of the corresponding row to receive image data asserted on the data line or bit line and place that image data into their respective memory circuitry. Typically, a signal on the gate of one or more transfer transistors in each memory circuitry is used to enable this. If the transfer transistor is an n-channel transistor, as is the case with the most common SRAM circuitry, the word line signal for the selected row is a high signal. If the transfer transistor is a p-channel transistor, the word line signal for the selected row is a voltage lower than the voltage on the unselected rows. In both cases, the signal that enables the transfer transistor to transfer image data is defined herein as a high state or a high data state, regardless of the actual voltage.

[0052] In most cases, the clock of shift register 173 is implemented as two non-overlapping clock signals that are substantially out of phase with each other. The duty cycle of either of these two non-overlapping clock signals can be appropriately set to allow for clock skew due to manufacturing tolerances of the process used.

[0053] To ensure that shift register assembly 176 functions correctly as a component of the display system, the shift register data sequence propagated through shift register 173 places only one shift register in a high data state at a time, since the data on the bit lines is intended for only one row. Therefore, if the length of the shift register data sequence is the same as the number of shift registers 173 in shift register assembly 176 configured to control the corresponding row drivers 174, only one shift register 173 is active at a time. If the shift register data sequence is longer than the number of shift registers 173 in shift register assembly 176, then more than one shift register 173 can be placed in a high data state, provided that only one of the two shift register data sequence points is high and they are spaced far apart in the sequence such that only one is placed on the shift register 173 operable to control one of the row drivers 174 to write data to said row. At least, this distance is at least the total number of shift registers 173 controlling the row drivers 174.

[0054] In some cases, the row controlled by a word line can be smaller than the entire row of the pixel driving circuitry. The remaining pixel driving circuitry can be controlled by one or more additional word lines that operate independently of the other word lines.

[0055] Figure 1D Presented Figure 1B A schematic diagram of an example pixel driving circuit 180(a) and timing diagram 180(b) of a pixel driving circuit array 151 with pulse width modulated current pixels. Figure 1D Taken from " A digitally driven pixel circuit with current compensation for AMOLED microdisplays (Digital Drive Pixel Circuit with Current Compensation for AMOLED Microdisplays), Yuan Ji et al., Journal of the Society for Information Display, Vol 22 / 9, pp. 465-472, San Jose, CA 2015. However, the following description is adapted from that reference.

[0056] The pixel driving circuit 180(a) includes two p-channel transistors T1 and T2 and a capacitor CS, and is therefore referred to herein as a 2T1C pixel driving circuit. Timing diagram 180(b) depicts a pulse train sequence that enables the pixel driving circuit 180(a) to emit current over a finite time period. The following description is taken directly from the text of the referenced paper just cited above. In the 2T1C pixel driving circuit 180(a), both T1 and T2 operate as switches. When the word line—here referred to as SEL—is low, T1 is off, and therefore T2 is turned on or off depending on the voltage level of node a driven by the bit line—here referred to as Data_line. When the word line SEL is high, T2 is off, and therefore the voltage level present at node a remains in CS. Therefore, the OLED pixel current I... OLED It is restricted to one of two states: on or off. I can be modulated by controlling the SEL and / or Data_line by changing the pulse width or density. OLED .

[0057] The signals supplied to word lines such as SEL can be adjusted depending on the details of the pixel driving circuitry used. In a classic 6-transistor SRAM cell (not shown), the gate transistors are two n-channel FETs that must be high so that the FETs conduct the data state present on the bit line to the SRAM cell. In the example of pixel driving circuitry 180(a), the word line SEL operates on a p-channel transistor, and the gate of that p-channel transistor must be brought low to conduct data from the Data_line to node a of the circuit. Both possibilities are considered in this application, and the use of terminology should be interpreted in this manner.

[0058] Figures 2A to 2C Hardware configurations of modified shift registers according to one or more embodiments are presented. Figures 3A to 3E It presents details on how shift registers can be manipulated, example sequences and constraints, and explains how the shift register data sequence can be determined.

[0059] Figure 2A This is a simplified block diagram of a backplane 200 having a modified shift register addressing component 206 according to one or more embodiments, the modified shift register addressing component 206 including both control shift registers and non-control shift registers. The backplane 200 includes the shift register addressing component 206 and a row component 201. The row component 201 includes rows 202a-202e. The shift register addressing component 206 includes row drivers 204a-204e, wherein each row driver 204a-204e drives a corresponding row 202a-202e of the row component 201. Figure 1C Unlike the prior art shown, the shift register addressing component 206 includes multiple shift registers 203 for each row 202. Data for the shift register addressing component 206 is received from the sequence generator 208a of the controller 207 via input 205. Each row driver 204a-204e is connected to a corresponding shift register 203a0-203e0, which is the only shift register that can put the row into a state of receiving data. The row drivers 204a-204e drive the word lines of the corresponding rows 202a-202e to a state operable so that the memory circuitry of the pixel driving circuitry of the row can receive new data, as described above. Figure 1DAs discussed above, shift registers 203a0-203e0 can be referred to as control shift registers. Other shift registers 203a1-203a3, 203b1-203b3, 203c1-203c3, 203d1-203d3, and 203e1-203e3 exist in the shift register sequence of shift register addressing component 206, but are not connected to the row driver and / or form word lines, and therefore do not place any row in a state to receive data via the column driver. Therefore, shift registers 203a1-203a3, 203b1-203b3, 203c1-203c3, 203d1-203d3, and 203e1-203e3 can be referred to as non-control shift registers. In some embodiments, sequence generator 208a loads a predefined shift register data sequence 190 (e.g., from a file, serial storage device, etc.). In other embodiments, controller 207 includes a programmable memory configured with shift register data sequence 190. Sequence generator 208a cooperates with column coordinator 208b within controller 207 to coordinate column data presented via column drivers 209a-209d, such that rows 202a-202e receive the correct data when in a data receiving state. For example, sequence generator 208a may send a row identifier determined by shift register data sequence 190 and the current position within the sequence to column coordinator 208b, such that column coordinator 208b places the data of the identified row on column drivers 209a-209d. In some embodiments, the activation of word lines by shift register data sequence 190 and row drivers 204a-204e is deterministic, thereby ensuring that input image data is arranged and fed to column drivers 209a-209d in the appropriate order, thus eliminating the need for additional coordination. That is, the shift register data sequence, and therefore the row activation order and timing, are known in advance, and the image data is assembled into the correct predetermined order based on this knowledge. Another consideration is finding the format of the image data. In general analog systems, voltage is stored on column drivers loaded into memory of the pixel driving circuitry. For TFTs, this is, for example, a single thin-film transistor. In digital systems, image data for each pixel is stored as a series of bit planes. The order in which these bit planes are presented to the view can have a significant impact on the perceived quality of the image. Therefore, the predetermined order of the image data is also based on the bit planes and write pointers defined within the shift register data sequence as described herein. Advantageously, the non-control shift register spatially partitions the data propagating within the shift register addressing component 206 to allow for greater control over the intervals and timing in the control of the row drivers 204a-204e.

[0060] Each row 202 is associated with only one control shift register, and the number of non-control shift registers following the control shift register associated with the first row is typically the same as the number of non-control shift registers following the shift registers of all other rows. In one possible exception, in one or more embodiments, the last control shift register (e.g., Figure 2A The number of uncontrolled shift registers following shift register 203e0 is zero (0). This is because there are no further row operations after shift register 203e0, and no additional shift registers are needed to provide data spacing within shift register addressing component 206. However, it may be beneficial to include uncontrolled shift registers after the last controlled shift register to improve manufacturing yield (e.g., by maintaining printing consistency in the lithography process). Furthermore, it may be beneficial to include uncontrolled shift registers after the last controlled shift register to ensure that the shift register chain maintains its existing propagation delay until the last controlled shift register, even though tail uncontrolled shift registers are logically unnecessary.

[0061] Figure 2B A second simplified block diagram of a backplane 210 according to one or more embodiments is presented, illustrating a row addressing implementation where a first modified shift register addresses the odd rows of the backplane, and a second modified shift register addresses the even rows of the backplane. Backplane 210 includes row components 211, a left shift register addressing component 216a operable to control data writing to the odd rows 212a, 212c, and 212e of row components 211, and a right shift register addressing component 216b operable to control data writing to the even rows 212b, 212d, and 212f of row components 211. One or more signals from a controller (not shown) can be applied to one or both of inputs 215a and 215b to determine when the left shift register addressing component 216a and the right shift register addressing component 216b are active. Clock signals (not shown) used to advance data within the shift register addressing components 216a and 216b can be operated in conjunction with selection signals. It should be understood that designating shift register addressing components 216a and 216b as "right" or "left" is merely for clear reference. Figure 2B This does not imply any limitation on the spatial layout or physical organization of the actual back panel beyond the details described herein.

[0062] In one embodiment, both the left shift register addressing component 216a and the right shift register addressing component 216b are active simultaneously. In such an instance, separate row data registers for the rows controlled by the left shift register addressing component 216a and the rows controlled by the right shift register addressing component 216b can be used simultaneously (e.g., see...). Figure 1AThe odd-column data register array 104U and the even-column data register array 104L are shown within the backplate 100.

[0063] In backplane 210, rows 212a, 212c, and 212e represent odd-numbered rows, while rows 212b, 212d, and 212f represent even-numbered rows. Left shift register addressing component 216a includes row drivers 214a, 214c, and 214e, which generate word lines for rows 212a, 212c, and 212e respectively in response to inputs received from control shift registers 213a0, 213c0, and 213e0. Non-control shift register 213a1 receives a data value from control shift register 213a0 in a first clock cycle, and non-control shift register 214a2 receives the same data value from non-control shift register 213a1 in a second clock cycle. In a third clock cycle, the data value from non-control shift register 213a2 is propagated to control shift register 213c0 via link 218a. In the fourth and fifth clock cycles, the state of control shift register 213c0 propagates to non-control shift register 213c1, and then to non-control shift register 213c2. In the sixth clock cycle, the state of non-control shift register 213c2 propagates to control shift register 213e0. In subsequent clock cycles, the data value from control shift register 213e0 can then propagate to non-control shift registers 213e1 and 213e2.

[0064] In embodiments where the control shift register 213e0 is the last control shift register in the left shift register addressing component 216a, the following non-control shift registers 213e1 and 213e2 may be omitted. In this case, when the output of the shift register chain is fed back to the controller (e.g., when the output from the end of the shift register chain is used to coordinate the timing of subsequent shift register input sequences), the backplane controller (not shown) can consider timing requirements to initiate the start of the next instance of the shift register data sequence. In embodiments where there is no feedback from the end of the shift register chain to the controller or the beginning of the shift register chain, the controller action does not need to differ depending on the presence of a last non-control shift register.

[0065] The operation of right shift register addressing component 216b is generally similar to that of left shift register addressing component 216a. Right shift register addressing component 216b includes row drivers 214b, 214d, and 214f, operable to operate the word lines of rows 212b, 212d, and 212f respectively in response to inputs received from control shift registers 213b0, 213d0, and 213f0. Non-control shift register 213b1 receives its data value from control shift register 213b0 in a first clock cycle, and non-control shift register 213b2 receives the same data value from non-control shift register 213b1 in a second clock cycle. In a third clock cycle, the data value from non-control shift register 213b2 is propagated to control shift register 213d0 via link 218b. In the fourth and fifth clock cycles, the data value of the control shift register is propagated to the non-control shift registers 213d1 and 213d2, respectively. In the sixth clock cycle, the data value of shift register 213d2 is propagated to the control shift register 213f0. In subsequent clock cycles, the data value of the control shift register 213f0 can then be propagated to the non-control shift registers 213f1 and 213f2.

[0066] In the previously described embodiment, where the control shift register 213f0 is the last control shift register in the right shift register addressing component 216b, the non-control shift registers 213f1 and 213f2 following the control shift register 213f0 can be omitted.

[0067] Note that in the illustrated embodiment, the left shift register addressing component 216a controls only the word lines of rows 214a, 214c, and 214e, and the right shift register addressing component 216b controls only the word lines of rows 214b, 214d, and 214f. These row distributions can optionally be hardwired to ensure that neither shift register addressing component controls the word lines of two immediately adjacent rows. This arrangement can be implemented as a hardware design decision and does not imply that non-adjacent rows are located arbitrarily.

[0068] Figure 2C A third simplified block diagram of example backplane 230 is presented, wherein the number of non-control shift registers following each control shift register in the sequence of shift register addressing components 236 can switch between four and two non-control shift registers. The actual number of shift registers in these two states is arbitrary and can be greater than or less than [the number of shift registers]. Figure 2C The number is shown in the example. Based on the principles disclosed herein, the number of states of the non-control shift registers that can be substituted can be greater than 2.

[0069] Backplane 230 includes row component 231 and shift register addressing component 236. Row component 231 includes five rows 232a, 232b, 232c, 232d, and 232e, each controlled by word lines generated by row drivers 234a, 234b, 234c, 234d, and 234e of shift register addressing component 236. Row drivers 234a, 234b, 234c, 234d, and 234e are operated via control shift registers 233a0, 233b0, 233c0, 233d0, and 233e0 of shift register addressing component 236, respectively. Shift register data sequences can be inserted into control shift register 233a0 via input 238.

[0070] The shift register addressing component 236 includes a set of non-control shift registers 233a1, 233a2, 233a3, and 233a4, configured to propagate the data value of the control shift register 233a0 over the next four clock cycles, and then, on the fifth clock cycle, propagate the data value of the non-control shift register 233a4 to one input of the multiplexer 237a. The data value of the non-control shift register 233a2 is also propagated to the other input of the multiplexer 237a.

[0071] The shift register addressing component 236 includes a set of uncontrolled shift registers 233b1, 233b2, 233b3, and 233b4; another set of uncontrolled shift registers 233c1, 233c2, 233c4, and 233c4; and another set of uncontrolled shift registers 233d1, 233d2, 233d3, and 233d4. Each of these sets operates in the manner previously described for the set of uncontrolled shift registers 233a1, 233a2, 233a3, and 233a4.

[0072] The operations of the non-control shift register groups 233e1, 233e2, 233e3, and 233e4 differ because they form part of the last row. In one embodiment, non-control shift registers 233e1, 233e2, 233e3, and 233e4 are absent, and the data shifted into the control shift register 233e0 ends the shift register operation. Because there are no rows other than row 232e, no corresponding multiplexer is required.

[0073] Multiplexers 237a, 237b, 237c, and 237d can be configured to select among inputs based on signals active on input 239. Each multiplexer is configured such that, in response to a first signal state active on input 239, multiplexer 237a selects a signal from uncontrolled shift register 233a2, multiplexer 237b selects a signal from uncontrolled shift register 233b2, multiplexer 237c selects a signal from uncontrolled shift register 233c2, and multiplexer 237d selects a signal from uncontrolled shift register 233d2. In response to a second signal state active on input 239, multiplexer 237a selects the signal from uncontrolled shift register 233a4, multiplexer 237b selects the signal from uncontrolled shift register 233b4, multiplexer 237c selects the signal from uncontrolled shift register 233c4, and multiplexer 237d selects the signal from uncontrolled shift register 233d4. Multiplexers 237a-237d allow selection of the number of uncontrolled shift registers following each controlled shift register.

[0074] Multiplexers 237a-237d increase the flexibility of otherwise hardwired shift register addressing components. The selection of the length of the non-control shift register can be done, for example, during initialization, to allow shorter shift register data sequences without increasing the dead time during which modulation does not occur. In some embodiments, the controller (e.g., Figure 2A The controller 207 can control input 239 to switch the length of the non-controlled shift register between displayed frames or when the effect is not visible on the display output. For example, switching from a longer shift register chain to a shorter shift register chain in conjunction with a slower clock rate can provide a change in state, such as switching to a nominal dark state of the display to reduce current flow. For example, changing the state of input 239 may require a reset of register 233 to allow generator 208a to initiate an alternative shift register data sequence on input 238.

[0075] Figures 3A to 3G An operational example of a specific shift register data sequence used with a specific shift register addressing component that includes both control shift registers and non-control shift registers is presented. Figure 3A A simplified block diagram of an example backplane 250, including shift register addressing component 256 and row component 255, is presented. The layout is chosen to facilitate cross-referencing between the various diagrams.

[0076] Row component 255 includes rows 252a, 252b, 252c, 252e, 252f, and 252g. Each row is connected to a corresponding one of the row drivers 254a, 254b, 254c, 254d, 254e, 254f, and 254g of shift register addressing component 256.

[0077] Each row driver 254a, 254b, 254c, 254d, 254e, 254f, and 254g is controlled by a corresponding control shift register 253a0, 253b0, 253c0, 253d0, 253e0, 253f0, and 253g0 in a manner similar to that described above. The row control shift register 253a0 receives a shift register data value via input 257, which determines the state of the word line (not shown) controlled by the row driver 254a. For example, the shift register data value is part of a shift register data sequence. The shift register data value is propagated through the shift registers of the shift register addressing component 256 in response to a series of clock signals (not shown). The clock signals cause the data value to propagate first to the non-control shift register 253a1, then to the non-control shift register 253a2. The next clock cycle propagates the data value to the control shift register 253b0, which determines the state of the row driver 254b. The next clock cycle causes the data value to first propagate to the uncontrolled shift register 253b1, and then to the uncontrolled shift register 253b2.

[0078] Further clock cycles propagate the shift register data value through control shift register 253c0, then through non-control shift registers 253c1 and 253c2, through control shift register 253d0, then through non-control shift registers 253d1 and 253d2, through control shift register 253e0, then through non-control shift registers 253e1 and 253e2, through control shift register 253f0, then through non-control shift registers 253f1 and 253f2, and finally through control shift register 253g0.

[0079] In one embodiment, there are no non-control shift registers 253g1 and 253g2, and the shift register data sequence ends after the control shift register 253g0. In one embodiment, after the first value of the shift register data sequence propagates to the control shift register 253g0, a delay equivalent to the time required to sequentially pass through the non-control shift registers 253g1 and 253g2 is observed, after which the first element of the shift register chain 253a0 receives a new instance of the shift register data value in the shift register data sequence via input 257.

[0080] Figure 3B An overview was presented. Figure 3ATable 270, which describes certain elements of the shift register addressing component 256, serves as an aid to further presentation of specific data sequences below. Table 270 will... Figure 3A The control shift register of the shift register addressing component 256 is placed in the column represented as shift register 0, and the non-control shift registers are placed in two columns, shift register 1 and shift register 2. The shift registers in each row are linked together, along with their corresponding columns. Figure 3A The logical arrangement is consistent throughout. The control shift registers in each row receive data values ​​from an external source, in the case of control shift register 253a0, or from the last non-control shift register of the previous row, in the case of all other control shift registers. The direction of data value movement is from left to right within each row, then from the last shift register in one row to shift register 0 in the next row. For example, control shift register 253a0 in row 0 propagates its data value to non-control shift register 253a1 in the next clock cycle. In the following clock cycle, non-control shift register 253a1 propagates its data value to non-control shift register 253a2. In the next clock cycle, non-control shift register 253a2 propagates its value to control shift register 253b0 in the second row. The rest of the shift register addressing component 256 operates in the same manner (with the exception of the last row, as described above). The order in which the non-control shift registers appear for each row is one of the distinguishing features among them, causing each shift register in a given row to be considered in a different group. exist Figure 3B In Explanation Table 270, all members of the control shift register group are found in column shift register 0, all members of the first non-control shift register group are found in the middle position of column shift register 1, and all members of the final non-control shift register group are found at the end position of column shift register 2. Therefore, the shift registers in each column represent a common type with similar operating order and function. The reason for this organization is discussed below.

[0081] It is important to note that the columns of the described shift registers are logical columns that may not be physically arranged in columns, but each shift register that is a member of the same column has the same relationship as the shift registers in adjacent columns. In this application, shift registers in all columns are considered logical columns, regardless of whether the columns are so indicated. Shift registers that are electrically connected to each other are considered logically adjacent or logically connected. Conversely, pixel driver circuits on the same row of the pixel driver circuit array are physically arranged in adjacent columns. This can be important because the pixel driver circuits perform modulation that converts electrical signals into an image. In addition to square or rectangular pixels, rhomboid and hexagonal pixels are contemplated in some embodiments, and the same modulation techniques as described herein can be used. Upon reading and understanding this disclosure, those skilled in the art will readily recognize many extensions, equivalents, and applications of the disclosed structures and techniques. Although Figure 3A The various shift registers of the backplane 250 are depicted as physical columns, and Figure 3B The corresponding information in Explanation Table 270 is organized into columns, but these schematic representations do not necessarily represent the physical layout of the underlying circuitry.

[0082] The shift register addressing components of the previous example can be organized in a manner similar to that described in Table 270. For example, in some embodiments, Figure 2A The shift registers of the shift register addressing component 206 can be organized into logical columns of control shift registers 203a0 to 203e0, logical columns of first intermediate non-control shift registers 203a1 to 203e1, logical columns of second intermediate non-control shift registers 203a2 to 203e2, and logical columns of final non-control shift registers 203a3 to 203e3. Each of the final non-control shift registers 203a3 to 203d3 passes its data value to the next row of the control shift register during the next clock cycle. Other shift register examples in this document can be organized similarly. The order of the control and non-control shift registers can be reversed without affecting the overall functionality of the shift register addressing component.

[0083] Figures 3C to 3H , Figures 4A to 4D ,and Figures 5A to 5C Tables are shown illustrating example operations over time in embodiments of this document, specifically illustrating how individual data values ​​of a shift register data sequence propagate through the shift register in response to a clock cycle, and how the shift register data sequence can be defined to enable rows to be written at different times. The time interval is defined as occurring once per clock cycle. In some of these tables, the values ​​contained in the shift register (e.g., Figure 2AThe diagram shows exemplary “1” and “0” data values ​​in shift registers 203a0…203a3, 203b0…203b3, 203c0…203c3, 203d0…203d3, 203e0…203e3. In other figures, certain patterns of data values ​​are represented as “write pointers.” A write pointer is a pattern of data values ​​in the shift register data sequence of the control and non-control shift registers within the shift register chain during a time interval, where the data value used to control the shift registers is fed to a logic “1” or high state by the row driver. The row driver then operates the word line of the corresponding row, causing that row to accept data fed by the bit line. Thus, when the write pointer is said to reside on a row at a particular time, that row is written.

[0084] Figure 3C The write pointer sequence table 275 is presented, which describes the shift register data sequence including multiple write pointers Wp0, Wp1, and Wp2. Figure 3A The propagation of data values ​​from backplane 250. Write pointer sequence table 275 represents 42 time intervals, where each time interval is one shift register clock cycle in which the shift register data sequence is advanced. In this example, Wp0 is input to input 257 at clock cycle 1, as shown in column 1 of write pointer sequence table 275. The row interval between write pointers Wp0 and Wp1 is one row, and Wp1 is input to input 257 at clock cycle 5, as shown in time interval 5 of write pointer sequence table 275. The row interval between write pointers Wp1 and Wp2 is two rows, and Wp2 is input to input 257 at clock cycle 12, and is shown in time interval 12 of write pointer sequence table 275. The row interval between write pointer Wp2 and the next instance of write pointer Wp0 (e.g., where the shift register data sequence repeats) is three rows, and Wp0 is input to input 257 at clock cycle 22, and is shown in time interval 22 of write pointer sequence table 275. To ensure that both rows are enabled simultaneously, the interval between Wp0 and Wp1 is four cycles (not three), because in clock cycle four, Wp0 propagates to enable row 2, as shown in time interval 4 of write pointer sequence table 275. Therefore, in write pointer sequence table 275, only zero or one write pointer appears in each time interval. This can be created for backplane 250. Figure 3C The write pointer sequence table 275, where the shift register data sequence input to input 257 (e.g., the row pointed to by the data) is determined by the row decoder circuitry and controller system. The following text illustrates how to... Figure 3A The shift register addressing component 256 creates a write pointer with the same pattern to achieve... Figure 1A The back panel is 100.

[0085] A bit plane defines the information to be displayed or output from a display device. For example, for each pixel driver circuit, a bit plane defines output settings or controls. In one example, a bit plane defines the pulse width modulation duration of the pixel driver circuit. In some embodiments, each write pointer may correspond to a specific bit plane. A write pointer Wp0 that writes to a row is considered to initiate bit plane 0 on that row. Bit plane 0 terminates when a subsequent write pointer writes to the same row. Figure 3C In the example, bit plane 0 is initiated when write pointer Wp0 writes row 252a (as designated row 1 of write pointer sequence list 275) during time interval 1, and terminates when write pointer Wp1 writes row 252a during time interval 5. This concept can be extended to other write pointers, such as Wp1 and Wp2, as further described below. The duration of bit plane 0 is 4 time intervals. The duration of bit plane 1 (associated with the time span between Wp1 and Wp2) is 7 time intervals, and the duration of bit plane 2 (associated with the time span between another instance of Wp2 and Wp0) is 10 time intervals. The relationship between row intervals and durations is not linear, but it is monotonic. The applicant's prior experience has shown that linearity increases with both the number of rows in the array and the number of write pointers.

[0086] Write pointer sequence table 275 begins with write pointer Wp0 at time interval 1 in row 1. No write operations occur in time intervals 2 and 3 because the shift register data sequence has just begun (e.g., the duration of bit plane 0 has not yet expired in row 1, and rows 2 and higher have not yet been written). Write pointer Wp0 is again written to row 2 at time interval 4, followed by write pointer Wp1 at row 1 in time interval 5, which terminates the data value set by write pointer Wp0 at time interval 1. Time interval 6 has no write operation because the duration of bit plane 1 has not yet expired in row 1, the duration of bit plane 0 has not yet expired in row 2, and rows 3 and higher have not yet been written. Write pointer Wp0 is then written to row 3 in time interval 7, followed by write pointer Wp1 at row 2 in time interval 8, which terminates the data state set by write pointer Wp0 at row 2 in time interval 4. No write operation occurs in time interval 9 for similar reasons to time interval 6. Write pointer Wp0 is then written to line 4 in time interval 10, followed by write pointer Wp1 in line 3 in time interval 11, and write pointer Wp2 in line 1 in time interval 12. Write pointer Wp1 in line 3 in time interval 11 terminates the data value set by write pointer Wp0 in line 3 in time interval 7, and write pointer Wp2 terminates the data value set by write pointer Wp1 in line 1 in time interval 5. At this point, all three write pointers have been introduced, and therefore the full range of modulation allowed by the three write pointers across the seven lines is now fully active.

[0087] The above pattern is maintained for subsequent time intervals. When the write pointer reaches the last row of the array—in this case, row 7—the next instance of the write pointer occurs on the top row of the array, in the next time interval in which the write pointer will appear. The pattern of write pointers Wp0, Wp1, and Wp2 is repeated again on the same row in time intervals 10, 11, and 12, starting at time interval 31.

[0088] therefore, Figure 3C Table 275, describing the write pointer sequence, illustrates how line spacing can be used to generate grayscale by propagating a pattern of write pointers across consecutive lines of the display over time. When using this modulation method, no two lines on the display are at exactly the same modulation point at any given time interval. Note that when the shift register data sequence (not shown) is passed down in response to a series of clock cycles, such as... Figure 1CThe backplane of the prior art backplane 170 is typically written from top to bottom in a series of operations. While functional, this is insufficient to generate grayscale in a single pass unless all pixel circuitry (not shown) of the row is analog and receives analog data. Generating grayscale using a pulse-width modulation scheme with the prior art backplane 170 requires many consecutive writes to the entire backplane, where the shortest write defines the least significant bit of image data that can be displayed. This is inefficient compared to the modulation method described in the MegaMod patent, which discloses a method that supports more uniform data bandwidth requirements without significant peaks and troughs in data transmission, achieving the same modulation objective.

[0089] Through analysis Figure 3C The selected time intervals of the write pointer sequence table 275 are used to illustrate the temporal relationship between the modulation of adjacent rows of the display. At time interval 21, the write pointer Wp2 for row 2 is at the 7th time interval out of 10 time intervals from time interval 15 until that row is rewritten; the write pointer Wp2 for row 3 is at the 4th time interval out of 10 time intervals from time interval 18 until that row is rewritten; and the write pointer Wp2 for row 4 is at its first time interval out of 10 time intervals until that row is rewritten. The rewrite action terminates the previous data state and initiates a new data state. The previous data state and the new data state that replaces it may be the same or different.

[0090] In the second example, at time interval 23, the write pointer Wp1 for line 5 is at the 7th time interval out of 7 time intervals, the write pointer Wp1 for line 6 is at the 4th time interval out of 7 time intervals starting at time interval 20, and the write pointer Wp1 for line 7 is at the 1st time interval out of 7 time intervals. This analysis spans all lines and time slots and shows how adjacent lines are not precisely in the same modulation state.

[0091] Combined with the above Figure 1C Compared to the modulation method described in the prior art backplane 170, another advantage of this modulation method is that it allows for a shorter duration of the least significant bit (LSB). Assuming a seven-line backplane (not shown) instead of the five lines of the prior art backplane 170, an LSB starting on the first line does not end until all other lines have been written and that line is then rewritten. Therefore, the minimum duration of the LSB is seven time intervals. Some types of dithering can be applied to reduce this, but these involve additional controller software. The above analysis teaches that a minimum duration LSB of four time intervals is possible, where... Figure 3A The back panel 250 is for Figure 3CIt operates as described. When the backplane includes a significantly larger number of rows, the advantage of being able to generate least significant bits with a shorter duration than that required to write the entire array is significant and advantageous.

[0092] These advantages and features are important because they allow for the efficient operation of a properly configured backplane.

[0093] Figure 3D The shift register data sequence table 280 is presented, which describes the shift register data sequence when used. Figure 3C When writing the pointer sequence as described in the document, Figure 3A An alternative view of the complete set of data values ​​for all seven rows of the shift register data sequence on the backplane 250. Shift register data sequence table 280 shows how data propagates through... Figure 3A The backplane 250 shows the physical layout of the shift registers and thus indicates when data is written to the rows driven by the control shift registers 253a0, 253b0, ..., 253g0. Across each time interval from left to right, the value of each time interval and row combination represents three values, 0 or 1 or a combination thereof, representing the value in the control shift register in each block, followed by the values ​​in the two non-control shift registers, in the same order as depicted in the backplane 250. Figure 3A The initial data values ​​of all shift registers 253 in the shift register addressing component 256 can be set to the data value 0 by a reset function.

[0094] Note that the previous example showed the movement of a single shift register data value through a series of shift registers. In reality, a series of combined data values ​​from all shift registers move through the shift registers in response to a clock signal. Values ​​in the shift register data sequence can be set to cause shift register 253 of shift register addressing component 256 to operate in a desired manner.

[0095] In the first example of shift register data sequence table 280, shift register data sequences in rows 1 and 2 are discussed, from time interval 1 to time interval 12, followed by selected additional time intervals. Each set of data values ​​in row 252 is presented as ABC, where A is the data value in the control shift register of the indicated row, and B and C are the data values ​​in the non-control shift registers of the indicated row. Thus, row 1 in time interval 1 shows a data value of 100, meaning that control shift register 253a0 is set to 1, while non-control shift registers 253a1 and 253a2 are set to 0. In time interval 2, the shift register data sequence moves one shift register by a clock signal and reads row 1 of shift register data sequence table 280. Thus, control shift register 253a0 is set to 0, non-control shift register 253a1 is set to 1, and non-control shift register 253a2 is set to 0. The data value 0 in the non-control shift register 253a2 is moved to the control shift register 253b0 on row 2, and so on, but in this example only the previous data value 0 is replaced. Note that because no entry in time interval 2 begins with the data value 1, no control shift register is active, and no write to the array occurs.

[0096] In time interval 3, the shift register data sequence is shifted by one shift register via a clock signal, causing the data value for time interval 3 to begin with 001 in row 1. Therefore, control shift register 253a0 and non-control shift register 253a1 are each set to 0, and non-control shift register 253a2 is set to 1. Because no entry in time interval 3 begins with the data value 1, no control shift register is active, and no writes to the array occur.

[0097] In time interval 4, the shift register data sequence is shifted by the clock signal, causing the data values ​​for time interval 4 in rows 1 and 2 to begin with 000 100. Therefore, the control shift register 253a0 and the non-control shift registers 253a1 and 253a2 in row 1 are both set to 0, and the control shift register 253b0 in row 2 is set to 1. This is consistent with... Figure 3C The write pointer sequence is consistent with 275.

[0098] In time interval 5, the shift register data sequence is shifted by one shift register by the clock signal, such that the data value for time interval 5 begins with 100 010 in rows 1 and 2. Control shift register 253a0 is set to 1, and non-control shift registers 253a1 and 253a2 are set to 0, just like control shift register 253b0. Non-control shift register 253b1 is set to 1, and non-control shift register 253b2 is set to 0.

[0099] Similar to time intervals 2 and 3, time interval 6 does not have an active control shift register. Time intervals 7 and 8 repeat the pattern of write pointers Wp0 and Wp1 previously shown in rows 2 and 1 of time intervals 4 and 5 on rows 3 and 2, so they can be considered to provide a write action offset by one row compared to the data values ​​of time intervals 4 and 5.

[0100] Similar to time intervals 2, 3, and 6, time interval 9 does not have an active control shift register. Time intervals 10 and 11 repeat the patterns previously indicated for time intervals 4 and 4 and for time intervals 7 and 8 for write pointers Wp0 and Wp1, with an offset of one line compared to the nearest previous instance at time intervals 7 and 8. In time interval 12, write pointer Wp2 is written with a two-line offset compared to the nearest instance of write pointer Wp1 in time interval 11. At this point, all three write pointers now exist. Figure 3A On the back panel of the 250 system.

[0101] An examination of the shift register data sequence revealed that no time interval higher than time interval 9 contained any instances where no write operation occurred. There were also no instances where more than one row had been written (e.g., in one of the control shift registers 253a0, 253b0, ..., 253g0, whose word line was pulled high with the data value 1). The write pointer sequence found in time intervals 10, 11, and 12 was then repeated at time intervals 31, 32, and 33, where write pointer Wp0 was at row 4 in time interval 10, write pointer Wp1 was at row 3 in time interval 11, and write pointer Wp2 was at row 1 in time interval 12. This repetition occurred because when a write pointer reached row 7 (e.g., row 252g), its next instance occurred at row 1 (e.g., row 252a).

[0102] For example, the write pointer Wp0 on row 7 (252g) at time interval 19 then appears on row 1 (252a) at time interval 22. It should also be noted that bit plane 0 (not shown) of row 7 (252g) which begins at time interval 19 terminates after 4 time intervals, that is, when the write pointer Wp1 is written to row 7 (252g) in time interval 23.

[0103] Figure 3D The shift register data sequence table 280 shows Figure 3CThe write pointers are presented in the write pointer sequence table 275. All points in a row that have write pointers in the write pointer sequence 275 (e.g., the intersection of a row and a time interval) have a 100 at the same point (row and time interval) in the shift register data sequence table 280, indicating that the control write pointer at that point makes the word line high, and both non-control shift registers have 0 data values. Note that a sequence at any point of 111 is not prohibited, but it may not be useful for practical modulation based on shift register data sequence schemes. In the case of a 111 sequence, the corresponding row component will experience two short bursts and one very long burst, which will not result in significant grayscale production.

[0104] The previous examples illustrated the construction of shift register data sequences that can be used to operate non-contiguous word lines in a time-ordered manner to produce grayscale modulation. Each available shift register data sequence has properties that can be used to develop other available shift register data sequences.

[0105] Construction of the shift register addressing component for use in this invention—such as Figure 3A The construction of the shift register addressing component 256 presupposes that each row of the display has a row driver (e.g., row drivers 254a-254g) controlled by a single control shift register (e.g., control shift registers 253a0-253g0). Each row driver 254a to row driver 254g controls a word line (not shown) of the corresponding row 252a-252g of the row component 255. Each row of the shift register addressing component 256 further includes the same number of non-control shift registers (with a possible exception for the last row). Figure 3A In an example of shift register addressing component 256, each row includes first non-control shift registers 253a1 to 253g1 that receive their data values ​​from corresponding control shift registers 253a0 to 253g0 during each clock cycle, and also includes second non-control shift registers 253a2 to 253g2 that receive their data values ​​from adjacent first non-control shift registers in the same row during each clock cycle. The shift register data sequence advances from the second non-control shift registers (e.g., 253a2-253f2) of each row to the control shift registers 253b0 to 253g0 of the next row.

[0106] What happens in the last line depends on the presence of optional uncontrolled shift registers 253g1 and 253g2. In some embodiments where uncontrolled shift registers 253g1 and 253g2 are present, the two shift registers can operate as described above, and the shift register data value in uncontrolled shift register 253g2 can be applied to the input of control shift register 253a0 in response to a clock cycle. When uncontrolled shift registers 253g1 and 253g2 are not present, other circuitry typically provides data values ​​to control shift register 253a0.

[0107] There are reasonable reasons to desire tighter timing of the shift register addressing component 256 compared to using LTPS or other related materials alone. Monocrystalline silicon has excellent timing performance, thus there are some advantages to not having uncontrolled shift registers 253g1 and 253g2 in the loop for timing purposes. This function can be performed by the display controller (not shown) as previously described. Typically, a time delay equal to the time required for both uncontrolled shift registers 253g1 and 253g2 to pass clockwise is generated, although some adjustments can be made to keep the modulation synchronized with the incoming data.

[0108] Backplane 250 enables shift register row addressing configurable to control modulation. A shift register data sequence is defined for a specific shift register arrangement to achieve the desired modulation. For example, in one embodiment, the shift register data sequence is arranged such that no more than one word line in the shift register arrangement is high at any given time interval. In embodiments with separate column register components, for example, one column register component feeds data to even rows and another column register component feeds data to odd rows, this limitation can still be applied to separate sets of even and odd rows.

[0109] Figure 3E , Figure 3F and Figure 3G The table presents detailed data values ​​285, 290, and 295, which are... Figure 3D Table 280 provides a more detailed table of shift register data values ​​from time interval 6 to time interval 32. Figure 3E Table 285 includes detailed data values ​​for time intervals 6 to 14; Figure 3F Table 290 includes detailed data values ​​for time intervals 15 to 23; and Figure 3GTable 295 includes detailed data values ​​for time intervals 24 to 32. The limited number of time intervals presented is sufficient to illustrate the advantages of a shift register data sequence operable to pulse-width modulate a backplane comprising multiple rows constructed with modified shift register addressing components. It will be shown that a particular shift register data sequence is operable to activate non-adjacent rows in a time-ordered sequence by controlling the activation of word lines of the non-adjacent rows. Note that some rows in the sequence may be adjacent to each other, but not all rows need to be adjacent to each other.

[0110] Figure 3E , Figure 3F and Figure 3G The header fields SReg 0, SReg 1, and SReg 2 describe how data values ​​are propagated. Figure 3A The shift register addressing component 256 comprises a control shift register, a first non-control shift register, and a second non-control shift register in each row. The entries under SReg 0 correspond to each time interval in the recorded time interval (e.g., Figure 3B The data values ​​in the control shift registers 253a0, 253b0, 253c0, 253d0, 253e0, 253f0, and 253g0 at all shift registers listed in column 0 of description table 270. The entries under SReg 1 correspond to the data values ​​of the first non-control shift registers (e.g., as listed in column 1 of description table 270), and the entries under SReg 2 correspond to the data values ​​of the second non-control shift registers (e.g., as listed in column 2 of description table 270). Figure 3E , Figure 3F and Figure 3G The row corresponds to Figure 3B The rows listed in the table.

[0111] In the first comparison point, Figure 3E The detailed data values ​​in table 285, time intervals 6 and 9, both display the value of SReg 0 for all rows as 0, compared to... Figure 3D The shift register data sequence table 280 is consistent with the above description, which explains that neither time intervals 6 nor 9 involve write operations.

[0112] Check Figure 3CThe write pointer sequence table 275 is used for time intervals 10, 11, and 12. At time interval 10, write pointer Wp0 is found in row 4; at time interval 11, write pointer Wp1 is found in row 3; and at time interval 12, write pointer Wp2 is found in row 1. This is compared to the detailed data value table 285 for the same time intervals. Data value 1 is found in row 4 at time interval 10, in row 3 at time interval 11, and in row 1 at time interval 12. Therefore, the position and timing of the data values ​​shown in the detailed data value table 285 reflect the positions of write pointers Wp0, Wp1, and Wp2 in the write pointer sequence table 275.

[0113] In detailed data value table 285, data value 1 indicates that the word line of the row is high (or low, depending on the design of the memory circuitry of the pixel driver circuitry for that row), thus allowing data to be written to the memory circuitry of that row. First, examine the write pointer Wp0, which writes row 4 at time interval 10. Figure 3C The write pointer sequence table 275 is then used, and next, at time interval 14, row 4 is written by write pointer Wp1. Looking at the detailed data value table 285 at time interval 14, SReg 0 is high again. Checks at time intervals 11, 12, and 13 reveal that row 4 of SReg 0 was not written during those time intervals; therefore, the data value of the memory circuitry for row 4 established at time interval 10 remains unchanged until time interval 14.

[0114] according to Figure 3C The write pointer sequence table 275 shows that write pointer Wp1 writes row 3 at time interval 11. Next, at time interval 18, row 3 is written via write pointer Wp2, and no additional data is written to that row. This is compared to... Figure 3E The detailed data values ​​in Table 285, including the data values ​​for time interval 11, and Figure 3F The detailed data values ​​in table 290 are compared with the data for time interval 18. SReg 0 for time interval 11 has 1 in row 3, and SReg 0 for time interval 18 also has 1 in row 3. Under SReg 0, there is no intervening time interval with 1 in row 3. This will cause the write pointer Wp1 in row 3 at time interval 11 to... Figure 3E The detailed data values ​​in table 285, at time interval 11, presented in row 3, are completely correlated, and will also be in Figure 3C The write pointer Wp2 at row 3 at time interval 18 on write pointer sequence table 275 is related to the data presented at row 3 at time interval 18 on detailed data value table 290.

[0115] Further analysis of the write pointers that generate write pointer sequence table 275 and... Figure 3EDetailed data value table 285 Figure 3F 290 and Figure 3G The same results are presented between the data on 295. Therefore, it is shown that a shift register data sequence can be developed that, when used on the modified shift register addressing component disclosed in this application, is operable to apply a pulse width modulation scheme that creates grayscale by using various line intervals between subsequent write pointers.

[0116] Regarding write pointer sequence list 275, a repeating pattern with row offsets between repetitions is clearly shown. For example, the pattern for time intervals 10, 11, and 12 shows write pointer Wp1 at row 4, write pointer Wp1 one row above write pointer Wp0 at row 3, and write pointer Wp2 two rows above write pointer Wp1 at row 1. This pattern repeats with a row offset starting at time interval 13, where write pointer Wp0 is shown at row 5, one row below write pointer Wp0 at time interval 10, followed by write pointer Wp1 at row 4 in time interval 14, one row below write pointer Wp1 at row 3 in time interval 11, then write pointer Wp2 at row 2 in time interval 14, and one row below write pointer Wp2 at row 1 in time interval 12. This pattern repeats for time intervals 16, 17, and 18, and for time intervals 19, 20, and 21. At time interval 22, there is no line 8 to which the write pointer Wp0 has moved, so instead, the write pointer Wp0 restarts on line 1 during that time interval.

[0117] Therefore, Tables 270, 275, and 280 are fully correlated with detailed data value tables 285 and 290 at each point. The correspondence for time intervals 10, 11, and 12 has been shown. Detailed data value table 285 shows SReg 0, which has a data value of 1 in row 5 at time interval 13 and a data value of 1 in row 4 at time interval 14. Detailed data status table 290 shows SReg 0, which has a data value of 1 in row 2 at time interval 15.

[0118] The correspondence between data tables 270, 275, 280, and 290 for time intervals 16, 17, and 18, and for time intervals 19, 20, and 21, can be shown in a similar manner. At time interval 19 in write pointer sequence table 275, write pointer Wp0 appears on line 7 (e.g., Figure 3A (The last line of the backplane 250). The next instance of the write pointer Wp0 is found at time interval 22 on line 1. The correlation with the detailed data value table 290 holds, because data value 1 is found on SReg0 at that time interval.

[0119] The previous example demonstrated how line spacing produces grayscale when using a modified shift register addressing component, wherein the modified shift register addressing component includes a control shift register—one per line—that can pull word lines high or has already pulled word lines high when the control shift register is brought high, and the modified shift register addressing component also includes non-control shift registers, wherein the number of non-control shift registers is the same for each line (possibly except for the last line, where the number of non-control shift registers after the last control shift register may be zero).

[0120] Figure 3E , Figure 3F and Figure 3G The detailed data values ​​presented in Tables 285, 290, and 295 illustrate data that can be advantageously used to successfully achieve, for example... Figure 3D The constraints of the shift register data sequence shown in shift register data sequence table 280.

[0121] In each time interval of detailed data value tables 285, 290, and 295, no more than one of SReg 0, SReg 1, and SReg 2 contains the value 1. As a first example, consider the three columns of time interval 6 in detailed data value table 285. The first column, SReg 0, does not have a shift register containing the value 1; column SReg 1 has a shift register containing the value 1 only in row 1, and column SReg 2 has a shift register containing the value 1 only in row 2. Considering time interval 11, the shift register data value in SReg 0 is 1 in row 3; the shift register data value in SReg 1 is 1 in row 4, and the shift register data value in SReg 2 is not 1 in any row. Considering time interval 14, the shift register data value in SReg 0 is 1 in row 4; the shift register data value in SReg 1 is 1 in row 5, and the shift register data value in SReg 2 is 1 in row 1. In another example, considering time interval 20, the shift register data value in SReg 0 is 1 in row 6; the shift register data value in SReg 1 is 1 in row 7; and the shift register data value in SReg 2 is 1 in row 3. Considering all other time intervals in SReg 0, SReg 1, and SReg 2 reveals that no column in each column has more than one shift register containing high data values.

[0122] Figure 3HDetailed data value table 298 describes what (disadvantageously) happens when more than one shift register data point is high simultaneously in a column of the table (e.g., for one of SReg 0, SReg 1, or SReg 2, but in different rows). Detailed data value table 298 presents a simplified sequence of shift register data over time intervals a through f, where the time intervals appear in alphabetical order. These time intervals do not correspond to... Figures 3E to 3G Any time interval. Detailed data values ​​are used in Table 298. Figure 3A The backplate is configured as 250, and the header items and line references are... Figures 3E to 3G same.

[0123] Table 298 includes two instances of the data value 1 in column SReg 1 at row 1 and 4 at time interval a, corresponding to the data stored in Figure 3A The data is stored in the uncontrolled shift registers 253a1 and 253d1 on the backplane 250. However, because the uncontrolled shift registers 253a1 and 253d1 are uncontrolled shift registers, the presence of the data value 1 in them has no effect on the word lines associated with row 1 and row 4.

[0124] In the subsequent time interval b, two instances of data value 1 are located in column SReg 2 on rows 1 and 4, corresponding to those stored in Figure 3A The data on the uncontrolled shift registers 253a2 and 253d2 of the backplane 250. Again, because the uncontrolled shift registers 253a2 and 253d2 are uncontrolled shift registers, the presence of the data value 1 within them has no effect on the state of the word line associated with row 1 or row 4.

[0125] In time interval c, two instances of the data value 1 are located in column SReg0 of rows 2 and 5, corresponding to the data stored in control shift registers 253b0 and 253e0. Because control shift registers 253b0 and 253e0 are control shift registers, the presence of the data value 1 in either of them causes the associated row drivers 254b and 254e to raise the word lines of rows 252b and 252e to the ON state.

[0126] The same sequence is repeated in time intervals d and e, where the shift register data values ​​for non-control shift registers 253b1 and 253b2 and for non-control shift registers 253e1 and 253e2 operate in a similar manner as before. In time interval f, the two instances of the data value 1 are again moved to column SReg 0 in rows 3 and 6, corresponding to control shift registers 253c0 and 253f0. Similarly, the word lines in rows 3 and 6 are both moved to the ON state. This creates a state that was previously specifically identified as unfavorable, since data to be written to one row should not be written to more than one row. As a general rule, it is not expected that the shift register data sequence according to one or more embodiments be configured such that at any given time, more than one element of the set of shift registers of a common type has the data value 1.

[0127] If the shift register data sequence is longer than the physical shift registers of the shift register array—processing more data elements—then the use of shift register data sequences and shift register arrays can be acceptable, provided that no shift register of a common type is filled with more than one data value of 1 during any given time interval. This conclusion is in addition to the previous conclusion, which indicated that a successful shift register data sequence can be constructed using no more than one data element from a column representing the data state of a shift register of a common type.

[0128] Figures 4A to 4E The following example is provided, where the shift register data sequence defines more write pointers than the number of shift registers on each row. Figures 4A to 4E based on Figure 3A Backplate 250 and Figure 3B Explanation Table 270.

[0129] Figure 4A An example of write pointer sequence table 300 is presented, where the total number of write pointers (e.g., six, Wp0-Wp5) is greater than the number of shift registers on each row (e.g., three in row 252a, 253a0, 253a1, and 253a2). As previously stated, the number of active shift registers in the shift register data sequence does not exceed the number of shift register groups. That is, only one row has an active word line in any given time interval.

[0130] For time intervals 1 to 21, Figure 4A Write pointer sequence table 300 and Figure 3CThe write pointer sequence table 275 is the same. Then, unlike write pointer sequence table 275, where the shift register data sequence repeats at time interval 22 in row 1 with Wp0, in table 300, write pointer Wp3 occurs at time interval 22 in row 1. After time interval 22, the time intervals and row positions of all remaining instances of write pointer Wp3 in write pointer sequence table 300 are the same as the remaining instances of write pointer Wp0 in write pointer sequence table 275. Therefore, the duration of the 10 time intervals of the bit plane initiated by write pointer Wp2 is the same in write pointer sequence tables 275 and 300. Write pointer Wp3 is terminated by write pointer Wp4, thus creating a bit plane with a duration of 7 time intervals. Write pointer Wp4 is terminated by write pointer Wp5, thus creating another bit plane with a duration of 7 time intervals. The last instance of write pointer Wp5 in row 1 at time interval 36 is the duration of at least seven time intervals at the end of write pointer sequence table 300. (Whether the write pointer Wp5 is for a duration of seven time intervals or longer depends on what happens during time interval 43 and any guaranteed time intervals, which are not depicted here.)

[0131] Note that although the write pointer Wp3 falls into the time interval and row starting at time interval 22 in the write pointer sequence list 300, they are determined by... Figure 3C An instance of write pointer Wp0 in write pointer sequence table 275 is occupied, but this does not apply to write pointer Wp4 relative to write pointer Wp1 or write pointer Wp5 relative to write pointer Wp2 in write pointer sequence table 300.

[0132] In the example of write pointer sequence table 300, the time interval following time interval 42 can utilize additional write pointers in different patterns, or a continuation of the pattern initiated at time interval 22. In the former case, the next pattern can be designed based on the rules presented herein. In the latter case, a continuation of an existing pattern can be used to close the modulation sequence. The continuation may involve setting the data value of the last instance of write pointer Wp3 on each row to 0, so that the bit plane has no data at the end. It may further involve other instances of write pointers Wp4 and Wp5 until these write pointers reach the last row, and then terminate. It can be seen that propagating write pointer Wp3 to the last row (e.g., to erase the last instance of Wp5 with data on it) takes 20 additional time intervals. Another method that can be used to close the modulation sequence is to use a shift register reset function to set all shift register data values ​​to 0.

[0133] Figure 4B The shift register data sequence table 305 is presented, which is related to... Figure 3DThe same method is illustrated in shift register data sequence table 280. Figure 3A The possible shift register data states of individual shift registers. The sequence of time intervals 1 to 21 in shift register data sequence table 305 is the same as the sequence in shift register data sequence table 280. At time interval 22, the shift register data value of row 1 is 100, which corresponds to the data value of write pointer Wp3 at time interval 22 in write pointer sequence table 300. At time interval 23, the shift register data value of row 7 is 100, which corresponds to the data value of write pointer Wp1 at time interval 23 in write pointer sequence table 300. At time interval 24, the shift register data value of row 5 is 100, which corresponds to the data value of write pointer Wp2 at time interval 24 in write pointer sequence table 300. At time interval 25, the shift register data value of row 2 is 100, which corresponds to the data value of write pointer Wp3 at time interval 25 in write pointer sequence table 300.

[0134] At time interval 26, the last instance of the write pointer Wp1 occurs. Wp1 is not carried in tables 300 and 305; therefore, the correspondence between tables 300 and 305 differs from that between tables 275 and 280 at time interval 26 and some subsequent time intervals. For example, by checking, for time interval 26 in tables 300 and 305, no row has the shift register data value 100, and therefore no write operation occurred on any row at time interval 26.

[0135] At time interval 27, the shift register data in row 6 is 100, which corresponds to the data value of the write pointer Wp2 in row 6 at time interval 27 in the write pointer sequence table 300. By inspection, the propagation of the shift register data value 100 from time intervals 28 to 32 in the shift register data sequence table 305 corresponds to the row position of the write pointer in time intervals 28 to 32 as illustrated in the write pointer sequence table 300.

[0136] At time interval 30, another instance of write pointer Wp2 appears in row 7 of write pointer sequence table 300. No further instances of write pointer Wp2 occur in subsequent time intervals in write pointer sequence table 300. At time interval 33, the shift register data value 100 is not found in shift register data sequence table 305, therefore no write operation occurs on any row.

[0137] At time intervals 34 to 36, shift register data 100 is found in rows 5, 3, and 1 of shift register data sequence table 305, respectively. These correspond to the positions of write pointers Wp3, Wp4, and Wp5 in those time intervals in write pointer sequence table 300. A similar pattern is repeated for time intervals 37 to 39 and for time intervals 40 to 42, as can be determined by checking both tables 300 and 305.

[0138] Figure 4C , Figure 4D and Figure 4E A more detailed table of shift register data values ​​is presented from time interval 19 to time interval 42, in tables 310, 315 and 320 below. Figure 4C Table 310 includes detailed data values ​​for time intervals 19 to 27; Figure 4D Table 315 includes detailed data values ​​for time intervals 28 to 36; and Figure 4E Table 320 includes detailed data values ​​for time intervals 37 to 42. The limited number of time intervals presented is sufficient to illustrate the point that shift register data sequences can be longer than the total number of shift registers present in the shift register addressing components. In this example, Figure 4B Shift register data sequence table 305 and Figure 3D The shift register data sequence table 280 is the same until time interval 26. This is because the write pointers Wp1 and Wp2 are relative to the write pointer Wp0 (see...). Figure 3C Compared to the position of write pointers Wp4 and Wp5 relative to write pointer Wp3 (see...), the write pointers Wp4 and Wp5 are... Figure 4A The change is caused by the position difference, so there is no write operation on its shift register for time interval 26. Note that the write pointer Wp3 occupies... Figure 4A Write pointer sequence table 300 and Figure 3C The write pointer sequence table 275 has the same row and time interval as the write pointer Wp0, starting at time interval 22.

[0139] exist Figure 4C , Figure 4D and Figure 4E In this context, all shift registers SReg 0 spanning rows 252a-252g can be considered as the first group, all shift registers SReg 1 spanning rows 252a-252g can be considered as the second group, and all shift registers SReg 2 spanning rows 252a-252g can be considered as the third group. By examination, at any given time interval between 19 and 42, each of these three groups of shift registers has at most one shift register with a data value of 1. This demonstrates that, at any given time interval, no more than one word line is active with shift registers.

[0140] The rules for establishing a shift register data sequence to perform in the same manner as the sequence just shown include several characteristics. The first rule, already stated, is to ensure that no more than one shift register in the set of shift registers at the same logical location has a data value of 1 at any given time. Because the sequence requires more than one data state on shift registers of a common type, this imposes a timing requirement on the shift register data sequence.

[0141] In Figure 4A Write pointer sequence table 300 and Figure 3C When comparing the write pointer sequence table 275, write pointer Wp0 is replaced by write pointer Wp3 at time interval 22. All instances of write pointer Wp3 occur during the time interval and... Figure 3C The write pointer sequence 275 occurred on the row where the write pointer Wp0 previously occurred. Figure 3C Compared to similar bit planes shown, this preserves the... Figure 4A The duration of the bit plane initiated by the write pointer Wp2 in the memory. Then, in Figure 4A In the sequence of write pointers, the write pointer Wp4 of write pointer sequence table 300 is typically similar to... Figure 3C The write pointer Wp1 is in the write pointer sequence table 275. However, at time interval 29 of the write pointer sequence table 300, a write pointer Wp4 is introduced at row 1, and at time interval 26 of the write pointer sequence table 275, a write pointer Wp1 is introduced a second time at row 1. This is a timing shift of three time intervals between the two write pointer sequences mentioned above, resulting in the duration of the bit plane initiated by the write pointer Wp3 of the write pointer sequence table 300 having a duration of seven time intervals, while the duration of the bit plane initiated by the write pointer Wp0 of the write pointer sequence table 275 at the same row and time interval is only four time intervals.

[0142] continue Figure 4A The write pointer sequence list 300, where a bit plane initiated by write pointer Wp4 at time interval 29 on row 1 terminates at time interval W36 by write pointer Wp5 over a duration of seven time intervals. In the example, the bit plane initiated by write pointer Wp5 on row 1 is not terminated. However, checking time interval 40, write pointer Wp3 is found on row 7, indicating that time interval 43 (not shown) will be the next instance of a write pointer from the group containing both write pointers Wp0 and Wp3 appearing on row 1 at time interval 3. In either case, the duration of the bit plane initiated by write pointer Wp5 will be 7.

[0143] exist Figure 4AFollowing the example, the illustrated examples generate a bit plane with a duration of 4 time intervals, four bit planes with a duration of 7 time intervals, and a bit plane with a duration of 10 time intervals. The four bit planes with a duration of 7 time intervals can operate as thermometer bits. This means that by manipulating the data values ​​of the memory circuitry in the pixel driver circuitry, a bit plane with a duration of 7 time intervals at a first position in the bit plane sequence can be turned on first in all instances. In all instances, a bit plane with a duration of 7 time intervals at a second position in the bit plane sequence can be turned on second. In all instances, a bit plane with a duration of 7 time intervals at a third position in the bit plane sequence can be turned on third, and in all instances, a bit plane with a duration of 7 time intervals can be turned on fourth. This means that if a pixel and its neighbor are both turned on, and one pixel has an active first thermometer bit, and a second pixel has active first and second thermometer bits, then the first thermometer bits occur simultaneously in the modulation sequence, and there is no phase difference between them at that point.

[0144] The resulting benefit is a reduction in the prevalence of image defects (such as dynamic false contours and liquid crystal lateral field effects, as are well known in the art). The general concept is to reduce the data phase timing difference between adjacent pixels by using the thermometer bits described above. This solution has been implemented by the applicant in practical applications and is documented in their previous patent applications.

[0145] In the write pointer sequence table 300, a write pointer Wp4 can be introduced at a location other than row 1 during time interval 29. For example, it could be placed at time interval 26 on row 1, although this would not be consistent with... Figure 3C The placement of write pointer Wp1 on row 1 at time interval 26 in the write pointer sequence table 275 is different. Write pointer Wp4 can also be introduced on row 1 at time interval 32, which will change the duration of the bit plane initiated by write pointer Wp3 at time interval 22 from 7 time intervals to 10 time intervals.

[0146] If write pointer Wp5 remains on line 1 at time slot 36, this will also change the duration of the bit plane initiated by write pointer Wp4 on line 1 at time slot 32 to four time intervals. If write pointer Wp5 moves to line 1 at time interval 39, the duration of the bit plane initiated by write pointer Wp4 on line 1 at time interval 32 is seven duration time intervals when it is terminated by write pointer Wp5 on line 1 at time interval 39.

[0147] Therefore, this demonstrates some flexibility in the development of write pointer sequences, allowing for the development of bit planes with varying durations. In practice, each application may require some degree of investigation of alternatives in order to select the best one from the available options.

[0148] The following is an overview of the various steps required to form the shift register data sequence previously disclosed in this application. Upon reading and understanding this disclosure, those skilled in the art will be able to develop, electronically or physically (e.g., on paper), the various tables and other aids described herein, depending on the complexity of the backplane and shift register structure to which the shift register data sequence is intended.

[0149] exist Figure 3A Backplate 250 and Figure 3B The information provided in Table 270 provides the basis for constructing a write pointer sequence that can use a shift register data sequence—such as in… Figure 3D In the shift register data sequence table 280 or in Figure 4B The shift register data sequence presented in shift register data sequence table 305 is used to achieve this.

[0150] Figure 3A The backplane 250 comprises seven rows, as previously described, each row associated with one control shift register and two non-control shift registers. The shift registers can be organized into a downward-sloping array of 3 columns and 7 rows. This corresponds to... Figure 3B The description is in the three right columns of Table 270. Rows are indicated for ease of reference, and row drivers are included for completeness. As mentioned above, in some embodiments, there is no non-control shift register for the last row, and the backplane controller adjusts the timing accordingly. For example, the controller can adjust the timing of subsequent shift register data sequences via a shift register chain of shift register components. For example, the controller can adjust the timing of subsequent shift register data sequences to at least match the input image data frame rate. Experience has shown that when the output is in bit-plane form, it can be difficult to match the output frame rate with the input data rate.

[0151] A more general case of a shift register addressing component is that it comprises N rows, each with M shift registers, except for the last row (which, in some embodiments, may not have non-control shift registers following the last control shift register, as described above). One and only one control shift register is associated with each of the N rows, and each row is associated with the same number of non-control shift registers, which are configured to address... Figure 3A The interconnection method described for the shift register addressing component 256 is as follows.

[0152] In some embodiments, the write pointer sequence table includes rows representing a list of rows on the backplane and columns corresponding to time intervals. This provides a template table on which write pointer sequences can be developed or visualized; Figure 3C Write pointer sequence table 275 and Figure 4A The write pointer sequence table 300 is an example. The overall shift register data sequence table may have more data points than the shift registers in the shift register addressing component it is designed for, but this is not mandatory. Figure 3C Write pointer sequence table 275 and Figure 4A The write pointer sequence table 300 represents the data propagated through the control shift register (the terminology of Wp0, etc., is for ease of reference, as the actual data is a series of 1 and 0 data values).

[0153] Next, we can develop and test synthetic write pointer sequences. From... Figure 3C The example considered in write pointer sequence table 275 begins with Wp0 on row 4 at time interval 10. The write pointer sequence including Wp0, Wp1, and Wp2 is fully developed at time intervals 10, 11, and 12, and a complete cycle is not reached until the same row pattern is found at time interval 31. Due to the nature of shift register addressing components such as those described, the number of write pointers present in the shift register addressing component at any given time advantageously does not exceed the number of shift registers associated with the rows of the display. This includes the control shift registers in the shift register addressing component and each of the subsequent non-control shift registers up to the next control shift register.

[0154] A characteristic of the shift register method is that the shift register data sequence is advantageously located at the beginning of the shift register chain—such as... Figure 3A The shift register addressing component 256 controls the shift register 253a0—initiated. As the data value propagates through the individual shift registers of the shift register addressing component, the modulation sequence develops more fully. As previously mentioned, this is from... Figure 3C The write pointer sequence table 275 begins to occur at time interval 10. This is a characteristic of the type of shift register addressing component disclosed herein, in which all shift registers form a continuous chain in series, such that the entire shift register data sequence advances through the chain.

[0155] Figure 5A , Figure 5B and Figure 5C Detailed shift register sequence data tables 325, 330, and 335 are presented, describing... Figure 3C The write pointer sequence is listed in tables 275, with time intervals 1 to 27. These tables are used to illustrate additional features in the development of the shift register data sequence.

[0156] In the illustrated example, when the write pointer Wp0 of the row write pattern template is initially applied to row 1 at time interval 1, followed by time intervals 2 and 3, no write pointer is applied anywhere during this period. This is because the data corresponding to the other write pointers Wp1 and Wp2 has not yet been introduced to the shift register addressing component. At time interval 4, another instance of write pointer Wp0 propagates to row 2. At time interval 5, write pointer Wp1 is introduced on row 1, thus partially establishing the shift register data sequence. There is no active write pointer in time interval 6 because if the complete sequence has propagated through the shift register and the later introduced Wp2 has wrapped up, i.e., propagated back to the beginning of the sequence, this would be the time interval for Wp2. Time interval 7 has write pointer Wp0 on row 3, and time interval 8 has write pointer Wp1 on row 2, followed by no active write pointer in time interval 9. If the complete sequence has wrapped up, this would again be the time interval for Wp2.

[0157] Starting at time interval 10, the write pointer sequence table is fully populated with all expected write pointers and remains so until time interval 42, which marks the end of write pointer sequence table 275. After propagation through the entire shift register addressing component, each write pointer wraps from the last row to the first row. For example, write pointer Wp0 is located on row 7 at time interval 19. The next instance of write pointer Wp0 is found on row 1 at time interval 22.

[0158] exist Figure 4A In the case of write pointer sequence table 300, write pointer Wp0 does not wrap to row 1 at time interval 22. Instead, write pointer Wp3 is found on row 1 at time interval 22. Although in Figure 3C In the case of write pointer sequence table 275, each instance of write pointer Wp3 starting at time interval 22 is found at the position occupied by Wp0, but write pointer Wp4 is not found in write pointer sequence table 300 at the point occupied by write pointer Wp1 previously written to in write pointer sequence table 275. The same is true for write point Wp5. This is the reason why there are no instances at time intervals 26 and 33 where the write row is not written.

[0159] The next step is to create something similar to Figure 3E The detailed data values ​​in table 285 are the detailed shift register data table. This can be repeated multiple times as needed. The table includes a series of column-based time intervals, each time interval including columns for each shift register group associated with a row, and each row of the display is assigned a row of this table. Advantageously, each row written to the pointer sequence table includes a reference to the expected row of the pixel array.

[0160] The method used to start the shift register data sequence table is to begin filling time intervals to correspond to the write pointer sequence table. When the write pointer component is reset, each data value in the shift register data sequence is zero (0). At each time interval and row where the write pointer is found, a 1 (1) should be written to the corresponding time interval at the corresponding row of the shift register data sequence table.

[0161] As mentioned above, zero corresponds to the following data value, when which, when found in the control shift register, will not cause the word line of that row to be placed in a state that causes the memory circuitry of that row to receive data from the bit line, while one corresponds to the following data value, when which, when found in the control shift register, will indeed cause the word line of that row to be placed in a state that causes the memory circuitry of that row to receive data from the bit line.

[0162] Therefore, the detailed shift register sequence data table 325 represents an intermediate level in the development of the detailed shift register data table. Starting at time interval 1, the table includes a data value of 1 in the control shift register, with all other shift registers set to 0. In time interval 4, this 1 has propagated to the control shift register in row 2. These data values ​​correspond to Wp0 at time intervals 1 and 4. The positions of the 1s between time intervals 1 and 4 are in the non-control shift registers in row 1 of SReg 1 at time interval 2 and SReg 2 at time interval 3, as expected.

[0163] At time interval 5, the data value 1 is placed at SReg 0 in row 1, which corresponds to Figure 3C The write pointer sequence table 275 specifies the write pointer Wp1. A 1 corresponding to write pointer Wp1 effectively terminates the single 1 at time interval 1 in row 1, as it allows new data to be written to that row. The data value 1 in row 2 is positioned at SReg 1 in the same time interval. At time interval 6, the 1 in row 1 has moved to SReg 1 in row 1, and the 1 in row 2 has moved to SReg 2. In time interval 6, there is no 1 in any SReg 0, and therefore no row has data written to it.

[0164] At time interval 7, the data value 1 is found in row 3 at SReg 0, which corresponds to... Figure 3C The write pointer sequence is located at Wp0 at point 275. A further data value 1 is found at row 1 of SReg 2, which moves to SReg 0 of row 2 during time interval 8. The 1 at row 3 moves to SReg 1 during time interval 8.

[0165] At time interval 9, the 1 in row 2 moves to SReg 1, and the 1 in row 3 moves to SReg 2. Figure 5BIn the detailed shift register sequence data table 330, at time interval 10, the data value 1 in row 3 is moved to SReg 1 in row 4, which corresponds to... Figure 3C The write pointer Wp0 in write pointer sequence table 275. The data value 1 is also found in line 2 at SReg 2, which propagated to SReg 0 in line 3 during time interval 11. This corresponds to Wp1 at that position in write pointer sequence table 275. The data value 1 in line 4 is now at SReg 1.

[0166] During time interval 12, a data value of 1 is inserted at row 1 of SReg 0, corresponding to Wp2 in write pointer sequence table 275. Thus, starting at time interval 12, the write pointer sequence is fully developed and can be pushed down the display during subsequent clock cycles by inserting a data value of 0 at row 1 of SReg 0 until the 1 corresponding to Wp0 reaches the last row of the display.

[0167] exist Figure 5C At time interval 19 in Table 335, the data value 1 is found in row 7, which corresponds to... Figure 3C The write pointer sequence table 275 contains the write pointer Wp0. In the following two time intervals, 1 is found at SReg 0 on line 6 at time interval 20, and 1 is found at SReg 0 on line 4 at time interval 21.

[0168] At time interval 22, the next instance of Wp0 appears in row 1 of write pointer sequence table 275. Therefore, the corresponding data value 1 is introduced at SReg 0 in row 1. While this may seem like a semantic issue, in one embodiment, this could be a continuation of an already in-place (e.g., wraparound) write pointer sequence, while in another embodiment, it could be a restart of a previous write pointer sequence. A practical difference is that a restart may require less digital memory than a continuation. Memory price may be more important than physical size or memory capacity, and this has not been a major issue in recent years. Larger memory is cheaper than smaller memory.

[0169] The preceding sections have demonstrated how to develop the desired sequence of write pointers using shift register addressing components similar to those described. Advantageously, the number of write pointers active at any given time in the shift register addressing component should not exceed the number of shift registers associated with each row, with the exception of the last row. Also advantageously, no two shift registers should be placed in a state where they simultaneously initiate transfers of data to a single row. This requires careful planning, and this specification has shown how such planning can be performed.

[0170] Figure 6 Depicting Figure 3AA detailed view of the shift register addressing component 256. Each shift register representation is also annotated with a value of the form p(j,k). The convention for p(j,k) is that the letter j indicates the row where data is found, and the letter k indicates the column where data is found. When p(j,k) has a value of 0, the associated row driver does not cause the word line of row j to place the memory circuitry of row j in a data-receiving state when the control shift register is active. When p(j,k) has a value of 1, the associated row driver does cause the memory circuitry operated by the word line of row j to be in a data-receiving state when the control shift register is active.

[0171] As previously targeted Figure 3A The row drivers 254a, 254b, 254c, 254d, 254e, 254f, and 254g are controlled by controlling shift registers 253a0, 253b0, 253c0, 253d0, 253e0, 253f, and 253g0, respectively. This control is achieved through signal lines 258a, 258b, 258c, 258d, 258e, 258f, and 258g, respectively. Figure 6 The row control shift register 253a0 receives a series of shift register data values ​​via input 257, which determine the state of the word line controlled by the row driver 254a. This value is propagated across the shift registers of the shift register addressing component via a series of clock signals (not shown). The clock first moves the signal to the non-control shift register 253a1 via signal line 259a1, and then to the non-control shift register 253a2 via signal line 259a2. The next clock cycle propagates the value to the control shift register 253b0 via signal line 260a, which determines the state of the row driver 254b. The next clock cycle first propagates the shift register data value to the non-control shift register 253b1 via signal line 259b1, and then to the non-control shift register 253b2 via signal line 259b2.

[0172] Further clock cycles propagate the shift register data value via signal line 260b through control shift register 253c0, then via signal lines 259c1 and 259c2 through non-control shift registers 253c1 and 253c2, via signal line 260c through control shift register 253d0, then via signal lines 259d1 and 259d2 through non-control shift registers 253d1 and 253d2, via signal line 260d through control shift register 253e0, then via signal lines 259e1 and 259e2 through non-control shift registers 253e1 and 253e2, then via signal line 260e through control shift register 253f0, then via signal lines 259f1 and 259f2 through non-control shift registers 253f1 and 253f2, and finally via signal line 260f to control shift register 253g0.

[0173] In one embodiment, there are no non-control shift registers 253g1 and 253g2, and the shift register data sequence ends when the final value of the shift register data sequence is propagated to the control shift register 253g0 via signal line 260f. If there are non-control shift registers 253g1 and 253g2, the signal from the control shift register 253g0 is passed to the non-control shift register 253g1 via signal line 259g1, and then to the non-control shift register 253g2 via signal line 259g2.

[0174] The separation of the shift register's data from the shift register itself allows for discussion of the data's nature. As mentioned earlier, p(j,k) has two possible values: 0 and 1. In the following embodiments, 1 represents a value that causes the word line to place the pixel driving circuitry of a row in a data-receiving state, while 0 does not.

[0175] Return to view Figure 3H The previous analysis of detailed data values ​​in Table 298 established a situation where placing more than one shift register in the same column of the table in a high (1) data state results in two word lines on different rows being pulled high simultaneously (e.g., the same data being incorrectly written to two rows). Therefore, as part of the suitability assessment of the shift register data sequence, it is determined whether the shift register data sequence is advantageous in causing this situation.

[0176] One method for assessing whether a shift register data sequence results in two word lines being placed such that the memory circuitry of two corresponding rows is in a state of receiving data is quite simple. This can be determined by analyzing the shift register data sequence values ​​attributed to individual shift register addressing components—such as shift register addressing component 256—according to the rules described herein.

[0177] exist Figure 3H The example of detailed data values ​​in Table 298 clearly establishes the disadvantage of having shift register data values ​​for more than one control shift register in the same column of Table 298, which can pull the word lines to a state that allows data to be written to more than one row simultaneously via the bit lines. Figure 3H The explanation also shows that having more than one such value in the column of the uncontrolled shift register causes the same problem after multiple clock cycles, because when the number of uncontrolled shift registers between the controlled shift registers is the same in all cases, the value from each column propagates at a uniform rate.

[0178] The following equation provides Figure 6 The first example of the case of a shift register addressing component.

[0179]

[0180] Where j is the row containing the control shift register addressing component. Since not all table columns must have any data value (e.g., logic 1) in a state where the word line is placed in a memory cell that enables pixel drive circuitry to receive data via the bit line, the less than or equal to sign must be used. The equation can be extended to table columns without control shift registers by switching to overwrite p(j,1) or p(j,2). Logically, if the above equation is true, the table column configuration is as desired because at any given time, no more than one row can be written simultaneously. If the above equation is false, the table column configuration is not as desired.

[0181] More generally, a shift register addressing component may comprise an m×n array of shift register circuitry, where m represents the number of rows of the shift register circuitry and n represents the number of columns of the shift register circuitry. That is, each row contains exactly one control shift register, and most rows include additional non-control shift registers. The number of non-control shift registers is the same between the first and next control shift registers. In some embodiments, the last row of shift register circuitry includes only control shift register circuitry. In other embodiments, the number of non-control shift registers after the last control shift register is the same as the number of shift registers in all other rows.

[0182] The following presents a more general version of the above equation for evaluating shift register data values ​​on a shift register addressing component that comprises m rows multiplied by n table columns (e.g., columns of a shift register, rather than columns of pixels or memory cells in an associated array).

[0183]

[0184] In this case, the evaluation must be run for each column of the shift register addressing component. In all instances, there is a control shift register for each row. In the previously mentioned embodiment where there is no non-control shift register after the last control shift register, there are m-1 rows with non-control shift registers. Therefore, the sum of those rows must end at m-2 instead of m-1.

[0185] Due to the nature of introducing a shift register data sequence into the shift register addressing component, choosing the time interval used to evaluate collisions is important. The first point for evaluation occurs when the modulation sequence is first fully introduced. An example of this is... Figure 3C , Figure 3D and Figure 3E It was found at time slot 12. Figure 3C In the write pointer sequence table 275, time interval 12 is the first time interval in which all three write pointers in the write pointer sequence table 275 appear simultaneously. Wp0 has appeared in time interval 10, Wp1 has appeared in time interval 11, and Wp2 has appeared in time interval 12.

[0186] exist Figure 3D During time intervals 10, 11, and 12 of the shift register data sequence table 280, the sequence clearly shows that only one control shift register is in position on the operation word line during each time interval. During each consecutive time interval, the data value of the shift register data table for the subsequent time interval is shifted one bit to the right. Figure 3E Table 285 presents a more detailed view of the shift register data values ​​over time interval 12. Examination of each column reveals that only one shift register data value is 1 in each column, and only SReg 0 is at the operation word line position in rows 1-252a. The sum of the data states in each column is 1, which passes the evaluation criteria for each column. Figure 3D Detailed data value table 285 Figure 3F Detailed data values ​​in Table 290 and Figure 3G Further examination of the detailed data values ​​in Table 295 for subsequent time intervals revealed that the criteria for satisfying the evaluation equation were met in each case. During time slot 33, the previous sequence, which began at time interval 22, was restarted without altering the elements of the shift register data sequence, such as... Figure 3D The shift register data sequence table 280 is shown.

[0187] Figure 3D The shift register data sequence of shift register data table 280 repeats itself and generates only the same number of bit planes as the number of columns in the shift register addressing component. Figure 4A The write pointer sequence table 300 uses six write pointers Wp0 to Wp5 to create six bit planes, as previously described.

[0188] Figure 4A The write pointer sequence table 300 contains the shift register data sequence, which is similar to the previously presented one. Figure 3C The write pointer sequence table 275 is identical at time intervals 1 to 21. For example, at time interval 22 of write pointer sequence table 300, write pointer Wp3 is found on line 1-RW 252a, while write pointer Wp0 is found at the same position on the same line in write pointer sequence table 275. Similarly, write pointer Wp1 at time interval 23 in write pointer sequence table 300 is located at the same position as write pointer Wp1 at time interval 23 in write pointer sequence table 275. The same applies to write pointer Wp2 at time interval 24 of write pointer sequence table 300 and write pointer Wp2 at time interval 24 of write pointer sequence table 275.

[0189] Typically, the position of write pointer Wp0 in write pointer sequence table 300 is related to the position of write pointer Wp3 in write pointer sequence table 275 at time intervals 25, 28, 31, 34, 37, and 40. Write pointer Wp4 in write pointer sequence table 300 at time intervals 29, 32, 35, 38, and 41 is not related to write pointer Wp1 in write pointer sequence table 275 at the same time interval in the row position, and write pointer Wp5 in write pointer sequence table 300 at time intervals 36, 39, and 42 is not related to write pointer Wp2 in write pointer sequence table 275 at the same time interval in the row position.

[0190] The candidate time interval for performing the evaluation of write pointer sequence list 300 is time interval 36, because all the last three write pointers are developed there. For Figure 4D The detailed data values ​​in Table 315 for time interval 36 show that there is only one shift register data value of 1 in each of columns SReg 0, SReg 1 and SReg 2, which means that the logical value of each column is true for the above equation.

[0191] In practice, each time interval of the candidate shift register data sequence can be analyzed sequentially, and the results can be reviewed using commonly available programming techniques or other analysis tools such as spreadsheets.

[0192] The suitability of a conforming shift register data sequence for generating the desired grayscale for any intended operation is generally best determined initially by testing candidate data sequences using a calibrated data collection system, combined with visual inspection by an experienced observer. Suitable testing equipment is available from various sources. A specific grayscale is achieved by selecting which available bit planes will be turned on and which will be turned off.

[0193] If the driving voltage is constant, the response of an LED to pulse width modulation (PWM) is highly linear. The response of a liquid crystal cell to PWM is more complex and depends heavily on the type of liquid crystal layer and the cell's construction. The material and alignment requirements for liquid crystal cells are well-known in the art and will not be elaborated upon here.

[0194] There are tens of thousands of published papers and numerous patents on the subject of liquid crystal cells. As a single example, it is recommended to view "Mixed mode twisted nematic liquid crystal cells for reflective displays," Applied Physics Letters 68, Volume 11, page 1455. Major universities and institutions, such as the Liquid Crystal Institute and CREOL at Kent State University, the College of Optics and Physics, and the University of Central Florida, are involved in research on this topic.

[0195] Those skilled in the art will recognize variations in the methods described herein. Upon reading and understanding this disclosure, those skilled in the art will be able to automate the process of developing shift register data sequences using common software development tools.

[0196] It is conceivable that the range of grayscale values ​​obtainable from this disclosure can be improved by using analog pixels instead of digital pixels, each analog pixel being set to a finite range of preselected values. These preselected values ​​can be row-independent and can differ for adjacent pixels, but are not limited thereto.

[0197] Modifications to the methods and systems described herein may be made without departing from the scope of this document. Therefore, it should be noted that the content contained in the above description or shown in the accompanying drawings should be interpreted as illustrative rather than restrictive. The appended claims are intended to cover all general and specific features described herein, as well as all statements regarding the scope of the methods and systems; as a matter of language, it can be said that these statements fall between them.

[0198] Combination of features

[0199] Without departing from the scope of this invention, the above-described features and the features claimed below can be combined in various ways. The following examples illustrate some possible non-limiting combinations:

[0200] (A1) A backplane configured to drive a display, the backplane comprising: a pixel driving circuit array organized into multiple rows and columns, each pixel driving circuit including memory circuitry operable to receive and store a display value; a plurality of word lines, each word line connected to a pixel driving circuitry in a corresponding row of the rows; a plurality of bit lines, each bit line operable to present the display value to all pixel driving circuitry along a corresponding column of the columns; and at least one shift register addressing component, the at least one shift register addressing component including: a plurality of control shift registers, Each of the control shift registers has an output operable to control different word lines among the plurality of word lines; a plurality of non-control shift registers connected in series with the plurality of control shift registers to form a shift register chain, wherein a group of at least one of the plurality of non-control shift registers is logically located among the sequential control shift registers among the plurality of control shift registers; and a sequence input of a first control shift register among the plurality of control shift registers for receiving a shift register data sequence that controls the selection of the plurality of word lines during operation.

[0201] (A2) In the embodiment of (A1), the first number of uncontrolled shift registers in any group is equal to the second number of uncontrolled shift registers in any other group.

[0202] (A3) In either embodiment (A1) or (A2), a first number of pixel driving circuits on one row of the row that can be operated by the first word line in the word line are the same as a second number of pixel driving circuits on any other row that can be operated by the word line in the word line.

[0203] (A4) In any of embodiments (A1)-(A3), the pixel driving circuitry of each row that can be operated by all word lines controlled by the shift registers of the same shift register addressing component is arranged across all columns of the array.

[0204] (A5) In any of embodiments (A1)-(A4), when the plurality of word lines are configured to drive even-numbered rows of the display, the backplane further includes: a second shift register addressing component, the second shift register addressing component including: a plurality of control shift registers, each of the control shift registers having an output operable to control different word lines of the plurality of word lines of the display to drive odd-numbered rows of the display; a plurality of non-control shift registers, the plurality of non-control shift registers being connected in series with the plurality of control shift registers to form a shift register chain, wherein a group of at least one of the plurality of non-control shift registers is logically located between sequential control shift registers of the plurality of control shift registers; and a sequence input of a first control shift register of the plurality of control shift registers for receiving a shift register data sequence operable to control the selection of the plurality of word lines.

[0205] (A6) In any of embodiments (A1)-(A5), by the action of a word line controlled by one of the control shift registers, the memory circuit of each pixel driving circuit corresponding to at least a portion of a row in the row is selectively enabled to receive a display value presented by the corresponding bit line of the memory circuit; each pixel driving circuit is capable of generating an output operable to drive the display element of the display according to the display value stored in the memory circuit of the pixel driving circuit; a first shift register of each shift register addressing component is operable to receive the data value from the sequence input; and the data value propagates through the shift register chain over consecutive clock cycles.

[0206] (A7) In any of embodiments (A1)-(A6), wherein, in operation, the display value stored in the memory circuit is a single bit, such that logic 1 stored in each memory circuit puts the corresponding pixel driving circuit on, and logic 0 stored in the memory circuit puts the corresponding pixel driving circuit off.

[0207] (A8) In any of the embodiments (A1)-(A7), wherein, in operation, the display value stored in the memory circuit is an analog value.

[0208] (A9) In any of embodiments (A1)-(A8), wherein, in operation, the data values ​​received by the first control shift register of the plurality of control shift registers are arranged in a predetermined sequence, and as the data values ​​propagate through the shift register chain, the predetermined sequence does not enable more than one row of the memory circuitry of the corresponding pixel driving circuitry on the row to receive and store the display values.

[0209] (B1) A method of operating a two-dimensional display of display elements, the method comprising: providing a backplane for driving the two-dimensional display, the backplane including: a two-dimensional pixel driving circuit array organized into multiple rows and multiple columns, each pixel driving circuit including: a corresponding memory circuit operable to receive and store a display value, and in operation, capable of generating an output based on the display value stored in the corresponding memory circuit, the output driving a display element of the two-dimensional display; a plurality of word lines, wherein each word line is connected to a pixel driving circuit of a corresponding row in the rows; a plurality of bit lines, wherein each bit line is operable to present the display value to all pixel driving circuits along a corresponding column in the columns; and a shift register addressing component including: a plurality of control shift registers, each control shift register operable to control different word lines among the plurality of word lines according to data values ​​in the control shift registers, wherein in operation, by the action of one of the word lines, the memory circuit of the pixel driving circuit corresponding to at least a portion of a row in the rows is selectively activated to receive... The method comprises: receiving a display value from the display value presented by the corresponding bit line in the memory circuit; and a plurality of uncontrolled shift registers, which are not operable to control any word line of the word line, wherein the control shift register and the uncontrolled shift register are connected in series in a shift register chain, wherein a group of one or more uncontrolled shift registers in the uncontrolled shift registers is logically arranged within the shift register chain, such that the data value propagates through both the control shift register and the uncontrolled shift register in response to a continuous period of a clock signal; the method further comprises: in each period of the clock signal, inputting a data value from a shift register data sequence into a first control shift register among the plurality of control shift registers, wherein the shift register data sequence is arranged such that the maximum value of one of the control shift registers operates its corresponding word line during any period of the clock signal; and providing a continuous period of the clock signal to the control shift register and the uncontrolled shift register to propagate the data value through the shift register chain.

[0210] (B2) In the embodiment of (B1), the first number of uncontrolled shift registers in any group is equal to the second number of uncontrolled shift registers in any other group.

[0211] (B3) In either embodiment (B1) or (B2), a first number of pixel driving circuits on a row of the rows operated by a first word line of the word line controlled by one of the shift registers are the same as a second number of pixel driving circuits on any other row operated by word lines of the word line controlled by other shift registers of the same shift register addressing component.

[0212] (B4) In any of embodiments (B1)-(B3), the pixel driving circuitry of each row operated by all word lines controlled by the shift registers of the same shift register addressing component is arranged across all columns of the two-dimensional array.

[0213] (B5) In any of embodiments (B1)-(B4), wherein, in operation: by the action of a word line of the word line controlled by one of the control shift registers, a memory circuit of the pixel driving circuit corresponding to at least a portion of a row in the row is selectively enabled to receive a display value from the display values ​​presented by the corresponding bit line of the memory circuit; each pixel driving circuit generates an output operable to drive the display element of the two-dimensional display according to the display value stored in the corresponding memory circuit of the pixel driving circuit; a first shift register of each shift register addressing component is operable to receive the data value from a sequence input; and the data value propagates through the shift register chain over consecutive clock cycles.

[0214] (B6) In any of embodiments (B1)-(B5), wherein, in operation, the display value stored in the memory circuit is a single bit, such that logic 1 stored in each memory circuit puts the corresponding pixel driving circuit on, and logic 0 stored in the memory circuit puts the corresponding pixel driving circuit off.

[0215] (B7) In any of embodiments (B1)-(B6), wherein, in operation, the display value stored in the memory circuit is an analog value.

[0216] (B8) In any of embodiments (B1)-(B7), wherein, in operation, the data values ​​received by the first control shift register are arranged in a predetermined sequence, and as the data values ​​propagate through the shift register chain, the predetermined sequence does not enable more than one row of the memory circuitry of the corresponding pixel driving circuitry on the row to receive and store the display values.

Claims

1. A back panel configured to drive a display, the back panel comprising: A pixel driving circuit array, the pixel driving circuit array being organized into multiple rows and multiple columns, the pixel driving circuit array including memory circuitry; Multiple character lines; Multiple bit lines; as well as At least one shift register addressing component, the at least one shift register addressing component comprising: A plurality of control shift registers, the plurality of control shift registers having outputs operable to control at least one of the plurality of word lines; A plurality of uncontrolled shift registers, wherein the plurality of uncontrolled shift registers are connected in series with the plurality of controlled shift registers to form a shift register chain, wherein a group of at least one of the plurality of uncontrolled shift registers is logically located among the sequentially controlled shift registers of the plurality of controlled shift registers; and The sequence input of the first control shift register among the plurality of control shift registers is used to receive a shift register data sequence that controls the non-contiguous selection of the plurality of word lines during operation, wherein the shift register data sequence includes a plurality of write pointers.

2. The backplate according to claim 1, wherein, The first number of uncontrolled shift registers in any group is equal to the second number of uncontrolled shift registers in any other group.

3. The backplate according to claim 1, wherein, A first number of pixel driving circuits on one of the multiple rows that can be operated by a first word line of the plurality of word lines are the same as a second number of pixel driving circuits on any other row that can be operated by a word line of the plurality of word lines.

4. The backplate according to claim 1, wherein, The pixel drive circuitry for each row, operable by all word lines controlled by the shift registers of the same shift register addressing component, is arranged across all columns of the array.

5. The backplate according to claim 1, wherein, The plurality of word lines are configured to drive an even number of rows of the display, and the back panel further includes: The second shift register addressing component includes: A plurality of control shift registers, each of the plurality of control shift registers having an output, the output being operable to control different word lines of a plurality of word lines of the display to drive the odd number of rows of the display; A plurality of uncontrolled shift registers, wherein the plurality of uncontrolled shift registers are connected in series with the plurality of controlled shift registers to form a shift register chain, wherein a group of at least one of the plurality of uncontrolled shift registers is logically located among the sequentially controlled shift registers of the plurality of controlled shift registers; and The sequence input of the first control shift register among the plurality of control shift registers is used to receive a shift register data sequence operable to control the selection of the plurality of word lines.

6. The backplate according to claim 1, wherein, During operation: By the action of one word line of the plurality of word lines controlled by one of the plurality of control shift registers, the memory circuit of each pixel driving circuit corresponding to at least a portion of one of the plurality of rows is selectively enabled to receive the display value presented by the corresponding bit line of the memory circuit. Each pixel driving circuit can generate an output that is operable to drive the display elements of the display according to the display value stored in the corresponding memory circuit. The first shift register of each shift register addressing component is operable to receive data values ​​from the sequence input; as well as The data value propagates through the shift register chain over consecutive clock cycles.

7. The backplate according to claim 6, wherein, In operation, the corresponding display value stored in the corresponding memory circuit in the pixel driving circuit array is a single bit, such that logic 1 stored in each memory circuit puts the corresponding pixel driving circuit into the ON state, and logic 0 stored in the memory circuit puts the corresponding pixel driving circuit into the OFF state.

8. The backplate according to claim 6, wherein, During operation, the corresponding display value stored in the corresponding memory circuit is an analog value.

9. The backplate according to claim 6, wherein, In operation, the data values ​​received by the first control shift register among the plurality of control shift registers are arranged in a predetermined sequence. As the data values ​​propagate through the shift register chain, the predetermined sequence prevents more than one row from enabling the corresponding memory circuit of the corresponding pixel driving circuit on that row to receive and store the display values.

10. A method for operating a two-dimensional display element, the method comprising: A backplane is provided to drive the two-dimensional display, the backplane comprising: A two-dimensional pixel driving circuit array, wherein the two-dimensional pixel driving circuit array is organized into multiple rows and multiple columns, wherein the pixel driving circuit array: Including the corresponding memory circuit, and During operation, an output can be generated based on the corresponding display value stored in the corresponding memory circuit, and the output drives the display element of the two-dimensional display. Multiple character lines; Multiple bit lines; and The shift register addressing component includes: A plurality of control shift registers, each operable to control at least one of a plurality of word lines according to a corresponding data value in the corresponding control shift register, wherein, in operation, by the action of one of the plurality of word lines, a corresponding memory circuit in the plurality of pixel driving circuits corresponding to at least a portion of one of the plurality of rows is selectively activated to receive a display value from a corresponding display value presented by a corresponding bit line in the corresponding memory circuit; and Multiple uncontrolled shift registers, which are not operable to control any word line of the multiple word lines, wherein the multiple controlled shift registers and the multiple uncontrolled shift registers are connected in series in a shift register chain, wherein a group of one or more of the multiple uncontrolled shift registers is logically set within the shift register chain, such that the corresponding data value propagates through both the multiple controlled shift registers and the multiple uncontrolled shift registers in response to a continuous period of a clock signal between consecutive controlled shift registers; The method further includes: In each cycle of the clock signal, a data value from a shift register data sequence is input to a first control shift register among the plurality of control shift registers, the shift register data sequence including a plurality of write pointers, wherein the shift register data sequence is arranged such that the maximum value of one of the plurality of control shift registers operates its corresponding word line during any time period of the clock signal, wherein the shift register data sequence includes a plurality of write pointers; and The clock signal is provided in continuous cycles to the plurality of control shift registers and the plurality of non-control shift registers to propagate the corresponding data values ​​through the shift register chain.

11. The method according to claim 10, wherein, The first number of uncontrolled shift registers in any group is equal to the second number of uncontrolled shift registers in any other group.

12. The method according to claim 10, wherein, A first number of pixel driving circuits on one of the multiple rows operated by a first word line of the plurality of word lines controlled by one of the multiple control shift registers are the same as a second number of pixel driving circuits on any other row operated by word lines of the plurality of word lines controlled by other shift registers of the same shift register addressing component.

13. The method according to claim 10, wherein, The pixel driving circuitry of each row operated by all word lines of the plurality of word lines, controlled by the shift registers of the same shift register addressing component, is arranged across all columns of the two-dimensional pixel driving circuitry array.

14. The method of claim 10, wherein, During operation: By the action of one word line of the plurality of word lines controlled by one of the plurality of control shift registers, the corresponding memory circuit of the pixel driving circuit corresponding to at least a portion of one of the plurality of lines is selectively enabled to receive the display value in the corresponding display value presented by the corresponding bit line of the corresponding memory circuit. Each pixel driving circuit generates an output that is operable to drive the display element of the two-dimensional display according to the corresponding display value stored in the corresponding memory circuit. The first shift register of each shift register addressing component is operable to receive the corresponding data value from the sequence input; as well as The corresponding data value propagates through the shift register chain over consecutive clock cycles.

15. The method according to claim 14, wherein, In operation, the corresponding display value stored in the corresponding memory circuit is a single bit, such that logic 1 stored in each memory circuit puts the corresponding pixel driving circuit into the ON state, and logic 0 stored in each memory circuit puts the corresponding pixel driving circuit into the OFF state.

16. The method of claim 14, wherein, In operation, the corresponding display value stored in the corresponding memory circuit is an analog value.

17. The method of claim 14, wherein, In operation, the data values ​​in the corresponding data values ​​received by the first control shift register are arranged in a predetermined sequence. When the corresponding data values ​​propagate through the shift register chain, the predetermined sequence prevents more than one row from enabling the corresponding memory circuit of the corresponding pixel driving circuit on the row to receive and store the display values.

18. The method according to claim 10, wherein, The operations performed on the plurality of word lines by the shift register data sequence are non-contiguous.

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