Write performance optimizations for on-demand erase

Abstract

Methods, apparatus, and systems relate to write performance optimization for on-demand erasure. The method includes erasing a portion of memory from a discarded item pool in response to detecting an idle period. A request to write data to the memory is received, and it is determined that a charge gain threshold is not met for the erased portion of the memory. In response to determining that the charge gain threshold is not met, the data is written to the erased portion of the memory.

Description

Technical Field

[0001] This disclosure generally relates to erasing portions of a memory device used for programming data, and more specifically, to optimizing an on-demand erasure scheme to provide and maintain a limited amount of erased memory when a request is anticipated to be used for programming data. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this disclosure relates to a method comprising: erasing a portion of memory from a pool of discarded items in response to detecting an idle period; receiving a request to write data into the memory; determining that a charge gain threshold is not met for the erased portion of the memory; and writing the data into the erased portion of the memory in response to determining that the charge gain threshold is not met.

[0004] On the other hand, this disclosure relates to a non-transitory computer-readable storage medium including instructions that, when executed by a processing device, cause the processing device to: erase a portion of memory from a discarded item pool in response to detecting an idle period; receive a request to write data into the memory; determine that a charge gain threshold is not met for the erased portion of the memory; and write the data into the erased portion of the memory in response to determining that the charge gain threshold is not met.

[0005] Furthermore, this disclosure relates to a system comprising: a plurality of memory devices; and a processing means operatively coupled to the plurality of memory devices to: erase a portion of memory from a discarded item pool in response to detecting an idle period; receive a request to write data into the memory; determine that a charge gain threshold is not met for the erased portion of the memory, wherein the charge gain threshold is a threshold time amount following the erasure of the portion of the memory; and write the data into the erased portion of the memory in response to determining that the charge gain threshold is not met. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a flowchart of an example method according to some embodiments of the present disclosure for optimizing an on-demand erasure scheme by providing a limited amount of erased memory when a request is anticipated to program data.

[0009] Figure 3 This is a flowchart of an example method according to some embodiments of the present disclosure for optimizing an on-demand erasure scheme by providing a limited amount of erased memory when a request is anticipated to program data.

[0010] Figure 4 This is an example block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0011] This disclosure relates to optimizing an on-demand erasure scheme to provide a limited amount of erasable memory in response to a request intended for programming data in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0012] Memory devices can be non-volatile memory devices. A non-volatile memory device is a package of one or more dies. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A die in a package may be assigned to one or more channels for communication with the memory subsystem controller. Each die may consist of one or more planes. Planes may be divided into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND memory devices), each plane consists of a set of physical blocks, which are groups of memory cells used to store data. A cell is an electronic circuit that stores information.

[0013] Depending on the cell type, a cell can store one or more bits of binary information and has various logic states related to the number of bits stored. These logic states can be represented by binary values ​​(e.g., "0" and "1" or combinations thereof). Various types of cells exist, such as single-level cells (SLC), multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC). For example, an SLC can store one bit of information and has two logic states.

[0014] The logic states in a memory cell are distinguished using charge distribution levels. For example, an MLC may be able to store four different charge levels L0, L1, L2, and L3 to represent four different binary values ​​11, 10, 01, and 00. The data charge level becomes a threshold voltage, such that when a read reference voltage is applied to the transistor of the memory cell, the transistor will conduct if the read reference voltage is higher than the threshold voltage. Charge gain (also known as charge distribution growth and charge migration) is a change in the threshold voltage that can lead to a loss of reliability in the state of the memory cell. Specifically, due to electron injection or hole decapture in / from the storage nitride layer, the L0 charge gain of a memory cell in an erased state (e.g., an MLC with a threshold voltage corresponding to the stored binary value "11") can cause the memory cell to appear to be in a non-erased state (e.g., corresponding to the threshold voltage for the stored binary value "10").

[0015] Advances in memory cell design (e.g., from floating-gate to replaced-gate architectures) bring improvements such as increased storage density, write endurance, and latency. These advancements also introduce greater sensitivity to charge gain. For example, the onset of L0 charge gain can begin seconds after erasing a replaced-gate memory cell, compared to several hours in a floating-gate memory cell. If an erased block of memory is not programmed within, for example, one hour after erasure, it may become unreliable. This greater sensitivity to charge gain leads to the avoidance of pre-erasing memory blocks. Erasure on demand (EOD) is a technique designed to address this faster charge gain. This approach erases the block only when the memory subsystem receives a request to program data into the block. Therefore, the time gap between erasing and programming the block is small, and the block does not suffer from unreliability due to L0 charge gain. However, EOD has disadvantages in terms of system performance because the programming time for each block includes erase time. For example, in an instantiated memory architecture, nearly ten percent of the time spent programming a page of memory can be attributed to block erase time. This additional time impacts sequential write throughput. For high-density drives (where the memory subsystem cannot erase all data blocks across each LUN in parallel due to peak power constraints), the impact of additional erase time is even greater.

[0016] This disclosure addresses the aforementioned and other drawbacks by providing a limited amount of erased memory when a request to program data in the memory subsystem is anticipated. For example, the memory subsystem can erase a block stripe using an idle cycle before a host request to program data. Additionally, the memory subsystem can maintain a limited pool of blocks by tracking a charge gain threshold (e.g., the amount of time since erasure) and moving erased blocks back to a discarded item pool when the charge gain threshold is met. When the memory subsystem cannot fulfill a programming request using the pool of erased blocks, it can revert to EOD and erase another stripe using the next idle cycle before the next programming request. As a result of maintaining a limited pool of erased blocks, the memory subsystem has improved sequential write throughput (e.g., in terms of burst performance) without consuming resources to erase excessive blocks that might suffer from charge gain.

[0017] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0018] The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0019] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., a computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0020] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0021] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110.

[0022] Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect Fast (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR) interfaces, Low Power Double Data Rate (LPDDR) interfaces, or any other interfaces. The physical host interface may be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize an NVM Fast (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 For example, memory subsystem 110 is described. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or a combination of communication connections.

[0023] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0024] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-situ write memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in volume resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without prior erasing. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0025] Although a non-volatile memory device (e.g., NAND-type memory (e.g., 2D NAND, 3D NAND) and a 3D cross-point array of non-volatile memory cells) is described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0026] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations (e.g., in response to commands scheduled by controller 115 on a command bus). The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0027] The memory subsystem controller 115 may include a processing means 117 (processor) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0028] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem 110).

[0029] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and translate them into instructions or appropriate commands to achieve the desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations associated with memory device 130, such as wear leveling operations, discard item collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses). The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions for accessing memory devices 130 and / or 140 and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0030] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0031] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0032] The memory subsystem 110 includes an erasure component 113 that optimizes the on-demand erasure scheme by providing a limited amount of erased memory when a request is anticipated to be used to program data. In some embodiments, the controller 115 includes at least a portion of the erasure component 113. For example, the controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the erasure component 113 is part of the host system 120, an application, or an operating system.

[0033] Erasure component 113 can provide a limited amount of erased memory in the event of a anticipated request to program data in the memory subsystem. For example, the memory subsystem can erase one or more blocks using idle cycles prior to a host request to program data. Additionally, the memory subsystem can maintain a limited pool of blocks by tracking a charge gain threshold and moving erased blocks back to a discarded item pool when the charge gain threshold is met. Further details regarding the operation of erasure component 113 are described below.

[0034] Figure 2 This is a flowchart of an example method 200, according to some embodiments of the present disclosure, for optimizing an on-demand erasure scheme by providing a limited amount of erasable memory when a request for programming data is anticipated. Method 200 may be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 200 is performed by… Figure 1 The erase component 113 performs the process. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other processes are possible.

[0035] At operation 205, the processing device detects a power-on event. For example, the processing device determines when the memory subsystem is in the process of restarting, rebooting, or other power-on process, or when a restart, rebooting, or other power-on process has been completed.

[0036] At operation 210, the processing device determines whether one or more portions of the memory are in an erase pool, marked as erased, or otherwise indicated as having been previously erased. For example, the processing device may maintain a list of blocks erased prior to a power-on event. If the processing device determines that one or more portions of the memory have been previously erased, then method 200 proceeds to operation 215. If the processing device determines that any portions of the memory have not been previously erased, then method 200 proceeds to operation 220.

[0037] At operation 215, the processing device will move one or more portions of memory identified as having been previously erased to a discarded item pool. For example, the processing device may maintain a list or other data structure identifying memory blocks to be erased before being programmed with valid data.

[0038] At operation 220, the processing device erases one or more portions of memory from a discarded item pool in response to the detection of an idle period. For example, the processing device may select one or more blocks from a discarded item pool data structure, erase those blocks, and mark them as erased. In one embodiment, the processing device moves the identifier of the erased block from the discarded item pool to an erase pool to indicate that the block is ready to be programmed. In one embodiment, the amount of memory selected from the discarded item pool is dynamically based on the host write pattern. For example, the processing device may receive or track data indicating the frequency of host writes and determine and update the number of blocks to match the estimated consumption of memory by host writes. Using this indication of the host write frequency, the processing device erases a matching number of blocks (or other portions of memory). In another embodiment, the amount of memory selected from the discarded item pool is a static value set at manufacturing time, selected by the user / administrator of the host device, etc.

[0039] Additionally, the processing device may start a timer to store the erase time along with the identifier of the erased block, or otherwise track the amount of time elapsed after erasure. In one embodiment, detecting an idle cycle includes detecting a power-on event, as described with reference to operation 205. In another embodiment, detecting an idle cycle includes determining that no new write request exists, as described below with reference to operation 245.

[0040] At operation 225, the processing device determines whether a programming request has been received. For example, the processing device detects whether any programming / write request has been received from the host system by the memory subsystem. If no programming request has been received, then method 200 proceeds to operation 230. If a programming request has been received, then method 200 proceeds to operation 235.

[0041] At operation 230, the processing device determines whether a charge gain threshold has been met. For example, the processing device may determine whether a threshold amount of time has elapsed since one or more blocks in the erase pool were erased, indicating that one or more blocks may no longer be reliably in an erased state. This determination may include checking the current value of a timer, comparing the stored erase time with the current time, etc. As another example, the processing device may use another indicator of the charge gain threshold. For example, the processing device may test the L0 value using a read operation. A portion of the memory whose threshold voltage distribution offset reaches or exceeds the threshold voltage amount can be considered to have met the charge gain threshold.

[0042] In one embodiment, the charge gain threshold is a static value. For example, the charge gain threshold may be set based on the worst-case scenario (e.g., end-of-life performance) of the memory subsystem. In another embodiment, the charge gain threshold is a dynamic value. For example, the processing device may update the charge gain threshold at different stages of the memory subsystem's lifespan (e.g., start of lifespan, mid-lifespan, and end of lifespan). The processing device may determine the different lifespan stages based on, for example, one or more of the following: the number of programming / erase cycles performed by the memory subsystem, the time the memory subsystem has been used, cross-temperature stress, etc. In embodiments with a dynamic charge gain threshold, the processing device may utilize the charge gain that occurs more slowly at the start of the memory subsystem's lifespan than at the end of its lifespan.

[0043] If the charge gain threshold is met, method 200 returns to operation 215 to refresh the erase pool. If the charge gain threshold is not met, method 200 returns to operation 225 to continue monitoring for programming requests.

[0044] At operation 235, the processing device determines whether a charge gain threshold has been met. In response to a programming request, similar to operation 230, the processing device may determine whether a threshold time has elapsed since one or more blocks in the erase pool were wiped. If the charge gain threshold has not been met, then method 200 proceeds to operation 240. If the charge gain threshold has been met, then method 200 proceeds to operation 255.

[0045] At operation 240, the processing device executes a programming request using an erase pool. For example, the processing device may write host data to one or more portions of the memory erased at operation 220 in response to determining that a charge gain threshold has not been met. Therefore, the processing device executes programming requests faster than when using a simple on-demand erase technique.

[0046] At operation 245, the processing device determines whether another programming request has been received. For example, the memory subsystem may receive one or more requests from the host system to write data in an amount exceeding one or more portions of the memory in the erase pool. Alternatively, the memory subsystem may receive multiple requests from the host system to write data without an intermediate idle period between the first request and subsequent requests. If another programming request has been received, then method 200 proceeds to operation 250. If no other programming request has been received, then method 200 returns to operation 220 to replenish the erase pool during idle time.

[0047] At operation 250, the processing device erases one or more portions of the memory on demand. For example, according to an on-demand erasure scheme, the processing device may select one or more blocks from a pool of discarded items and erase said one or more blocks when an additional request for writing data is fulfilled. Method 200 may return to operation 240 to perform data programming to one or more portions of the memory that are being erased on demand.

[0048] At operation 255, the processing device moves one or more portions of the memory identified as having been previously erased to a discarded item pool. For example, in response to determining that a charge gain threshold has been met upon receiving a programming request, the processing device may move the identifier of the erased block from the erase pool to the discarded item pool, as described above with reference to operation 215. Method 200 may proceed to operation 250 to erase one or more portions of the memory on demand to fulfill the programming request, as described above.

[0049] Figure 3 This is a flowchart of an example method 300 according to some embodiments of the present disclosure for optimizing an on-demand erasure scheme by providing a limited amount of erasable memory when a request for programming data is anticipated. Method 300 may be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1The erase component 113 performs the process. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other processes are possible.

[0050] At operation 305, the processing apparatus erases a portion of the memory from the discarded item pool when the memory subsystem is idle. For example, the processing apparatus may erase a limited portion of the memory when a future request for writing data is anticipated, as described above with reference to operation 220.

[0051] At operation 310, the processing device receives a request to write data to memory. For example, the processing device detects whether any write request has been received from the host system by the memory subsystem, as described above with reference to operation 225.

[0052] At operation 315, the processing device determines that a charge gain threshold is not met for the erased portion of the memory. For example, the processing device may determine the amount of time that has not elapsed since one or more blocks in the erase pool were erased in response to a programming request, as described above with reference to operation 235.

[0053] At operation 320, the processing device writes the data requested for the write to the erased portion of the memory. For example, in response to determining at operation 315 that the charge gain threshold is not met, the processing device may write host data to one or more portions of the memory erased at operation 305. Therefore, the processing device fulfills the programming request faster than when using a simple on-demand erase technique.

[0054] Figure 4 An example machine illustrating computer system 400 may be executed within said machine, providing a set of instructions for causing said machine to perform any one or more methodologies discussed herein. In some embodiments, computer system 400 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Figure 1(Operation of the erasure component 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0055] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying the action to be taken by that machine. Furthermore, while a single machine is described, the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set (or more) of instructions to perform any of the methodologies discussed herein.

[0056] The example computer system 400 includes a processing device 402, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 406 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 418, which communicate with each other via a bus 430.

[0057] Processing device 402 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing combinations of instruction sets. Processing device 402 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. Computer system 400 may further include a network interface device 408 for communicating via network 420.

[0058] Data storage system 418 may include a machine-readable storage medium 424 (also referred to as computer-readable medium) storing one or more sets of instructions 426 or software embodying any of the methodologies or functions described herein. Instructions 426 may also reside wholly or at least partially within main memory 404 and / or processing device 402 during execution by computer system 400, which also constitute machine-readable storage medium. Machine-readable storage medium 424, data storage system 418, and / or main memory 404 may correspond to... Figure 1 The memory subsystem 110.

[0059] In one embodiment, instruction 426 includes instructions for implementing a component corresponding to an erasing component (e.g., Figure 1 The machine-readable storage medium 424 is shown as a single medium in the exemplary embodiments, but the term "machine-readable storage medium" should be understood as a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be understood as any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more methodologies of this disclosure. Therefore, the term "machine-readable storage medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0060] Some portions of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. Algorithms are, and generally are, considered as a self-consistent sequence of operations that leads to a desired result. These operations are those that require physical manipulation of physical quantities. Typically, though not required, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for general reasons, it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0061] However, it should be remembered that all these and similar terms are associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device, which manipulates and converts data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0062] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. For example, a computer system or other data processing system (e.g., controller 115) may implement computer implementation schemes 200 and 300 in response to its processor executing a computer program (e.g., a sequence of instructions) contained in memory or other non-transitory machine-readable storage media. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0063] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods. The architectures of many such systems will appear as described below. Furthermore, this disclosure does not refer to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0064] This disclosure may be provided as a computer program product or software that may include machine-readable media having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0065] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method comprising: erasing a portion of memory from a scrap pool in response to detecting an idle period; receiving a request to write data to the memory; determining that a charge gain threshold is not met for the erased portion of memory; and writing the data to the erased portion of memory in response to determining that the charge gain threshold is not met.

2. The method of claim 1, wherein the charge gain threshold is a threshold amount of time after the portion of memory is erased.

3. The method of claim 1, wherein detecting the idle period includes detecting a power on event.

4. The method of claim 3, further comprising: moving a second portion of memory to a scrap pool to be erased in response to determining that the second portion of memory was erased prior to the power on event.

5. The method of claim 1, wherein detecting the idle period includes determining that there are no new write requests.

6. The method of claim 1, further comprising: determining that a charge gain threshold has been met for a second erased portion of memory; moving the second erased portion of memory to a scrap pool in response to determining that the charge gain threshold has been met; and erasing a third portion of memory from the scrap pool in response to detecting an idle period.

7. The method of claim 1, further comprising: receiving a second request to write data to the memory prior to a subsequent idle period; and erasing a second portion of memory on demand in implementing the second request to write data.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: erase a portion of memory from a scrap pool in response to detecting an idle period; receive a request to write data to the memory; determine that a charge gain threshold is not met for the erased portion of memory; and write the data to the erased portion of memory in response to determining that the charge gain threshold is not met.

9. The non-transitory computer-readable storage medium of claim 8, wherein the charge gain threshold is a threshold amount of time after the portion of memory is erased.

10. The non-transitory computer-readable storage medium of claim 8, wherein detecting the idle period includes detecting a power on event.

11. The non-transitory computer-readable storage medium of claim 10, wherein the processing device is further to: move a second portion of memory to a scrap pool to be erased in response to determining that the second portion of memory was erased prior to the power on event.

12. The non-transitory computer-readable storage medium of claim 8, wherein detecting the idle period includes determining that there are no new write requests.

13. The non-transitory computer-readable storage medium of claim 8, wherein the processing device is further to: determine that a charge gain threshold has been met for a second erased portion of memory; erase a third portion of memory from the scrap pool in response to detecting an idle period. moving a second erased portion of memory to a scrap pool in response to determining that the charge gain threshold has been met; and erasing a third portion of memory from the scrap pool in response to detecting an idle period.

14. The non-transitory computer-readable storage medium of claim 8, wherein the processing device is further to: receive a second request to write data to the memory prior to a subsequent idle period; and erasing a second portion of memory on demand in implementing the second request to write data.

15. A system comprising: a memory device; and a processing device operably coupled with the memory device to: erase a portion of memory from a scrap pool in response to detecting an idle period; receive a request to write data to the memory; determine that a charge gain threshold is not met for the erased portion of memory, wherein the charge gain threshold is a threshold amount of time after the portion of memory is erased; and write the data to the erased portion of memory in response to determining that the charge gain threshold is not met.

16. The system of claim 15, wherein detecting the idle period includes detecting a power on event.

17. The system of claim 16, wherein the processing device is further to: move a second portion of memory to a scrap pool to be erased in response to determining that the second portion of memory was erased prior to the power on event.

18. The system of claim 15, wherein detecting the idle period includes determining that there is no new write request.

19. The system of claim 15, wherein the processing device is further to: determine that a charge gain threshold has been met for a second erased portion of memory; move the second erased portion of memory to a scrap pool in response to determining that the charge gain threshold has been met; and erase a third portion of memory from the scrap pool in response to detecting an idle period.

20. The system of claim 15, wherein the processing device is further to: receive a second request to write data to the memory prior to a subsequent idle period; and erasing a second portion of memory on demand in implementing the second request to write data.

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