Display panel, manufacturing method thereof and display device

Abstract

The application discloses a display panel and a manufacturing method thereof, and a display device. The display panel comprises an array substrate, the array substrate comprises a first substrate, a second metal layer and a common electrode; the second metal layer comprises data lines arranged along a first direction and extending along a second direction, the data lines and the common electrode at least partially overlap in the orthogonal projection of the first substrate; at least a display area further comprises a first trace, the first trace is located on one side of the common electrode, and the first trace is directly connected with the common electrode; the first trace comprises first sub-traces extending along the second direction; or, the first trace comprises second sub-traces extending along the first direction; or, the first trace comprises the first sub-traces extending along the second direction and the second sub-traces extending along the first direction, and the second sub-traces are connected with the first sub-traces. The application can reduce the resistance of the common electrode, reduce the voltage recovery time of the common electrode, and avoid the appearance of horizontal bright lines.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] Currently, display technology has permeated all aspects of people's daily lives, and correspondingly, more and more materials and technologies are being used in displays. Display panels, as a crucial component of display devices, are used to realize the display function. Today, the mainstream display panels are mainly liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays. LCDs have advantages such as being thin and light, having low power consumption, and low radiation, and are widely used in various fields.

[0003] A liquid crystal display (LCD) panel typically includes a color filter substrate and an array substrate arranged opposite each other, as well as a liquid crystal layer between the color filter substrate and the array substrate. The color filter substrate has a black matrix and a color resist layer on the side closest to the array substrate. The electric field between the pixel electrodes and the common electrode in the display panel can deflect the liquid crystal molecules. After the liquid crystal molecules are deflected, the light generated by the backlight assembly passes through the display panel. By adjusting the magnitude of the electric field, the degree of deflection of the liquid crystal molecules can be varied. Different degrees of deflection result in different light transmittance of the display panel, and thus different amounts of light transmitted through the backlight assembly, thereby achieving image display. However, in existing technologies, LCD panels generate bright lines (crosstalk) during the display process, affecting display performance.

[0004] Therefore, there is an urgent need to provide a display panel and its manufacturing method and display device that can improve brightness lines and enhance display performance. Summary of the Invention

[0005] In view of this, the present invention provides a display panel and a method for manufacturing the same, as well as a display device, to improve the voltage recovery capability of the common electrode, improve bright lines, and enhance display performance.

[0006] On one hand, the present invention provides a display panel, including a color filter substrate and an array substrate disposed opposite to each other, the array substrate comprising:

[0007] First substrate;

[0008] A first metal layer is located on one side of the first substrate, and a second metal layer is located on the side of the first metal layer away from the first substrate. A first insulating layer is included between the first metal layer and the second metal layer. The second metal layer includes data lines, and multiple data lines are arranged along a first direction and extend in a second direction.

[0009] A common electrode is located on the side of the second metal layer away from the first substrate. A second insulating layer is included between the second metal layer and the common electrode. The orthographic projection of the data line onto the plane of the first substrate and the orthographic projection of the common electrode onto the plane of the first substrate overlap at least partially.

[0010] The display panel also includes a display area and a non-display area that at least partially surrounds the display area. The display area also includes a first trace, which is located on the side of the common electrode away from the first substrate, or the first trace is located on the side of the common electrode close to the first substrate, and the first trace is in direct contact with the common electrode.

[0011] The first routing includes a first sub-routes extending along the second direction;

[0012] Alternatively, the first routing includes a second sub-routes extending along the first direction;

[0013] Alternatively, the first routing includes a first sub-routing extending along a second direction and a second sub-routing extending along a first direction, the second sub-routing being connected to the first sub-routing.

[0014] On the other hand, the present invention also provides a method for manufacturing a display panel, for manufacturing the above-mentioned display panel, the method comprising:

[0015] Provide color filter substrates;

[0016] Fabrication of the array substrate includes:

[0017] Provide a first substrate;

[0018] A first metal layer is formed on one side of the first substrate.

[0019] A first insulating layer is formed on the side of the first metal layer away from the first substrate.

[0020] A second metal layer is formed on the side of the first insulating layer away from the first substrate, and the second metal layer is etched to form data lines arranged in the first direction and extending in the second direction;

[0021] A second insulating layer is formed on the side of the second metal layer away from the first substrate.

[0022] A common electrode is formed on the side of the second insulating layer away from the first substrate, and the orthographic projection of the data line onto the plane of the first substrate and the orthographic projection of the common electrode onto the plane of the first substrate overlap at least partially.

[0023] At least in the display area of ​​the display panel, a third metal layer is formed on the side of the common electrode away from the first substrate. The third metal layer is etched to form a first trace, such that the first trace is in direct contact with the common electrode. The first trace includes a first sub-trace extending along a second direction; or, the first trace includes a second sub-trace extending along a first direction; or, the first trace includes a first sub-trace extending in a second direction and a second sub-trace extending in a first direction, wherein the second sub-trace is connected to the first sub-trace.

[0024] Alternatively, at least in the display area of ​​the display panel, a third metal layer is formed on the side of the second insulating layer away from the first substrate, and the third metal layer is etched to form a first trace, wherein the first trace includes a first sub-trace extending along the second direction; or, the first trace includes a second sub-trace extending along the first direction; or, the first trace includes a first sub-trace extending along the second direction and a second sub-trace extending along the first direction, the second sub-trace being connected to the first sub-trace; a common electrode is formed on the side of the first trace away from the first substrate, the orthographic projection of the data line on the plane of the first substrate at least partially overlaps with the orthographic projection of the common electrode on the plane of the first substrate, and the first trace is in direct contact with the common electrode.

[0025] On the other hand, the present invention also provides a display device including the above-described display panel.

[0026] Compared with the prior art, the display panel, its manufacturing method, and the display device provided by the present invention achieve at least the following beneficial effects:

[0027] This invention provides a first trace on the side of the common electrode away from the first substrate, or the first trace is located on the side of the common electrode closer to the first substrate. The first trace is in direct contact with the common electrode, thus forming a parallel connection. The first trace can be made of metal or other conductors with low impedance. According to the principle of resistance, the total resistance after parallel connection is less than the two resistances connected in parallel. Therefore, the total resistance after the common electrode and the first trace are connected in parallel is reduced. When the data voltage changes, the common voltage can quickly recover to the reference, improving horizontal crosstalk bright lines. In this invention, the first trace is in direct contact with the common electrode, eliminating the need to first set an insulating layer on one side of the common electrode, then fabricate the first trace, and then connect it through a via. This not only complicates the manufacturing process but also increases the thickness of the display panel. The direct contact between the first trace and the common electrode simplifies the process and also helps to reduce the thickness of the display panel. The first trace includes a first sub-trace extending along a second direction. The first sub-trace is directly connected to the common electrode, forming a parallel connection. The total resistance after the first sub-trace and the common electrode are connected in parallel is reduced. When the data voltage changes, the common voltage can quickly recover to the reference, improving horizontal crosstalk bright lines. Alternatively, the first trace includes a second sub-trace extending along a first direction. The second sub-trace is directly connected to the common electrode, forming a parallel connection. The total resistance after the second sub-trace and the common electrode are connected in parallel is reduced. When the data voltage changes, the common voltage can quickly recover to the reference, improving horizontal crosstalk bright lines. Alternatively, the first trace includes a first sub-trace extending along the second direction and a second sub-trace extending along the first direction. The second sub-trace is connected to the first sub-trace, forming a mesh that is directly connected to the common electrode. This further reduces the total resistance after parallel connection. The reduced total resistance allows the common voltage to quickly recover to the reference when the data voltage changes, improving horizontal crosstalk bright lines.

[0028] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0029] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0030] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0031] Figure 1 This is a schematic diagram of a planar structure of a display panel provided by the present invention;

[0032] Figure 2 yes Figure 1 A cross-sectional view along line A-A' in the middle;

[0033] Figure 3 This is a schematic diagram of a planar structure of a display panel provided by the present invention;

[0034] Figure 4 yes Figure 3 A cross-sectional view along the K-K' direction;

[0035] Figure 5 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0036] Figure 6 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0037] Figure 7 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0038] Figure 8 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0039] Figure 9 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0040] Figure 10 yes Figure 7 A cross-sectional view along the B-B' direction;

[0041] Figure 11 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0042] Figure 12 yes Figure 11 A cross-sectional view along the C-C' direction;

[0043] Figure 13 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0044] Figure 14 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0045] Figure 15 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0046] Figure 16 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0047] Figure 17 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0048] Figure 18 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0049] Figure 19 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0050] Figure 20 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0051] Figure 21 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0052] Figure 22 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0053] Figure 23 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0054] Figure 24 yes Figure 23 A cross-sectional view along the D-D' direction;

[0055] Figure 25 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0056] Figure 26 yes Figure 25 A cross-sectional view along the E-E' direction;

[0057] Figure 27 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0058] Figure 28 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0059] Figure 29 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0060] Figure 30 yes Figure 29 A cross-sectional view along the F-F' direction;

[0061] Figure 31 This is a flowchart of a method for manufacturing a display panel provided by the present invention;

[0062] Figure 32 This is a schematic diagram of the planar structure of the display device provided in an embodiment of the present invention. Detailed Implementation

[0063] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0064] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0065] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0066] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0067] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0068] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 , Figure 1 This is a schematic diagram of a planar structure of a display panel provided by the present invention. Figure 2 yes Figure 1 A cross-sectional view along line A-A'. Figure 3 This is a schematic diagram of a planar structure of a display panel provided by the present invention. Figure 4 yes Figure 3 A cross-sectional view along the K-K' direction. Figure 5 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 6This is a schematic diagram of a planar structure of another display panel provided by the present invention. This embodiment provides a display panel 100, including a color filter substrate 1 and an array substrate 2 disposed opposite to each other. The array substrate 2 includes: a first substrate 201; a first metal layer 202 located on one side of the first substrate 201; a second metal layer 204 located on the side of the first metal layer 202 away from the first substrate 201; a first insulating layer 203 between the first metal layer 202 and the second metal layer 204; the second metal layer 204 includes data lines 3, multiple data lines 3 arranged along a first direction X and extending in a second direction Y; a common electrode 206 located on the side of the second metal layer 204 away from the first substrate 201; and the second metal... A second insulating layer 205 is included between the base layer 204 and the common electrode 206. The orthographic projection of the data line 3 onto the plane of the first substrate 201 and the orthographic projection of the common electrode 206 onto the plane of the first substrate 201 overlap at least partially. The display panel 100 also includes a display area AA and a non-display area BB that at least partially surrounds the display area AA. The display area AA also includes a first trace 4. The first trace 4 is located on the side of the common electrode 206 away from the first substrate 201, or the first trace 4 is located on the side of the common electrode 206 close to the first substrate 201. The first trace 4 is in direct contact with the common electrode 206.

[0069] like Figure 1 As shown, the first trace 4 includes a first sub-trace 41 extending along the second direction Y;

[0070] Or, such as Figure 5 As shown, the first trace 4 includes a second sub-trace 42 extending along the first direction X;

[0071] Or, such as Figure 6 As shown, the first trace 4 includes a first sub-trace 41 extending along the second direction Y and a second sub-trace 42 extending along the first direction X, and the second sub-trace 42 is connected to the first sub-trace 41.

[0072] Specifically, refer to Figure 2 The color filter substrate 1 and the array substrate 2 have liquid crystal molecules 6 between them. The array substrate 2 includes a first substrate 201, and a first metal layer 202, a first insulating layer 203, a second metal layer 204 and a common electrode 206 stacked on the first substrate 201. Of course, the array substrate 2 also includes a pixel electrode 207. In the direction perpendicular to the plane where the first substrate 201 is located, a third insulating layer 208 is also included between the pixel electrode 207 and the common electrode 206. After applying voltage to the pixel electrode 207 and the common electrode 206 respectively, the deflection of the liquid crystal molecules 6 in the corresponding area can be controlled for display. Figure 2The image only shows the side of the common electrode 206 away from the first substrate 201, where the pixel electrode 207 is located. It can be understood that the common electrode 206 is a single layer. When the pixel electrode 207 is connected to the drain T3 of the transistor TFT, it needs to be connected through a via. Therefore, at the location of the via, a portion of the common electrode 206 needs to be removed by drilling through a hole, such as... Figure 2 As shown, this is to prevent crosstalk between the driving signal of the pixel electrode 207 and the signal of the common electrode 206. Of course, the pixel electrode 207 can also be located on the side of the common electrode 206 closer to the second metal layer 204, which is not shown here. Figure 2 The common electrode 206, the first insulating layer 203, the second insulating layer 205, the third insulating layer 208, the first substrate 201, and the color filter substrate 1 are not patterned. Optionally, the pixel electrode 207 and the common electrode 206 can be made of indium tin oxide (ITO), but other materials are also possible; no specific limitation is made here. Figure 1 , Figure 5 and Figure 6 This explanation focuses on the pixel electrode 207 as a dual-domain structure. It's understandable that liquid crystal display panels suffer from anisotropic viewing angles. This is because liquid crystal molecules 6 are approximately cylindrical, possessing a long axis and a short axis. The different deflection directions of these molecules result in different optical path differences for light passing through the liquid crystal display panel, thus causing anisotropy in the viewing angle. By configuring the pixel electrode 207 as a dual-domain structure, two adjacent domains are formed within the same sub-pixel P. The liquid crystal molecules 6 in these two adjacent domains rotate in opposite directions. From different viewing angles, the viewing angles of these two adjacent domains can be complementary, thus solving the viewing angle problem in the horizontal or vertical directions. The dual-domain structure can increase the viewing angle of the liquid crystal display panel and improve the color shift problem of the display panel 100. Of course, the pixel electrode 207 can also be a single-domain or pseudo-dual-domain structure; no specific limitation is made here.

[0073] certainly Figure 2 The diagram also shows a transistor T for driving the pixel electrode 207. The transistor T includes a gate T1, a source T2, and a drain T3. The drain T3 is electrically connected to the pixel electrode 207 via a via. Both the source T2 and drain T3 are electrically connected to the semiconductor T4 via vias. It is understood that the semiconductor T4, gate T1, source T2, and drain T3 also include an interlayer insulating layer. The gate T1 is located in the first metal layer 202, and the source T2 and drain T3 are located in the second metal layer 204. The first insulating layer 203 specifically refers to the interlayer insulating layer between the semiconductor T4 and the second metal layer 204, and between the gate T1 and the semiconductor T4. Figure 2 The interlayer insulation layer was not patterned. Figure 2 The image only shows transistor T as a bottom-gate structure.

[0074] The orthographic projection of data line 3 onto the plane of the first substrate 201 at least partially overlaps with the orthographic projection of common electrode 206 onto the plane of the first substrate 201. Figure 1 , Figure 5 and Figure 6 The diagram shows a situation where the orthographic projection of data line 3 onto the plane of the first substrate 201 lies within the orthographic projection of common electrode 206 onto the plane of the first substrate 201. As a result, data line 3 will generate coupling capacitance with common electrode 206. When the data voltage transmitted on data line 3 changes, it will disturb the common voltage of common electrode 206. In related technologies, common electrode 206 is usually made of indium tin oxide (ITO). Common electrode 206 has a large resistance, so the voltage of common electrode 206 cannot quickly recover to the level after the voltage change, resulting in horizontal crosstalk.

[0075] The present invention provides a third metal layer 209 for setting the first trace 4. The third metal layer 209 can be located on the side of the common electrode 206 close to the first substrate 201, or on the side of the common electrode 206 away from the first substrate 201. Figure 1 and Figure 2 The diagram shows a first trace 4 disposed on the side of the common electrode 206 away from the first substrate 201. Figure 3 and Figure 4 The diagram shows a first trace 4 disposed on the side of the common electrode 206 near the first substrate 201. The first trace 4 is in direct contact with the common electrode 206, thus forming a parallel connection between the first trace 4 and the common electrode 206. The first trace 4 can be made of metal or other conductors with low impedance. According to the principle of resistance, the total resistance after parallel connection is less than the two parallel resistors. Therefore, the total resistance after the common electrode 206 and the first trace 4 are connected in parallel is reduced. When the data voltage changes, the common voltage can quickly recover to the reference, improving horizontal crosstalk bright lines. It should be noted that the following embodiments of the present invention only illustrate the case where the first trace 4 is located on the side of the common electrode 206 away from the first substrate 201. In any of the following embodiments, the first trace 4 can be located on the side of the common electrode 206 near the first substrate 201, and will not be described again below.

[0076] In this invention, the first trace 4 is in direct contact with the common electrode 206. This eliminates the need to first create an insulating layer on one side above the common electrode 206, then fabricate the first trace 4, and finally connect it via a via. This process would not only be more complex but would also increase the thickness of the display panel 100. Direct contact between the first trace 4 and the common electrode 206 simplifies the process and helps reduce the thickness of the display panel 100.

[0077] like Figure 1As shown, the first trace 4 includes a first sub-trace 41 extending along the second direction Y. The first sub-trace 41 is directly connected to the common electrode 206 to form a parallel connection. The total resistance of the first sub-trace 41 and the common electrode 206 after being connected in parallel is reduced. When the data voltage changes, the common voltage can quickly recover to the reference, improving the horizontal crosstalk bright line.

[0078] like Figure 5 As shown, the first trace 4 includes a second sub-trace 42 extending along the first direction X. The second sub-trace 42 is directly connected to the common electrode 206 to form a parallel connection. The total resistance of the second sub-trace 42 and the common electrode 206 after being connected in parallel is reduced. When the data voltage changes, the common voltage can quickly recover to the reference, improving the horizontal crosstalk bright line.

[0079] like Figure 6 As shown, the first trace 4 includes a first sub-trace 41 extending along the second direction Y and a second sub-trace 42 extending along the first direction X. The second sub-trace 42 is connected to the first sub-trace 41, and the first sub-trace 41 and the second sub-trace 42 form a mesh, which is directly connected to the common electrode 206. This can further reduce the total resistance after parallel connection. With the total resistance reduced, when the data voltage changes, the common voltage can quickly recover to the reference, improving the horizontal crosstalk bright lines. In addition, after the first sub-trace 41 and the second sub-trace 42 form a mesh structure, the uniformity of the common voltage is also significantly improved.

[0080] Understandably, since the wiring space of the third metal layer 209 is relatively large, the first trace 4 can be set in the first direction X and / or the second direction Y. The first sub-trace 41 or the second sub-trace 42 can be set according to the actual needs of the product, making the structure more flexible and the applicability more extensive.

[0081] In some alternative embodiments, refer to Figure 7 , Figure 8 , Figure 9 ,as well as Figure 10 , Figure 7 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 8 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 9 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 10 yes Figure 7 A cross-sectional view along the B-B' direction, the color filter substrate 1 includes a second substrate 101 and a black matrix BM located on one side of the second substrate 101, and the orthographic projection of the first trace 4 onto the plane where the first substrate 201 is located is located within the orthographic projection of the black matrix BM onto the plane where the first substrate 201 is located.

[0082] Specifically, the color filter substrate 1 includes a second substrate 101, a black matrix BM located on the side of the second substrate 101 near the array substrate 2, and a color filter 102. Figure 10 The color resist 102 is not patterned. The black matrix BM is used to block backlight leakage outside the pixel opening and is a pre-existing film layer in the color filter substrate 1.

[0083] Understandably, since the material of the first trace 4 is metal, and metal has light-shielding properties, the first trace 4 is covered by the projection of the black matrix BM, so the first trace 4 will not occupy the aperture space and will not affect the pixel aperture ratio. In addition, metal is reflective, and the black matrix BM can minimize the metal reflection problem of the first trace 4. In this embodiment, the orthographic projection of the first trace 4 on the plane of the first substrate 201 is located within the orthographic projection of the black matrix BM on the plane of the first substrate 201, thus it will not affect the pixel aperture ratio, and at the same time, it can minimize the metal reflection problem of the first trace 4.

[0084] The black matrix BM includes black matrices along the first direction X and the second direction Y. When the first trace 4 includes a first sub-trace 41 extending along the second direction Y, the orthographic projection of the first sub-trace 41 onto the plane of the first substrate 201 lies within the orthographic projection of the black matrix BM onto the plane of the first substrate 201, thereby reducing the impact on the pixel aperture ratio and minimizing the metallic reflection problem of the first sub-trace 41. When the first sub-trace 41 includes a second sub-trace 42 extending along the first direction X, the orthographic projection of the second sub-trace 42 onto the plane of the first substrate 201 lies within the orthographic projection of the black matrix BM onto the plane of the first substrate 201. This reduces the impact on pixel aperture ratio and minimizes the metallic reflection problem of the second sub-trace 42. When the first trace 4 includes a first sub-trace 41 extending along the second direction Y and a second sub-trace 42 extending along the first direction X, and the second sub-trace 42 is connected to the first sub-trace 41, forming a mesh, the orthographic projection of the first sub-trace 41 and the second sub-trace 42 onto the plane of the first substrate 201 is located within the orthographic projection of the black matrix BM onto the plane of the first substrate 201, thereby reducing the impact on pixel aperture ratio and minimizing the metallic reflection problem of the first sub-trace 41 and the second sub-trace 42.

[0085] In some alternative embodiments, refer to Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 16 , Figure 18 , Figure 19and Figure 20 , Figure 11 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 12 yes Figure 11 A cross-sectional view along the C-C' direction. Figure 13 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 14 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 15 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 16 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 17 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 18 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 19 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 20 This is a schematic diagram of a planar structure of another display panel provided by the present invention.

[0086] The color filter substrate 1 includes a second substrate 101; the display panel 100 also includes a support pillar 7, which is located between the first substrate 201 and the second substrate 101.

[0087] In a direction perpendicular to the plane of the first substrate 201, the first trace 4 at least partially overlaps with the support pillar 7; or, in a direction perpendicular to the plane of the first substrate 201, at least part of the first trace 4 partially surrounds the support pillar 7; or, the first trace 4 includes a notch 8, and in a direction perpendicular to the plane of the first substrate 201, the notch 8 overlaps with the support pillar 7.

[0088] The liquid crystal display panel is a liquid crystal cell formed by aligning and bonding an array substrate 2 and a color filter substrate 1 that are arranged opposite each other. When the array substrate 2 and the color filter substrate 1 are aligned and bonded, support pillars 7 are used between the array substrate 2 and the color filter substrate 1 to maintain the cell thickness of the liquid crystal cell. The support pillars 7 include main support pillars 71 and auxiliary support pillars 72, which together support the cell thickness of the liquid crystal cell. There is a certain height difference between the main support pillars 71 and the auxiliary support pillars 72. The main support pillars 71 play a decisive role in supporting the cell thickness of the liquid crystal cell of the display panel 100, while the auxiliary support pillars 72 play a role in increasing the elasticity when the liquid crystal display panel is subjected to external force.

[0089] Figure 11 The first routing line 4 includes a first sub-route 41 extending along the second direction Y. Figure 13 The first routing line 4 includes a second sub-route 42 extending along the first direction X. Figure 14The first trace 4 includes a first sub-trace 41 extending along the second direction Y and a second sub-trace 42 extending along the first direction X, and the first sub-trace 41 and the second sub-trace 42 are connected. Of course, the color filter substrate 1 may include a black matrix BM, and the support pillar 7 is also located within the black matrix BM in a direction perpendicular to the plane of the first substrate 201. Figure 12 Not shown in the diagram. In a direction perpendicular to the plane of the first substrate 201, the first trace 4 at least partially overlaps with the support pillar 7, and the support pillar 7 contacts the color filter substrate 1 and the array substrate 2 respectively, as shown in the diagram. Figure 12 As shown, although a third metal layer 209 is provided in the array substrate 2 for making the first trace 4, the main support column 71 is in contact with the array substrate 2, and can prevent the support column 7 from displacing when the display panel 100 is squeezed by external force.

[0090] Figure 15 The first routing line 4 includes a first sub-route 41 extending along the second direction Y. Figure 16 The first routing line 4 includes a second sub-route 42 extending along the first direction X. Figure 17 The first routing line 4 includes a first sub-routing line 41 extending along the second direction Y and a second sub-routing line 42 extending along the first direction X, and the first sub-routing line 41 and the second sub-routing line 42 are connected. Figures 15 to 17 In this embodiment, at least a portion of the first trace 4 partially surrounds the support pillar 7 in a direction perpendicular to the plane of the first substrate 201. That is, the first trace 4 winds around the support pillar 7. Furthermore, in a direction perpendicular to the plane of the first substrate 201, the first trace 4 and the support pillar 7 at least partially do not overlap. In this embodiment, the fact that at least a portion of the first trace 4 partially surrounds the support pillar 7 in a direction perpendicular to the plane of the first substrate 201 ensures better flatness at the contact point of the end of the support pillar 7 near the array substrate, thereby improving the flatness of the support pillar 7 and enhancing the light leakage performance during extrusion.

[0091] Figure 18 The first routing line 4 includes a first sub-route 41 extending along the second direction Y. Figure 19 The first routing line 4 includes a second sub-route 42 extending along the first direction X. Figure 20 The first routing line 4 includes a first sub-routing line 41 extending along the second direction Y and a second sub-routing line 42 extending along the first direction X, and the first sub-routing line 41 and the second sub-routing line 42 are connected. Figures 18 to 20 In the first trace 4, there is a notch 8. In a direction perpendicular to the plane of the first substrate 201, the notch 8 overlaps with the support post 7, that is, the first trace 4 is interrupted at the position of the support post 7. For example... Figures 18 to 20The first sub-trace 41 in the middle section has a notch 8, which means it is broken at the position of the support pillar 7. In this embodiment, in the direction perpendicular to the plane of the first substrate 201, the notch 8 overlaps with the support pillar 7, so that the flatness of the end of the support pillar 7 near the array substrate is better, which can improve the flatness of the support pillar 7 position and improve the extrusion light leakage performance. Optionally, the purpose of the main support pillar 71 is to maintain the thickness of the liquid crystal cell, so it needs to contact the array substrate 2. This position is more likely to affect the flatness and cause light leakage when subjected to external force. The first sub-trace 41 and / or the second sub-trace 42 having a notch 8 at the position of the main support pillar 71 can more effectively improve the flatness and improve the extrusion light leakage performance. Figure 20 In the middle, some of the first sub-routes have gaps 8, and some of the second sub-routes 42 have gaps 8, but it can ensure that the other parts of the first sub-routes 41 and the second sub-routes 42 are connected together to form a mesh structure.

[0092] In some alternative embodiments, refer to Figure 21 , Figure 21 This is a schematic diagram of a planar structure of another display panel provided by the present invention. In the direction perpendicular to the plane of the first substrate 201, at least part of the first trace 4 partially surrounds the support column 7.

[0093] The first trace 4 includes a winding portion 9, which partially surrounds the support post 7 in a direction perpendicular to the plane of the first substrate 201.

[0094] In a direction perpendicular to the plane of the first substrate 201, the winding portion 9 and the support post 7 have a first interval 10.

[0095] Figure 21 The illustration only takes the first routing line 4, which includes a second sub-route 42 extending along the first direction X, as an example. Of course, the first routing line 4 may also include a first sub-route 41 extending along the second direction Y, or the first routing line 4 may also include a second sub-route 42 extending along the first direction X and a first sub-route 42 extending along the second direction Y. The first sub-route 41 and the second sub-route 42 are connected, as not shown in the figure.

[0096] Figure 21In this embodiment, the first sub-trace 41 includes a winding portion 9, which partially surrounds the support pillar 7 in a direction perpendicular to the plane of the first substrate 201. A first gap 10 exists between the winding portion 9 and the support pillar 7 in the same direction, meaning they do not overlap. In this embodiment, the winding portion 9 of the first trace 4 partially surrounds the support pillar 7, and the first gap 10 exists between the winding portion 9 and the support pillar 7 in a direction perpendicular to the plane of the first substrate 201. This ensures better flatness at the end of the support pillar 7 that contacts the array substrate, improving the flatness of the support pillar 7 position and reducing light leakage during extrusion. Furthermore, due to the first gap 10, even with a certain degree of alignment deviation, the flatness of the corresponding position of the support pillar 7 can be guaranteed, further improving the light leakage problem during extrusion.

[0097] In some alternative embodiments, reference continues to be made to... Figure 21 The first interval 10 is greater than or equal to 3μm.

[0098] It is understandable that a larger first interval 10 improves the flatness of the support pillar 7 and enhances the performance of extrusion light leakage. Conversely, a smaller first interval 10 means that the winding portion 9 and the support pillar 7 are more likely to overlap in the direction perpendicular to the plane of the first substrate 201, leading to more extrusion light leakage. In this embodiment, the first interval 10 is greater than or equal to 3 μm, ensuring good flatness of the support pillar 7 and effectively improving the performance of extrusion light leakage.

[0099] In some alternative embodiments, reference continues to be made to... Figures 18 to 20 The first trace 4 includes a notch 8, which overlaps with the support post 7 in a direction perpendicular to the plane of the first substrate 201.

[0100] In a direction perpendicular to the plane of the first substrate 201, there is a second gap 11 between the edge of the notch 8 and the support post 7, the second gap 11 being greater than or equal to 3.5 μm.

[0101] It is understandable that after forming the first trace 4, a planarization layer needs to be formed on the side of the first trace 4 away from the first substrate 201. The planarization of the support pillar 7 is poor, and when the display panel 100 is subjected to pressure, squeezing the support pillar 7 may cause light leakage. In this embodiment, the notch 8 overlaps with the support pillar 7 in the direction perpendicular to the plane of the first substrate 201, which can improve the planarization of the support pillar 7 and improve the squeezing light leakage performance. In the direction perpendicular to the plane of the first substrate 201, the larger the second interval 11 between the edge of the notch 8 and the support pillar 7, the better the planarization of the support pillar 7 is improved, and the better the effect of improving the squeezing light leakage performance. The smaller the second interval 11, that is, the easier it is for the first trace 4 and the support pillar 7 to overlap in the direction perpendicular to the plane of the first substrate 201, the easier it is to generate squeezing light leakage. In this embodiment, the second interval 11 is greater than or equal to 3.5 μm, which can ensure good planarization of the support pillar 7 and improve the squeezing light leakage performance.

[0102] In some alternative embodiments, refer to Figure 22 , Figure 22 This is a schematic diagram of a planar structure of another display panel provided by the present invention. The non-display area BB also includes a common electrode signal line 12. The common electrode signal line 12 at least partially surrounds the display area AA. The common electrode signal line 12 is electrically connected to the driving chip and is electrically connected to the common electrode 206. The common electrode signal line 12 is located in the second metal layer 204.

[0103] Reference Figure 22 The figure does not show part of the film structure in display area AA; only the first trace 4 of the mesh structure is schematically shown. The film structure in display area AA can be referred to... Figures 1 to 21 In this embodiment, the structure of the display area AA is applicable to any of the above embodiments, and will not be described again here.

[0104] Figure 22 The illustration only uses the example of the driver chip being bonded to the array substrate 2 (COG). Of course, it could also be COF, where the driver chip is bonded to a flexible circuit board and bent to the back of the display panel 100, with the flexible circuit board bonded to the array substrate 2, thereby reducing the width of the non-display area BB. The common electrode 206 line is electrically connected to the input pad on the driver chip via the output pad on the array substrate 2. The input and output pads are not shown in the figure.

[0105] Figure 22 The non-display area BB has multiple common electrode signal lines 12, of course. Figure 22The above describes only possible connection methods for the common electrode signal line 12 and is not intended to be the only limitation of the actual product. The common electrode signal line 12 is electrically connected to the driver chip and the common electrode 206 respectively. The common electrode signal line 12 transmits the common voltage of the driver chip to the common electrode 206. The common electrode signal line 12 is located in the second metal layer 204 and can be electrically connected to the common electrode 206 through vias.

[0106] Specifically, the common electrode signal line 12 can be divided into three categories: external common electrode signal line 121, feedback common electrode signal line 122, and internal common electrode signal line 123. Figure 22 In the middle, the inner common electrode signal line 123 surrounds the display area AA as a whole, while the outer common electrode signal line 121 and the feedback common electrode signal line 122 partially surround the display area AA. Figure 22 In the middle, the external common electrode signal line 121 and the feedback common electrode signal line 122 are electrically connected to the internal common electrode signal line 123 at the far end (the side away from the driver chip) and are also electrically connected to the common electrode 206. At the near end (the end closer to the driver chip), the internal common electrode signal line 123 is also electrically connected to the common electrode 206. This can prevent the common voltage signal from generating a voltage drop and improve the uniformity of the signal.

[0107] In some alternative embodiments, refer to Figure 23 and Figure 24 , Figure 23 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 24 yes Figure 23 A cross-sectional view along the D-D' direction, the non-display area BB includes a first non-display area BB1 and a second non-display area BB2 arranged opposite to each other along the second direction Y, and a third non-display area BB3 and a fourth non-display area BB4 arranged opposite to each other along the first direction X, the first non-display area BB1 includes a driver chip;

[0108] The second non-display area BB2, the third non-display area BB3 and / or the fourth non-display area BB4 also include a second trace 13, which is on the same layer as the first trace 4 and is electrically connected to the common electrode 206.

[0109] Specifically, the driver chip is located in the first non-display area. Figure 23The second non-display area BB2, the third non-display area BB3, and the fourth non-display area BB4 may all include the second trace 13. Alternatively, the second non-display area BB2 may include the second trace 13, or the third non-display area BB3 may include the second trace 13, or the fourth non-display area BB4 may include the second trace 13, or the second non-display area BB2 and the third non-display area BB3 may include the second trace 13, or the second non-display area BB2 and the fourth non-display area BB4 may include the second trace 13, or the third non-display area BB3 and the fourth non-display area BB4 may include the second trace 13. The second trace 13 can be located on the third metal layer 209. The second trace 13 is set on the same layer as the first trace 4. The third metal layer 209 is set in the display area AA, and the second trace 13 is also set on the third metal layer 209 in the non-display area BB. The second trace 13 is electrically connected to the common electrode 206. Optionally, the second trace 13 is directly connected to the common electrode 206 without the need for vias, which can reduce the difficulty of manufacturing process and does not increase the thickness of the display panel 100. The second trace 13 and the first trace 4 can be manufactured in the same process, which simplifies the process.

[0110] It should be noted that the second trace 13 and the first trace 4 are located on the same side. That is, when the first trace 4 is located on the side of the common electrode 206 close to the first substrate 201, the second trace 13 is also located on the side of the common electrode 206 close to the first substrate 201. When the first trace 4 is located on the side of the common electrode 206 away from the first substrate 201, the second trace 13 is also located on the side of the common electrode 206 away from the first substrate 201. At this time, the second trace 13 is in direct contact with the common electrode trace 12.

[0111] The first trace 4 in the display area AA is connected in parallel with the common electrode 206. The total resistance after the common electrode 206 and the first trace 4 are connected in parallel is reduced. At the same time, in this embodiment, the second trace 13 is directly electrically connected to the common electrode 206, which can make full use of the space in the non-display area BB. The second trace 13 is connected in parallel with the common electrode 206. The total resistance after the common electrode 206, the second trace 13, and the first trace 4 are connected in parallel is further reduced. When the data voltage changes, the common voltage can recover to the reference more quickly, further improving the horizontal crosstalk bright lines.

[0112] Optionally, in the non-display area BB, Figure 24 In the process, the second trace 13 is in direct contact with the common electrode 206, and the common electrode trace 12 is also in direct contact with the common electrode 206 (or the common electrode trace 12 and the common electrode 206 are connected through a via), forming a stacked structure of the second trace 13, the common electrode 206, and the common electrode trace 12, thereby further reducing the total resistance. When the data voltage changes, the common voltage can recover to the reference more quickly, further improving the horizontal crosstalk bright line.

[0113] In some alternative embodiments, reference continues to be made to... Figure 23 In a direction perpendicular to the plane of the first substrate 201, the second trace 13 overlaps at least partially with the common electrode signal line 12.

[0114] Figure 23 The diagram only schematically shows the case where the common electrode signal line 12 is located within the second trace 13 in the direction perpendicular to the plane of the first substrate 201. Of course, the second trace 13 may also partially overlap with the common electrode signal line 12 in the direction perpendicular to the plane of the first substrate 201, which is not shown here.

[0115] It should be noted that the second trace 13 is made of a metallic material, which is reflective. Therefore, if the second trace 13 is placed in the non-display area BB, the non-display area BB will reflect light, which is detrimental to achieving a seamless black finish on the display panel 100. In this embodiment, the second trace 13 at least partially overlaps with the common electrode signal line 12 in a direction perpendicular to the plane of the first substrate 201. This minimizes the space occupied by the second trace 13, thereby reducing the reflection caused by the second trace 13 and facilitating the achievement of a seamless black finish on the display panel.

[0116] In some alternative embodiments, refer to Figure 25 and Figure 26 , Figure 25 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 26 yes Figure 25 A cross-sectional view along the E-E' direction, the non-display area BB includes a first non-display area BB1 and a second non-display area BB2 arranged opposite to each other along the second direction Y, and a third non-display area BB3 and a fourth non-display area BB4 arranged opposite to each other along the first direction X, the first non-display area BB1 includes a driver chip;

[0117] The first non-display area BB1 also includes a third trace 14. In a direction perpendicular to the plane of the first substrate 201, the third trace 14 is located on the side of the common electrode signal line 12 close to the common electrode 206, and the third trace 14 is in direct contact with the common electrode signal line 12.

[0118] Optionally, the second non-display area BB2, the third non-display area BB3, and / or the fourth non-display area BB4 may also include a second trace 13. The second trace 13 is on the same layer as the first trace 4 and is directly connected to the common electrode 206 to further reduce the total resistance after being connected in parallel with the common electrode 206. For details, please refer to [reference needed]. Figure 23 and Figure 24 No specific limitations are made here.

[0119] It is understandable that the common electrode 206 is typically located in the first non-display area BB1 and does not completely cover the first non-display area BB1 along the second direction Y. The portion of the common electrode signal line 12 connected to the driver chip is not covered by the common electrode 206. Optionally, the third trace 14 can be made of the same material and in the same process as the first trace 4, which helps simplify the manufacturing process.

[0120] The first non-display area BB1 on the film layer also includes a third trace 14. In the direction perpendicular to the plane of the first substrate 201, the third trace 14 is located on the side of the common electrode signal line 12 close to the common electrode 206. Since the common electrode 206 does not completely cover the first non-display area BB1, the third trace 14 is directly connected to the common electrode signal line 12. The third trace 14 and the common electrode signal line 12 are connected in parallel. The total resistance after the third trace 14 and the common electrode signal line 12 are connected in parallel can be reduced, thereby reducing the voltage drop of the common voltage, improving the uniformity of the common voltage, and also making use of the space of the third metal layer 209.

[0121] In some alternative embodiments, reference continues to be made to... Figure 25 and Figure 26 The width of the third trace 14 is m, and the width of the first trace 4 is n, where m > n.

[0122] Understandably, in the display area AA, to avoid the first trace 4 being too wide and affecting the pixel aperture ratio, the width of the first trace 4 should be as small as possible. However, in the first non-display area BB1, the third metal layer 209 is set to set the third trace 14, so there is no need to consider the aperture ratio. The width of the third trace 14 can be increased. For the same metal material, the larger the cross-sectional area, the smaller the resistance. After the width of the third trace 14 is increased, the cross-sectional area of ​​the third trace 14 increases, and the resistance is smaller. Therefore, the total resistance after being connected in parallel with the common electrode signal line 12 is smaller, which can better prevent the voltage drop of the common voltage and improve the uniformity of the common voltage.

[0123] In some alternative embodiments, reference continues to be made to... Figure 1 The first metal layer 202 includes scan lines 5 arranged along the second direction Y and extending in the first direction X. The scan lines 5 and data lines 3 intersect to define the region of sub-pixels P. The first trace 4 is located between at least a portion of the sub-pixels P.

[0124] Figure 1 In the middle, the scan line 5 is located in the first metal layer 202, is arranged along the second direction Y and extends along the first direction X, and the scan line 5 intersects with the data line 3 to define the area where the sub-pixel P is located.

[0125] Figure 1 A first trace 4 is set between the middle sub-pixels P. Figure 1The illustration uses only the first routing line 4, including the first sub-routes 41 extending along the second direction Y, as an example. Figure 1 A first sub-line 41 is set every two sub-pixels P, but this is only for illustrative purposes.

[0126] In this invention, the first trace 4 is combined with the sub-pixel P and set according to the arrangement of the sub-pixel P, which is more reasonable. Moreover, the first trace 4 is set between the sub-pixels P, and there are scan lines 5 and data lines 3 between the sub-pixels P. There is a black matrix BM between adjacent sub-pixels P (see reference). Figure 7 To block light, the first trace 4 is disposed on a different metal layer from the scan line 5 and the data line 3. The first trace 4 is located on at least part of the sub-pixel P. In the direction perpendicular to the first substrate 201, the distance between the first trace 4 and the scan line 5 and the data line 3 is as small as possible, or the first trace 4 and the scan line 5 and the data line 3 overlap as much as possible, so as not to reduce the pixel aperture ratio. Furthermore, since the sub-pixels P are arranged in multiple rows and columns, setting the first trace 4 between the sub-pixels P provides ample space and quantity for the first trace 4. The position and quantity of the first trace 4 can be flexibly set according to the recovery time requirements of the common voltage signal and the different degrees of bright line generation. The first trace 4 can also be set according to different specifications of the display panel. It is not only suitable for regular display panels, but also for irregular display panels, such as display panels with under-display cameras, rounded corners, and other irregular shapes. Setting the first trace 4 between the sub-pixels P provides ample space and quantity for the first trace 4. The first trace 4 can be set in special locations mentioned above, and of course, in areas with more traces, avoiding areas with fewer traces and more space.

[0127] In some alternative embodiments, refer to Figure 1 , Figure 5 and Figure 6 Along the first direction X, sub-pixels P form a pixel row; along the second direction Y, sub-pixels P form a pixel column.

[0128] The first sub-line 41 is located between at least a portion of the pixel columns;

[0129] Alternatively, the second sub-routes 42 are located between at least some of the pixel rows;

[0130] Alternatively, the first sub-routes 41 are located between at least a portion of the pixel columns, and the second sub-routes 42 are located between at least a portion of the pixel rows.

[0131] Specifically, multiple sub-pixels P along the first direction X form a pixel row, and multiple sub-pixels P along the second direction Y form a pixel column. Figure 1 The first sub-line 41 is located between at least a portion of the pixel columns. Figure 5In the middle, the second sub-line 42 is located between at least a portion of the pixel rows. Figure 6 In the first sub-line 41, the first sub-line 41 is located between at least a portion of the pixel columns, and the second sub-line 42 is located between at least a portion of the pixel rows. The first sub-line 41 and the second sub-line 42 are connected.

[0132] In this embodiment, the first sub-line 41 extending along the second direction Y is combined with pixel columns and located between at least some pixel columns. The second sub-line 42 extending along the first direction X is combined with pixel rows. The arrangement of pixel rows and pixel columns is more reasonable, the structure is more diverse, and the application range is wider. In this invention, the first line 4 is combined with sub-pixels P and arranged according to the sub-pixel P's arrangement, making the arrangement more reasonable. Furthermore, the first line 4 is set between sub-pixels P, and scan lines 5 and data lines 3 are present between sub-pixels P. A black matrix BM (see reference) is present between adjacent sub-pixels P. Figure 7 To block light, the first trace 4 is disposed on a different metal layer from the scan line 5 and the data line 3. The first trace 4 is located on at least part of the sub-pixel P. In the direction perpendicular to the first substrate 201, the distance between the first trace 4 and the scan line 5 and the data line 3 is as small as possible, or the first trace 4 and the scan line 5 and the data line 3 overlap as much as possible, so as not to reduce the pixel aperture ratio. Furthermore, since the sub-pixels P are arranged in multiple rows and columns, setting the first trace 4 between the sub-pixels P provides ample space and quantity for the first trace 4. The position and quantity of the first trace 4 can be flexibly set according to the recovery time requirements of the common voltage signal and the different degrees of bright line generation. The first trace 4 can also be set according to different specifications of the display panel. It is not only suitable for regular display panels, but also for irregular display panels, such as display panels with under-display cameras, rounded corners, and other irregular shapes. Setting the first trace 4 between the sub-pixels P provides ample space and quantity for the first trace 4. The first trace 4 can be set in special locations mentioned above, and of course, in areas with more traces, avoiding areas with fewer traces and more space.

[0133] In some alternative embodiments, reference continues to be made to... Figure 7 , Figure 8 , Figure 9 , Figure 11 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 and Figure 21 .

[0134] The first sub-line 41 is located between any two adjacent pixel columns;

[0135] Alternatively, the second sub-routes 42 are located between any two adjacent pixel rows;

[0136] Alternatively, the first sub-routes 41 are located between any two adjacent pixel columns, and the second sub-routes 42 are located between any two adjacent pixel rows.

[0137] Specifically, Figure 7 , Figure 11 , Figure 13 , Figure 18 In the first trace 4, there are first sub-traces 41 extending along the second direction Y. The first sub-traces 41 are located between any two adjacent pixel columns, that is, along the first direction X. The more first sub-traces 41 there are, the more stable the connection with the common electrode 206. After being connected in parallel with the common electrode 206, the resistance is reduced. When the data voltage changes, the common voltage can be restored to the reference more quickly, which further improves the horizontal crosstalk bright lines. Since the sub-pixel P is set in multiple rows and columns, the first trace 4 is set between the sub-pixels P, so that the first trace has sufficient setting space and number.

[0138] Figure 8 , Figure 15 , Figure 16 , Figure 19 and Figure 21 In the first trace 4, there is a second sub-trace 42 extending in the first direction X. The second sub-trace 42 is located between any two adjacent pixel rows, that is, along the second direction Y. There is a second sub-trace 42 between any two sub-pixels. The more second sub-traces 42 there are, the more stable the connection with the common electrode 206 is. After being connected in parallel with the common electrode 206, the resistance is reduced. When the data voltage changes, the common voltage can be restored to the reference more quickly, which further improves the horizontal crosstalk bright lines.

[0139] Figure 9 , Figure 14 , Figure 17 , Figure 20 The first trace 4 includes a first sub-trace 41 and a second sub-trace 42 that are interconnected. The first sub-trace 41 is located between any two adjacent pixel columns, and the second sub-trace 42 is located between any two adjacent pixel rows. That is, the first trace 4 is set between any two sub-pixels along the first direction X and between any two sub-pixels along the second direction Y. The more first sub-trace 41 and second sub-trace 42 there are, the more stable the connection with the common electrode 206 will be. After being connected in parallel with the common electrode 206, the resistance will be reduced. When the data voltage changes, the common voltage can be restored to the reference more quickly, which further improves the horizontal crosstalk bright lines.

[0140] In this invention, the first trace 4 is combined with sub-pixels and set according to the arrangement of sub-pixels, which makes the setting more reasonable.

[0141] In some alternative embodiments, refer to Figure 27 and Figure 28 , Figure 27 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 28 This is a schematic diagram of a planar structure of another display panel provided by the present invention.

[0142] Figure 27 and Figure 28 The first trace 4 includes a second sub-trace 42 extending along the first direction X. The second sub-trace 42 includes at least a first segment 15 and a second segment 16. The first segment 15 is connected to a portion of the first sub-trace 41, and the second segment 16 is connected to other portions of the first sub-trace 41.

[0143] Along the first direction X, the extension line of the first segment 15 and the extension line of the second segment 16 are on the same straight line, or the extension lines of the first segment 15 and the extension lines of the second segment 16 do not coincide.

[0144] like Figure 27 As shown, the first segment 15 is connected to the first sub-trace 41 from the 1st to the 9th, and the second segment 16 is connected to the first sub-trace 41 from the 10th to the 18th. Along the first direction X, the extension lines of the first segment 15 and the second segment 16 are on the same straight line. In this way, the first segment 15 and the second segment 16 can be etched at the same time during manufacturing, and the etching is more convenient.

[0145] like Figure 28 As shown, along the first direction X, the extension lines of the first segment 15 and the second segment 16 are on the same straight line, or the extension lines of the first segment 15 and the second segment 16 do not coincide. The first segment 15 is connected to the 1st to 8th first sub-routes 41, and the second segment 16 is connected to the 8th to 10th first sub-routes 41. The first segment 15 and the second segment 16 are not on the same straight line, that is, the first segment 15 and the second segment 16 are misaligned. Of course... Figure 28 The diagram also shows that the second sub-routes 42 include a third segment, which is on the same extension line as the first segment 15, and the third segment is also staggered from the second segment 16.

[0146] In this embodiment, the second sub-routing 42 can be partitioned. For irregularly shaped display panels 100, such as waterdrop screens, or those with under-display cameras, rounded corners, or other special features... Figure 28This illustration uses an under-display camera as an example. To avoid affecting the display or camera functions of the irregularly shaped display panel 100, the placement of second sub-routes 42 in these special locations should be minimized to prevent them from becoming visible and affecting their display or camera functions. In this embodiment, the special locations of the under-display camera are avoided by staggering the placement, making the design more flexible and practical.

[0147] Of course, in this invention, the second sub-routes 42 can be set in different areas according to actual needs and the special functions of the display panel 100, and the density of the second sub-routes 42 can be changed, making it more targeted and applicable to a wider range.

[0148] In some alternative embodiments, reference continues to be made to... Figure 1 , Figure 2 and reference Figure 29 and Figure 30 , Figure 29 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 30 yes Figure 29 A cross-sectional view along the F-F' direction. The first metal layer 202 includes scan lines 5 arranged along the second direction Y and extending in the first direction X. The scan lines 5 and data lines 3 intersect to define the region of sub-pixel P.

[0149] The display panel 100 further includes an active layer 207, which is located between the first substrate 201 and the first metal layer 202, or between the first metal layer 202 and the second metal layer 204; the display panel 100 also includes a transistor T, the semiconductor T4 layer of which is located in the active layer 207.

[0150] Figure 1 and Figure 2 The diagram shows that the active layer 207 is located between the first metal layer 202 and the second metal layer 204, and the transistor T has a bottom gate structure. Figure 29 and Figure 30 The diagram shows an active layer 207 located between a first substrate 201 and a first metal layer 202, and the transistor T is a top-gate structure. When it is a top-gate structure, it also includes a light-shielding layer 2010, which is located on the side of the semiconductor T4 near the first substrate 201, and is used to prevent leakage current from the semiconductor T4.

[0151] The structure of this invention is applicable to both top-gate and bottom-gate structures, and has a wide range of applications.

[0152] Based on the same inventive concept, the present invention also provides a method for manufacturing a display panel 100, referring to... Figure 31 , Figure 31 This is a flowchart of a method for manufacturing a display panel according to the present invention, used for manufacturing... Figures 1 to 30 The display panel 100 in any embodiment is described in detail below. Figures 1 to 30 The display panel 100 includes a color filter substrate 1 and an array substrate 2 disposed opposite to each other. The array substrate 2 includes: a first substrate 201; a first metal layer 202 located on one side of the first substrate 201; a second metal layer 204 located on the side of the first metal layer 202 away from the first substrate 201; a first insulating layer 203 is included between the first metal layer 202 and the second metal layer 204; the second metal layer 204 includes data lines 3, a plurality of data lines 3 arranged along a first direction X and extending in a second direction Y; a common electrode 206 located on the side of the second metal layer 204 away from the first substrate 201; the second metal layer 201... A second insulating layer 205 is included between the data line 3 and the common electrode 206. The orthographic projection of the data line 3 onto the plane of the first substrate 201 at least partially overlaps with the orthographic projection of the common electrode 206 onto the plane of the first substrate 201. The display panel 100 also includes a display area AA and a non-display area BB that at least partially surrounds the display area AA. The display area AA also includes a first trace 4. The first trace 4 is located on the side of the common electrode 206 away from the first substrate 201, or the first trace 4 is located on the side of the common electrode 206 close to the first substrate 201. The first trace 4 is in direct contact with the common electrode 206.

[0153] The first routing line 4 includes a first sub-routes 41 extending along the second direction Y;

[0154] Alternatively, the first routing 4 includes a second sub-routes 42 extending along the first direction X;

[0155] Alternatively, the first trace 4 includes a first sub-trace 41 extending in the second direction Y and a second sub-trace 42 extending in the first direction X, wherein the second sub-trace 42 is connected to the first sub-trace 41.

[0156] The production method includes the following steps:

[0157] S1: Provides color filter substrate 1;

[0158] S2: Fabrication of array substrate 2, including:

[0159] S201: Provide a first substrate 201;

[0160] S202: A first metal layer 202 is formed on one side of the first substrate 201;

[0161] S203: A first insulating layer 203 is formed on the side of the first metal layer 202 away from the first substrate 201;

[0162] S204: A second metal layer 204 is formed on the side of the first insulating layer 203 away from the first substrate 201. The second metal layer 204 is etched to form data lines 3 arranged along the first direction X and extending in the second direction Y.

[0163] S205: A second insulating layer 205 is formed on the side of the second metal layer 204 away from the first substrate 201;

[0164] S206: A common electrode 206 is formed on the side of the second insulating layer 205 away from the first substrate 201, and the orthographic projection of the data line 3 onto the plane of the first substrate 201 at least partially overlaps with the orthographic projection of the common electrode 206 onto the plane of the first substrate 201.

[0165] S207: In at least the display area AA of the display panel 100, a third metal layer 209 is formed on the side of the common electrode 206 away from the first substrate 201. The third metal layer 209 is etched to form a first trace 4, such that the first trace 4 is in direct contact with the common electrode 206. The first trace 4 includes a first sub-trace 41 extending along the second direction Y; or, the first trace 4 includes a second sub-trace 42 extending along the first direction X; or, the first trace 4 includes a first sub-trace 41 extending along the second direction Y and a second sub-trace 42 extending along the first direction X, and the second sub-trace 42 is connected to the first sub-trace 41.

[0166] Alternatively, S206: In at least the display area AA of the display panel 100, a third metal layer 209 is formed on the side of the second insulating layer 205 away from the first substrate 201, and the third metal layer 209 is etched to form a first trace 4, wherein the first trace 4 includes a first sub-trace 41 extending along the second direction Y; or, the first trace 4 includes a second sub-trace 42 extending along the first direction X; or, the first trace 4 includes a first sub-trace 41 extending along the second direction Y and a second sub-trace 42 extending along the first direction X, wherein the second sub-trace 42 is connected to the first sub-trace 41;

[0167] S207: A common electrode 206 is formed on the side of the first trace 4 away from the first substrate 201. The orthographic projection of the data line 3 onto the plane of the first substrate 201 and the orthographic projection of the common electrode 206 onto the plane of the first substrate 201 overlap at least partially. The first trace 4 is in direct contact with the common electrode 206.

[0168] Figure 31 The illustration will be based on the example of the first trace 4 being located on the side of the common electrode 206 away from the first substrate 201.

[0169] Optionally, the first metal layer 202 can be etched by wet etching to obtain the scan line 5, the second metal layer 204 can be etched by wet etching to obtain the data line 3, and the third metal layer 209 can be etched by wet etching to obtain the first trace 4.

[0170] In this invention, the first trace 4 is in direct contact with the common electrode 206, eliminating the need to form an insulating layer between the common electrode 206 and the first trace 4 before drilling holes. Connecting vias not only complicates the manufacturing process but also increases the thickness of the display panel 100. Direct contact between the first trace 4 and the common electrode 206 simplifies the process and also helps reduce the thickness of the display panel 100.

[0171] Reference Figure 32 , Figure 32 This is a schematic diagram of the planar structure of a display device provided in an embodiment of the present invention. The display device 1000 provided in this embodiment includes the display panel 100 provided in the above embodiment of the present invention. Figure 32 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device 1000 provided in this embodiment can be any other display device 1000 with display functions, such as a computer, television, or vehicle-mounted display device; this invention does not impose specific limitations on this. The display device 1000 provided in this embodiment has the beneficial effects of the display panel provided in this embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0172] As can be seen from the above embodiments, the display panel, its manufacturing method, and the display device provided by the present invention achieve at least the following beneficial effects:

[0173] This invention provides a first trace on the side of the common electrode away from the first substrate. The first trace is in direct contact with the common electrode, forming a parallel connection. The first trace can be made of metal or other conductors with low impedance. According to the principle of resistance, the total resistance after parallel connection is less than the two resistances connected in parallel. Therefore, the total resistance of the common electrode and the first trace in parallel is reduced. When the data voltage changes, the common voltage can quickly recover to the reference, improving horizontal crosstalk bright lines. In this invention, the first trace is in direct contact with the common electrode, eliminating the need to first set an insulating layer on one side of the common electrode, then fabricate the first trace, and then connect it through a via. This not only complicates the manufacturing process but also increases the thickness of the display panel. The direct contact between the first trace and the common electrode simplifies the process and helps reduce the thickness of the display panel. The first trace includes a first sub-trace extending along a second direction. The first sub-trace is directly connected to the common electrode, forming a parallel connection. The total resistance after the first sub-trace and the common electrode are in parallel is reduced. When the data voltage changes, the common voltage can quickly recover to the reference, improving horizontal crosstalk bright lines. Alternatively, the first trace includes a second sub-trace extending along a first direction. The second sub-trace is directly connected to the common electrode, forming a parallel connection. The total resistance after the second sub-trace and the common electrode are connected in parallel is reduced. When the data voltage changes, the common voltage can quickly recover to the reference, improving horizontal crosstalk bright lines. Alternatively, the first trace includes a first sub-trace extending along a second direction and a second sub-trace extending along the first direction. The second sub-trace is connected to the first sub-trace, forming a mesh that is directly connected to the common electrode. This further reduces the total resistance after parallel connection. With the reduced total resistance, when the data voltage changes, the common voltage can quickly recover to the reference, improving horizontal crosstalk bright lines.

[0174] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, It includes a color filter substrate and an array substrate disposed opposite to each other, the array substrate comprising: First substrate; A first metal layer is located on one side of the first substrate, and a second metal layer is located on the side of the first metal layer away from the first substrate. A first insulating layer is included between the first metal layer and the second metal layer. The second metal layer includes data lines, and a plurality of the data lines are arranged along a first direction and extend in a second direction. A common electrode is located on the side of the second metal layer away from the first substrate. A second insulating layer is included between the second metal layer and the common electrode. The orthographic projection of the data line on the plane where the first substrate is located at least partially overlaps with the orthographic projection of the common electrode on the plane where the first substrate is located. The display panel further includes a display area and a non-display area that at least partially surrounds the display area. At least the display area also includes a first trace, which is located on the side of the common electrode away from the first substrate, or the first trace is located on the side of the common electrode close to the first substrate, and the first trace is in direct contact with the common electrode. The first trace includes a first sub-trace extending along the second direction; Alternatively, the first trace may include a second sub-trace extending along the first direction; Alternatively, the first trace may include a first sub-trace extending along the second direction and a second sub-trace extending along the first direction, wherein the second sub-trace is connected to the first sub-trace; The non-display area also includes a common electrode signal line, which at least partially surrounds the display area. The common electrode signal line is electrically connected to the driver chip and to the common electrode. The common electrode signal line is located in the second metal layer. The non-display area includes a first non-display area and a second non-display area disposed opposite to each other along the second direction, and a third non-display area and a fourth non-display area disposed opposite to each other along the first direction, wherein the first non-display area includes the driver chip; The second non-display area, the third non-display area and / or the fourth non-display area further include a second trace, the second trace being on the same layer as the first trace, and the second trace being electrically connected to the common electrode; In a direction perpendicular to the plane of the first substrate, the second trace at least partially overlaps with the common electrode signal line.

2. The display panel according to claim 1, characterized in that, The color filter substrate includes a second substrate and a black matrix located on one side of the second substrate, wherein the orthographic projection of the first trace on the plane of the first substrate is located within the orthographic projection of the black matrix on the plane of the first substrate.

3. The display panel according to claim 1, characterized in that, The color filter substrate includes a second substrate. The display panel further includes a support pillar, which is located between the first substrate and the second substrate. In a direction perpendicular to the plane of the first substrate, the first trace at least partially overlaps with the support post; Alternatively, in a direction perpendicular to the plane of the first substrate, at least a portion of the first trace partially surrounds the support pillar; Alternatively, the first trace may include a notch that overlaps with the support post in a direction perpendicular to the plane of the first substrate.

4. The display panel according to claim 3, characterized in that, In a direction perpendicular to the plane of the first substrate, at least a portion of the first trace partially surrounds the support pillar; The first trace includes a winding portion, which partially surrounds the support post in a direction perpendicular to the plane of the first substrate. In a direction perpendicular to the plane of the first substrate, there is a first gap between the winding portion and the support post.

5. The display panel according to claim 4, characterized in that, The first interval is greater than or equal to 3 μm.

6. The display panel according to claim 3, characterized in that, The first trace includes a notch, and in a direction perpendicular to the plane of the first substrate, the notch overlaps with the support post; In a direction perpendicular to the plane of the first substrate, there is a second gap between the edge of the notch and the support post, the second gap being greater than or equal to 3.5 μm.

7. The display panel according to claim 1, characterized in that, The first non-display area also includes a third trace, which is located on the side of the common electrode signal line close to the common electrode in a direction perpendicular to the plane of the first substrate, and the third trace is in direct contact with the common electrode signal line.

8. The display panel according to claim 7, characterized in that, The width of the third trace is m, and the width of the first trace is n, where m > n.

9. The display panel according to claim 1, characterized in that, The first metal layer includes scan lines arranged along the second direction and extending in the first direction, the scan lines and the data lines intersecting to define a region of a sub-pixel, and the first trace is located between at least a portion of the sub-pixels.

10. The display panel according to claim 9, characterized in that, Along the first direction, the sub-pixels form a pixel row; along the second direction, the sub-pixels form a pixel column. The first sub-trace is located between at least a portion of the pixel columns; Alternatively, the second sub-trace is located between at least a portion of the pixel rows; Alternatively, the first sub-routes are located between at least a portion of the pixel columns, and the second sub-routes are located between at least a portion of the pixel rows.

11. The display panel according to claim 10, characterized in that, The first sub-trace is located between any two adjacent pixel columns; Alternatively, the second sub-trace may be located between any two adjacent pixel rows; Alternatively, the first sub-routes may be located between any two adjacent pixel columns, and the second sub-routes may be located between any two adjacent pixel rows.

12. The display panel according to claim 1, characterized in that, When the first trace includes a second sub-trace extending along the first direction, the second sub-trace includes at least a first segment and a second segment, the first segment being connected to a portion of the first sub-trace, and the second segment being connected to the other portions of the first sub-trace. Along the first direction, the extension line of the first segment and the extension line of the second segment are on the same straight line, or the extension line of the first segment and the extension line of the second segment do not coincide.

13. The display panel according to claim 1, characterized in that, The first metal layer includes scan lines arranged along the second direction and extending in the first direction, wherein the scan lines and the data lines intersect to define the region of a sub-pixel; The display panel further includes an active layer, which is located between the first substrate and the first metal layer, or between the first metal layer and the second metal layer; the display panel further includes a transistor, the semiconductor layer of which is located in the active layer.

14. A method for manufacturing a display panel, characterized in that, The display panel includes a color filter substrate and an array substrate disposed opposite to each other, the array substrate comprising: First substrate; A first metal layer is located on one side of the first substrate, and a second metal layer is located on the side of the first metal layer away from the first substrate. A first insulating layer is included between the first metal layer and the second metal layer. The second metal layer includes data lines, and a plurality of the data lines are arranged along a first direction and extend in a second direction. A common electrode is located on the side of the second metal layer away from the first substrate. A second insulating layer is included between the second metal layer and the common electrode. The orthographic projection of the data line on the plane where the first substrate is located at least partially overlaps with the orthographic projection of the common electrode on the plane where the first substrate is located. The display panel further includes a display area and a non-display area that at least partially surrounds the display area. At least the display area also includes a first trace, which is located on the side of the common electrode away from the first substrate, or the first trace is located on the side of the common electrode close to the first substrate, and the first trace is in direct contact with the common electrode. The first trace includes a first sub-trace extending along the second direction; Alternatively, the first trace may include a second sub-trace extending along the first direction; Alternatively, the first trace includes a first sub-trace extending in the second direction and a second sub-trace extending in the first direction, wherein the second sub-trace is connected to the first sub-trace; The non-display area also includes a common electrode signal line, which at least partially surrounds the display area. The common electrode signal line is electrically connected to the driver chip and to the common electrode. The common electrode signal line is located in the second metal layer. The non-display area includes a first non-display area and a second non-display area disposed opposite to each other along the second direction, and a third non-display area and a fourth non-display area disposed opposite to each other along the first direction, wherein the first non-display area includes the driver chip; The second non-display area, the third non-display area and / or the fourth non-display area further include a second trace, the second trace being on the same layer as the first trace, and the second trace being electrically connected to the common electrode; In a direction perpendicular to the plane of the first substrate, the second trace at least partially overlaps with the common electrode signal line; The manufacturing method includes: Provide color filter substrates; Fabrication of the array substrate includes: Provide a first substrate; A first metal layer is formed on one side of the first substrate. A first insulating layer is formed on the side of the first metal layer away from the first substrate. A second metal layer is formed on the side of the first insulating layer away from the first substrate, and the second metal layer is etched to form data lines arranged in a first direction and extending in a second direction; A second insulating layer is formed on the side of the second metal layer away from the first substrate. A common electrode is formed on the side of the second insulating layer away from the first substrate. The orthographic projection of the data line onto the plane of the first substrate at least partially overlaps with the orthographic projection of the common electrode onto the plane of the first substrate. In at least the display area of ​​the display panel, a third metal layer is formed on the side of the common electrode away from the first substrate. The third metal layer is etched to form a first trace, such that the first trace is in direct contact with the common electrode. The first trace includes a first sub-trace extending along the second direction; or, the first trace includes a second sub-trace extending along the first direction; or, the first trace includes a first sub-trace extending along the second direction and a second sub-trace extending along the first direction, wherein the second sub-trace is connected to the first sub-trace. Alternatively, at least in the display area of ​​the display panel, a third metal layer is formed on the side of the second insulating layer away from the first substrate, and the third metal layer is etched to form a first trace, wherein the first trace includes a first sub-trace extending along the second direction; or, the first trace includes a second sub-trace extending along the first direction; or, the first trace includes a first sub-trace extending along the second direction and a second sub-trace extending along the first direction, the second sub-trace being connected to the first sub-trace; a common electrode is formed on the side of the first trace away from the first substrate, the orthographic projection of the data line on the plane of the first substrate at least partially overlaps with the orthographic projection of the common electrode on the plane of the first substrate, and the first trace is in direct contact with the common electrode.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 13.

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