Last level cache based on linked list structure and supporting dynamic partition granularity access

Abstract

This application discloses a last-level cache, including a data memory, a tag memory, a miss lock information memory, a hit test unit, and a miss status processing register. The data memory includes multiple cache lines, each including a high-order partition and a low-order partition. The tag memory stores multiple tag information and multiple partition validity information. The miss lock information memory stores miss lock information corresponding to the multiple cache lines. Based on the tag information field and partition information field, the hit test unit determines whether a high-order partition or a low-order partition has been hit. If a first request and a second request have the same tag information field and partition information field, and when the hit test unit determines that the first request is a cache miss and the second request is a cache miss hit, the miss status processing register temporarily stores the first request and the second request in a linked list format according to the time order in which they entered the last-level cache.

Description

Technical Field

[0001] This invention relates to a cache, and more specifically to a last-level cache based on a linked list structure that supports dynamic partition-level access. Background Technology

[0002] A cache is a high-speed but small-capacity storage device located between the central processing unit (CPU) and main memory, significantly reducing the time spent repeatedly accessing main memory during process execution. However, typical caches use fixed-size cache lines to read data from main memory, offering little flexibility in adjusting the granularity of memory accesses, thus hindering the efficiency of cache line utilization. Therefore, dynamically adjusting the granularity of cache memory accesses while simultaneously considering the order in which requests are processed to avoid errors is a pressing problem in this field. Summary of the Invention

[0003] One of the purposes of this application is to disclose a final-level cache and its associated calculator system to solve the above-mentioned problems.

[0004] One embodiment of this application relates to a final-level cache, used to receive multiple requests from a computing engine through a first interface and access memory through a second interface, wherein each of the multiple requests includes a tag information field and a partition information field. The final-level cache includes a data memory, a tag memory, a miss lock information memory, a hit test unit, and a miss status processing register. The data memory includes multiple cache lines, each cache line including a high-order partition and a low-order partition, the width of which is the same as the width of the low-order partition. The tag memory stores multiple tag information and multiple partition validity information. The multiple tag information corresponds to multiple cache lines, and the multiple partition validity information corresponds to multiple cache lines, wherein each partition validity information includes a high-order valid bit and a low-order valid bit, used to indicate whether the high-order and low-order partitions of the corresponding multiple cache lines are in a valid state. The miss lock information memory stores multiple miss lock information corresponding to the multiple cache lines, wherein each miss lock information includes a high-order miss lock bit and a low-order miss lock bit, used to indicate whether the high-order and low-order partitions of the corresponding multiple cache lines are in a locked state. Based on the tag information field and partition information field, the hit test unit determines whether a high-order or low-order partition of multiple cache lines has been hit. These multiple requests include a first request and a second request. The tag information field of the first request is the same as that of the second request, and the partition information field of the first request is also the same as that of the second request. When the hit test unit determines that the first request is a cache miss and the second request is a cache miss hit, the miss status processing register temporarily stores the first request and the second request in a linked list format according to the time sequence in which they entered the last-level cache.

[0005] Another embodiment of this application relates to a calculator system, including a final-level cache, a computing engine, and memory.

[0006] Because the last-level cache of this application can dynamically adjust the granularity of memory access, the cache lines can be used more efficiently. In addition, through the linked list structure, the last-level cache of this application can maintain the order in which requests are returned according to the time order in which requests enter the last-level cache, thereby achieving consistency of requests entering and leaving the last-level cache. Attached Figure Description

[0007] The aspects of this disclosure will be better understood from the following embodiments when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various structures are not drawn to scale. In fact, the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 This is a schematic diagram of an embodiment of the final-level cache of this application.

[0009] Figure 2 A comparison table of final-level cache configurations for different settings.

[0010] Figure 3 This diagram illustrates the execution of a hit test for the hit test unit of the final cache in this application.

[0011] Figure 4 This diagram illustrates the execution of a hit test for the hit test unit of the final cache in this application.

[0012] Figure 5 This diagram illustrates the execution of a hit test for the hit test unit of the final cache in this application.

[0013] Figure 6 This application's final-level cache is a table that reads data from memory for partial write operations.

[0014] Figure 7 This is a schematic diagram of an embodiment of the calculator system of this application. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples of various components for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, such examples are merely illustrative and are not intended to be limiting. For example, in the following description, embodiments in which a first component is formed above or on a second component may include instances in which the first and second components are in direct contact, and embodiments in which additional components may be formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” “above,” and similar terms may be used herein to describe the relationship of one component or member to another component or member illustrated in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise) and therefore the spatial relative descriptors used herein may be interpreted in the same way.

[0017] As used herein, terms such as “first,” “second,” and “third” describe various components, parts, areas, layers, and / or sections, but such components, parts, areas, layers, and / or sections should not be limited by such terms. Such terms are used only to distinguish one component, part, area, layer, or section from another. The use of terms such as “first,” “second,” and “third” herein does not imply sequence or order unless explicitly indicated by the context.

[0018] The singular forms "a," "an," and "the" may also include plural forms unless the context explicitly indicates otherwise. The term "connection," along with its derivatives, may be used herein to describe structural relationships between components. "Connection" may be used to describe two or more components in direct physical or electrical contact with each other. "Connection" may also be used to indicate two or more components in direct or indirect physical or electrical contact with each other (with intervening components between them), and / or two or more components cooperating or interacting with each other.

[0019] Figure 1 This is a schematic diagram of an embodiment of the final-level cache 10 of this application. Figure 1 As shown, the last-level cache (LLC) 10 may include a first interface 110, a second interface 120, a data memory 130, a tag memory 140, a miss lock information memory 150, a hit test unit 160, and a miss status handle register (MSHR) 170. In this embodiment, the last-level cache 10 can receive multiple requests from the computing engine (not shown in the figure) through the first interface 110, and can access memory (not shown in the figure) through the second interface 120, wherein the types of multiple requests may include read operations and write operations.

[0020] The data storage 130 may include multiple cache lines, each cache line including a high-order sector and a low-order sector, wherein the width of the high-order sector and the width of the low-order sector are the same. For example, if the width of each cache line is 128 bytes, then the width of both the high-order sector and the low-order sector is 64 bytes.

[0021] The tag memory 140 can be used to store multiple tag information and multiple partition validity information. The multiple tag information can correspond to the multiple cache lines respectively, and the multiple partition validity information can correspond to the multiple cache lines respectively. Each partition validity information may include a high-order valid bit and a low-order valid bit, which are used to indicate whether the high-order partition and the low-order partition of the corresponding multiple cache lines are in a valid state.

[0022] The miss lock information memory 150 can be used to store multiple miss lock information corresponding to the plurality of cache lines. Each miss lock information may include a high-order miss lock bit and a low-order miss lock bit, which are used to indicate whether the high-order partition and the low-order partition corresponding to the plurality of cache lines are in a locked state, respectively. For example, when a cache line (or any partition therein) is allocated to a request that is determined to be a cache miss, the miss lock information may indicate that the cache line (or any partition therein) is in a locked state to prevent the cache line (or any partition therein) from being allocated to other requests before the data of the requested request is read back from memory from the cache line.

[0023] In one embodiment, each of the plurality of requests includes a tag information field and a partition information field. Based on the tag information field and the partition information field, the hit test unit 160 determines whether the high-order partition or the low-order partition of the plurality of cache lines has been hit. The hit test unit 160 can determine whether each request is a cache hit, a cache miss, or a cache hit-on-miss, and the determination criteria will be explained later.

[0024] In one embodiment, the plurality of requests includes a first request and a second request. The tag information field of the first request is the same as that of the second request, and the partition information field of the first request is the same as that of the second request. In other words, the first request and the second request have the same address. In this case, when the hit test unit 160 determines that the first request is a cache miss and the second request is a cache miss hit, the miss status processing register 170 can temporarily store the first request and the second request in a linked list format according to the time order in which the first request and the second request entered the last-level cache 10. That is, the miss status processing register 170 has the function of maintaining the access order of each request. Since the order in which requests with the same address are returned to the computing engine must be the same as the time order in which each request enters the last-level cache 10, the miss status processing register 170 can maintain the order of the plurality of requests determined to be cache misses or cache miss hits through the linked list.

[0025] Figure 2Table 20 compares the different configurations of the final level cache. The following explanations all use a final level cache with a data memory capacity of 1MB and divided into 16 ways as an example. Taking configuration 202 as an example, each cache line is 64 bytes in size, and its tag information requires 14 bits. The entire final level cache will have 1MB / 64 bytes = 16384 cache lines, and each way will have 16384 / 16 = 1024 sets. The required tag memory capacity is 16384 * 14 bits, and the granularity of accessing this final level cache is 64 bytes. In configuration 204, each cache line is 128 bytes in size, and its tagging information requires 15 bits. The entire last-level cache will have 1MB / 128 bytes = 8192 cache lines, and each path will have 8192 / 16 = 512 groups. The required tagging memory capacity is 8192 * 15 bits, and the granularity of accessing this last-level cache is 128 bytes. Configuration 206 is the configuration method of the last-level cache 10 of this application. In configuration 206, each cache line is 128 bytes in size, and the cache lines are partitioned. In addition to the original 15 bits of tagging information, an additional 2 bits of partition validity information are required. The entire last-level cache will have 1MB / 128Bytes = 8192 cache lines, and each path will have 8192 / 16 = 512 groups. The required tag memory capacity needs to accommodate tag information and partition validity information, so it needs 8192*(15+2) bits, and the granularity of accessing this last-level cache is 64 bytes.

[0026] Depend on Figure 2 It can be seen that the granularity of the last-level cache in access configuration 206 can be the same as that of the last-level cache in access configuration 202, but its required tag memory capacity can be reduced by about 40%. Compared to the last-level cache in configuration 204, the last-level cache in access configuration 206 uses only about 13% more tag memory capacity to halve the access granularity. Therefore, by using partitions in the cache line, the last-level cache 10 can improve the access granularity without significantly increasing costs.

[0027] In one embodiment, the plurality of requests includes a third request. When the high-order and low-order valid bits corresponding to the third request indicate that the high-order and low-order partitions are in a valid state, and the high-order and low-order missing lock bits corresponding to the third request indicate that the high-order and low-order partitions are not in a locked state, the hit test unit 160 determines that the third request is a cache hit. In one embodiment, the last-level cache 10 further includes a hit queue for storing the third requests determined by the hit test unit 160 to be cache hits. In one embodiment, the hit queue is a first-in-first-out queue.

[0028] In one embodiment, the plurality of requests includes a fourth request. When the valid bit of the high-order partition corresponding to the fourth request indicates that the high-order partition corresponding to the fourth request is not in a valid state, the hit test unit 160 determines that the fourth request is a cache miss. That is, when the size of the accessed memory is 64 bytes, the last-level cache 10 can only use the high-order partitions in the cache line. In one embodiment, the last-level cache 10 also includes a miss queue for storing the fourth requests determined by the hit test unit 160 to be cache misses. In one embodiment, the miss queue is a first-in-first-out queue.

[0029] In one embodiment, the plurality of requests includes a fifth request. When the high-order and low-order valid bits corresponding to the fifth request indicate that at least one of the high-order and low-order partitions corresponding to the fifth request is not in a valid state (or both partitions are not in a valid state), the hit test unit 160 determines that the fifth request is a cache miss. In this case, the last-level cache 10 reads the data corresponding to the invalid partitions in the high-order and low-order partitions from memory through the second interface 120. That is, when the size of the accessed memory is 128 bytes, the last-level cache 10 can simultaneously enable the high-order and low-order partitions in the cache line. In one embodiment, the last-level cache 10 also includes a miss queue to store the fifth requests determined by the hit test unit 160 as cache misses. In one embodiment, the miss queue is a first-in-first-out queue.

[0030] In one embodiment, the plurality of requests includes a sixth request. When the high-order and low-order valid bits corresponding to the sixth request respectively indicate that the high-order and low-order partitions corresponding to the sixth request are in a valid state, and the high-order and low-order missing lock bits corresponding to the sixth request respectively indicate that at least one of the high-order and low-order partitions corresponding to the sixth request is in a locked state, the hit test unit 160 determines that the sixth request is a cache miss hit. More specifically, when the fifth request is determined to be a cache miss by the hit test unit 160, if the sixth request has the same address as the fifth request, then the sixth request is determined to be a cache miss hit by the hit test unit 160. After the data corresponding to the fifth request is read back from memory to the last-level cache 10, the sixth request can directly use the data corresponding to the fifth request.

[0031] In one embodiment, when a cache line is evicted, the last-level cache 10 writes the data corresponding to the high-order and / or low-order partitions in the cache line back to memory via the second interface 120. Specifically, the last-level cache 10 only writes data from partitions that have been used in the cache line back to memory.

[0032] Figure 3 This diagram illustrates the execution of a hit test 30 for the hit test unit 160 of the final cache 10 of this application. Figure 3 In the cache line, there are high-order partition 300 and low-order partition 301. The initial partition validity information, sect_vld, indicates that neither high-order partition 300 nor low-order partition 301 is in a valid state (sect_vld = 2'b00).

[0033] When request 310, which requests to read data from the corresponding high-order partition 300, enters the last-level cache 10, the hit test unit 160 determines that request 310 is a cache miss because the partition validity information (sect_vld) of the corresponding high-order partition 300 indicates that the high-order partition 300 is not in a valid state. In this case, the last-level cache 10 reads the data corresponding to the high-order partition 300 from memory through the second interface 120, stores the data in the high-order partition 300, and sends the data back to the computing engine. At this time, the partition validity information (sect_vld) indicates that the high-order partition 300 is in a valid state, but indicates that the low-order partition 301 is not in a valid state (sect_vld = 2'b10).

[0034] Next, when request 320, which requests to read data from the corresponding low-order partition 301, enters the final cache 10, the hit test unit 160 determines that request 320 is a cache miss because the partition validity information (sect_vld) of the corresponding low-order partition 301 indicates that the low-order partition 301 is not in a valid state. In this case, the final cache 10 reads the data corresponding to the low-order partition 301 from memory through the second interface 120, stores the data in the low-order partition 301, and sends the data back to the computing engine. At this time, the partition validity information (sect_vld) indicates that both the high-order partition 300 and the low-order partition 301 are in a valid state (sect_vld = 2'b11).

[0035] Next, when request 330, which reads data from the corresponding high-order partition 300 and low-order partition 301, enters the last-level cache 10, since the partition validity information `sect_vld` for the corresponding high-order partition 300 and low-order partition 301 indicates that both high-order partition 300 and low-order partition 301 are in a valid state, the hit test unit 160 determines that request 330 is a cache hit. In this case, the last-level cache 10 directly sends the data corresponding to the high-order partition 300 and low-order partition 301 back to the computing engine. At this time, the partition validity information `sect_vld` indicates that both high-order partition 300 and low-order partition 301 are in a valid state (`sect_vld = 2'b11`).

[0036] Next, when request 340, which writes data to the corresponding high-order partition 300, enters the last-level cache 10, the hit test unit 160 determines that request 340 is a cache hit because the partition validity information (sect_vld) of the corresponding high-order partition 300 indicates that the high-order partition 300 is in a valid state. In this case, the last-level cache 10 directly writes the data to the high-order partition 300 and then sends it back to the computing engine. At this time, the partition validity information (sect_vld) indicates that both the high-order partition 300 and the low-order partition 301 are in a valid state (sect_vld = 2'b11).

[0037] Finally, when the cache line needs to be evicted, the last-level cache 10 writes the current data of the corresponding high-order partition 300 and low-order partition 301 back to memory through the second interface 120, and clears the data in the high-order partition 300 and low-order partition 301. At this time, the partition validity information section_vld indicates that both the high-order partition 300 and low-order partition 301 are not in a valid state (section_vld = 2'b00).

[0038] Figure 4 This diagram illustrates the execution of a hit test 40 for the hit test unit 160 of the final cache 10 of this application. Figure 4In this example, requests enter the request sequence 400 of the last-level cache 10 sequentially from right to left. Multiple requests have five different addresses: address 0, address 1, address 2, address 3, and address 4. Based on the tag information in the tag memory 140, requests corresponding to addresses 1 and 3 are determined to have cache hits by the hit test unit 160, while requests corresponding to addresses 0, 2, and 4 are determined to have cache misses by the hit test unit 160. It should be noted that the hit status indicated in the request sequence 400 is for illustrative purposes only; the requests in the request sequence 400 have not yet undergone the hit test by the hit test unit 160, and therefore their hit status is unknown.

[0039] Requests with address 1 or address 3 are sequentially placed into the hit queue 410, and the last-level cache 10 can directly send the data corresponding to address 1 or address 3 back to the computing engine in sequence.

[0040] The first request with addresses 0, 2, and 4 is sequentially placed into the miss queue 420 and stored in the miss status processing register 170. The last-level cache 10 reads the data corresponding to addresses 0, 2, and 4 from memory via the second interface 120. Since a request for address 0 already exists in the miss queue 420, before that request in the miss queue 420 is completed, the second request with address 0 is determined to be a cache miss hit by the hit test unit 160 and stored in the miss status processing register 170 in a linked list format. This linked list indicates that the second request with address 0 follows the first request with address 0. Then, before the request with address 0 in the miss queue 420 is completed, the third request with address 0 is determined to be a cache miss hit by the hit test unit 160 and stored in the miss status processing register 170 in a linked list format. This linked list indicates that the third request with address 0 follows the second request with address 0.

[0041] As described above, the Miss Status Handling Register 170 stores all requests determined to be cache misses and cache miss hits, and ensures the order of multiple requests with the same address in a linked list format. Based on the linked list and the order in which data corresponding to the requests determined to be cache misses is returned to the last-level cache 10, the Miss Status Handling Register 170 generates a return queue 430. Assuming the data returned from memory corresponds sequentially to addresses 4, 0, and 2 (as shown in queue 440), the last-level cache 10 first returns the data of the first request with address 4 to the compute engine. Then, according to the linked list, the last-level cache 10 sequentially returns the data of the second, third, and so on requests with address 4 to the compute engine. Once all requests with address 4 have been responded to by the compute engine, the last-level cache 10 then returns the data of the first request with address 0 to the compute engine, and sequentially returns the data of the second, third, and so on requests with address 0 to the compute engine according to the linked list. Once all requests with address 0 have been responded to by the computing engine, the last-level cache 10 then sends back the data for the first request with address 2 to the computing engine, and sequentially sends back the data for the second, third, and so on requests with address 2 to the computing engine according to the linked list. In other words, using a linked list format, the last-level cache 10 sends back the multiple requests according to the time sequence in which they entered request sequence 400.

[0042] In one embodiment, the plurality of requests includes a seventh request and an eighth request. If the seventh request enters the cache line earlier than the eighth request, the eighth request is then passed back to the computing engine by the last-level cache 10 after the seventh request is passed back to the computing engine. That is, the memory may not pass the data of the plurality of requests to the last-level cache 10 in the order in which the data corresponding to the plurality of requests (such as the seventh and eighth requests mentioned above) is read; however, the last-level cache 10 passes the plurality of requests back in the order in which they enter the cache line. In this scenario, since the seventh request enters the cache line earlier than the eighth request, even if the data of the eighth request is sent back to the last-level cache 10 earlier than the data of the seventh request, the last-level cache 10 will only send back the data of the eighth request (which entered the cache line earlier) to the computing engine after waiting for the data of the seventh request (which entered the cache line earlier) to be sent back to the last-level cache 10 and then sent back to the computing engine.

[0043] Figure 5 This diagram illustrates the execution of a hit test 50 for the hit test unit 160 of the final cache 10 of this application. Figure 5In the cache line, there are high-order partition 500 and low-order partition 501.

[0044] First, request 510, which reads data corresponding to the high-order partition 500, enters the last-level cache 10. Request 510 is determined to be a cache miss by the hit test unit 160, and the last-level cache 10 reads the data corresponding to the high-order partition 500 from memory through the second interface 120. Next, request 520, which reads data corresponding to the low-order partition 501, enters the last-level cache 10. Request 520 is determined to be a cache miss by the hit test unit 160, and the last-level cache 10 reads the data corresponding to the low-order partition 501 from memory through the second interface 120. If the response to request 510, which entered the last-level cache 10 earlier, has not yet been received by the last-level cache 10 (i.e., the data corresponding to the high-order partition 500 has not yet been returned from memory to the last-level cache 10), while the response to request 520, which entered the last-level cache 10 later, has been received by the last-level cache 10 (i.e., the data corresponding to the low-order partition 501 has been returned from memory to the last-level cache 10), the last-level cache 10 will still wait for the data corresponding to the high-order partition 500 to be returned from memory to the last-level cache 10, and for the data corresponding to the high-order partition 500 to be returned to the computing engine, in order to respond to request 510, which entered the last-level cache 10 earlier, before returning the data of the low-order partition 501 to the computing engine in order to respond to request 520, which entered the last-level cache 10 later.

[0045] Next, request 530, which reads data corresponding to high-order partition 500 and low-order partition 501, enters the last-level cache 10. At this time, if the last-level cache 10 has already received responses corresponding to requests 510 and 520, request 530 is determined to be a cache hit by the hit test unit 160. Next, request 540, which writes data corresponding to high-order partition 500, enters the last-level cache 10. Request 540 is determined to be a cache hit by the hit test unit 160, and the last-level cache 10 writes the data to high-order partition 500. Finally, when it is necessary to evict the cache line, the last-level cache 10 writes the current data corresponding to high-order partition 500 and low-order partition 501 to memory through the second interface 120, and clears the data in high-order partition 500 and low-order partition 501.

[0046] In one embodiment, the width of both the high-order partition and the low-order partition is twice the bus width of the second interface 120, and the types of requests also include some write operations. That is, if the partition width is 64 bytes, the bus width of the second interface 120 is only 32 bytes, which is half the partition width.

[0047] In one embodiment, the high-order partition and the low-order partition further include a high-order sub-partition and a low-order sub-partition, respectively, and the order of the multiple sub-partitions from high to low is: high-order sub-partition of the high-order partition, low-order sub-partition of the high-order partition, high-order sub-partition of the low-order partition, and low-order sub-partition of the low-order partition. Each request in the multiple requests also includes a sub-partition information field. For example, the width of two sub-partitions in a partition can be half the width of the partition. If the width of the partition is 64 bytes, and the width of each sub-partition is 32 bytes, it can be used to read requests of type partial write operation from memory through the second interface 120.

[0048] In one embodiment, the plurality of requests includes a ninth request of type partial write operation. If the ninth request is determined to be a cache miss, the last-level cache 10 reads data from at least one sub-partition corresponding to the ninth request from memory via the second interface 120. That is, for a request of type partial write operation, when the request is determined to be a cache miss, the last-level cache 10 can read only the data of the missing sub-partition from memory, without having to read the entire cache line. In this case, compared to reading the entire 128 bytes of data corresponding to the cache line from memory, a partial write operation miss read can only read data from 1 to 3 sub-partitions (i.e., only 32 bytes, 64 bytes, or 96 bytes of data need to be read), saving up to 96 bytes of data reading.

[0049] In one embodiment, if a ninth request intends to perform a partial write operation on at least one specific sub-partition among the plurality of sub-partitions corresponding to the ninth request, and does not perform a partial write operation on the remaining at least two sub-partitions among the plurality of sub-partitions corresponding to the ninth request, and the remaining two sub-partitions are sandwiched between at least one specific sub-partition, then the last-level cache 10 reads the data from memory of the remaining two sub-partitions and the at least one specific sub-partition between the plurality of sub-partitions corresponding to the ninth request. That is, to simplify the process, the last-level cache 10 only transmits one read request for cache misses. In this case, the last-level cache 10 may still read data from sub-partitions that were not originally required to be read (i.e., the data from the remaining two sub-partitions and the at least one specific sub-partition between the plurality of sub-partitions).

[0050] Figure 6 The final-level cache 10 of this application is a table 60 that reads data from memory for partial write operation requests. For example... Figure 6 As shown, assuming the final cache 10 receives partial write operation requests with a cache line size of 128 bytes, there are 15 possible scenarios (numbered 0-14) with a sub-partition size of 32 bytes. Figure 6The subpartitions are arranged from left to right as follows: the high-order subpartition of the high-order partition, the low-order subpartition of the high-order partition, the high-order subpartition of the low-order partition, and the low-order subpartition of the low-order partition. In all subpartitions, 1 indicates that the data in the subpartition does not need to be read, and 0 indicates that the data in the subpartition must be read.

[0051] Taking case 0 as an example, the high-order sub-partition of the high-order partition, the low-order sub-partition of the high-order partition, and the high-order sub-partition of the low-order partition need to be read, while the low-order sub-partition of the low-order partition does not need to be read. Since the three sub-partitions that need to be read are connected, the last-level cache 10 can read the data of these three sub-partitions at once.

[0052] Taking scenario 5 as an example, the high-order subpartition of the high-order partition and the low-order subpartition of the low-order partition need to be read, while the low-order subpartition of the high-order partition and the high-order subpartition of the low-order partition do not need to be read. However, there are two subpartitions that do not need to be read sandwiched between the subpartitions that need to be read (i.e., the low-order subpartition of the high-order partition and the high-order subpartition of the low-order partition). In order to avoid reading the memory multiple times, the last-level cache 10 will read the data of the four subpartitions at once.

[0053] Taking scenario 9 as an example, the data in the low-order subpartitions of the high-order partition and the low-order subpartitions of the low-order partition must be read, while the data in the high-order subpartitions of the high-order partition and the high-order subpartitions of the low-order partition do not need to be read. However, there is a subpartition that does not need to be read sandwiched between the subpartitions that need to be read (i.e., the high-order subpartition of the low-order partition). Similarly, to avoid multiple reads from memory, the last-level cache 10 will read the data from the three subpartitions between the low-order subpartition of the high-order partition and the low-order subpartition of the low-order partition (including the high-order subpartition of the low-order partition that does not need to be read) all at once. The other scenarios follow the same logic.

[0054] Depend on Figure 6 As shown in the table: In cases 1, 3, and 5, the last-level cache 10 still needs to read data from all sub-partitions, and cannot save the capacity of the last-level cache 10 to read data from memory; in cases 0, 4, 7, and 9, the last-level cache 10 only needs to read data from three sub-partitions, which can save 32 bytes of read capacity; in cases 2, 8, and 11, the last-level cache 10 only needs to read data from two sub-partitions, which can save 64 bytes of read capacity; in cases 6, 10, 12, and 13, the last-level cache 10 only needs to read data from one sub-partition, which can save 96 bytes of read capacity.

[0055] Figure 7 This is a schematic diagram of one embodiment of the calculator system 70 of this application. Figure 7In the computing system 70, a last-level cache 700, a computing engine 710, and memory 720 are included. The last-level cache 70 may be the last-level cache 10 of this application. The computing engine 710 is coupled to the last-level cache 700 and is used to send multiple requests to the last-level cache 700 and receive data from the last-level cache 700 in response to the multiple requests. The memory 720 is coupled to the last-level cache 700 and is used to receive requests to read data from the last-level cache 700 and to send back data corresponding to the requests to the last-level cache 700.

[0056] In summary, the last-level cache of this application can dynamically adjust the granularity of data read from memory: in the case of partitioning, the granularity can be reduced to half the original cache line size; and for requests of the type of partial write operation, the granularity can be reduced to at most one-quarter of the original cache line size. Compared with a last-level cache without partitioning, the last-level cache of this application can utilize cache lines more efficiently. Furthermore, through a linked list structure, the miss status handling register in the last-level cache of this application can maintain the order in which requests are returned according to the time order in which requests enter the last-level cache.

[0057] The foregoing outlines the structures of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other manufacturing processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A last-level cache, used to receive multiple requests from a computing engine through a first interface and access memory through a second interface, wherein the multiple requests include read operations and write operations, characterized in that, The final-level cache includes: Data storage, including: Multiple cache lines, each cache line including a high-order partition and a low-order partition, wherein the width of the high-order partition and the width of the low-order partition are the same; Tag memory, used to store: Multiple marker information, each corresponding to one of the multiple cache lines; and Multiple partition validity information, each corresponding to the multiple cache lines, wherein each partition validity information includes a high-order valid bit and a low-order valid bit, which are used to indicate whether the high-order partition and the low-order partition of the corresponding multiple cache lines are in a valid state; Missing lock information memory, used to store multiple missing lock information corresponding to the multiple cache lines. The information includes high-order missing lock bits and low-order missing lock bits, which are used to indicate whether the high-order partition and the low-order partition corresponding to the multiple cache lines are in a locked state. A hit test unit, wherein each of the plurality of requests includes a tag information field and a partition information field, determines, based on the tag information field and the partition information field, whether the high-order partition or the low-order partition of the plurality of cache lines is hit; and A missing status processing register, wherein the plurality of requests includes a first request and a second request, the tag information field of the first request is the same as the tag information field of the second request, and the partition information field of the first request is the same as the partition information field of the second request, and when the hit test unit determines that the first request is a cache miss and determines that the second request is a cache miss hit, the missing status processing register temporarily stores the first request and the second request in a linked list format according to the time order in which the first request and the second request entered the last-level cache.

2. The final-level cache according to claim 1, characterized in that, The plurality of requests includes a third request. When the high-order partition valid bit and the low-order partition valid bit corresponding to the third request respectively indicate that the high-order partition and the low-order partition are in a valid state, and the high-order missing lock bit and the low-order missing lock bit corresponding to the third request respectively indicate that the high-order partition and the low-order partition corresponding to the third request are not in a locked state, the hit test unit determines that the third request is a cache hit.

3. The final-level cache according to claim 2, characterized in that, The final-level cache further includes a hit queue for storing the third request that is determined by the hit test unit to be a cache hit.

4. The final-level cache according to claim 3, characterized in that, The hit queue is a first-in-first-out queue.

5. The final-level cache according to claim 1, characterized in that, The plurality of requests includes a fourth request. When the valid bits of the high-order partition corresponding to the fourth request indicate that the high-order partition corresponding to the fourth request is not in a valid state, the hit test unit determines that the fourth request is a cache miss.

6. The final-level cache according to claim 5, characterized in that, The final-level cache also includes a missing queue, used to store the fourth request that is determined by the hit test unit to be missing from the cache.

7. The final-level cache according to claim 6, characterized in that, The missing queue is a first-in, first-out queue.

8. The final-level cache according to claim 1, characterized in that, The plurality of requests includes a fifth request. When the valid bits of the high-order partition and the valid bits of the low-order partition corresponding to the fifth request respectively indicate that at least one of the high-order partition and the low-order partition corresponding to the fifth request is not in a valid state, the hit test unit determines that the fifth request is a cache miss.

9. The final-level cache according to claim 8, characterized in that, Through the second interface, the final-level cache reads data from the memory corresponding to the high-order partition and the partitions in the low-order partition that are not in a valid state.

10. The final-level cache according to claim 8, characterized in that, The final-level cache also includes a missing queue, used to store the fifth request that is determined by the hit test unit to be missing from the cache.

11. The final-level cache according to claim 10, characterized in that, The missing queue is a first-in, first-out queue.

12. The final-level cache according to claim 1, characterized in that, The plurality of requests includes a sixth request. When the high-order partition valid bit and the low-order partition valid bit corresponding to the sixth request respectively indicate that the high-order partition and the low-order partition corresponding to the sixth request are in a valid state, and the high-order missing lock bit and the low-order missing lock bit corresponding to the sixth request respectively indicate that at least one of the high-order partition and the low-order partition corresponding to the sixth request is in a locked state, the hit test unit determines that the sixth request is a cache miss hit.

13. The final-level cache according to claim 1, characterized in that, When a cache line is evicted, the last-level cache writes back the data corresponding to the high-order partition and / or the low-order partition in the cache line to the memory through the second interface.

14. The final-level cache according to claim 1, characterized in that, The plurality of requests includes a seventh request and an eighth request. If the seventh request enters the cache line earlier than the eighth request enters the cache line, after the seventh request is returned to the computing engine by the last-level cache, the eighth request is returned to the computing engine by the last-level cache.

15. The final-level cache according to claim 1, characterized in that, The width of the high-order partition and the width of the low-order partition are both twice the bus width of the second interface, and the types of the multiple requests also include some write operations.

16. The final-level cache according to claim 15, characterized in that, The high-order partition and the low-order partition further include a high-order sub-partition and a low-order sub-partition, respectively, and the order of the multiple sub-partitions from high to low is the high-order sub-partition of the high-order partition, the low-order sub-partition of the high-order partition, the high-order sub-partition of the low-order partition, and the low-order sub-partition of the low-order partition, and each of the multiple requests also includes a sub-partition information field.

17. The final-level cache according to claim 16, characterized in that, The plurality of requests includes a ninth request of the type of partial write operation. If the ninth request is determined to be a cache miss, the last-level cache reads data from at least one of the plurality of sub-partitions corresponding to the ninth request from the memory through the second interface.

18. The final-level cache according to claim 17, characterized in that, If the ninth request intends to perform the partial write operation on at least one specific sub-partition among the plurality of sub-partitions corresponding to the ninth request, and not perform the partial write operation on the remaining at least two sub-partitions among the plurality of sub-partitions corresponding to the ninth request, and the at least one specific sub-partition is sandwiched between the remaining two sub-partitions, then the last-level cache reads the data of the remaining two sub-partitions and the at least one specific sub-partition between the plurality of sub-partitions corresponding to the ninth request from the memory.

19. A computer system, characterized in that, include: Last-level cache as described in any one of claims 1 to 18; The computing engine; as well as The memory.

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