A continuous data transmission method, apparatus, electronic device, and storage medium

Abstract

Embodiments of the application disclose a continuous data transmission method and device, electronic equipment and a storage medium. The method comprises: collecting data packets from a continuous data sensor by an FPGA in a preset period; sending a trigger signal and the data packets to a DSP based on a clock signal of an internal timer; reading data of the data packets sent by the FPGA based on the trigger signal by the DSP; and updating the data packets by the FPGA based on an acknowledgement signal if the FPGA receives the acknowledgement signal sent by the DSP within a preset time length. The method can uniformly manage the clock of the DSP and the FPGA, ensure the stability of data transmission between the FPGA and the DSP, and improve the motion uniformity of the system.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor detection, and in particular to a continuous data transmission method and device, electronic equipment and storage medium. BACKGROUND

[0002] With the requirement of precision and high resolution of semiconductor detection scheme, continuous scanning type motion control system is widely used in detection equipment. The use of high-precision scanning type system requires high speed uniformity, which requires more and more stability of data packet reading of different master control system communication protocol. The current industrial control system includes high-speed serial data communication protocol, such as SRIO (Serial Rapid IO), PCIE (PCI Express) and the like, but it is very difficult to meet the requirement of large data bandwidth and data stability in the process of using the protocol.

[0003] In the existing continuous data transmission method, the field programmable gate array (FPGA) is clocked by the FPGA crystal oscillator, and when the value of the FPGA register reaches a fixed value, a trigger signal is generated to send the SRIO data packet to the digital signal processor (DSP). The DSP interrupt generates an interrupt signal according to the central processor clock, and notifies the central processor to read data through the interrupt signal. In this method, because there is a cross-clock domain problem between the two master devices (FPGA and DSP) (FPGA clock is based on physical crystal oscillator, and DSP is based on central processor clock), the DSP timing will fluctuate relative to the FPGA interrupt, and in the process of continuous data transmission, the difference of hardware clock will be accumulated. For continuous scanning type control system, there is fluctuation between two adjacent periods of system scanning data, which further leads to poor motion uniformity of the system. SUMMARY

[0004] The present application provides a continuous data transmission method, device, electronic equipment and storage medium, which uniformly manages the clock of DSP and FPGA, ensures the stability of data transmission between FPGA and DSP, and improves the motion uniformity of the system.

[0005] In a first aspect, embodiments of the present application provide a continuous data transmission method applied to a continuous data transmission system, the system including a continuous data sensor, a digital signal processor (DSP) and a field programmable gate array (FPGA), the FPGA including an internal timer, and the method including:

[0006] acquiring a data packet from the continuous data sensor by the FPGA in a preset period;

[0007] send a trigger signal and the data packet to the DSP based on a clock signal of the internal timer;

[0008] read, by the DSP, data of the data packet sent by the FPGA based on the trigger signal;

[0009] update, by the FPGA, the data packet based on the confirmation signal if the FPGA receives the confirmation signal sent by the DSP within a preset time length.

[0010] In a second aspect, the embodiments of the present application further provide a continuous data transmission system, which comprises a continuous data sensor, a digital signal processor (DSP) and a field programmable gate array (FPGA), and the FPGA comprises an internal timer;

[0011] The FPGA is configured to collect a data packet from the continuous data sensor within a preset period, send a trigger signal to the DSP based on a clock signal of the internal timer, send a trigger signal and the data packet to the DSP based on the clock signal of the internal timer, and update the data packet based on a confirmation signal if the FPGA receives the confirmation signal sent by the DSP within a preset time length.

[0012] The DSP is configured to read data of the data packet sent by the FPGA based on the trigger signal, and send the confirmation signal to the FPGA if the reading is successful.

[0013] In a third aspect, the embodiments of the present application further provide a continuous data transmission device, which comprises:

[0014] A data collection module is configured to collect a data packet from the continuous data sensor by the FPGA within a preset period.

[0015] A signal sending module is configured to send a trigger signal and the data packet to the DSP based on a clock signal of the internal timer.

[0016] A data reading module is configured to read, by the DSP, data of the data packet sent by the FPGA based on the trigger signal.

[0017] A signal receiving module is configured to update, by the FPGA, the data packet based on the confirmation signal if the FPGA receives the confirmation signal sent by the DSP within a preset time length.

[0018] In a fourth aspect, the embodiments of the present application further provide an electronic device, which comprises:

[0019] One or more processors;

[0020] a memory for storing one or more programs;

[0021] When the one or more programs are executed by the one or more processors, the one or more processors implement the continuous data transmission method as provided in any embodiment of the present application.

[0022] In a fifth aspect, the embodiments of the present application further provide a computer readable storage medium, having stored thereon a computer program, which, when executed by a processor, implements the continuous data transmission method as provided in any embodiment of the present application.

[0023] In the embodiments of the present application, data packets are collected from a continuous data sensor by an FPGA in a preset period; a trigger signal and the data packets are sent to a DSP based on a clock signal of an internal timer; the data of the data packets sent by the FPGA are read by the DSP based on the trigger signal; and the data packets are updated by the FPGA based on an acknowledgement signal if the FPGA receives the acknowledgement signal sent by the DSP in a preset time length. That is, the method of the embodiments of the present application can uniformly manage the clocks of the DSP and the FPGA, guarantee the stability of data transmission between the FPGA and the DSP, and improve the motion uniformity of the system. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be considered as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0025] Figure 1 is a first flowchart of the continuous data transmission method provided by the embodiments of the present application;

[0026] Figure 2 is a second flowchart of the continuous data transmission method provided by the embodiments of the present application;

[0027] Figure 3 is a first structural schematic diagram of the continuous data transmission system provided by the embodiments of the present application;

[0028] Figure 4 is a second structural schematic diagram of the continuous data transmission system provided by the embodiments of the present application;

[0029] Figure 5 is a first time-domain diagram of the continuous data transmission system provided by the embodiments of the present application;

[0030] Figure 6 is a first timing diagram of the continuous data transmission system provided by the embodiments of the present application;

[0031] Figure 7 is a second time domain diagram of a continuous data transmission system provided by an embodiment of the present application;

[0032] Figure 8 is a second timing diagram of a continuous data transmission system provided by an embodiment of the present application;

[0033] Figure 9 is a structural schematic diagram of a continuous data transmission apparatus provided by an embodiment of the present application;

[0034] Figure 10 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0035] The present application will be further described below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only the parts related to the present application are shown in the drawings, but not all the structures.

[0036] In order to make the person skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the person skilled in the art without creative labor should be within the scope of protection of the present application.

[0037] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, but not necessarily to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to include only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0038] Figure 1is a first flowchart of a continuous data transmission method provided by the embodiment of the application. The method of the embodiment unifies the management of the clocks of the DSP and the FPGA, ensures the stability of data transmission between the FPGA and the DSP, and improves the motion uniformity of the system. The method can be executed by a continuous data transmission device in the embodiment of the application. The device can be integrated in an electronic device, which can be a server. The server comprises a continuous data transmission system, and the method can be implemented in the software and / or hardware manner. The continuous data transmission method provided by the embodiment specifically comprises the following steps:

[0039] Step 101: collecting data packets from a continuous data sensor by the FPGA in a preset period.

[0040] The preset period is related to the data transmission protocol used between the FPGA and the DSP and the transmission mode of the data transmission protocol. Different data transmission protocols and data transmission modes correspond to different preset periods. Common transmission protocols include SRIO, PCIE, SATA (Serial Advanced Technology Attachment) and Aurora, etc. These data transmission protocols can be used for the interface of data communication, but their design purposes, characteristics and application occasions are different, so the data grabbing period (the preset period) is also different. The continuous data sensor is a sensor that can generate continuous signals, and its output directly corresponds to the input quantity. The continuous data sensor can provide continuous position data, high position resolution and high-speed response.

[0041] The continuous data transmission of the scheme comprises a continuous data sensor, a DSP and an FPGA. The FPGA comprises an internal timer. The internal timer is a hardware clock inside the FPGA. The internal timer can send a clock signal to the FPGA according to a fixed time interval. The FPGA collects continuous data from the continuous data sensor according to the received clock signal, and generates a data packet according to the collected continuous data.

[0042] Step 102: sending a trigger signal and a data packet to the DSP based on the clock signal of the internal timer.

[0043] The trigger signal is sent by the FPGA to the DSP, and is used to instruct the DSP to read the data packet. The trigger signal in the scheme can be a TRIG pulse. When the FPGA receives the clock signal sent by the internal timer, the FPGA can send a high-level pulse (with a duration of at least 10 microseconds) to the DSP, that is, send a trigger signal to the DSP.

[0044] Optionally, the data packet comprises an SRIO data packet, and the sending of the data packet to the DSP based on the clock signal of the internal timer comprises: the FPGA sends the SRIO data packet to the DSP through the SWRITE mode of the SRIO.

[0045] SRIO is a high-speed serial communication protocol widely used in high-performance computing, data storage, and data transmission. In the data transmission process between FPGA and DSP, SRIO can provide high-speed communication, low latency, and powerful debugging and diagnostic capabilities. The SWRITE mode is a write operation in the SRIO protocol, and its main function is to write data to a specified address space. The advantage of this mode is that it can directly write to the target address without the need to read data through the NREAD transaction first and then write data through the NWRITE transaction, thereby reducing the overall transmission delay. In an optional implementation, the FPGA packages the data packet through the input port into the SRIO protocol and uses the SRIO to send the data packet to the DSP through high-speed serial communication. In this process, the FPGA can use different transaction types of SRIO to perform different operations. For example, when reading data in the DSP, the NREAD transaction can be used; when writing data to a specific address in the DSP, the NWRITE transaction can be used.

[0046] The above steps enable the Swrite SRIO to be applied to a continuous scanning multi-master interactive system without affecting the SRIO Swrite bandwidth, thereby enhancing the stability of the data.

[0047] Step 103, reading the data of the data packet sent by the FPGA based on the trigger signal through the DSP.

[0048] The trigger signal is sent by the FPGA to the DSP to indicate that the DSP reads the data packet. Specifically, after the DSP receives the trigger signal sent by the FPGA, the DSP reads the data packet data sent by the FPGA based on the trigger signal. First, the DSP needs to be notified that the data is ready through hardware interruption or software triggering. For example, the FPGA can send an interruption to the DSP through the input and output (GPIO). When the DSP receives the interruption from the FPGA, the DSP will perform read and write operations on the corresponding memory area of the FPGA.

[0049] In the scheme, when the internal timer sends the clock signal, the packet identifier of the data packet is generated by the FPGA; the trigger signal is generated based on the packet identifier, and is sent to the DSP through the pre-set shared transmission line or transmission interface. The trigger signal is determined as the interrupt signal of the DSP, and the DSP is adjusted from the current state to the interrupt state based on the interrupt signal; in the interrupt state, the data of the data packet sent by the FPGA is read by the DSP based on the trigger signal.

[0050] In step 104, if the FPGA receives the confirmation signal sent by the DSP within the preset time length, the FPGA updates the data packet based on the confirmation signal.

[0051] The preset time length is a time length determined by the continuous data transmission system according to the clock signal, the data transmission protocol and the like. The confirmation signal is sent by the DSP to the FPGA, and is used to instruct the FPGA to continue to acquire the data packet of the continuous data sensor. In the scheme, the confirmation signal can be an acknowledge character (ACK).

[0052] Specifically, after receiving the data packet, the DSP reads the data of the data packet. After the data reading is completed, the DSP can pull up the ACK (the confirmation signal output by the DSP to the FPGA), and if the FPGA detects the rising edge of the ACK, the register data of the FPGA is refreshed, that is, the data packet is updated based on the confirmation signal. Otherwise, the register data is not updated, that is, the register data is latched. In the scheme, if the FPGA does not receive the confirmation signal sent by the DSP within the preset time length, the FPGA repeatedly sends the trigger signal to the DSP according to the clock signal until the FPGA receives the confirmation signal sent by the DSP.

[0053] In an optional embodiment, the DSP reads the data packet, and if the reading is successful, the DSP can send the confirmation signal to the FPGA within the preset time length, and the FPGA can update the data packet according to the confirmation signal. If the FPGA does not receive the confirmation signal within the preset time length, the FPGA can pull up the TRIG again to start the next period.

[0054] The technical scheme of the embodiment is applied to a continuous data transmission system, the system comprises a continuous data sensor, a digital signal processor (DSP) and a field programmable gate array (FPGA), the FPGA comprises an internal timer, and the method comprises the following steps: collecting, by the FPGA, data packets from the continuous data sensor in a preset period; sending, based on a clock signal of the internal timer, a trigger signal and the data packets to the DSP; reading, by the DSP, data of the data packets sent by the FPGA based on the trigger signal; and updating, by the FPGA, the data packets based on an acknowledgement signal if the FPGA receives the acknowledgement signal sent by the DSP in a preset time length. In the technical scheme of the embodiment, the clock of the DSP and the FPGA is uniformly managed, the stability of data transmission between the FPGA and the DSP is ensured, and the motion uniformity of the system is improved.

[0055] Figure 2 FIG. 2 is a second flowchart of a continuous data transmission method provided by the embodiment of the application, as shown in the figure, the method mainly comprises the following steps: Figure 2

[0056] Step 201: collecting, by the FPGA, data packets from the continuous data sensor in a preset period.

[0057] Step 202: generating, by the FPGA, a packet identifier of the data packets when the internal timer sends a clock signal.

[0058] The packet identifier can also be referred to as a packet ID (Identity document), and the packet identifier is used to mark different data packets. In an optional implementation, the FPGA can be configured with a counter which is incremented in each clock cycle. When the value of the counter reaches a preset threshold, the FPGA can send out the current data packet and reset the counter to prepare for the next data packet. For example, it is assumed that the FPGA has a 16-bit counter, and the value of the counter is increased by 1 each time the clock rising edge is triggered. When the value of the counter reaches 1024, the FPGA can send out the current data packet and reset the counter to 0. In this way, the FPGA can generate a new data packet and a packet identifier every 1 second and send them out.

[0059] Step 203: generating a trigger signal based on the packet identifier and sending the trigger signal to the DSP through a pre-set shared transmission line or transmission interface.

[0060] ​Specifically, after the packet identifier is generated, the FPGA can generate a trigger signal by configuring a corresponding logic circuit, and send the trigger signal to the DSP through a shared transmission line or a specific transmission interface. For example, the trigger signal is sent to the DSP using a universal asynchronous receiver-transmitter serial communication interface. The universal asynchronous receiver-transmitter serial communication interface is a widely used short-distance serial transmission interface. In actual applications, the trigger signal generation method and the transmission interface can be determined according to actual application requirements and the characteristics of the hardware device.

[0061] Step 204, based on a clock signal of an internal timer, sending the data packet to the DSP.

[0062] Step 205, determining the trigger signal as an interrupt signal of the DSP, and adjusting the DSP from a current state to an interrupt state based on the interrupt signal.

[0063] The trigger signal is a signal sent by the FPGA to the DSP to indicate that the DSP reads the data packet. In the DSP, the interrupt is an important technology that allows real-time control, fault handling, and data transmission operations. The interrupt is a driving signal generated by hardware or software, which requires the DSP to suspend the program being executed and execute a task called an interrupt service subroutine.

[0064] In an optional embodiment, the FPGA can send a TRIG pulse to the DSP according to the clock signal, and the DSP receives the TRIG pulse as an interrupt signal of the DSP. The DSP can suspend the current program according to the interrupt signal and jump to the execution of the interrupt service subroutine, that is, adjust the DSP from the current state to the interrupt state. After the execution of the interrupt service subroutine is completed, the DSP returns to the interrupted program for continuous execution.

[0065] Step 206, reading the data of the data packet sent by the FPGA based on the trigger signal by the DSP in the interrupt state.

[0066] Specifically, when the DSP is in the interrupt state, after the DSP receives the data packet sent by the FPGA, the DSP suspends the program being executed and jumps to the interrupt service subroutine (ISR). In the ISR, the DSP first needs to parse the data packet to determine the format and content of the data packet. According to the format and content of the data packet, the specific reading method can be determined, and the data packet is read according to the reading method of the data packet. For example, if the data packet is a byte stream, the DSP can use the direct memory access technology to copy the data from the memory space of the FPGA to the memory space of the DSP. If the data packet is a structure or an array, the DSP can directly access the data through a pointer.

[0067] Step 207, if the FPGA receives the confirmation signal sent by the DSP within the preset time length, the FPGA updates the data packet based on the confirmation signal.

[0068] Step 208, if the FPGA does not receive the confirmation signal sent by the DSP within the preset time length, the FPGA repeatedly sends the trigger signal to the DSP according to the clock signal until the FPGA receives the confirmation signal sent by the DSP.

[0069] The continuous data transmission method provided by the embodiment of the application acquires the data packet from the continuous data sensor through the FPGA within the preset period. The trigger signal is generated based on the packet identifier, and the trigger signal is sent to the DSP through the pre-set shared transmission line or transmission interface. The data packet is sent to the DSP based on the clock signal of the internal timer. The trigger signal is determined as the interrupt signal of the DSP, and the DSP is adjusted from the current state to the interrupt state based on the interrupt signal. The data of the data packet sent by the FPGA is read by the DSP in the interrupt state based on the trigger signal. If the FPGA receives the confirmation signal sent by the DSP within the preset time length, the FPGA updates the data packet based on the confirmation signal. If the FPGA does not receive the confirmation signal sent by the DSP within the preset time length, the FPGA repeatedly sends the trigger signal to the DSP according to the clock signal until the FPGA receives the confirmation signal sent by the DSP. The technical solution of the embodiment adopts the combination of the double handshaking mechanism between the FPGA and the DSP and the data packet ID, and uniformly manages the clock of the DSP+FPGA system, so as to move the DSP interrupt clock to the FPGA, and ensure the stability of the data packet sent between the FPGA and the DSP.

[0070] Figure 3 FIG. 1 is a first structural schematic diagram of a continuous data transmission system provided by an embodiment of the application. As shown in FIG. 1, the continuous data transmission system includes a continuous data sensor, a DSP, and an FPGA. The FPGA includes an internal timer. Figure 3 The FPGA is configured to acquire the data packet from the continuous data sensor within a preset period. The FPGA sends the trigger signal to the DSP based on the clock signal of the internal timer. The FPGA sends the trigger signal and the data packet to the DSP based on the clock signal of the internal timer. If the FPGA receives the confirmation signal sent by the DSP within the preset time length, the FPGA updates the data packet based on the confirmation signal. The DSP is configured to read the data of the data packet sent by the FPGA based on the trigger signal. If the reading is successful, the DSP sends the confirmation signal to the FPGA.

[0071] The preset period is related to the data transmission protocol used between the FPGA and DSP, as well as the transmission mode of the data transmission protocol. A continuous data sensor is a sensor that generates a continuous signal, whose output directly corresponds to the input quantity. A continuous data sensor can provide continuous position data, high position resolution, and high-speed response. In an optional embodiment, the FPGA is specifically configured to generate a packet identifier for a data packet when an internal timer issues a clock signal; generate a trigger signal based on the packet identifier, and transmit the trigger signal to the DSP via a pre-set shared transmission line or transmission interface.

[0072] Figure 4 This is a second structural diagram of the continuous data transmission system provided in the embodiment of the present application. Figure 4 As shown, the continuous data transmission system includes a DSP, an FPGA, and a continuous data sensor. The FPGA includes a data driver module, a data acquisition module, an ID generation module, a signal transceiver module, and a register. The DSP includes a signal transceiver module, an interface module, and a storage device. The FPGA register can instruct the FPGA's data driver module to send data parameters to the continuous data sensor. The data acquisition module receives the data packet sent by the continuous data sensor and sends the data packet to the register. After the register generates a packet ID through the ID generation module, it sends a trigger signal to the DSP through the signal transceiver module. The register sends the data packet to the storage device through the data interface. The DSP receives the trigger signal through the signal transceiver module, determines an interrupt signal based on the trigger signal, and reads the data packet received by the storage device based on the interrupt signal. The storage device can send the read data to the interface module and generate a confirmation signal, which is then sent to the FPGA's signal transceiver module through the signal transceiver module.

[0073] In this system, if the FPGA receives a confirmation signal from the DSP within a preset time, the FPGA updates the data packet based on the confirmation signal. If the FPGA does not receive a confirmation signal from the DSP within a preset time, the FPGA repeatedly sends a trigger signal to the DSP based on the clock signal until the FPGA receives a confirmation signal from the DSP. For example, Figure 5 This is the first time domain diagram provided by the embodiment of the present application. Figure 5 As shown, the FPGA receives the confirmation signal sent by the DSP within the preset time. Figure 5The left side is the FPGA time domain, and the right side is the DSP time domain. The FPGA sends data packets with packet identifiers x (ID=x) and x+1 (ID=x+1) to the DSP through SRIO. When the FPGA sends a data packet with packet identifier x+2 to the DSP, the FPGA sends a TRIG signal to the DSP through a signal transceiver module (TRIG & ACK) at the same time. After the DSP receives the TRIG signal, the DSP sends the data packet to a storage device of the DSP. Further, the FPGA continues to send data packets with packet identifiers x+3 (ID=x+3) and x+4 (ID=x+4) to the DSP through SRIO. Figure 6 is a first timing diagram of a continuous data transmission system provided by an embodiment of the present application. As shown in Figure 6 , the FPGA receives an acknowledgement signal sent by the DSP within a preset time length. FPGA_CLK represents a clock signal, FPGA_data packet represents a data packet obtained by the FPGA (represented by a packet identifier in the figure), SRIO_data packet represents a data packet sent by the FPGA to the DSP through SRIO, DSP TRIG (FPGA output) represents a TRIG signal sent by the FPGA to the DSP, and DSP ACK (FPGA input) represents an acknowledgement signal returned by the DSP to the FPGA. Figure 6 It can be seen from Figure 6 that when the FPGA sends a data packet with packet identifier x+2 to the DSP, the FPGA sends a TRIG signal to the DSP at the same time. DSP ACK (FPGA input) is an acknowledgement signal returned by the DSP to the FPGA after the DSP receives a data packet with packet identifier x+2.

[0074] , the FPGA repeatedly sends a TRIG signal and a data packet until the DSP receives the data packet. Figure 7 is a second timing diagram of a continuous data transmission system provided by an embodiment of the present application. As shown in Figure 7 , when the FPGA does not receive an acknowledgement signal sent by the DSP within a preset time length, the FPGA repeatedly sends a TRIG signal and a data packet until the DSP receives the data packet. Figure 7The left side of the figure is the FPGA time domain, and the right side is the DSP time domain. The FPGA sends data packets with packet identifiers x (ID=x) and x+1 (ID=x+1) to the DSP through SRIO. When the FPGA sends a data packet with a packet identifier x+2 to the DSP, the FPGA simultaneously sends a TRIG signal to the DSP through a signal transceiver module (TRIG & ACK). The DSP does not receive or read the data packet successfully, so the FPGA does not receive the return signal sent by the DSP. Further, the FPGA repeatedly sends a data packet with a packet identifier x+2 and a TRIG signal to the DSP through SRIO until the DSP receives the TRIG signal and sends the data packet to a storage device of the DSP. After receiving the data packet, the DSP sends an ACK signal to the FPGA. After receiving the ACK signal, the FPGA sends the data packet and the packet ID obtained at the current time. If the packet ID at the current time is x+3, the FPGA sends a data packet with a packet identifier x+3 to the DSP. Further, the FPGA continues to send a data packet with a packet identifier x+4 (ID=x+4), and completes the data transmission process of the current period. Figure 8 is a second timing diagram of the continuous data transmission system provided in the embodiment of the application. As shown in the figure, Figure 8 the FPGA does not receive an ACK signal sent by the DSP within a preset time length. As can be seen from the figure, Figure 8 when the FPGA sends a data packet with a packet identifier x+2 to the DSP, the FPGA simultaneously sends a TRIG signal to the DSP. Since the DSP does not receive the data packet or read the data packet successfully, the FPGA does not receive the return signal sent by the DSP. Then, the FPGA repeatedly sends a data packet with a packet identifier x+2 and a TRIG signal to the DSP through SRIO, Figure 8 the horizontal line of DSP TRIG (FPGA output) has 6 protrusions, indicating that the TRIG signal is sent for 6 times. After the DSP successfully receives the data packet with a packet identifier x+2, the DSP sends an ACK signal to the FPGA.

[0075] The system provided in the embodiment includes a continuous data sensor, a DSP, and an FPGA. The FPGA includes an internal timer. The FPGA is configured to collect data packets from the continuous data sensor within a preset period. The FPGA is configured to send a trigger signal to the DSP based on a clock signal of the internal timer. The FPGA is configured to send the trigger signal and the data packet to the DSP based on the clock signal of the internal timer. If an ACK signal sent by the DSP is received within a preset time length, the FPGA is configured to update the data packet based on the ACK signal. The DSP is configured to read data of the data packet sent by the FPGA based on the trigger signal. If the reading is successful, the DSP is configured to send an ACK signal to the FPGA. The system provided in the embodiment uniformly manages the clocks of the DSP and the FPGA, ensures the stability of data transmission between the FPGA and the DSP, and improves the motion uniformity of the system.

[0076] Figure 9Figure 1 is a structural schematic diagram of a continuous data transmission device provided by an embodiment of the present application. The embodiment of the present application provides a continuous data transmission device, which comprises:

[0077] The data acquisition module 901 is configured to acquire, by the FPGA, a data packet from the continuous data sensor within a preset period.

[0078] The signal sending module 902 is configured to send a trigger signal and the data packet to the DSP based on a clock signal of the internal timer.

[0079] The data reading module 903 is configured to read, by the DSP, data of the data packet sent by the FPGA based on the trigger signal.

[0080] The signal receiving module 904 is configured to update, by the FPGA, the data packet based on an acknowledgement signal sent by the DSP if the FPGA receives the acknowledgement signal within a preset time length.

[0081] Optionally, the signal sending module 902 is specifically configured to generate a packet identifier of the data packet by the FPGA when the internal timer sends the clock signal.

[0082] The trigger signal is generated based on the packet identifier, and the trigger signal is sent to the DSP through a pre-set shared transmission line or transmission interface.

[0083] Optionally, the data reading module 903 is specifically configured to determine the trigger signal as an interrupt signal of the DSP, and adjust the DSP from a current state to an interrupt state based on the interrupt signal.

[0084] The data of the data packet sent by the FPGA is read by the DSP in the interrupt state based on the trigger signal.

[0085] Optionally, the signal receiving module 904 is specifically configured to repeatedly send, by the FPGA, the trigger signal to the DSP according to the clock signal if the FPGA does not receive the acknowledgement signal sent by the DSP within the preset time length, until the FPGA receives the acknowledgement signal sent by the DSP.

[0086] Optionally, the data packet comprises a data packet of an SRIO serial bus protocol, and the signal sending module 902 is further configured to send, by the FPGA, the data packet of the SRIO to the DSP through an SWRITE mode of the SRIO based on the clock signal of the internal timer.

[0087] The continuous data transmission apparatus provided by the embodiments of the present application can execute the continuous data transmission method provided by any of the embodiments of the present application, and has the corresponding function modules and beneficial effects of the execution method.

[0088] Figure 10 is a structural schematic diagram of an electronic device provided by the embodiments of the present application, referring to Figure 10 which shows a structural schematic diagram of a computer system 12 suitable for implementing the electronic device of the embodiments of the present application.

[0089] Figure 10 The electronic device shown is only an example, and should not bring any limitation to the functions and use range of the embodiments of the present application. The components of the electronic device 12 can include but are not limited to one or more processors or processing units 16, a system memory 28, a bus 18 connecting different system components including the system memory 28 and the processing unit 16.

[0090] The bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor or local bus using any of a variety of bus architectures. By way of example, these architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0091] The electronic device 12 typically includes a variety of computer system readable media. These media can be any available media that is accessible by the electronic device 12 and includes both volatile and non-volatile media, removable and non-removable media.

[0092] The system memory 28 can include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The electronic device 12 can further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 34 can be used for reading from and writing to non-removable, non-volatile magnetic media (e.g., a "hard drive"). Figure 10 not shown, commonly referred to as a "hard disk drive", for reading from and writing to non-removable, non-volatile magnetic media (e.g., a "hard drive"). Although not specifically shown, such computer system typically can further include other removable / non-removable, volatile / non-volatile computer system storage media including, but not limited to, magnetic tape cassettes, flash memory cards, digital versatile disks, storage, memories, solid state drives, or other storage devices. Figure 10A disk drive, a floppy disk drive, a CD-ROM drive, a DVD-ROM drive, or other removable media drive, can be provided in the system for reading from or writing to a removable nonvolatile media (e.g., a floppy disk, a CD-ROM, a DVD-ROM, etc.). In such instances, each drive can be connected to the system bus 18 by one or more data media interfaces. The memory 28 can include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the application.

[0093] The program / utility 40, having a set (at least one) of program modules 42, can be stored in memory 28 by way of example, and not limitation, as well as an operating system, one or more application programs, other program modules, and program data, each or some combination thereof, can include implementation of a networking environment. The program modules 42 generally carry out the functions and / or methodologies of embodiments of the application as described herein.

[0094] The electronic device 12 can also communicate with one or more external devices 14 such as a keyboard or a pointing device, a display 24, etc. ; other devices such as a joystick, game pad, satellite dish, scanner, or the like; and / or Figure 10 Other hardware and / or software modules can be used in conjunction with the electronic device 12 in system 10, including, but not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

[0095] The processing unit 16 executes various function applications and continuous data transmission by running programs stored in the system memory 28, such as implementing a continuous data transmission method provided by the embodiments of the present application: collecting data packets from the continuous data sensor by the FPGA in a preset period; sending a trigger signal and the data packets to the DSP based on a clock signal of the internal timer; reading data of the data packets sent by the FPGA based on the trigger signal by the DSP; and updating the data packets by the FPGA based on an acknowledgement signal sent by the DSP if the FPGA receives the acknowledgement signal within a preset time length.

[0096] The embodiments of the present application provide a computer readable storage medium, which stores a computer program, and the program is executed by a processor to implement a continuous data transmission method provided by all the embodiments of the present application: collecting data packets from the continuous data sensor by the FPGA in a preset period; sending a trigger signal and the data packets to the DSP based on a clock signal of the internal timer; reading data of the data packets sent by the FPGA based on the trigger signal by the DSP; and updating the data packets by the FPGA based on an acknowledgement signal sent by the DSP if the FPGA receives the acknowledgement signal within a preset time length. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any suitable combination of the above. More specific examples (a non-exhaustive list) of the computer readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer readable storage medium can be any tangible medium that contains or stores a program used by or in connection with an instruction execution system, apparatus or device.

[0097] The computer readable signal medium can include a data signal conveyed in a baseband or as part of a carrier wave transporting the program code. Such a data signal can take any of a variety of forms, including but not limited to electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium can be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate or transport program for use by or in connection with an instruction execution system, apparatus, or device.

[0098] The program code embodied on the computer readable media may be transmitted using any appropriate medium, including but not limited to wireless, wire line, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0099] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0100] Note that the foregoing are merely preferred embodiments and the principles of the application. Those skilled in the art will understand that the application is not limited to the specific embodiments described herein, and that various obvious changes, modifications and substitutions can be made without departing from the scope of the application. Therefore, although the application has been described in detail by way of the above embodiments, the application is not limited to the above embodiments, and includes other equivalent embodiments without departing from the concept of the application, and the scope of the application is determined by the appended claims.

Claims

1. A continuous data transmission method, characterized by The method is applied to a continuous data transmission system, the system comprising a continuous data sensor, a digital signal processor (DSP) and a field programmable gate array (FPGA), the FPGA comprising an internal timer, the method comprising: collecting, by the FPGA, a data packet from the continuous data sensor within a preset period; sending, to the DSP, a trigger signal and the data packet based on a clock signal of the internal timer; reading, by the DSP, data of the data packet sent by the FPGA based on the trigger signal; updating, by the FPGA, the data packet based on an acknowledgement signal sent by the DSP if the FPGA receives the acknowledgement signal within a preset time length; wherein sending, to the DSP, the trigger signal based on the clock signal of the internal timer comprises: generating, by the FPGA, a packet identifier of the data packet when the internal timer sends the clock signal; generating the trigger signal based on the packet identifier and sending the trigger signal to the DSP through a pre-set shared transmission line or transmission interface.

2. The method of claim 1, wherein, reading, by the DSP, the data of the data packet sent by the FPGA based on the trigger signal comprises: determining the trigger signal as an interrupt signal of the DSP and adjusting the DSP from a current state to an interrupt state based on the interrupt signal; reading, by the DSP in the interrupt state, the data of the data packet sent by the FPGA based on the trigger signal.

3. The method of claim 1, wherein, The method further comprises: repeatedly sending, by the FPGA, the trigger signal to the DSP according to the clock signal if the FPGA does not receive the acknowledgement signal sent by the DSP within the preset time length, until the FPGA receives the acknowledgement signal sent by the DSP.

4. The method of claim 1, wherein, The data packet comprises a data packet of a serial rapid IO (SRIO) protocol, and sending, to the DSP, the trigger signal and the data packet based on the clock signal of the internal timer comprises: sending, by the FPGA, the data packet of the SRIO to the DSP through a SWRITE mode of the SRIO.

5. A continuous data transmission system, characterized by The system comprises a continuous data sensor, a digital signal processor (DSP) and a field programmable gate array (FPGA), the FPGA comprising an internal timer; the FPGA is configured to collect a data packet from the continuous data sensor within a preset period; send, to the DSP, a trigger signal and the data packet based on a clock signal of the internal timer; update the data packet based on an acknowledgement signal if the FPGA receives the acknowledgement signal within a preset time length; the DSP is configured to read data of the data packet sent by the FPGA based on the trigger signal, and send the acknowledgement signal to the FPGA if the reading is successful. The apparatus comprises:

6. A continuous data transmission apparatus, characterized by ​ The data collection module is configured to collect data packets from the continuous data sensor through the FPGA in a preset period. The signal sending module is configured to send a trigger signal and the data packets to the DSP based on a clock signal of an internal timer. The data reading module is configured to read data of the data packets sent by the FPGA based on the trigger signal through the DSP. The signal receiving module is configured to update the data packets based on an acknowledgement signal sent by the DSP through the FPGA if the FPGA receives the acknowledgement signal within a preset time length. The signal sending module is specifically configured to: generate a packet identifier of the data packets through the FPGA when the internal timer sends the clock signal; generate the trigger signal based on the packet identifier, and send the trigger signal to the DSP through a pre-set shared transmission line or transmission interface.

7. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the program to implement the continuous data transmission method according to any one of claims 1 to 4.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that The program is executed by the processor to implement the continuous data transmission method according to any one of claims 1 to 4.

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