Semiconductor structure and method of manufacturing the same

Abstract

The application discloses a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: providing a substrate, and forming a metal layer on the substrate; forming an initial mask layer on the metal layer, wherein the initial mask layer comprises a core region and a peripheral region, and the peripheral region comprises a first region and a second region; patterning a pattern of the first region to form a first pattern with a first interval; patterning a pattern of the second region to form a second pattern with a second interval, wherein the width of the first interval is greater than the width of the second interval, and the patterns of the first pattern, the second pattern and the core region jointly form a metal mask pattern; and patterning the metal layer by taking the metal mask pattern as a mask. The preparation method can realize relatively independent control of line intervals and line widths of different regions, so as to improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor structure and its fabrication method. Background Technology

[0002] In existing semiconductor memories, high integration is one of the many important technical factors. The circuit layout of a semiconductor chip includes core areas, peripheral areas, etc. During the fabrication of semiconductor memories, for example, during the etching process of the metal layer (MO) of the semiconductor memory, the pattern density of each area is different. However, the mask patterns of the metal layers in different areas are etched synchronously, resulting in consistent pattern etching line spacing in different pattern areas. This makes it impossible to control the line spacing and line width of different areas individually, which can easily lead to the risk of breakage and short circuit. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor structure and its fabrication method. The fabrication method enables relatively independent control of the line spacing and linewidth of different regions, such as the core region, the first region, and the second region, in order to improve the performance of the semiconductor structure and reduce the risk of short circuits and fractures in the metal layers of different regions.

[0004] A method for fabricating a semiconductor structure according to an embodiment of the present invention includes: providing a substrate on which a metal layer is formed; forming an initial mask layer on the metal layer, the initial mask layer including a core region and a peripheral region, the peripheral region including a first region and a second region; patterning a pattern of the first region to form a first pattern having a first spacing; patterning a pattern of the second region to form a second pattern having a second spacing, the width of the first spacing being greater than the width of the second spacing, the first pattern, the second pattern, and the pattern of the core region together forming a metal mask pattern; and patterning the metal layer using the metal mask pattern as a mask.

[0005] According to some embodiments of the present invention, the graphic density of the first region is less than that of the second region.

[0006] According to some embodiments of the present invention, the step of patterning the pattern of the first region to form a first pattern having a first spacing includes: forming a masking layer on the core region and the second region and exposing the first region; etching the pattern of the first region to form a first initial pattern having a first initial spacing, the width of the first initial spacing being smaller than the width of the first spacing; and in the step of patterning the pattern of the second region to form a second pattern having a second spacing, simultaneously etching the first initial pattern to form a first pattern having a first spacing.

[0007] According to some embodiments of the present invention, in the step of patterning the second region to form a second pattern having a second spacing, the masking layer located on the surface of the second region is removed, exposing the first region and the second region.

[0008] According to some embodiments of the present invention, the masking layer may be formed as a photoresist layer, and the step of forming the metal mask pattern includes: forming the photoresist layer on the surface of the initial mask layer; in the step of patterning the pattern of the first region to form a first pattern with a first spacing, controlling the exposure and development of the photoresist layer to expose the first region, and etching the pattern of the first region to form a first initial pattern with a first initial spacing;

[0009] In the step of patterning the second region to form a second pattern with a second spacing, the exposure and development of a portion of the photoresist layer on the surface of the core region and the second region are controlled to expose the second region and etch the first region and the second region.

[0010] According to some embodiments of the present invention, in the step of controlling the exposure and development of the photoresist layer to expose the first region, the photoresist layer on the surface of the second region is simultaneously controlled to develop, so that a portion of the photoresist layer remains on the pattern surface of the second region to cover the pattern of the second region.

[0011] According to some embodiments of the present invention, the thickness of the photoresist layer on the residual portion of the pattern surface in the second region is 0-20 nm.

[0012] According to some embodiments of the present invention, in the step of controlling the exposure and development of the photoresist layer to expose the first region, the exposure dose of the first region is greater than the development threshold, and the exposure dose of the second region is less than the development threshold.

[0013] According to some embodiments of the present invention, the development threshold is a light intensity threshold.

[0014] According to some embodiments of the present invention, in the step of controlling the exposure and development of the photoresist layer to expose the first region, the exposure and development time and temperature are controlled so that the first region is fully developed and the second region is partially developed to leave a portion of the photoresist layer on its surface.

[0015] According to some embodiments of the present invention, in the step of patterning the pattern of the second region to form a second pattern having a second spacing, an etching process is used to etch the pattern of the second region, wherein the flow rate of the etching gas is less than 100 sccm and the etching power is 200W to 300W.

[0016] According to some embodiments of the present invention, in the step of etching the pattern of the first region to form a first initial pattern having a first initial spacing, the etching rate is not less than 1 nm / 10 s and the etching time is 70 s; in the step of patterning the pattern of the second region to form a second pattern having a second spacing, an etching process is used to etch the first initial pattern and the pattern of the second region, the etching rate is not less than 1 nm / 10 s and the etching time is 40 s-60 s.

[0017] According to some embodiments of the present invention, the width of the first spacing is 24nm to 26nm, and the width of the second spacing is 15nm to 22nm.

[0018] According to some embodiments of the present invention, the method for fabricating the semiconductor structure further includes: sequentially forming an amorphous carbon layer and a silicon oxynitride layer on the surface of the metal layer, wherein the initial mask layer is formed on the surface of the silicon oxynitride layer.

[0019] The present invention also proposes a semiconductor structure.

[0020] A semiconductor structure according to an embodiment of the present invention includes: a substrate, on which a metal layer is formed, the metal layer including a core region and a peripheral region, the peripheral region including a first region and a second region, the first region having a first metal pattern with a first spacing, the second region having a second metal pattern with a second spacing, and the width of the first spacing being greater than the width of the second spacing.

[0021] According to some embodiments of the present invention, the graphic density of the first region is less than that of the second region.

[0022] The semiconductor structure and its fabrication method according to embodiments of the present invention can independently control the line spacing of different regions, such as the core region, the first region, and the second region, to meet the line width and line spacing requirements of the metal layers in different regions. It can also reduce the risk of short circuits and fractures during aging tests of the semiconductor structure and improve the performance of the semiconductor structure. Attached Figure Description

[0023] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0024] Figures 2-7 These are cross-sectional views corresponding to each step of the semiconductor structure fabrication method according to an embodiment of the present invention.

[0025] Figure label:

[0026] 100 semiconductor structure;

[0027] 1: Substrate, 11: Metal layer, 12: Amorphous carbon layer, 13: Silicon oxynitride layer;

[0028] 2: Initial mask layer, 21: First spacing, 22: First pattern, 23: Second spacing, 24: Second pattern, 25: First initial spacing, 26: First initial pattern;

[0029] D10: Width of the first spacing, D20: Width of the second spacing, D30: Width of the first initial spacing, D1: Line spacing dimension of the pattern in the first region within the initial metal layer, D2: Line spacing dimension of the pattern in the second region within the initial metal layer;

[0030] 3: Photoresist layer;

[0031] A: Core area, P1: First area, P2: Second area. Detailed Implementation

[0032] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the semiconductor structure 100 and its preparation method proposed in this invention.

[0033] The semiconductor structure 100 and its fabrication method according to an embodiment of the present invention are described below with reference to the accompanying drawings.

[0034] Combination Figures 1-7 As shown, the method for fabricating a semiconductor structure 100 according to an embodiment of the present invention may include: Step S1: providing a substrate 1, on which a metal layer 11 is formed; Step S2: forming an initial mask layer 2 on the metal layer 11, the initial mask layer 2 including a core region A and a peripheral region, the peripheral region including a first region P1 and a second region P2; Step S3: patterning the pattern of the first region P1 to form a first pattern 22 having a first spacing 21; Step S4: patterning the pattern of the second region P2 to form a second pattern 24 having a second spacing 23, the width of the first spacing 21 being greater than the width of the second spacing 23, the first pattern 22, the second pattern 24 and the pattern of the core region A together forming a metal mask pattern; Step S5: patterning the metal layer 11 using the metal mask pattern as a mask.

[0035] The following is combined Figures 2-7 A method for fabricating the semiconductor structure 100 according to an embodiment of the present invention is described. Figures 2-7 These are cross-sectional views corresponding to each step of the method for preparing the semiconductor structure 100 according to an embodiment of the present invention.

[0036] like Figure 2As shown, step S1 involves providing a substrate 1, on which a metal layer 11 is formed. The metal layer 11 can be used to form a metal interconnect structure. For example, the metal layer 11 can be a zero-th metal layer or a first metal layer. In some examples of the present invention, the substrate 1 can be a semiconductor substrate, and the metal layer 11 can be a zero-th metal layer. In other examples of the present invention, the substrate 1 can also include a substrate and a device structure on the substrate, and the metal layer 11 can be formed as a first metal layer or other metal layers (e.g., a second metal layer) connected to the device structure. In this embodiment of the present invention, the substrate 1 is described as a semiconductor substrate, and the metal layer 11 is a zero-th metal layer. The substrate can be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example of a semiconductor substrate. In other embodiments, the substrate can also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.

[0037] like Figure 2 As shown, in step S2: an initial mask layer 2 is formed on the metal layer 11. The initial mask layer 2 includes a core region A and a peripheral region. The peripheral region includes a first region P1 and a second region P2, wherein the pattern density of the first region P1 is less than the pattern density of the second region P2. In this step, the line spacing of the pattern in the first region P1 can be D1, and the line spacing of the pattern in the second region P2 can be D2.

[0038] Specifically, at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition can be used to deposit a mask layer on the metal layer 11. Then, the mask layer is patterned and etched through a preliminary multiple photolithography process to form an initial mask layer 2. For example, the mask layer can be photolithographically etched along a first direction and a second direction, with a certain angle between the first direction and the second direction, so that the mask layer forms an initial mask layer 2 with multiple mask pillar structures. Then, the initial mask layer 2 is photolithographically etched.

[0039] The initial mask layer 2 may include a core region A (Array) and a peripheral region. The core region A is used to form the device structure, and the peripheral region surrounding the core region A is used to form the circuit structure, etc. The peripheral region may include a first region P1 and a second region P2. The first region P1 may be a word line control region (SWC), and the second region P2 may include a word line drive region (SWD) and an amplifier region (S / A). Figure 2 As shown, the pattern density of the first region P1 is less than that of the second region P2, and the line width of the pattern in the first region P1 is greater than that of the pattern in the second region P2.

[0040] like Figures 3-6 As shown, the initial mask layer 2 is etched to form a metal mask pattern, which can be used as a mask for photolithography of the metal layer 11 to etch the metal layer 11.

[0041] The inventors discovered that the initial mask layer 2 has different regions (e.g., core region A, first region P1, and second region P2). These regions have different functions and pattern densities. When photolithography is performed on the initial mask layer 2, if the different regions are etched simultaneously, the etching rate and the line spacing of the etched patterns in different regions will be basically the same. However, different regions require different line spacings to meet different needs due to differences in linewidth, function, and density. Simultaneous etching of different regions makes it impossible to control the line spacing individually. As a result, after patterning the metal layer 11 using this mask, the metal layer 11 is prone to short circuits and fractures. For example, after synchronous etching, the line spacing of the first region P1 is small. During aging tests, there is a large voltage difference between the power supply voltage of the first region P1 and the power supply voltage of the second region P2. Under the aging test conditions, this voltage difference may cause some metal layer 11 of the first region P1 to break. Furthermore, when different regions are etched synchronously, while increasing the pattern line spacing of the first region P1, the pattern line spacing of the second region P2 and the core region A will also increase. This may lead to a larger line spacing and a smaller line width in the metal layer 11 of the second region P2, ultimately causing the metal layer 11 of the second region P2 to break.

[0042] like Figures 3-6 As shown, the step of forming a metal mask pattern according to an embodiment of the present invention may include:

[0043] Step S3: Graphicalize the pattern of the first region P1 to form a first pattern 22 with a first spacing 21;

[0044] Step S4: Graphicalize the pattern of the second region P2 to form a second pattern 24 with a second spacing 23. The width of the first spacing 21 is greater than the width of the second spacing 23. The first pattern 22, the second pattern 24 and the pattern of the core region A together form a metal mask pattern.

[0045] Specifically, the pattern in the first region P1 can be photolithographically etched to form a first pattern 22 in the first region P1. The line spacing of the first pattern 22 can be formed as a first spacing 21. The pattern in the second region P2 can be photolithographically etched to form a second pattern 24 in the second region P2. The line spacing of the second pattern 24 can be formed as a second spacing 23. The size of the first spacing 21 is larger than that of the second spacing 23. Therefore, it is not necessary to simultaneously etch the first region P1 and the second region P2. The line spacing of the patterns in the first region P1 and the second region P2 can be controlled separately, which can meet the line spacing requirements of the first region P1 and the second region P2. The first pattern 22, the second pattern 24, and the pattern in the core region A can together constitute a metal mask pattern, and then... Figure 7As shown, in step S5, the metal mask pattern can be used to pattern the metal layer 11, thereby enabling separate control of the line spacing of the first region P1 and the second region P2 of the etched metal layer 11, which can reduce the risk of short circuits and breakage during aging tests.

[0046] In some embodiments of the present invention, the pattern of the first region P1 can be photolithographically etched to form a first pattern 22 having a first spacing 21, and then the pattern of the second region P2 can be photolithographically etched to form a second pattern 24 having a second spacing 23. In other embodiments of the present invention, since the size of the first spacing 21 is larger than the size of the second spacing 23, the pattern of the first region P1 can be photolithographically etched once to increase the line spacing of the pattern of the first region P1, and then the pattern of the first region P1 can be etched simultaneously when the pattern of the second region P2 is photolithographically etched to further increase the line spacing of the pattern of the first region P1, thereby forming the first pattern 22 having the first spacing 21.

[0047] In some examples of the present invention, the step of patterning the pattern of the first region P1 to form a first pattern 22 having a first spacing 21 may include: forming a masking layer on the core region A and the second region P2 and exposing the first region P1; etching the pattern of the first region P1 to form a first initial pattern 26 having a first initial spacing 25, the width D30 of the first initial spacing 25 being smaller than the width D10 of the first spacing 21; and in the step of patterning the pattern of the second region P2 to form a second pattern 24 having a second spacing 23, simultaneously etching the first initial pattern 26 to form the first pattern 22 having the first spacing 21.

[0048] Specifically, a masking layer is formed on the surface of the core region A and the second region P2. The masking layer covers the surface of the core region A and the second region P2 to mask the pattern of the core region A and the pattern of the second region P2, so that the first region P1 is exposed. Then, the pattern of the first region P1 is etched separately, which can realize the control of the line spacing and line width of the pattern of the first region P1. At this time, etching the pattern of the first region P1 can form a first initial pattern 26. The line spacing of the first initial pattern 26 after etching is increased to form a first initial spacing 25. The size D30 of the first initial spacing 25 is smaller than the size D10 of the first spacing 21.

[0049] Then, the pattern in the second region P2 can be etched. Specifically, a portion of the masking layer on the second region P2 can be removed to expose the second region P2. At this time, both the pattern in the second region P2 and the first initial pattern 26 in the first region P1 are exposed. While etching the pattern in the second region P2, the first initial pattern 26 can also be etched, thereby forming a second pattern 24 with a second spacing 23 in the second region P2 and a second pattern 24 with a first spacing 21 in the first region P1. Therefore, compared to etching the pattern in the first region P1 separately to directly form the first pattern 22, it is not necessary to mask the pattern in the first region P1 when etching the pattern in the second region P2, nor is it necessary to remove the masking layer during etching. This simplifies the process, makes the process simple, and enables separate control of the line spacing and line width of the patterns in the first region P1 and the second region P2.

[0050] like Figures 3-6 As shown, before etching the initial mask layer 2, the line spacing of the pattern in the first region P1 can be D1, the line spacing of the pattern in the second region P2 can be D2, the width of the first initial spacing of the first initial pattern 26 can be D30, the width of the first spacing of the first pattern 22 can be D10, and the width of the second spacing of the second pattern 24 can be D20. The relationship between D1, D2, D10, D20 and D30 satisfies: D1 < D30 < D10, D2 < D20.

[0051] In some specific examples of the present invention, the shielding layer may be a photoresist material. Of course, it is understood that the shielding layer may also be formed of other materials, as long as it can play a shielding role and can be removed after etching.

[0052] like Figure 3 As shown, in a specific embodiment of the present invention, the masking layer is described as photoresist layer 3, and the step of forming a metal mask pattern may include:

[0053] A photoresist layer 3 is formed on the surface of the initial mask layer 2;

[0054] In the step of patterning the first region P1 to form a first pattern 22 with a first spacing 21, the exposure and development of the photoresist layer 3 are controlled to expose the first region P1, and the pattern of the first region P1 is etched to form a first initial pattern 26 with a first initial spacing 25.

[0055] In the step of patterning the second region P2 to form a second pattern 24 with a second spacing 23, the exposure and development of a portion of the photoresist layer 3 on the surface of the core region A and the second region P2 are controlled to expose the second region P2 and etch the first region P1 and the second region P2.

[0056] Specifically, a photoresist layer 3 can be formed on the surface of the initial mask layer 2. The photoresist layer 3 is located on and fills the surface of the initial mask layer 2. Then, a photomask can be used to expose and develop the photoresist layer 3 to transfer the pattern onto the photoresist layer 3. In this step, such as Figures 3-4 As shown, the exposure and development process of the photoresist layer 3 can be controlled to define the first region P1 and the second region P2, and a pattern exposing the first region P1 is formed on the photoresist layer 3, so that the first region P1 is exposed, while the second region P2 and the core region A surface are not exposed. This allows the pattern of the first region P1 to be etched to form a first initial pattern 26 with a first initial spacing 25. Then, as... Figures 5-6 As shown, the photoresist layer 3 corresponding to the second region P2 is then exposed and developed to expose the second region P2, thereby allowing etching of the second region P2 and the first region P1. In this way, by controlling the exposure and development of the photoresist layer 3 in the photolithography process, the etching of the first region P1 and the second region P2 can be controlled separately.

[0057] In some examples of the present invention, during the step of controlling the exposure and development of the photoresist layer 3 to expose the first region P1, the photoresist layer 3 on the surface of the second region P2 is partially developed at the same time, so that the residual photoresist layer 3 on the pattern surface of the second region P2 covers the pattern of the second region P2.

[0058] Specifically, the photoresist layer 3 can be a positive photoresist. In the step of photolithographically patterning the first region P1, for example, in the process of exposing and developing the photoresist layer 3 on the first region P1 using a photomask, the photoresist layer 3 on the surface of the first region P1 can be fully exposed and developed, while the second region P2 can be partially exposed and developed to remove part of the photoresist layer 3 on the surface of the second region P2. This not only fully exposes the first region P1 but also reduces the thickness of the photoresist layer 3 on the second region P2. This allows for a reduction in photolithography time and an increase in etching rate when photolithographically patterning the second region P2. Simultaneously, when etching the first region P1, the photoresist layer 3 on the second region P2 can also block the pattern of the first region P1. In some embodiments, the thickness of the remaining photoresist layer 3 on the surface of the pattern in the second region P2 is 0-20 nm, for example, 5 nm, 10 nm, or 15 nm.

[0059] Furthermore, when performing photolithography on the pattern of the first region P1, the design of the photomask, the thickness of the photoresist layer 3, and the lighting conditions during exposure and development can be optimized to ensure that the core region A is not developed, the second region P2 is partially developed, and the first region P1 is fully developed.

[0060] In some embodiments of the present invention, in the step of controlling the exposure and development of the photoresist layer 3 to expose the first region P1, the exposure dose of the first region P1 is greater than the development threshold, thereby enabling the first region P1 to be fully exposed, and the exposure dose of the second region P2 is less than the development threshold, thereby causing the bottom of the photoresist layer 3 in the second region P2 to be incompletely exposed, leaving a portion of the photoresist layer 3 on the second region P2, so as to block the pattern of the second region P2 when the pattern of the first region P1 can be etched.

[0061] In some embodiments, the development threshold can be a light intensity threshold. The exposure and development of the photoresist layer 3 in the first region P1 and the second region P2 are controlled by controlling the light intensity. Specifically, when the photoresist layer 3 is exposed and developed by patterning the first region P1, the light intensity of the first region P1 is above the light intensity threshold so that the first region P1 can be fully exposed, while the exposure intensity of the second region P2 is lower. For example, the light intensity of the second region P2 is less than the light intensity of the first region P1 and less than the light intensity threshold, so that the second region P2 is not fully exposed. Thus, after development, the photoresist layer 3 in the second region P2 is not completely dissolved, and there is a partial residual photoresist layer 3 in the second region P2.

[0062] Furthermore, in the step of controlling the exposure and development of the photoresist layer 3 to expose the first region P1, the exposure and development time and temperature can be controlled to ensure that the first region P1 is fully developed and the second region P2 is partially developed so that a portion of the photoresist layer 3 remains on its surface. Thus, by controlling the exposure and development time and temperature, the development effect can be controlled, ensuring that the first region P1 is fully exposed while the second region P2 is partially exposed. Specifically, after the exposure reaction, a drying process can be performed in the development step. During the development process, both the exposed and unexposed photoresist react with the developer. By changing the development temperature, developer composition, and development method, the dissolution rate of the exposed and unexposed photoresist can be accelerated. Therefore, by controlling the temperature or time of the exposure and development, the dissolution rate of the photoresist can be controlled, thereby controlling the amount of photoresist layer 3 dissolved in the first region P1 and the second region P2, to achieve complete exposure of the first region P1 and partial photoresist residue on the surface of the second region P2.

[0063] In some embodiments of the present invention, in the step of patterning the pattern of the second region P2 to form the second pattern 24 having the second spacing 23, the pattern of the second region P2 can be etched by wet etching or dry etching to form the second pattern 24. When dry etching is used, the flow rate of the etching gas is less than 100 sccm and the etching power is 200W to 300W. In this way, by using a small flow rate of etching gas and a relatively reduced etching rate, the photoresist layer 3 of the second region P2 can be removed and the photoresist layer 3 on the core region A can be thinned.

[0064] In some embodiments of the present invention, in the step of etching the pattern of the first region P1 to form a first initial pattern 26 having a first initial spacing 25, wet etching can be used to etch the pattern of the first region P1, wherein the etching rate is not less than 1 nm / 10 s. It should be noted that the etching rate here is the rate at which the line spacing increases during the etching of the pattern of the first region P1. The etching time can be 70 s. Optionally, the initial mask layer 2 can be a silicon oxide layer. Specifically, hydrofluoric acid (DHF) diluted 200:1 can be used to etch the pattern of the first region P1. In the step of patterning the pattern of the second region P2 to form the second pattern 24 with the second spacing 23, an etching process can be used to etch the first initial pattern 26 and the pattern of the second region P2, wherein the etching rate is not less than 1 nm / 10 s and the etching time is 40 s-60 s. It should be noted that the etching rate here refers to the rate at which the line spacing increases when the pattern of the second region P2 is etched in this etching step. In this step, hydrofluoric acid (DHF) diluted 200:1 can also be used to etch the pattern of the second region P2 and the pattern of the first region P1.

[0065] In some embodiments of the present invention, the width D10 of the first spacing 21 can be 24nm to 26nm, and the width D20 of the second spacing 23 can be 15nm to 22nm. Specifically, before etching the initial mask layer 2 to form a metal mask pattern, the line spacing D2 of the pattern in the second region P2 can be 0-15nm, and the line spacing D1 of the pattern in the first region P1 can be 0-13nm. The pattern density of the first region P1 is relatively small, resulting in a smaller line spacing after etching. After etching the initial mask layer 2 to form a metal mask pattern, the first region P1 forms a first pattern 22 with the first spacing 21, and the second region P2 forms a second pattern 24 with the second spacing 23. The width of the first spacing 21 is the line spacing dimension of the first pattern 22 in the first region P1, and the width of the second spacing 23 is the line spacing dimension of the second pattern 24 in the second region P2. The second spacing 23 can be 15nm to 22nm, and the first spacing 21 can be 24nm to 26nm.

[0066] In some embodiments of the present invention, the method for fabricating the semiconductor structure 100 may further include: sequentially forming an amorphous carbon layer 12 and a silicon oxynitride layer 13 on the surface of a metal layer 11, with an initial mask layer 2 formed on the surface of the silicon oxynitride layer 13. Specifically, an amorphous carbon layer 12 (ACL) may be deposited on the surface of the metal layer 11, and then a silicon oxynitride layer 13 may be formed on the amorphous carbon layer 12. The initial mask layer 2 may be formed on the silicon oxynitride layer 13, and the initial mask layer 2 may be a silicon oxide layer. After etching the initial mask layer 2 to form a metal mask pattern, the amorphous carbon layer 12 and the silicon oxynitride layer 13 may be etched to transfer the pattern of the metal mask pattern onto the amorphous carbon layer 12 and the silicon oxynitride layer 13. Then, the metal mask pattern may be removed, and the metal layer 11 may be etched using the etched amorphous carbon layer 12 and the silicon oxynitride layer 13 as a mask to transfer the pattern of the metal mask pattern onto the metal layer 11.

[0067] The present invention also proposes a semiconductor structure 100, which can be formed by the preparation method of the semiconductor structure 100 in the above embodiments.

[0068] As shown in the figure, the semiconductor structure 100 according to an embodiment of the present invention may include a substrate 1, on which a metal layer 11 is formed. The metal layer 11 includes a core region A and a peripheral region. The peripheral region includes a first region P1 and a second region P2. The first region P1 has a first metal pattern with a first spacing 21, and the second region P2 has a second metal pattern with a second spacing 23. The width of the first spacing 21 is greater than the width of the second spacing 23.

[0069] In some embodiments of the present invention, the graphic density of the first region P1 is less than the graphic density of the second region P2.

[0070] Therefore, the semiconductor structure 100 and its fabrication method according to the present invention can independently control the line spacing of different regions such as core region A, first region P1, and second region P2 to meet the line width and line spacing requirements of the metal layer 2 in different regions. It can also reduce the risk of short circuits and breakages during aging tests of the semiconductor structure 100 and improve the performance of the semiconductor structure 100.

[0071] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided on which a metal layer is formed; An initial mask layer is formed on the metal layer, the initial mask layer including a core region and a peripheral region, the peripheral region including a first region and a second region; The pattern of the first region is graphically represented to form a first pattern with a first spacing. The pattern of the second region is graphically represented to form a second pattern with a second spacing, the width of the first spacing being greater than the width of the second spacing, and the first pattern, the second pattern, and the pattern of the core region together form a metal mask pattern; The metal layer is patterned using the metal mask pattern as a mask; The step of graphically representing the pattern of the first region to form a first pattern having a first spacing includes: A shielding layer is formed on the core region and the second region, while exposing the first region; The pattern in the first region is etched to form a first initial pattern having a first initial spacing, the width of which is smaller than the width of the first spacing. In the step of patterning the second region to form a second pattern with a second spacing, the first initial pattern is simultaneously etched to form a first pattern with a first spacing.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The graphic density of the first region is less than that of the second region.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, In the step of patterning the second region to form a second pattern with a second spacing, the masking layer located on the surface of the second region is removed, exposing the first region and the second region.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The shielding layer can be formed as a photoresist layer, and the step of forming the metal mask pattern includes: The photoresist layer is formed on the surface of the initial mask layer; In the step of patterning the first region to form a first pattern with a first spacing, the exposure and development of the photoresist layer are controlled to expose the first region, and the pattern of the first region is etched to form a first initial pattern with a first initial spacing. In the step of patterning the second region to form a second pattern with a second spacing, the exposure and development of a portion of the photoresist layer on the surface of the core region and the second region are controlled to expose the second region and etch the first region and the second region.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, In the step of controlling the exposure and development of the photoresist layer to expose the first region, the photoresist layer on the surface of the second region is simultaneously controlled to develop, so that a portion of the photoresist layer remains on the pattern surface of the second region to cover the pattern of the second region.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The thickness of the photoresist layer on the residual portion of the pattern surface in the second region is 0-20 nm.

7. The method for preparing a semiconductor structure according to claim 5, characterized in that, In the step of controlling the exposure and development of the photoresist layer to expose the first region, the exposure dose of the first region is greater than the development threshold, and the exposure dose of the second region is less than the development threshold.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The development threshold is the light intensity threshold.

9. The method for preparing a semiconductor structure according to claim 5, characterized in that, In the step of controlling the exposure and development of the photoresist layer to expose the first region, the exposure and development time and temperature are controlled so that the first region is fully developed and the second region is partially developed so that a portion of the photoresist layer remains on its surface.

10. The method for preparing a semiconductor structure according to claim 1, characterized in that, In the step of patterning the second region to form a second pattern with a second spacing, an etching process is used to etch the pattern of the second region, wherein the flow rate of the etching gas is less than 100 sccm and the etching power is 200W to 300W.

11. The method for preparing a semiconductor structure according to claim 1, characterized in that, In the step of etching the pattern of the first region to form a first initial pattern with a first initial spacing, the etching rate is not less than 1 nm / 10 s and the etching time is 70 s. In the step of patterning the second region to form a second pattern with a second spacing, an etching process is used to etch the first initial pattern and the pattern of the second region, with an etching rate of not less than 1 nm / 10 s and an etching time of 40 s-60 s.

12. The method for preparing a semiconductor structure according to claim 1, characterized in that, The width of the first spacing is 24nm to 26nm, and the width of the second spacing is 15nm to 22nm.

13. The method for preparing a semiconductor structure according to claim 1, characterized in that, Also includes: An amorphous carbon layer and a silicon oxynitride layer are sequentially formed on the surface of the metal layer, and the initial mask layer is formed on the surface of the silicon oxynitride layer.

14. A semiconductor structure, characterized in that, Prepared by the method for preparing the semiconductor structure according to claim 1, comprising: A substrate on which a metal layer is formed, the metal layer comprising a core region and a peripheral region, the peripheral region comprising a first region and a second region, the first region having a first metal pattern with a first spacing, the second region having a second metal pattern with a second spacing, the width of the first spacing being greater than the width of the second spacing.

15. The semiconductor structure according to claim 14, characterized in that, The graphic density of the first region is less than that of the second region.

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