Gallium oxide substrate-based ring gate field effect transistor and method of manufacturing the same

Abstract

The present disclosure provides a gallium oxide substrate-based ring-gate field effect transistor and a preparation method thereof, which comprises: an N-type doped gallium oxide substrate; a columnar channel formed on the gallium oxide substrate and adapted to provide a passage for current flow; a first insulating layer arranged on the gallium oxide substrate and surrounding a region around the columnar channel; a gate dielectric layer arranged on the first insulating layer and extending to a side region surrounding the columnar channel; a gate metal layer arranged on the gate dielectric layer and annularly surrounding the gate dielectric layer and adapted to control the current flow in the columnar channel; a second insulating layer arranged on the gate metal layer and having an electrode hole penetrating to the gate metal layer, the electrode hole being annular with the columnar channel as the center; a gate electrode arranged on the second insulating layer and penetrating the electrode hole and in contact with the gate metal layer; a source electrode arranged on the top of the columnar channel; and a drain electrode arranged at the bottom of the gallium oxide substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor electronic devices, and in particular, to a gallium oxide substrate-based ring gate field effect transistor and a preparation method thereof. BACKGROUND

[0002] With the continuous development of semiconductor technology, in order to improve the functional density and performance of integrated circuits, the size of semiconductor devices is continuously reduced, and the challenge of Moore's law is becoming greater and greater. And a series of problems have appeared, one of which is the short channel effect, that is, when the channel length is reduced to a certain extent, the current is easy to flow from the source to the drain, causing the occurrence of leakage phenomenon. The influence of the short channel effect makes the leakage phenomenon more obvious, and the control ability of the gate to the channel is also weakened, which cannot effectively control the current in the channel, hindering the further reduction of device size, thereby limiting the improvement of chip transistor density. SUMMARY

[0003] Therefore, the present disclosure provides a gallium oxide substrate-based ring gate field effect transistor and a preparation method thereof to at least partially solve the above technical problems.

[0004] In order to solve the above technical problems, the technical solutions provided by the present disclosure are as follows:

[0005] As an aspect of the present disclosure, a gallium oxide substrate-based ring gate field effect transistor is provided, comprising:

[0006] An N-doped gallium oxide substrate;

[0007] A columnar channel formed on the N-doped gallium oxide substrate and adapted to provide a passage for current flow;

[0008] A first insulating layer disposed on the N-doped gallium oxide substrate and surrounding a region around the columnar channel;

[0009] A gate dielectric layer disposed on the first insulating layer and extending to a side region surrounding the columnar channel;

[0010] A gate metal layer disposed on the gate dielectric layer and surrounding the gate dielectric layer in a ring shape, and adapted to control the current flow in the columnar channel;

[0011] A second insulating layer disposed on the gate metal layer and having an electrode hole penetrating the gate metal layer (5), the electrode hole being annular with the columnar channel as the center;

[0012] A gate disposed on the second insulating layer and penetrating the electrode hole, and in contact with the gate metal layer;

[0013] A source disposed on the top of the columnar channel; and

[0014] a drain disposed at the bottom of the N-doped gallium oxide substrate.

[0015] According to an embodiment of the present disclosure, the doping ions of the N-doped gallium oxide substrate include silicon and / or tin, and the doping concentration is 1.0×10 15 ~1.0×10 20 cm -3 .

[0016] According to an embodiment of the present disclosure, the columnar channel is etched from the N-doped gallium oxide substrate and extends in a direction perpendicular to the N-doped gallium oxide substrate.

[0017] According to an embodiment of the present disclosure, the material of the first and second insulating layers includes silicon oxide or aluminum oxide, and the thickness is 0.01-50 μm.

[0018] According to an embodiment of the present disclosure, the material of the gate dielectric layer includes any one or more of aluminum oxide, hafnium oxide, lanthanum oxide, and tantalum oxide.

[0019] The thickness of the gate dielectric layer is 0.01-0.1 μm.

[0020] According to an embodiment of the present disclosure, the chemical composition of the gate metal layer, the gate, the source, and the drain includes any one or more of chromium, titanium, aluminum, nickel, platinum, and gold.

[0021] According to an embodiment of the present disclosure, the chemical composition of the source and the drain is preferably titanium and / or chromium.

[0022] As another aspect of the present disclosure, a preparation method of the above-mentioned gallium oxide substrate-based ring-gate field effect transistor is provided, comprising:

[0023] forming a columnar channel on the N-doped gallium oxide substrate to provide a channel for current flow;

[0024] preparing a first insulating layer on the N-doped gallium oxide substrate and surrounding the columnar channel;

[0025] preparing a gate dielectric layer on the first insulating layer and extending to the side area surrounding the columnar channel;

[0026] preparing a gate metal layer on the gate dielectric layer, the gate metal layer being in a ring-shaped three-dimensional structure surrounding the gate dielectric layer and used for controlling the current flow in the columnar channel;

[0027] etching the gate metal layer and the gate dielectric layer above the columnar channel to expose the top end of the columnar channel;

[0028] preparing a second insulating layer on the gate metal layer and the exposed columnar channel, etching the second insulating layer above the gate metal layer to form a ring-shaped electrode hole with the columnar channel as the center.

[0029] A gate is made on the second insulating layer, penetrates the annular electrode hole, and contacts the gate metal layer to form an annular gate;

[0030] The second insulating layer on the top of the columnar channel is etched to form an electrode through hole, and a source is made;

[0031] A drain is made at the bottom of the N-doped gallium oxide substrate.

[0032] According to an embodiment of the present disclosure, making a columnar channel on an N-doped gallium oxide substrate comprises:

[0033] A photoresist is made on the N-doped gallium oxide substrate, and silicon dioxide is deposited as a hard mask, the photoresist is removed, and a structure pattern is formed;

[0034] The gallium oxide substrate with the structure pattern is etched by inductively coupled plasma (ICP) etching to form a columnar channel.

[0035] According to an embodiment of the present disclosure, the depth of the etching treatment is 2-5 pm.

[0036] Based on the above technical solution, the gallium oxide substrate-based ring gate field effect transistor and its preparation method provided by the present disclosure have at least one of the following beneficial effects:

[0037] (1) In an embodiment of the present disclosure, N-doped gallium oxide (Ga2O3) is used as a substrate layer and a columnar channel to optimize the current transmission capacity and electron mobility of the conductive channel, provide a higher breakdown field strength for the transistor, have a higher switching speed and working frequency, enable the transistor to work in a high field strength application environment, and have better electrical performance and reliability. Combined with the excellent performance of gallium oxide itself and the design of the device structure, it is helpful to achieve a higher breakdown voltage and a smaller device size, and is more suitable for high-voltage and small-size application environments, such as high-power electronic devices and radio frequency applications.

[0038] (2) In an embodiment of the present disclosure, a columnar channel is designed in a vertical structure, and a gate metal layer surrounding the columnar channel in a ring shape can achieve a sidewall control effect, enhance the switching characteristics and current transmission capacity of the transistor, and the introduction of the annular gate also makes the electric field distribution in the channel more uniform, which can better control the current in the columnar channel. And by introducing a second insulating layer and optimizing the device structure, the leakage current of the device can be effectively reduced, and the performance and reliability of the device are improved. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 The structure diagram of the gallium oxide substrate-based ring gate field effect transistor in the embodiment of the present disclosure;

[0040] Figure 2 A top view of a top structure of a ring gate field effect transistor based on a gallium oxide substrate in an embodiment of the present disclosure;

[0041] Figure 3 A process flow chart of a preparation method of a ring gate field effect transistor based on a gallium oxide substrate in an embodiment of the present disclosure;

[0042] Figure 4 A schematic diagram of a gallium oxide substrate in a ring gate field effect transistor in an embodiment of the present disclosure;

[0043] Figure 5 A schematic diagram after a columnar channel is prepared in a ring gate field effect transistor in an embodiment of the present disclosure;

[0044] Figure 6 A top view of a structure after a columnar channel is prepared in a ring gate field effect transistor in an embodiment of the present disclosure;

[0045] Figure 7 A schematic diagram after a first insulating layer is prepared in a ring gate field effect transistor in an embodiment of the present disclosure;

[0046] Figure 8 A schematic diagram after a gate dielectric layer is prepared in a ring gate field effect transistor in an embodiment of the present disclosure;

[0047] Figure 9 A schematic diagram after a gate metal layer is prepared in a ring gate field effect transistor in an embodiment of the present disclosure;

[0048] Figure 10 A schematic diagram after the gate metal layer and the gate dielectric layer are etched in a ring gate field effect transistor in an embodiment of the present disclosure;

[0049] Figure 11 A schematic diagram after a second insulating layer is prepared in a ring gate field effect transistor in an embodiment of the present disclosure;

[0050] Figure 12 A schematic diagram after an electrode via hole is formed by etching in a ring gate field effect transistor in an embodiment of the present disclosure;

[0051] Figure 13 A schematic diagram after a gate electrode is prepared in a ring gate field effect transistor in an embodiment of the present disclosure;

[0052] Figure 14 A side view of a ring gate field effect transistor in an embodiment of the present disclosure;

[0053] Figure 15 A top surface view of a ring gate field effect transistor in an embodiment of the present disclosure; and

[0054] Figure 16 A top view of a ring gate field effect transistor array structure in an embodiment of the present disclosure.

[0055] Reference signs are explained as follows:

[0056] 1-gallium oxide substrate layer;

[0057] 2-columnar channel layer;

[0058] 3-first insulating layer;

[0059] 4-gate dielectric layer;

[0060] 5-gate metal layer;

[0061] 6-second insulating layer;

[0062] 7-gate;

[0063] 8-source;

[0064] 9-drain. DETAILED DESCRIPTION

[0065] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will further describe the present disclosure in conjunction with specific embodiments and with reference to the drawings.

[0066] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. However, it will be apparent to one skilled in the art that one or more embodiments can be practiced without these specific details. In addition, in the following description, descriptions of well-known structures and techniques have been omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0067] The terms used herein are merely used to describe specific embodiments and are not intended to limit the present disclosure. The terms "include", "comprise" and the like used herein indicate the presence of the features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0068] All terms used herein (including technical and scientific terms) have meanings commonly understood by one of ordinary skill in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having meanings consistent with the context of the present specification, and should not be interpreted in an idealized or overly formal manner.

[0069] In cases where expressions like "at least one of A, B, and C, etc." are used, it is generally intended that the inclusion of at least one of A or B or C in a given situation is intended to be construed in accordance with the meaning of this expression in normal use by those skilled in the art (e.g., "a system having at least one of A, B, and C" is intended to include, a system having A alone, a system having B alone, a system having C alone, a system having both A and B, a system having both A and C, a system having both B and C, and / or a system having A, B, and C, etc.).

[0070] At present, in order to overcome the short channel effect and the weakening of the gate control ability, various three-dimensional structure bulk effect transistors are developed, and the common three-dimensional structure transistors are fin field effect transistor (FINFET) and gate all around field effect transistor (GAAFET). Among them, the fin field effect transistor (FINFET) increases a fin structure above the channel, so that the gate can control the current in the channel from multiple directions, even if the channel length is very short, the gate can still effectively control the flow of current, reducing the influence of the short channel effect; the gate all around field effect transistor (GAAFET) completely surrounds the gate around the channel, forming a completely closed structure, further increasing the contact area of the gate and the channel, improving the control ability of the gate to the channel, and the GAAFET has great potential in reducing size and improving performance.

[0071] In general, unlike the traditional planar MOSFET, the three-dimensional structure FINFET and GAAFET increase the contact area of the gate and the channel through structural design, enhance the control ability of the gate to the channel, and can better control the current in the channel, thereby effectively overcoming the problems of short channel effect and weakening of gate control ability caused by size reduction. The development of these technologies provides new possibilities for the improvement of chip transistor density.

[0072] In the process of implementing the present disclosure, it is found that gallium oxide is a new type of ultra-wide bandgap semiconductor material with excellent breakdown field strength, Baliga figure of merit and cost control characteristics, and it has broad application prospects in the field of high-power power electronic devices. However, gallium oxide devices have leakage problems and heat dissipation problems, and the solutions mainly focus on material selection, process optimization, etc., without providing more structure and preparation options, which are too single and need to be continuously explored and developed to provide more structure and preparation options to fully exert the advantages of gallium oxide devices and improve their performance.

[0073] Therefore, the present disclosure provides a gallium oxide substrate-based ring gate field effect transistor and a preparation method thereof.

[0074] As an aspect of the present disclosure, a gallium oxide substrate-based ring gate field effect transistor is provided, which has a structure as shown inFigure 1 and Figure 2 As shown in the structure diagram of the ring gate field effect transistor based on gallium oxide substrate, the ring gate field effect transistor based on gallium oxide substrate comprises, from bottom to top: an N-doped gallium oxide substrate 1, a columnar channel 2, a first insulating layer 3, a gate dielectric layer 4, a gate metal layer 5, a second insulating layer 6, a gate 7, a source 8 and a drain 9.

[0075] Specifically, Figure 1 The structure diagram of the ring gate field effect transistor based on gallium oxide substrate in the embodiment of the present disclosure, Figure 2 The top structure diagram of the ring gate field effect transistor based on gallium oxide substrate in the embodiment of the present disclosure, the ring gate field effect transistor comprises:

[0076] The N-doped gallium oxide substrate 1;

[0077] The columnar channel 2 is formed on the N-doped gallium oxide substrate 1 and is suitable for providing a channel for current flow;

[0078] The first insulating layer 3 is arranged on the N-doped gallium oxide substrate 1 and surrounds the columnar channel 2;

[0079] The gate dielectric layer 4 is arranged on the first insulating layer 3 and extends to the side area surrounding the columnar channel 2;

[0080] The gate metal layer 5 is arranged on the gate dielectric layer 4 and surrounds the gate dielectric layer 4 in a ring shape, and is suitable for controlling the current flow in the columnar channel 2;

[0081] The second insulating layer 6 is arranged on the gate metal layer 5 and has an electrode hole penetrating the gate metal layer 5, and the electrode hole is annular with the columnar channel as the center;

[0082] The gate 7 is arranged on the second insulating layer 6 and penetrates the electrode hole, and is in contact with the gate metal layer 5;

[0083] The source 8 is arranged on the top of the columnar channel 2; and

[0084] The drain 9 is arranged at the bottom of the N-doped gallium oxide substrate 1.

[0085] According to the embodiment of the present disclosure, the structure of the ring gate field effect transistor comprises, from bottom to top: an N-doped gallium oxide substrate layer; a columnar channel formed on the substrate layer, which can be made into a columnar channel array as needed, for forming a conductive channel and providing a channel for current flow; a first insulating layer for isolating the substrate layer and the gate metal layer; a gate dielectric layer for isolating the gate metal layer and the channel and providing good electrical properties to ensure the control of the gate on the channel; a gate metal layer surrounding the columnar channel in a ring shape; and a second insulating layer for protection and reducing leakage; a source, a drain and a gate and the like.

[0086] According to embodiments of the present disclosure, compared with a planar structure, the vertical structure increases two dimensions, and the gate can surround the channel, so that the electric lines emitted by the gate are concentrated in the channel region, a more uniform gate electric field is provided, the control ability of the gate to the channel can be enhanced, so that the gate voltage can more effectively control the opening and closing of the device, further weakening the influence of short channel and narrow channel effects, thereby reducing leakage and improving sub-threshold region characteristics. The ring gate structure can make the device work normally at a smaller size, avoid the degradation of device performance caused by small size effect, which can integrate more devices in the same chip area, thereby improving the overall integration.

[0087] According to embodiments of the present disclosure, N-type doped gallium oxide (Ga2O3) as a substrate layer provides a higher breakdown field strength for the transistor, so that the transistor can work in a high field strength application environment, and the structure design is helpful to realize a higher breakdown voltage and can reduce the device size.

[0088] According to embodiments of the present disclosure, the N-type doped gallium oxide substrate 1 is preferably an N-type doped β-Ga2O3 crystal, and the doping ions include silicon and / or tin, but are not limited to silicon or tin. Other materials with corresponding functional properties can also be used as doping ions.

[0089] According to embodiments of the present disclosure, the material of the columnar channel is selected to be the same N-type doped gallium oxide as the substrate. By doping silicon and / or tin, the electron concentration in the gallium oxide substrate can be controlled, the electron mobility of the gallium oxide substrate can be improved, the mobility of electrons in the material can be enhanced, the conductivity can be improved, and by controlling the doping concentration and type, the conductivity of the material can be changed to adapt to different device application requirements.

[0090] According to embodiments of the present disclosure, the doping concentration of the doping ions in the gallium oxide substrate 1 is 1.0×10 15 ~1.0×10 20 cm -3 , for example, it can be 1.0×10 15 cm -3 , 1.0×10 16 cm -3 , 5.0×10 16 cm -3 , 1.0×10 17 cm -3 , 8.0×10 18 cm -3But not limited to the listed values, other values not listed in the range are also applicable. The doping concentration of the gallium oxide substrate 1 determines the conductivity of the channel, the higher the doping concentration, the higher the free carrier concentration in the channel, the better the conductivity of the channel region. But with the increase of the free carrier concentration in the channel, the device will become more difficult to turn off, resulting in the increase of the gate threshold voltage of the device, which is not conducive to the overall power consumption of the device. When the doping concentration is reduced, the conductivity of the channel region will be poor, and the saturation current of the device under the on state will be relatively low, therefore, too low doping concentration will bring lower source-drain saturation voltage, resulting in the reduction of the on-off ratio of the device.

[0091] According to an embodiment of the present disclosure, the columnar channel 2 is etched from the N-type doped gallium oxide substrate 1 and extends in a direction perpendicular to the N-type doped gallium oxide substrate 1.

[0092] According to an embodiment of the present disclosure, the columnar channel with a vertical structure is designed, combined with the gate metal layer surrounding the columnar channel in a ring shape, which can achieve better current control and electric field distribution, and by introducing the second insulating layer and optimizing the device structure, the leakage current of the device can be effectively reduced, and the performance and reliability of the device are improved. The depth of the columnar channel 2 is 2-5 μm, for example, it can be 2 μm, 3.6 μm, 4.2 μm, 5 μm, etc. But not limited to the listed values, other values not listed in the range are also applicable. The height of the channel determines the length of the channel region, and a longer channel region can weaken the influence of small size effect on the performance of the device to a certain extent.

[0093] According to an embodiment of the present disclosure, the material of the first insulating layer 3 and the second insulating layer 6 includes silicon oxide or aluminum oxide, and preferably the first insulating layer and the second insulating layer are the same material, and the thickness is 0.01-50 μm, for example, it can be 0.05 μm, 15 μm, 28 μm, 36 μm, 42.5 μm, etc. But not limited to the listed values, other values not listed in the range are also applicable.

[0094] According to an embodiment of the present disclosure, the first insulating layer separates the gate dielectric layer and the gallium oxide substrate, and the second insulating layer separates the gate metal layer and the gate, which can prevent current leakage and avoid mutual influence between structures, and is conducive to improving the voltage resistance and anti-interference performance of the device.

[0095] According to an embodiment of the present disclosure, the material of the gate dielectric layer 4 is a high dielectric material, including any one or more of aluminum oxide, hafnium oxide, lanthanum oxide, and tantalum oxide, which can reduce the physical thickness of the gate dielectric as much as possible while ensuring the gate capacitance unchanged, achieving the dual purpose of reducing gate leakage current and improving device reliability.

[0096] The thickness of the gate dielectric layer 4 is 0.01-0.1 μm, for example, it can be 0.02 μm, 0.05 μm, 0.07 μm, 0.09 μm, 0.1 μm, etc., but is not limited to the listed values, and other values not listed in the range are also applicable.

[0097] According to an embodiment of the present disclosure, the chemical composition of the gate metal layer 5, the gate 7, the source 8 and the drain 9 includes any one or more of chromium, titanium, aluminum, nickel, platinum and gold. Preferably, the same metal material with a specific work function is used to ensure N-type ohmic contact and reduce the resistance caused by Schottky contact.

[0098] According to an embodiment of the present disclosure, the thickness of the gate metal layer, the gate, the source and the drain is 0.01 μm-2 μm, for example, it can be 0.02 μm, 0.05 μm, 0.12 μm, 0.15 μm, 0.18 μm, etc., but is not limited to the listed values, and other values not listed in the range are also applicable.

[0099] According to an embodiment of the present disclosure, more preferably, the chemical composition of the source 8 and the drain 9 is titanium and / or chromium.

[0100] According to an embodiment of the present disclosure, the ring gate field effect transistor is arranged in an array on the same N-type doped gallium oxide substrate, which can increase the total area of the transistor, thereby increasing the power output capability. Further, the array of ring gate field effect transistors can provide higher current and lower resistance, reducing power consumption, thereby improving the switching speed and working efficiency of the transistor, and maintaining normal operation when a certain transistor fails, with higher reliability.

[0101] As another aspect of the present disclosure, a preparation method of the above-mentioned gallium oxide substrate-based ring gate field effect transistor is provided, comprising:

[0102] A columnar channel is made on the N-type doped gallium oxide substrate to provide a passage for current flow;

[0103] A first insulating layer is prepared around the columnar channel on the N-type doped gallium oxide substrate;

[0104] A gate dielectric layer is prepared on the first insulating layer and extends to the side area surrounding the columnar channel;

[0105] A gate metal layer is prepared on the gate dielectric layer, which is in a ring-shaped three-dimensional structure surrounding the gate dielectric layer, for controlling the current flow in the columnar channel;

[0106] The gate metal layer and the gate dielectric layer above the columnar channel are etched to expose the top end of the columnar channel;

[0107] A second insulating layer is prepared on the gate metal layer and the exposed columnar channel, and the second insulating layer above the gate metal layer is etched to form a ring-shaped electrode hole centered on the columnar channel;

[0108] A gate electrode is prepared on the second insulating layer and penetrates the ring-shaped electrode hole to contact the gate metal layer, thereby forming a ring-shaped gate electrode;

[0109] The second insulating layer on the top of the columnar channel is etched to form an electrode via hole, and a source electrode is prepared.

[0110] A drain electrode is prepared at the bottom of the N-type doped gallium oxide substrate.

[0111] According to an embodiment of the present disclosure, the second insulating layer is present between the gate electrode and the gate metal layer, which insulates and protects the entire device and prevents short circuiting of the device due to leakage.

[0112] According to an embodiment of the present disclosure, the preparation of the columnar channel on the N-type doped gallium oxide substrate comprises:

[0113] A photoresist is prepared on the N-type doped gallium oxide substrate, and silicon dioxide is deposited as a hard mask. The photoresist is removed to form a structure pattern.

[0114] The gallium oxide substrate with the structure pattern is etched using inductively coupled plasma (ICP) etching to form a columnar channel.

[0115] According to an embodiment of the present disclosure, the etching depth is 2-5 μm, for example, 2 μm, 3.6 μm, 4.2 μm, 5 μm, etc. However, it is not limited to the listed values, and other values not listed in this range are also applicable. The etching depth affects the length of the channel region of the device, which can be adjusted according to the influence of the channel length on the performance of the device.

[0116] According to an embodiment of the present disclosure, Figure 3 A process flow chart for the preparation method of the gallium oxide substrate-based ring gate field effect transistor in an embodiment of the present disclosure is shown below. Figure 3 The preparation method is described in detail below, which comprises steps S01-S09:

[0117] Step S01: An N-type doped gallium oxide substrate is prepared, and a doping material (silicon or tin) is introduced into the gallium oxide substrate by ion implantation or other technical means, and the concentration and distribution of the doping material are ensured to be uniform.

[0118] Step S02: define the array structure pattern using photolithography or chemical etching method. When using photolithography, after coating the photosensitive glue on the substrate, exposing and developing to form the photoresist pattern, depositing SiO2 as a hard mask, removing the photoresist, and etching the part of the substrate where the photoresist has been removed by inductively coupled plasma (ICP), a columnar channel with the target size and shape is made on the N-doped gallium oxide substrate.

[0119] Step S03: define the pattern using photolithography as in step S02, and use physical vapor deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition (PECVD) and other technologies to deposit insulating material on the surface of the substrate. The first insulating layer is prepared around the columnar channel on the N-doped gallium oxide substrate.

[0120] Step S04: use physical vapor deposition, chemical vapor deposition and other technologies to deposit dielectric material on the surface of the first insulating layer to form a gate dielectric layer.

[0121] Step S05: use physical vapor deposition, chemical vapor deposition and other technologies to deposit metal material on the surface of the gate dielectric layer to prepare a gate metal layer, and make the gate metal layer present a ring-shaped three-dimensional structure to surround the gate dielectric layer.

[0122] Step S06: use physical etching, chemical etching and other technologies to etch away the gate metal layer and gate dielectric layer above the columnar channel, exposing the top end of the columnar channel, and ensuring that the etched surface is flat and clear.

[0123] Step S07: use physical vapor deposition, chemical vapor deposition and other technologies to deposit insulating material on the gate metal layer and exposed columnar channel to form a second insulating layer.

[0124] Step S08: use physical etching, chemical etching and other technologies to etch the second insulating layer above the gate metal layer to form a ring-shaped electrode hole with the columnar channel as the center.

[0125] Step S09: use physical vapor deposition, chemical vapor deposition, evaporation and other technologies to deposit metal material on the second insulating layer to make a gate that penetrates the ring-shaped electrode hole, ensure the uniformity of the gate electrode, and contact with the gate metal layer to form a ring-shaped gate.

[0126] Step S10: use physical etching, chemical etching and other technologies to etch the second insulating layer at the top of the columnar channel to form an electrode via hole, and evaporate metal material to form a source electrode.

[0127] Step S11: make a drain electrode at the bottom of the N-doped gallium oxide substrate, ensure the uniformity of the drain electrode, and cover the bottom of the N-doped gallium oxide substrate well.

[0128] Step S12: cleaning and inspecting the sample, removing impurities and residual chemicals on the surface, observing the morphology and size of the device vertical structure by means of optical microscope and scanning electron microscope (SEM) to ensure that it meets the design requirements.

[0129] In order to make the purpose, technical scheme and advantages of the present disclosure more clear and definite, the technical scheme and principles of the present disclosure are further described and explained in the following by specific examples combined with the drawings. It should be noted that the following specific examples are only illustrative, and the protection scope of the present disclosure is not limited thereto.

[0130] The test materials and reagents used in the following examples, unless otherwise specified, can be obtained commercially. If the specific techniques or conditions are not specified in the examples, they are conventional methods, which can be performed according to the techniques or conditions described in the literature in the art or according to the product instructions.

[0131] Example 1

[0132] Preparation of a ring gate field effect transistor based on a gallium oxide substrate:

[0133] First, an N-type doped gallium oxide (β-Ga2O3) substrate 1 as shown in Figure 4 is prepared, with tin (Sn) as the doping ion and a doping concentration of 1.0×10 17 cm -3 .

[0134] The array structure pattern is defined using photolithography technology, SiO2 is deposited as a hard mask, and the N-type doped gallium oxide substrate 1 is etched using inductively coupled plasma (ICP), down to 3 μm to form a columnar channel 2 as shown in Figure 5 , and the Figure 6 structure relationship between the columnar channel 2 formed by etching and the substrate can be seen.

[0135] The pattern is defined using photolithography technology, and SiO2 is deposited around the columnar channel on the substrate surface using plasma enhanced chemical vapor deposition (PECVD), as shown in Figure 7 , forming a first insulating layer 3 with a thickness of 0.3 μm on the substrate, and a distance of 0.5 μm from the columnar channel 2.

[0136] A high dielectric medium layer of hafnium oxide (HfO2) is deposited on the structure after the formation of the first insulating layer 3, as shown in Figure 8 , forming a gate dielectric layer 4 with a thickness of 0.05 μm.

[0137] A gate metal layer 5 is deposited on the gate dielectric layer 4, with titanium and gold as the metal material, and the deposition thicknesses are 0.02 μm and 0.5 μm, respectively. The structure after the formation of the gate metal layer is shown in Figure 9 .

[0138] A via is defined by photolithography, and the gate metal layer 5 above the columnar channel is etched by chemical etching. The gate dielectric layer 4 above the columnar channel is etched by inductively coupled plasma (ICP), and the top end of the columnar channel is exposed, as shown in FIG. 3. Figure 10

[0139] A second insulating layer 6 with a thickness of 0.3 μm is deposited above the gate metal layer 5 and the columnar channel 2 by plasma enhanced chemical vapor deposition (PECVD), covering the entire device, as shown in FIG. 4. Figure 11

[0140] A via is defined by photolithography, and the top of the columnar channel 2 and the gate metal layer 5 are exposed by etching the second insulating layer 6 by inductively coupled plasma (ICP), forming an electrode via above the columnar channel 2 and a ring-shaped electrode via above the second insulating layer 6 with the columnar channel as the center, as shown in FIG. 5. Figure 12

[0141] A gate electrode 7 is deposited in the ring-shaped electrode via by photolithography and evaporation of gold (Au) with a thickness of 0.5 μm, as shown in FIG. 6. Figure 13

[0142] A source electrode 8 is deposited in the electrode via above the columnar channel 2, and a good ohmic contact is formed between the metal titanium and the β-Ga2O3 of the columnar channel. The source electrode material is titanium (Ti) and gold (Au) with a thickness of 0.02 μm and 0.5 μm, respectively. A drain electrode 9 is deposited at the bottom of the gallium oxide substrate, and the drain electrode metal is also titanium (Ti) and gold (Au) with a thickness of 0.02 μm and 0.2 μm, respectively. Thus, a ring gate field effect transistor device with a structure as shown in FIG. 7 is obtained, and the cross-sectional view is as shown in FIG. 8 and FIG. 9. Figure 1 Figure 14 Figure 15 Figure 14 is a side cross-sectional view of the gallium oxide ring gate field effect transistor in the embodiment of the present disclosure, Figure 15 is a top surface cross-sectional view of the gallium oxide ring gate field effect transistor in the embodiment of the present disclosure.

[0143] In addition, Figure 16 is a top view of the array structure of the ring gate field effect transistor in the embodiment of the present disclosure. The array structure formed based on the columnar channel can obtain a ring gate field effect transistor with an array structure as shown in FIG. 10. Figure 16

[0144] ​​​​​​​​The ring gate field effect transistor prepared based on the above scheme adopts N-type doped gallium oxide as a substrate layer and a columnar channel to optimize the current transmission capacity and electron mobility of the conductive channel, provide a higher breakdown field strength for the transistor, and through the columnar channel of the vertical structure design, in combination with the gate metal layer surrounding the columnar channel in a ring shape, the sidewall control effect can be realized, the switching characteristics and current transmission capacity of the transistor are enhanced, the current control and electric field distribution are better, and the performance and reliability of the device are improved.

[0145] The above specific embodiments further specifically describe the purposes, technical solutions and beneficial effects of the present disclosure, and it should be understood that the above are only specific embodiments of the present disclosure and are not used to limit the present disclosure, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A ring gate field effect transistor based on gallium oxide substrate, comprising: a N-type doped gallium oxide substrate (1); a columnar channel (2) formed on the N-type doped gallium oxide substrate (1) and in direct contact with the gallium oxide substrate (1), adapted to provide a path for current flow; a first insulating layer (3) disposed on the N-type doped gallium oxide substrate (1) around the area surrounding the columnar channel (2), the first insulating layer (3) having a spacing distance with the columnar channel (2) in horizontal direction, the first insulating layer (3) adapted to isolate the N-type doped gallium oxide substrate (1) and a gate metal layer (5); a gate dielectric layer (4) disposed on the first insulating layer (3) and extending to the side area surrounding the columnar channel (2), adapted to isolate the gate metal layer (5) and the columnar channel (2) so that a gate (7) controls the columnar channel (2); the gate metal layer (5) disposed on the gate dielectric layer (4) and surrounding the gate dielectric layer (4) in a ring shape, adapted to control the current flow in the columnar channel (2); a second insulating layer (6) disposed on the gate metal layer (5) and having an electrode hole penetrating to the gate metal layer (5), the electrode hole being in a ring shape with the columnar channel as the center; the gate (7) disposed on the second insulating layer (6) and penetrating the electrode hole, in contact with the gate metal layer (5); a source (8) disposed on the top of the columnar channel (2); and a drain (9) disposed on the bottom of the N-type doped gallium oxide substrate (1).

2. The field effect transistor according to claim 1, wherein 3. The field effect transistor according to claim 1, wherein The doping ions of the N-type doped gallium oxide substrate (1) include silicon and / or tin, and the doping concentration is 1.0 x 10 15 ~ 1.0 x 10 20 cm -3 . the columnar channel (2) is formed by etching the N-type doped gallium oxide substrate (1) and extends in a direction perpendicular to the N-type doped gallium oxide substrate (1).

4. The field effect transistor according to claim 1, wherein the material of the first insulating layer (3) and the second insulating layer (6) comprises silicon oxide or aluminum oxide, and the thickness is 0.01-50 μm.

5. The field effect transistor according to claim 1, wherein the material of the gate dielectric layer (4) comprises any one or more of aluminum oxide, hafnium oxide, lanthanum oxide, and tantalum oxide; and the thickness of the gate dielectric layer (4) is 0.01-0.1 μm.

6. The field effect transistor according to claim 1, wherein the chemical composition of the gate metal layer (5), the gate (7), the source (8), and the drain (9) comprises any one or more of chromium, titanium, aluminum, nickel, platinum, and gold.

7. The field effect transistor according to claim 6, wherein the chemical composition of the source (8) and the drain (9) is titanium and / or chromium.

8. A method for preparing a ring gate field effect transistor based on gallium oxide substrate as claimed in any one of claims 1 to 7, comprising: forming a columnar channel on a N-type doped gallium oxide substrate to provide a path for current flow; ​ ​ A first insulating layer is prepared on the N-doped gallium oxide substrate around the columnar channel; A gate dielectric layer is prepared on the first insulating layer and extends to the side area surrounding the columnar channel; A gate metal layer is prepared on the gate dielectric layer, which is in a ring-shaped three-dimensional structure surrounding the gate dielectric layer, for controlling the current flow in the columnar channel; The gate metal layer and the gate dielectric layer above the columnar channel are etched to expose the top end of the columnar channel; A second insulating layer is prepared on the gate metal layer and the exposed columnar channel, and the second insulating layer above the gate metal layer is etched to form a ring-shaped electrode hole with the columnar channel as the center; A gate is made on the second insulating layer and penetrates through the ring-shaped electrode hole to contact the gate metal layer, forming a ring-shaped gate; The second insulating layer at the top of the columnar channel is etched to form an electrode via hole, and a source electrode is made; A drain electrode is made at the bottom of the N-doped gallium oxide substrate.

9. The preparation method of claim 8, wherein, The columnar channel prepared on the N-doped gallium oxide substrate comprises: A photoresist is prepared on the N-doped gallium oxide substrate in a pattern, and silicon dioxide is deposited as a hard mask, the photoresist is removed to form a structure pattern; The gallium oxide substrate with the structure pattern is etched by inductively coupled plasma etching to form the columnar channel.

10. The preparation method of claim 9, wherein, The etching depth is 2-5 μm.

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