Solar crystalline silicon cell and preparation method thereof

Abstract

The present invention discloses a solar crystalline silicon cell and a method for preparing the same. The method comprises the following steps: performing texturing and diffusion of doping elements on the light-receiving surface and the backlight surface of the silicon substrate respectively; + Emitter junction; removing the doped oxide layer on the light-receiving surface and the backlight surface of the silicon substrate; preparing an anti-reflection layer on the light-receiving surface of the silicon substrate; preparing a passivation layer on the backlight surface of the silicon substrate; preparing at least one first opening area extending to the silicon substrate on the passivation layer, preparing at least one second opening area extending to the silicon substrate on the anti-reflection layer, depositing an intrinsic amorphous silicon layer and an n-type doped layer in the first opening area; preparing a conductive film layer on the backlight surface of the silicon substrate, forming an isolation groove for isolating the first opening area on the conductive film layer; and preparing a front electrode and a back electrode on the light-receiving surface and the backlight surface of the silicon substrate, respectively. The preparation method of the present invention has a relatively simple process, a short step flow, and a low production cost.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar crystalline silicon cell and a preparation method thereof. Background Art

[0002] With the iterative development of crystalline silicon cell technology, the research on high-efficiency cell technology based on N-type silicon wafers has been increasingly sought after by the industry. At present, the mainstream N-type high-efficiency cell technology is represented by HJT and Topcon cells. At the same time, the demand for technological innovation and diversity has led to the emergence of a variety of cell technologies. Since HJT cells use an intrinsic amorphous silicon layer as a passivation film layer, excellent open-circuit voltage can be obtained. The light-receiving area of ​​the light-receiving surface of the HJT cell is amorphous silicon or microcrystalline silicon and TCO film layer. The outer layer of TCO is deposited with anti-reflection film layers such as aluminum oxide, silicon oxide and magnesium fluoride. The technical effect is better, but the process is difficult to implement. The refractive index of the outermost TCO is usually 1.8~2.1. If the optical performance of TCO is improved, the electrical properties of TCO may be affected; in addition, the parasitic absorption caused by the amorphous or microcrystalline film layer on the light-receiving surface reduces the short-circuit current to a certain extent. Summary of the invention

[0003] Based on this, it is necessary to provide a solar crystalline silicon cell. The process steps of the solar crystalline silicon cell of the present invention are relatively simple, the method is easy to operate and implement, and can reduce costs and increase production capacity. Furthermore, the front side of the solar crystalline silicon cell of the present application adopts the excellent optical performance design of the light-receiving surface of the Topcon cell, and the local metallized area on the back side adopts the HJT cell design method, which concentrates the advantages of the two cells, thereby greatly improving the cell efficiency.

[0004] An embodiment of the present application provides a solar crystalline silicon cell.

[0005] A method for preparing a solar crystalline silicon cell comprises the following steps:

[0006] The light-receiving surface and the backlight surface of the silicon substrate are respectively textured and doped with elements to form a p + Launch knot;

[0007] Removing the doped oxide layers on the light-receiving surface and the backlight surface of the silicon substrate;

[0008] Preparing an anti-reflection layer on the light-receiving surface of the silicon substrate;

[0009] Prepare a passivation layer on the backlight side of the silicon substrate;

[0010] Prepare at least one first opening region extending to the silicon substrate on the passivation layer, prepare at least one second opening region extending to the silicon substrate on the anti-reflection layer, and deposit an intrinsic amorphous silicon layer and an n-type doping layer in the first opening region;

[0011] A conductive film layer is prepared on the backlight surface of the silicon substrate, and an isolation groove for isolating the first opening area is formed on the conductive film layer; and

[0012] A front electrode and a back electrode are respectively prepared on the light-receiving surface and the backlight surface of the silicon substrate.

[0013] In some of the embodiments, when the light-receiving surface and the backlight surface of the silicon substrate are textured respectively, the texture morphology includes positive pyramid patterns and / or inverted pyramid patterns, and the reflectivity of the light-receiving surface of the silicon substrate after textured is 6% to 15%.

[0014] In some embodiments, the doping element during the diffusion of the doping element includes boron or phosphorus.

[0015] In some of the embodiments, when the light-receiving surface and the backlight surface of the silicon substrate are diffused with doping elements respectively, the following steps are included: high-temperature boron diffusion is performed on the light-receiving surface and the backlight surface of the silicon substrate respectively, the diffusion equipment is a high-temperature tubular diffusion furnace, the diffusion temperature is 800℃~1000℃, and the diffusion square resistance is 80Ω / sq~150Ω / sq.

[0016] In some embodiments, when removing the doped oxide layer on the light-receiving surface and the backlight surface of the silicon substrate, the following steps are included: chemically wet cleaning the light-receiving surface and the backlight surface of the silicon substrate after diffusion to remove the doped oxide layer.

[0017] In some embodiments, the anti-reflection layer is AlO x Layer, SiN x Layer, SiN x O y One or more laminated structures;

[0018] And / or, the anti-reflection layer has a thickness of 70 nm to 120 nm.

[0019] In some embodiments, the passivation layer is an aluminum oxide layer;

[0020] And / or, the thickness of the passivation layer is 70nm~120nm.

[0021] In some embodiments, the thickness of the intrinsic amorphous silicon layer is 8 nm to 18 nm;

[0022] And / or, the thickness of the n-type doping layer is 10 nm to 30 nm.

[0023] In some embodiments, the conductive film layer includes an ITO film layer, an ICO film layer, an IWO film layer, an AZO film layer or a GAZO film layer;

[0024] And / or, the thickness of the conductive film layer is 40nm~130nm.

[0025] An embodiment of the present application also provides a solar crystalline silicon cell.

[0026] A solar crystalline silicon cell is prepared by adopting the preparation method.

[0027] The preparation method of the solar crystalline silicon cell of the present application has a relatively simple process, a short process flow, reduces the production cost, and is easy to produce. In the solar crystalline silicon cell prepared by the preparation method of the solar crystalline silicon cell of the present application, the light-receiving surface of the cell follows the front design concept of the classic Topcon cell, reducing optical absorption loss and increasing the short-circuit current of the cell; the metal area on the back of the cell adopts HJT intrinsic amorphous silicon and n-type doped amorphous or amorphous silicon to improve the interface passivation performance, reduce the dark saturation current density, and also reduce the metal semiconductor contact resistance, and the n+ back field plays a role in reducing minority carrier transmission losses; the non-metallic area on the backlight side of the cell still maintains the velvet structure and the matching p-type passivation layer, increasing the internal reflection of the incident light and improving the passivation performance of the film layer, thereby playing a role in improving the efficiency of the cell.

[0028] Furthermore, in the preparation method of the solar crystalline silicon cell in the present invention, firstly, several high-temperature processes such as high-temperature diffusion are performed, which have certain requirements on the quality of the silicon substrate and the impurity absorption effect, thereby ensuring the premise of high conversion efficiency of the cell; then, low-temperature processes such as deposition of a passivation layer and an anti-reflection layer are performed to ensure the good performance of each film layer on the back of the cell, and an anti-reflection film layer with excellent optical properties is deposited on the front, such as an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer or a multi-layer stack, and aluminum oxide is first deposited on the back to prepare the first opening area, and intrinsic amorphous silicon and an n-type doped layer such as an n-type doped amorphous silicon layer or a microcrystalline silicon layer are deposited to improve the interface passivation performance, reduce the dark saturation current density, and also reduce the metal semiconductor contact resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0030] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings. In the following description, the same reference numerals represent the same parts.

[0031] Figure 1 This is a schematic diagram of a process flow of a method for preparing a solar crystalline silicon cell according to an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of the structure of a solar crystalline silicon cell according to an embodiment of the present invention.

[0033] Description of Reference Numerals

[0034] 10. Solar crystalline silicon cell; 100. Silicon substrate; 101. p + Emitter junction; 102, anti-reflection layer; 103, front electrode; 201, doped polysilicon layer; 202, passivation layer; 203, intrinsic amorphous silicon layer; 204, n-type doped layer; 205, conductive film layer; 2051, isolation groove; 206, back electrode. DETAILED DESCRIPTION

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0036] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0037] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0038] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0039] In the description of the present invention, "several" means more than one, "many" means more than two, "greater than", "less than", "exceed" etc. are understood to exclude the number itself, and "above", "below", "within" etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0040] In the present invention, unless otherwise stated, the sum of the parts of each component in the composition can be 100 parts by weight. Unless otherwise specified, the basis of the percentages (including weight percentages) of the present invention is the total weight of the composition. In addition, "wt%" herein means mass percentage, and "at%" means atomic percentage.

[0041] In this article, unless otherwise stated, each reaction step may be carried out in the order described herein or may not be carried out in the order described herein. For example, other steps may be included between each reaction step, and the order of the reaction steps may also be appropriately swapped. This can be determined by the technician based on common knowledge and experience. Preferably, the reaction method herein is carried out sequentially.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0043] The present application provides a solar crystalline silicon cell 10 and a method for preparing the same, in order to solve the problems of complicated process steps, high difficulty in method operation, high production cost and limited production capacity in the production of N-type high-efficiency cells such as HJT and Topcon cells in the conventional technology. The solar crystalline silicon cell 10 will be described below in conjunction with the accompanying drawings.

[0044] The solar crystalline silicon cell 10 and the preparation method thereof provided in the embodiment of the present application are exemplary, please refer to Figure 1 As shown, Figure 1 The schematic diagram of the structure of the solar crystalline silicon cell 10 provided in the embodiment of the present application. The process steps of the solar crystalline silicon cell 10 of the present application are relatively simple, and the method is easy to operate and implement, which can reduce costs and increase production capacity. In order to more clearly illustrate the structure of the solar crystalline silicon cell 10, the solar crystalline silicon cell 10 will be introduced in conjunction with the accompanying drawings.

[0045] Exemplarily, a method for preparing a solar crystalline silicon cell 10 comprises the following steps:

[0046] (1) The light-receiving surface and the backlight surface of the silicon substrate 100 are textured and doped with elements to form a doped polysilicon layer 201 and a doped oxide layer. The light-receiving surface of the silicon substrate 100 is formed into a p + Emitting knot 101;

[0047] (2) The doped oxide layers on the light-receiving surface and the backlight surface of the silicon substrate 100 are removed.

[0048] (3) An anti-reflection layer 102 is formed on the light-receiving surface of the silicon substrate 100 .

[0049] (4) A passivation layer 202 is prepared on the backlight side of the silicon substrate 100 .

[0050] (5) At least one first opening region extending to the silicon substrate 100 is prepared on the passivation layer 202, at least one second opening region extending to the silicon substrate 100 is prepared on the anti-reflection layer 102, and an intrinsic amorphous silicon layer 203 and an n-type doping layer 204 are deposited in the first opening region.

[0051] (6) A conductive film layer 205 is prepared on the backlight surface of the silicon substrate 100 , and an isolation groove 2051 for isolating the first opening area is formed on the conductive film layer 205 .

[0052] (7) A front electrode 103 and a back electrode 206 are prepared on the light-receiving surface and the back-lighting surface of the silicon substrate 100, respectively.

[0053] In the solar crystalline silicon cell 10 prepared by the preparation method of the present application, the light-receiving surface of the cell follows the front design concept of the classic Topcon cell, which reduces optical absorption loss and improves the short-circuit current of the cell; the metal area on the back of the cell adopts HJT intrinsic amorphous silicon and n-type doping layer such as n-type doped amorphous or amorphous silicon, which improves the interface passivation performance, reduces the dark saturation current density, and also reduces the metal semiconductor contact resistance. The n+ back field also reduces the minority carrier transmission loss; the non-metallic area on the backlight side of the cell still maintains the velvet structure and the matching p-type passivation layer 202, which increases the internal reflection of the incident light and improves the passivation performance of the film layer, thereby improving the cell efficiency.

[0054] In some of the embodiments, when the light-receiving surface and the backlight surface of the silicon substrate 100 are textured respectively, the texture morphology includes a positive pyramid pattern and / or an inverted pyramid pattern, and the reflectivity of the light-receiving surface of the silicon substrate 100 after texturing is 6% to 15%.

[0055] In some of the embodiments, the width dimension of the pyramid image is 0.5 μm-10 μm.

[0056] In some of these embodiments, the texturing is performed using a chemical wet process.

[0057] In some embodiments, the doping element during diffusion of the doping element includes boron or phosphorus. Correspondingly, the doped oxide layer obtained after doping is BSG (boron-doped silicon oxide) or PSG (phosphorus-doped silicon oxide).

[0058] In some of the embodiments, when the light-receiving surface and the backlight surface of the silicon substrate 100 are diffused with doping elements respectively, the following steps are included: high-temperature boron diffusion is performed on the light-receiving surface and the backlight surface of the silicon substrate 100 respectively, the diffusion equipment is a high-temperature tubular diffusion furnace, the diffusion temperature is 800°C~1000°C, and the diffusion square resistance is 80Ω / sq~150Ω / sq.

[0059] In some embodiments, the removal of the doped oxide layer on the light-receiving surface and the backlight surface of the silicon substrate 100 includes the following steps: chemically wet cleaning the light-receiving surface and the backlight surface of the silicon substrate 100 after diffusion to remove the doped oxide layer.

[0060] In some embodiments, the anti-reflection layer 102 is AlO x Layer, SiN x Layer, SiN x O y One or more laminated structures.

[0061] In some embodiments, the thickness of the anti-reflection layer 102 is 70 nm to 120 nm. For example, in one specific example, the thickness of the anti-reflection layer 102 is 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm or other values.

[0062] In some embodiments, the passivation layer 202 is an aluminum oxide layer.

[0063] In some embodiments, the thickness of the passivation layer 202 is 70 nm to 120 nm. For example, in one specific example, the thickness of the passivation layer 202 is 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm or other values.

[0064] In some embodiments, the thickness of the intrinsic amorphous silicon layer 203 is 8 nm to 18 nm. For example, in one specific example, the thickness of the intrinsic amorphous silicon layer 203 is 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm or other values.

[0065] In some embodiments, the thickness of the n-type doping layer 204 is 10 nm to 30 nm. For example, in one specific example, the thickness of the n-type doping layer 204 is 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm or other values.

[0066] In some embodiments, the n-type doped layer 204 is an n-type doped amorphous silicon layer or a microcrystalline silicon layer.

[0067] In some of the embodiments, a mask method is used when preparing the intrinsic amorphous silicon layer 203 and the n-type doping layer 204 , and the mask method includes but is not limited to deposition using a fine pattern mask plate shielding method.

[0068] In some embodiments, the conductive film layer 205 includes an ITO (tin-doped indium oxide) film layer, an ICO (cerium-doped indium oxide) film layer, an IWO (tungsten-doped indium oxide) film layer, an AZO (aluminum-doped zinc oxide) film layer or a GAZO (aluminum-gallium co-doped zinc oxide) film layer.

[0069] In some embodiments, the thickness of the conductive film layer 205 is 40 nm to 130 nm. For example, in one specific example, the thickness of the conductive film layer 205 is 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm or other values.

[0070] In some of the embodiments, the preparation of the isolation groove 2051 includes the following steps: preparing the conductive film layer 205 using a mask method, wherein a preset area of ​​the conductive film layer 205 has the isolation groove 2051, or preparing the entire conductive film layer 205, and then using a laser grooving method to form an isolation groove 2051 in a preset area of ​​the conductive film layer 205.

[0071] In some of the embodiments, when preparing the front electrode 103 and the back electrode 206 on the light-receiving surface and the backlight surface of the silicon substrate 100 respectively, the following steps are included: using screen printing low-temperature silver paste or silver-clad copper material to form metal grid lines on the light-receiving surface and the backlight surface of the silicon substrate 100 to form the front electrode 103 and the back electrode 206 respectively.

[0072] An embodiment of the present application further provides a solar crystalline silicon cell 10 .

[0073] A solar crystalline silicon cell 10 is prepared by a preparation method.

[0074] Example 1

[0075] This embodiment provides a solar crystalline silicon cell 10. The solar crystalline silicon cell 10 of this embodiment is prepared by the following preparation method.

[0076] A method for preparing a solar crystalline silicon cell 10 comprises the following steps:

[0077] (1) The light-receiving surface and the back-lighting surface of the n-type silicon substrate 100 are textured by a chemical wet process. The textured surface of the light-receiving surface is a positive pyramid pattern, and the textured surface of the back-lighting surface is an inverted pyramid pattern. The reflectivity of the light-receiving surface of the silicon substrate 100 is 6% to 15%. The width of the positive pyramid image is 0.5 μm, and the width of the inverted pyramid image is 0.5 μm.

[0078] (2) A high-temperature tubular diffusion furnace is used to perform high-temperature boron diffusion on the light-receiving surface and the back-lighting surface of the silicon substrate 100. The diffusion temperature is 800°C and the diffusion square resistance is 80Ω / sq. The light-receiving surface of the silicon substrate 100 forms a p + Emitting knot 101.

[0079] (3) After diffusion, chemical wet cleaning is performed to remove the BSG on the light-receiving surface and the backlight surface of the silicon substrate 100.

[0080] (4) An aluminum oxide layer is deposited on the light-receiving surface of the silicon substrate 100 as an anti-reflection layer 102 . The thickness of the anti-reflection layer 102 is 70 nm.

[0081] (5) An aluminum oxide layer is prepared on the backlight side of the silicon substrate 100 as a passivation layer 202 . The thickness of the passivation layer 202 is 70 nm.

[0082] (6) Laser cutting is performed on the passivation layer 202 on the backlight surface of the silicon substrate 100 to prepare a plurality of first opening regions extending to the silicon substrate 100 .

[0083] (7) Laser grooves are formed on the anti-reflection layer 102 on the light-receiving surface of the silicon substrate 100 to prepare a plurality of second opening regions extending to the silicon substrate 100. The first opening region and the second opening region on the light-receiving surface of the silicon substrate 100 on the backlight side are cleaned using a wet chemical method.

[0084] (8) Deposit an intrinsic amorphous silicon layer 203 and an n-type doped amorphous silicon layer in the first opening region by using a mask method, and the deposition temperature is 160° C. The thickness of the intrinsic amorphous silicon layer 203 is 8 nm, and the thickness of the n-type doped amorphous silicon layer is 10 nm.

[0085] (9) A conductive film layer 205 is prepared on the backlight side of the silicon substrate 100. The thickness of the conductive film layer 205 is 40 nm~.

[0086] (10) An isolation groove 2051 for isolating the first opening area is formed on the conductive film layer 205 by laser grooving.

[0087] (11) A low-temperature silver paste is screen-printed to form metal grid lines on the light-receiving side and the backlight side of the silicon substrate 100, respectively, to form a front electrode 103 and a back electrode 206.

[0088] Example 2

[0089] This embodiment provides a solar crystalline silicon cell 10. The solar crystalline silicon cell 10 of this embodiment is prepared by the following preparation method.

[0090] A method for preparing a solar crystalline silicon cell 10 comprises the following steps:

[0091] (1) The light-receiving surface and the back-lighting surface of the n-type silicon substrate 100 are textured by a chemical wet process. The textured surface of the light-receiving surface is a positive pyramid pattern, and the textured surface of the back-lighting surface is an inverted pyramid pattern. The reflectivity of the light-receiving surface of the silicon substrate 100 is 6% to 15%. The width of the positive pyramid image is 10 μm, and the width of the inverted pyramid image is 10 μm.

[0092] (2) A high-temperature tubular diffusion furnace is used to perform high-temperature phosphorus diffusion on the light-receiving surface and the backlight surface of the silicon substrate 100. The diffusion temperature is 1000°C and the diffusion square resistance is 150Ω / sq. The light-receiving surface of the silicon substrate 100 forms a phosphorus layer. + Emitting knot 101.

[0093] (3) After diffusion, chemical wet cleaning is performed to remove the PSG on the light-receiving surface and the backlight surface of the silicon substrate 100.

[0094] (4) A silicon nitride layer is deposited on the light-receiving surface of the silicon substrate 100 as an anti-reflection layer 102 . The thickness of the anti-reflection layer 102 is 120 nm.

[0095] (5) An aluminum oxide layer is prepared on the backlight side of the silicon substrate 100 as a passivation layer 202 . The thickness of the passivation layer 202 is 120 nm.

[0096] (6) Laser cutting is performed on the passivation layer 202 on the backlight surface of the silicon substrate 100 to prepare a plurality of first opening regions extending to the silicon substrate 100 .

[0097] (7) Laser grooves are formed on the anti-reflection layer 102 on the light-receiving surface of the silicon substrate 100 to prepare a plurality of second opening regions extending to the silicon substrate 100. The first opening region and the second opening region on the light-receiving surface of the silicon substrate 100 on the backlight side are cleaned using a wet chemical method.

[0098] (8) Deposit an intrinsic amorphous silicon layer 203 and an n-type doped amorphous silicon layer in the first opening region by using a mask method at a deposition temperature of 220° C. The thickness of the intrinsic amorphous silicon layer 203 is 18 nm, and the thickness of the n-type doped amorphous silicon layer is 30 nm.

[0099] (9) A conductive film layer 205 is prepared on the backlight surface of the silicon substrate 100 using a mask method, and the mask plate enables a predetermined area of ​​the conductive film layer 205 to have an isolation groove 2051. The thickness of the conductive film layer 205 is 130 nm.

[0100] (10) A low-temperature silver-coated copper material is screen-printed to form metal grid lines on the light-receiving side and the backlight side of the silicon substrate 100 to form a front electrode 103 and a back electrode 206, respectively.

[0101] The performance of the solar crystalline silicon cells 10 in Example 1 and Example 2 was tested, and the test results are shown in Table 1.

[0102] Table 1

[0103]

[0104] In summary, the preparation method of the solar crystalline silicon cell 10 of the present application is relatively simple, the steps are short, the production cost is reduced, and it is easy to produce. In the preparation method of the solar crystalline silicon cell 10 of the present invention, first, there are several high-temperature processes such as high-temperature diffusion, etc., which have certain requirements on the quality of the silicon substrate 100 and the impurity absorption effect, ensuring the premise of high conversion efficiency of the battery; then through low-temperature processes such as deposition to prepare the passivation layer 202 and the anti-reflection layer 102, etc., to ensure the good performance of each film layer on the back of the battery, and deposit an anti-reflection film layer with excellent optical properties on the front, such as an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer or a multi-layer stack, and first deposit aluminum oxide on the back to prepare the first opening area, and deposit and prepare intrinsic amorphous silicon and n-type doped amorphous silicon layer or microcrystalline silicon layer, which improves the interface passivation performance, reduces the dark saturation current density, and also reduces the metal semiconductor contact resistance.

[0105] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0106] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a solar crystalline silicon cell, characterized in that: The steps include: The light-receiving surface and the backlight surface of the silicon substrate are respectively textured and doped with elements to form a doped polysilicon layer and a doped oxide layer. + Launch knot; Removing the doped oxide layers on the light-receiving surface and the backlight surface of the silicon substrate; Preparing an anti-reflection layer on the light-receiving surface of the silicon substrate; Preparing a passivation layer on the backlight surface of the silicon substrate, wherein the passivation layer is an aluminum oxide layer; Prepare at least one first opening region extending to the silicon substrate on the passivation layer, prepare at least one second opening region extending to the silicon substrate on the anti-reflection layer, and deposit an intrinsic amorphous silicon layer and an n-type doping layer in the first opening region; Preparing a conductive film layer on the backlight surface of the silicon substrate, and forming an isolation groove for isolating the first opening area on the conductive film layer; as well as A front electrode and a back electrode are respectively prepared on the light-receiving surface and the backlight surface of the silicon substrate.

2. The solar crystalline silicon cell according to claim 1, characterized in that: When the light-receiving surface and the backlight surface of the silicon substrate are textured respectively, the textured surface morphology includes positive pyramid patterns and / or inverted pyramid patterns. After the texture, the reflectivity of the light-receiving surface of the silicon substrate is 6% to 15%.

3. The solar crystalline silicon cell according to claim 1, characterized in that: The doping element during the diffusion of the doping element includes boron.

4. The solar crystalline silicon cell according to claim 1, characterized in that: When the light-receiving surface and the backlight surface of the silicon substrate are diffused with doping elements respectively, the following steps are included: high-temperature boron diffusion is performed on the light-receiving surface and the backlight surface of the silicon substrate respectively, the diffusion equipment is a high-temperature tubular diffusion furnace, the diffusion temperature is 800°C to 1000°C, and the diffusion square resistance is 80Ω / sq to 150Ω / sq.

5. The solar crystalline silicon cell according to claim 1, characterized in that: When removing the doped oxide layer on the light-receiving surface and the backlight surface of the silicon substrate, the following steps are included: chemically wet cleaning the light-receiving surface and the backlight surface of the silicon substrate after diffusion respectively to remove the doped oxide layer.

6. The solar crystalline silicon cell according to any one of claims 1 to 5, characterized in that: The anti-reflection layer is AlO x Layer, SiN x Layer, SiN x O y One or more laminated structures; And / or, the anti-reflection layer has a thickness of 70 nm to 120 nm.

7. The solar crystalline silicon cell according to any one of claims 1 to 5, characterized in that: The thickness of the passivation layer is 70nm-120nm.

8. The solar crystalline silicon cell according to any one of claims 1 to 5, characterized in that: The thickness of the intrinsic amorphous silicon layer is 8nm to 18nm; And / or, the thickness of the n-type doping layer is 10 nm to 30 nm.

9. The solar crystalline silicon cell according to any one of claims 1 to 5, characterized in that: The thickness of the conductive film layer is 40nm-130nm.

10. The solar crystalline silicon cell according to any one of claims 1 to 5, characterized in that: The conductive film layer includes an ITO film layer, an ICO film layer, an IWO film layer, an AZO film layer or a GAZO film layer.

11. A solar crystalline silicon cell, characterized in that: The solar crystalline silicon cell is prepared by the preparation method according to any one of claims 1 to 10.

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