Flexible circuit substrate and method of manufacturing thin film flip chip package structure

Abstract

A flexible circuit substrate for carrying a chip having a plurality of bumps is provided. The flexible circuit substrate includes a flexible dielectric substrate and a bonding circuit. The bonding circuit includes at least a first circuit group, a second circuit group, and a third circuit group. Each first circuit group includes a plurality of first pins. The bumps between adjacent two first pins to be correspondingly bonded have a first predetermined pitch. A first pitch between the adjacent two first pins is equal to the first predetermined pitch multiplied by a first compensation value. Each second circuit group includes a plurality of second pins. The bumps between adjacent two second pins to be correspondingly bonded have a second predetermined pitch. A second pitch between the adjacent two second pins is equal to the second predetermined pitch multiplied by a second compensation value. The second compensation value is not equal to the first compensation value.

Description

Technical Field

[0001] This invention relates to a flexible circuit board, and more particularly to a flexible circuit board and a method for manufacturing a thin-film flip-chip package structure comprising the aforementioned flexible circuit board. Background Technology

[0002] With advancements in semiconductor technology, liquid crystal displays (LCDs) have become widely used in everyday electronic products such as mobile phones, laptops, desktop computers, and LCD televisions, offering advantages like low power consumption, thinness, light weight, high resolution, high color saturation, and long lifespan. The driver IC is an indispensable component of LCDs. To meet the diverse application requirements of LCD driver chips, tape-on-board (TAB) packaging technology is typically employed. Chip-on-Film (COF) packaging is one such example of a packaging structure utilizing TAB technology.

[0003] Thin-film flip-chip packaging is a packaging technology that achieves electrical connection by bonding the chip to the pins on a flexible circuit substrate using conductive bumps. Among these processes, inner lead bonding (ILB) is a particularly critical step. However, with the trend towards increasingly dense and complex circuit layouts, maintaining the overall yield of inner lead bonding is becoming increasingly difficult. Summary of the Invention

[0004] The present invention provides a flexible circuit board and a method for manufacturing a thin-film flip-chip package structure including the aforementioned flexible circuit board, which can improve the problem that the flexible circuit board causes unequal pin offsets due to different degrees of shrinkage caused by heat during the chip bonding process, resulting in partial pin misalignment during chip bonding.

[0005] At least one embodiment of the present invention provides a flexible circuit substrate for carrying a chip having multiple bumps. The flexible circuit substrate includes a flexible dielectric substrate and bonding lines. The upper surface of the flexible dielectric substrate has a chip bonding region. The chip bonding region has a long side and includes a central region, two first variation regions, and two outer regions arranged along the long side. The central region is located between the two first variation regions, and the two first variation regions and the central region are located between the two outer regions. Bonding lines are formed on the upper surface of the flexible dielectric substrate and within the chip bonding region for corresponding bonding of the multiple bumps of the chip. The bonding lines include at least one first line group, multiple second line groups, and multiple third line groups. The first line groups are located in the central region. Each first line group includes multiple first pins arranged adjacent to each other along the long side. A first predetermined spacing is provided between the bumps corresponding to bonding two adjacent first pins. The first spacing between two adjacent first pins is equal to the first predetermined spacing multiplied by a first compensation value. The second line groups are respectively located in the two first variation regions. Each second line group includes multiple second pins arranged adjacent to each other along the long side. The bumps used to engage two adjacent second pins have a second predetermined spacing. The second spacing between two adjacent second pins is equal to the second predetermined spacing multiplied by a second compensation value. Third line groups are located in two outer regions. Each third line group includes multiple third pins arranged adjacently along its long side. The bumps used to engage two adjacent third pins have a third predetermined spacing. The third spacing between two adjacent third pins is equal to the third predetermined spacing multiplied by a third compensation value. The second compensation value is not equal to the first compensation value.

[0006] At least one embodiment of the present invention provides a method for manufacturing a thin-film flip-chip package structure, comprising the following steps: A flexible circuit substrate as described above is provided. A thermo-pressing process is performed to place a chip in a chip bonding region. The flexible circuit substrate is heated and shrunk, such that a plurality of bumps on the chip are respectively bonded to a plurality of first pins, a plurality of second pins, and a plurality of third pins of the flexible circuit substrate at a plurality of first predetermined spacings, a plurality of second predetermined spacings, and a plurality of third predetermined spacings.

[0007] Based on the above, this invention divides the chip bonding area into regions and presets different compensation values ​​for the spacing of the pins of the bonding lines in each region. As a result, the problem of pin misalignment bonding bumps caused by inconsistent expansion or contraction in different regions of the chip bonding area is improved, and the yield of the internal pin bonding process can be effectively increased. Attached Figure Description

[0008] Figure 1 This is a top view schematic diagram of a flexible circuit board according to an embodiment of the present invention;

[0009] Figure 2This is a partial top view of the active surface of a chip according to an embodiment of the present invention;

[0010] Figure 3A yes Figure 1 A partially enlarged schematic diagram of the central area of ​​the chip bonding region of a flexible circuit board.

[0011] Figure 3B yes Figure 1 A partially enlarged schematic diagram of the first variation region of the chip bonding area of ​​a flexible circuit board.

[0012] Figure 3C yes Figure 1 A partially enlarged schematic diagram of the outer region of the chip bonding area of ​​a flexible circuit board.

[0013] Figure 3D yes Figure 1 A partially enlarged schematic diagram of the second variation region of the chip bonding area of ​​the flexible circuit board.

[0014] Figure 3E yes Figure 1 A partially enlarged schematic diagram of the third variation region of the chip bonding area of ​​a flexible circuit board.

[0015] Figure 4 yes Figure 1 A partial bottom view of the flexible circuit board.

[0016] Figure 5 This is a top view schematic diagram of the chip bonding area of ​​a flexible circuit board according to an embodiment of the present invention.

[0017] Figure 6 This is a top view schematic diagram of a thin-film flip-chip packaging structure according to an embodiment of the present invention;

[0018] Figure 7 yes Figure 6 A partial cross-sectional schematic diagram of a thin-film flip-chip packaging structure;

[0019] Figure 8 yes Figure 6 A partially enlarged schematic diagram of the outer region of the thin-film flip-chip packaging structure. Detailed Implementation

[0020] Figure 1 This is a top view schematic diagram of a flexible circuit board according to an embodiment of the present invention. Figure 2 This is a partial top view of the active surface of a chip according to an embodiment of the present invention.

[0021] Please refer to this first. Figure 1 and Figure 2The flexible circuit board 10 is used to support a chip CP having multiple bumps BP1 to BP10, wherein Figure 1 The flexible circuit substrate 10 is shown before it is bonded to the chip CP.

[0022] The flexible circuit board 10 includes a flexible dielectric substrate FS. The flexible dielectric substrate FS is made of materials such as polyethylene terephthalate (PET), polyimide (PI), polyethersulfone (PES), polycarbonate (PC), or other suitable flexible materials.

[0023] The upper surface of the flexible dielectric substrate FS has a chip bonding region 100. The chip bonding region 100 includes a central region 110, two first variation regions 120, and two outer regions 130. In some embodiments, the chip bonding region 100 further includes two second variation regions 140 and two third variation regions 150.

[0024] The chip bonding region 100 includes a long side 102, another long side 104 opposite to the long side 102, and two short sides 106. A central region 110, two first variant regions 120, two third variant regions 150, two second variant regions 140, and two outer regions 130 are arranged along the long side 102 of the chip bonding region 100. The central region 110 is located between the two first variant regions 120. The two first variant regions 120 are respectively located between the two third variant regions 150 and the central region 110. The two third variant regions 150 are respectively located between the two first variant regions 120 and the two second variant regions 140. The two second variant regions 140 are respectively located between the two outer regions 130 and the two third variant regions 150. The central region 110, the two first variant regions 120, the two second variant regions 140, and the two third variant regions 150 are located between the two outer regions 130. In this embodiment, the chip bonding region 100 consists of an outer region 130, a second variant region 140, a third variant region 150, a first variant region 120, and a central region 110, connected sequentially from the outermost to the center. However, this invention is not limited to this. In other embodiments, the second variant region 140 and / or the third variant region 150 may be omitted. Furthermore, this invention does not limit the number of variant regions. In other embodiments, more variant regions (e.g., a fourth variant region, a fifth variant region, etc.) may be further included between the first variant region 120 and the third variant region 150 or between the second variant region 140 and the third variant region 150.

[0025] Figure 1 The upper-layer UC is only used to illustrate its approximate location. The upper-layer UC consists of multiple separate signal lines, and is not as shown in the image. Figure 1 The diagram shows the entire structure. The upper layer circuitry UC is formed on the upper surface of the flexible dielectric substrate FS. The upper layer circuitry UC extends outward from within the chip bonding region 100. Bonding lines 200 in the upper layer circuitry UC are located within the chip bonding region 100 and are used to correspond to the bumps BP1 to BP10 of the chip CP. In some embodiments, the bonding lines 200 include at least one first line group 210 located in the central region 110, a plurality of second line groups 220 located in two first variation regions 120, a plurality of third line groups 230 located in two outer regions 130, a plurality of fourth line groups 240 located in two second variation regions 140, and a plurality of fifth line groups 250 located in two third variation regions 150. In other embodiments, when the chip bonding region 100 does not include the second variation region 140 and / or the third variation region 150, the bonding lines 200 do not include the fourth line group 240 and / or the fifth line group 250.

[0026] in addition, Figure 2 The diagram shows a portion of the active surface of the chip CP corresponding to the central region 110, a portion corresponding to one of the first variation regions 120, a portion corresponding to one of the outer regions 130, a portion corresponding to one of the second variation regions 140, and a portion corresponding to one of the third variation regions 150, with other portions of the chip CP omitted. Bumps BP1 to BP10 are located on the active surface of the chip CP, wherein bumps BP1 and BP6 correspond to the central region 110, bumps BP2 and BP7 correspond to the first variation region 120, bumps BP3 and BP8 correspond to the outer region 130, bumps BP4 and BP9 correspond to the second variation region 140, and bumps BP5 and BP10 correspond to the third variation region 150. The chip CP can be a driver chip or any suitable chip.

[0027] Figure 3A yes Figure 1 A partially enlarged schematic diagram of the central region 110 of the chip bonding area 100 of the flexible circuit board 10. Figure 3B yes Figure 1 A partially enlarged schematic diagram of the first variation region 120 of the chip bonding region 100 of the flexible circuit board 10. Figure 3C yes Figure 1 A partially enlarged schematic diagram of the outer region 130 of the chip bonding region 100 of the flexible circuit board 10. Figure 3D yes Figure 1 A partially enlarged schematic diagram of the second variation region 140 of the chip bonding region 100 of the flexible circuit board 10. Figure 3E yes Figure 1 A partially enlarged schematic diagram of the third variation region 150 of the chip bonding region 100 of the flexible circuit board 10. Figures 3A to 3EThe default positions of bumps BP1-BP10 and SBP on the chip CP are shown in dashed lines; however, these default positions are for illustrative purposes only. In reality, in... Figures 3A to 3E In this structure, the chip CP is not bonded to the flexible circuit substrate 10. When the internal pin bonding process is performed by thermocompression to bond the chip CP to the flexible circuit substrate 10, the high temperature will cause the flexible circuit substrate 10 to shrink or expand significantly, which will lead to a change in the pin position of the bonding line 200. Therefore, before performing the chip bonding (i.e., internal pin bonding) process, the pin position of the bonding line 200 is offset from the preset position of the bumps BP1 to BP10 of the chip CP. After performing the chip bonding process, the flexible circuit substrate 10 shrinks or expands, causing the pin of the bonding line 200 to shift and align with the position of the bumps BP1 to BP10 of the chip CP.

[0028] Please refer to Figure 3A Each first line group 210 includes a plurality of first pins 212 arranged adjacently along the long side 102 of the chip bonding region 100. A first predetermined spacing PX1 is provided between bumps BP1 corresponding to the bonding of two adjacent first pins 212. In other words, the first predetermined spacing PX1 is the spacing between preset positions of the two bumps BP1 corresponding to the bonding of two adjacent first pins 212. Before bonding with the chip CP, there is a first spacing X1 between two adjacent first pins 212. The first spacing X1 is not equal to the first predetermined spacing PX1, and the first spacing X1 is equal to the first predetermined spacing PX1 multiplied by a first compensation value. In some embodiments, the plurality of first predetermined spacings PX1 corresponding to each first line group 210 may be equal to or unequal to each other. Furthermore, in this embodiment, the first compensation value is a fixed value, and the value of the first compensation value is determined based on the estimated shrinkage or expansion of the flexible circuit board 10 in subsequent processes.

[0029] In some embodiments, the bonding line 200 further includes a plurality of first input pins 214. The first input pins 214 are located in the central region 110. The first input pins 214 are arranged adjacently along another long side 104 of the chip bonding region 100. A first predetermined input pitch PX6 is present between the bumps BP6 corresponding to the bonding of two adjacent first input pins 214. In other words, the first predetermined input pitch PX6 is the distance between preset positions of the two bumps BP6 corresponding to the bonding of two adjacent first input pins 214. Before bonding with the chip CP, the first input pitch PX6 between two adjacent first input pins 214 is not equal to the first predetermined input pitch PX6, and the first input pitch PX6 is equal to the first predetermined input pitch PX6 multiplied by a first compensation value. In some embodiments, the plurality of first predetermined input pitches PX6 corresponding to the plurality of first input pins 214 may be equal to or unequal to each other.

[0030] Please refer to Figure 3B Each second circuit group 220 includes a plurality of second pins 222 arranged adjacently along the long side 102 of the chip bonding region 100. A second predetermined spacing PX2 is provided between bumps BP2 corresponding to the bonding of two adjacent second pins 222. In other words, the second predetermined spacing PX2 is the spacing between preset positions of the two bumps BP2 corresponding to the bonding of two adjacent second pins 222. Before bonding with the chip CP, there is a second spacing X2 between two adjacent second pins 222. The second spacing X2 is not equal to the second predetermined spacing PX2, and the second spacing X2 is equal to the second predetermined spacing PX2 multiplied by a second compensation value. The second compensation value is not equal to the first compensation value. For example, the second compensation value is greater than the first compensation value. In some embodiments, the plurality of second predetermined spacings PX2 corresponding to each second circuit group 220 may be equal to or unequal to each other. Furthermore, in this embodiment, the second compensation value is a fixed value, and the value of the second compensation value is determined based on the estimated shrinkage or expansion of the flexible circuit substrate 10 in subsequent processes.

[0031] In some embodiments, the bonding line 200 further includes a plurality of second input pins 224. The second input pins 224 are located in the first variation region 120. The second input pins 224 are arranged adjacently along another long side 104 of the chip bonding region 100. A second predetermined input pitch PX7 is provided between the bumps BP7 corresponding to the bonding of two adjacent second input pins 224. In other words, the second predetermined input pitch PX7 is the distance between preset positions of the two bumps BP7 corresponding to the bonding of two adjacent second input pins 224. Before bonding with the chip CP, the second input pitch PX7 between two adjacent second input pins 224 is not equal to the second predetermined input pitch PX7, and the second input pitch PX7 is equal to the second predetermined input pitch PX7 multiplied by a second compensation value. In some embodiments, the plurality of second predetermined input pitches PX7 corresponding to the plurality of second input pins 224 may be equal to or unequal to each other.

[0032] Please refer to Figure 3CEach third circuit group 230 includes a plurality of third pins 232 arranged adjacently along the long side 102 of the chip bonding region 100. A third predetermined spacing PX3 is provided between bumps BP3 corresponding to the bonding of two adjacent third pins 232. In other words, the third predetermined spacing PX3 is the spacing between preset positions of the two bumps BP3 corresponding to the bonding of two adjacent third pins 232. Before bonding with the chip CP, there is a third spacing X3 between two adjacent third pins 232. The third spacing X3 is not equal to the third predetermined spacing PX3, and the third spacing X3 is equal to the third predetermined spacing PX3 multiplied by a third compensation value. The third compensation value may be equal to or not equal to the first compensation value. In some embodiments, the plurality of third predetermined spacings PX3 corresponding to each third circuit group 230 may be equal to or not equal to each other. Furthermore, in this embodiment, the third compensation value is a fixed value, and the value of the third compensation value is determined based on the estimated shrinkage or expansion of the flexible circuit board 10 in subsequent processes.

[0033] In some embodiments, the bonding line 200 further includes a plurality of third input pins 234. The third input pins 234 are located in the outer region 130. The third input pins 234 are arranged adjacently along another long side 104 of the chip bonding region 100. A third predetermined input pitch PX8 is present between the bumps BP8 corresponding to the bonding of two adjacent third input pins 234. In other words, the third predetermined input pitch PX8 is the distance between preset positions of the two bumps BP8 corresponding to the bonding of two adjacent third input pins 234. Before bonding with the chip CP, the third input pitch X8 between two adjacent third input pins 234 is not equal to the third predetermined input pitch PX8, and the third input pitch X8 is equal to the third predetermined input pitch PX8 multiplied by a third compensation value. In some embodiments, the plurality of third predetermined input pitches PX8 corresponding to the plurality of third input pins 234 may be equal to or unequal to each other.

[0034] In some embodiments, the bonding line 200 further includes a plurality of short-side pins 236 located in two outer regions 130. The short-side pins 236 are arranged adjacently along the short side 106 of the chip bonding region 100 to correspond to the bumps SBP of the chip CP.

[0035] Please refer to Figure 3DEach fourth line group 240 includes a plurality of fourth pins 242 arranged adjacently along the long side 102 of the chip bonding region 100. A fourth predetermined spacing PX4 exists between bumps BP4 used to correspondingly bond two adjacent fourth pins 242. In other words, the fourth predetermined spacing PX4 is the spacing between preset positions of the two bumps BP4 used to correspondingly bond two adjacent fourth pins 242. Before bonding with the chip CP, there is a fourth spacing X4 between two adjacent fourth pins 242. The fourth spacing X4 is not equal to the fourth predetermined spacing PX4, and the fourth spacing X4 is equal to the fourth predetermined spacing PX4 multiplied by a fourth compensation value. The fourth compensation value is not equal to the first compensation value, the second compensation value, and the third compensation value. For example, the second compensation value is greater than the fourth compensation value, and the fourth compensation value is greater than the first compensation value. In some embodiments, the plurality of fourth predetermined spacings PX4 corresponding to each fourth line group 240 may be equal to or unequal to each other. Furthermore, in this embodiment, the fourth compensation value is a fixed value, and the value of the fourth compensation value is determined based on the estimated shrinkage or expansion of the flexible circuit board 10 in subsequent processes.

[0036] In some embodiments, the bonding line 200 further includes a plurality of fourth input pins 244. The fourth input pins 244 are located in the second variation region 140. The fourth input pins 244 are arranged adjacently along another long side 104 of the chip bonding region 100. A fourth predetermined input pitch PX9 is present between the bumps BP9 corresponding to the bonding of two adjacent fourth input pins 244. In other words, the fourth predetermined input pitch PX9 is the distance between preset positions of the two bumps BP9 corresponding to the bonding of two adjacent fourth input pins 244. Before bonding with the chip CP, the fourth input pitch X9 between two adjacent fourth input pins 244 is not equal to the fourth predetermined input pitch PX9, and the fourth input pitch X9 is equal to the fourth predetermined input pitch PX9 multiplied by a fourth compensation value. In some embodiments, the plurality of fourth predetermined input pitches PX9 corresponding to the plurality of fourth input pins 244 may be equal to or unequal to each other.

[0037] Please refer to Figure 3EEach fifth line group 250 includes a plurality of fifth pins 252 arranged adjacently along the long side 102 of the chip bonding region 100. A fifth predetermined spacing PX5 is provided between bumps BP5 corresponding to the bonding of two adjacent fifth pins 252. In other words, the fifth predetermined spacing PX5 is the spacing between preset positions of the two bumps BP5 corresponding to the bonding of two adjacent fifth pins 252. Before bonding with the chip CP, there is a fifth spacing X5 between two adjacent fifth pins 252. The fifth spacing X5 is not equal to the fifth predetermined spacing PX5, and the fifth spacing X5 is equal to the fifth predetermined spacing PX5 multiplied by a fifth compensation value. The fifth compensation value is not equal to the second compensation value and the fourth compensation value. In some embodiments, the plurality of fifth predetermined spacings PX5 corresponding to each fifth line group 250 may be equal to or unequal to each other. Furthermore, in this embodiment, the fifth compensation value is a fixed value, and the value of the fifth compensation value is determined based on the estimated shrinkage or expansion of the flexible circuit board 10 in subsequent processes.

[0038] In some embodiments, the bonding line 200 further includes a plurality of fifth input pins 254. The fifth input pins 254 are located in a third variation region 150. The fifth input pins 254 are arranged adjacently along another long side 104 of the chip bonding region 100. A fifth predetermined input pitch PX10 is present between the bumps BP10 used to correspondingly bond two adjacent fifth input pins 254. In other words, the fifth predetermined input pitch PX10 is the distance between preset positions of the two bumps BP10 used to correspondingly bond two adjacent fifth input pins 254. Before bonding with the chip CP, the fifth input pitch X10 between two adjacent fifth input pins 254 is not equal to the fifth predetermined input pitch PX10, and the fifth input pitch X10 is equal to the fifth predetermined input pitch PX10 multiplied by a fifth compensation value. In some embodiments, the plurality of fifth predetermined input pitches PX10 corresponding to the plurality of fifth input pins 254 may be equal to or unequal to each other.

[0039] Before bonding with the chip CP, the pins of the bonding line 200 (including the first pin 212 to the fifth pin 252 and the first input pin 214 to the fifth input pin 254) are offset from the preset positions of the corresponding bumps (including bumps BP1 to BP10), and the degree of offset between the pins and the bumps varies in different regions. For example, the closer to the central region 110, the smaller the degree of offset between the pins and the bumps; while the closer to the outer region 130, the greater the degree of offset between the pins and the bumps.

[0040] For more details, please also refer to Figures 3A to 3EIn this embodiment, the first pin 212 includes a first outer row pin 212a, a first inner row pin 212b, and a first pad 212c. The first inner row pin 212b is farther from the long side 102 than the first outer row pin 212a. The first outer row pin 212a extends outward from within the chip bonding region 100 through the long side 102. The first inner row pin 212b extends within the chip bonding region 100 in a direction away from the long side 102 and connects to the first pad 212c. The second pin 222 includes a second outer row pin 222a, a second inner row pin 222b, and a second pad 222c. The second inner row pin 222b is farther from the long side 102 than the second outer row pin 222a. The second outer row pin 222a extends outward from within the chip bonding region 100 through the long side 102. The second inner row pin 222b extends within the chip bonding region 100 in a direction away from the long side 102 and connects to the second pad 222c. The third pin 232 includes a third outer row pin 232a, a third inner row pin 232b, and a third pad 232c. The third inner row pin 232b is farther from the long side 102 than the third outer row pin 232a. The third outer row pin 232a extends outward from within the chip bonding area 100 through the long side 102. The third inner row pin 232b extends within the chip bonding area 100 in a direction away from the long side 102 and connects to the third pad 232c. The fourth pin 242 includes a fourth outer row pin 242a, a fourth inner row pin 242b, and a fourth pad 242c. The fourth inner row pin 242b is farther from the long side 102 than the fourth outer row pin 242a. The fourth outer row pin 242a extends outward from within the chip bonding area 100 through the long side 102. The fourth inner row pin 242b extends within the chip bonding area 100 in a direction away from the long side 102 and connects to the fourth pad 242c. The fifth pin 252 includes a fifth outer row pin 252a, a fifth inner row pin 252b, and a fifth pad 252c. The fifth inner row pin 252b is farther from the long side 102 than the fifth outer row pin 252a. The fifth outer row pin 252a extends outward from within the chip bonding area 100 through the long side 102. The fifth inner row pin 252b extends within the chip bonding area 100 in a direction away from the long side 102 and connects to the fifth pad 252c.

[0041] Figure 4 yes Figure 1 A partial bottom view of the flexible circuit board. Please also refer to... Figures 3A to 3E and Figure 4 In some embodiments, the flexible circuit substrate 10 further includes a lower layer line DC and a plurality of conductive vias CH. The lower layer line DC is formed on the lower surface of the flexible dielectric substrate FS. The conductive vias CH penetrate the flexible dielectric substrate FS and electrically connect the bonding line 200 to the lower layer line DC.

[0042] Specifically, in some embodiments, the lower layer line DC includes a plurality of lower layer pins 312a and a plurality of lower layer pads 312b. The lower layer pins 312a are respectively connected to the lower layer pads 312b. The lower layer pads 312b respectively correspond to the first pads 212c to the fifth pads 252c of the bonding line 200. The conductive vias CH respectively connect the first pads 212c to the fifth pads 252c located on the upper surface of the flexible dielectric substrate FS and the lower layer pads 312b located on the lower surface of the flexible dielectric substrate FS.

[0043] Figure 5 This is a top view schematic diagram of the chip bonding area of ​​a flexible circuit board according to an embodiment of the present invention. It must be noted that... Figure 5 The embodiments follow Figures 1 to 4 The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0044] Please refer to Figure 5 In this embodiment, the chip bonding region 100 is divided into a central region 110, two first variation regions 120, two outer regions 130, and two second variation regions 140. The lengths (lengths S1 to S4) of each region on the long side 102 are determined based on the degree of pin offset that may occur due to the shrinkage or expansion of the flexible circuit substrate 10 in subsequent processes. The bonding circuit 200 includes a total of 38 circuit groups, with four first circuit groups 210 in the central region 110. Figure 5 The numbers are respectively marked as 18 to 21; each of the two first variation regions 120 contains fourteen second line groups 220. Figure 5 The numbers are respectively labeled as 4-17 and 22-35; each of the two second variation regions 140 contains two fourth line groups 240 ( Figure 5 The numbers are respectively labeled as 2-3 and 36-37; each of the two outer zones 130 has a third line group 230. Figure 5 They are labeled as number 1 and number 38 respectively.

[0045] Generally, after being heated, the heated area of ​​the flexible circuit board 10 will shrink towards the center or expand outward from the center. In other words, the expansion and contraction of the chip bonding area 100 will be based on the center. Therefore, in this embodiment, with the center line c of the chip bonding area 100 as the origin (marked as 0), the first line group 210 to the fourth line group 240 are respectively arranged with pins extending outward to the left and right sides to compensate for the pin spacing. Specifically, the first line group 210 (numbered 18-19), the second line group 220 (numbered 4-17), the fourth line group 240 (numbered 2-3), and the third line group 230 (numbered 1) located on the left side of the center line c are respectively provided with pins extending outward to the left side of the center line c with the first compensation value Z1, the second compensation value Z2, the fourth compensation value Z4, and the third compensation value Z3; the first line group 210 (numbered 20-21), the second line group 220 (numbered 22-35), the fourth line group 240 (numbered 36-37), and the third line group 230 (numbered 38) located on the right side of the center line c are respectively provided with pins extending outward to the right side of the center line c with the first compensation value Z1, the second compensation value Z2, the fourth compensation value Z4, and the third compensation value Z3. In this embodiment, for example, the length S1 of the central region 110 on the long side 102 of the chip bonding region 100 is approximately 3 mm and its corresponding first compensation value Z1 is 1.0009; the length S3 of the outer region 130 is approximately 1 mm and its corresponding third compensation value Z3 is 1.0009; the length S4 of the second variation region 140 is approximately 1.5 mm and its corresponding fourth compensation value Z4 is 1.00097; and the length S2 of the first variation region 120 is approximately (L-8) / 2 mm (where L is the length of the long side 102 of the chip bonding region 100) and its corresponding second compensation value Z2 is 1.001023. In other words, the second line group 220 located in the first variation area 120 will be given a larger pin pitch compensation than the first line group 210 located in the central area 110; the fourth line group 240 located in the second variation area 140 will be given a pin pitch compensation that is larger than that of the first line group 210 but smaller than that of the second line group 220; and the third line group 230 located in the outer area 130 will be given the same pin pitch compensation as the first line group 210.

[0046] Figure 6 This is a top view schematic diagram of a thin-film flip-chip packaging structure according to an embodiment of the present invention. Figure 7 yes Figure 6 A partial cross-sectional schematic diagram of the thin-film flip-chip packaging structure. Please refer to... Figure 6 and Figure 7 A thermo-pressing process is performed to deposit the chip CP onto the chip bonding region 100 of the flexible circuit board 10. For a description of the flexible circuit board 10 and the chip CP, please refer to [link to relevant documentation]. Figures 1 to 4 Please refer to this. Figure 7The flexible circuit substrate 10 may further include a first insulating layer SR1 and a second insulating layer SR2 located on the upper and lower surfaces of the flexible dielectric substrate FS, respectively. The first insulating layer SR1 covers a portion of the upper circuit UC and exposes the chip bonding region 100, while the second insulating layer SR2 covers a portion of the lower circuit DC. In some embodiments, the thin-film flip-chip package structure COF includes the flexible circuit substrate 10, a chip CP, and an underfill material UF. The bumps BP of the chip CP correspond to the bonding lines 200 of the flexible circuit substrate 10. The underfill material UF fills at least between the chip CP and the flexible circuit substrate 10 to protect the electrical contacts.

[0047] In the thermo-pressing process, the flexible circuit board 10 shrinks due to heat, changing the spacing between the pins of the flexible circuit board 10. Therefore, the multiple bumps BP1 to BP5 of the chip CP are respectively connected to the first pin 212 to the fifth pin 252 with a first predetermined spacing PX1 to a fifth predetermined spacing PX5, and the bumps BP6 to BP10 are respectively connected to the first input pin 214 to the fifth input pin 254 with a first predetermined input spacing PX6 to a fifth predetermined input spacing PX10.

[0048] In detail, after the hot-pressing process, the spacing X1' (not shown) between the first pins 212 of the flexible circuit board 10 is substantially equal to the first predetermined spacing PX1, the spacing X2' (not shown) between the second pins 222 is substantially equal to the second predetermined spacing PX2, and the spacing X3' (see reference) between the third pins 232 Figure 8 The spacing between the first input pins 214 and 224 is essentially equal to the third predetermined spacing PX3. The spacing between the fourth pins 242 and 252 is essentially equal to the fourth predetermined spacing PX4. The spacing between the fifth pins 252 and 252 is essentially equal to the fifth predetermined spacing PX5. Similarly, after the thermoforming process, the spacing between the first input pins 214 and 224 is essentially equal to the first predetermined input spacing PX6. The spacing between the second input pins 224 and 224 is essentially equal to the second predetermined input spacing PX7. The spacing between the third input pins 234 and 234 is essentially equal to the third predetermined spacing PX7. Figure 8 The spacing between the third predetermined input pitch PX8, the spacing between the fourth input pins 244 and 244 is X9' (not shown), which is essentially equal to the fourth predetermined input pitch PX9, and the spacing between the fifth input pins 252 and 252 is X10' (not shown), which is essentially equal to the fifth predetermined input pitch PX10.

[0049] For example, Figure 8 yes Figure 6 This is a magnified view of a portion of the outer region in a thin-film flip-chip package structure, where the chip CP is shown using perspective mapping. Please also refer to... Figure 3C and Figure 8 After the hot-pressing process, due to the thermal shrinkage of the flexible circuit board 10, the third pin 232 and the third input pin 234, which were originally offset due to the preset pin spacing compensation, are now separated. Figure 3C As shown, the bumps BP3 and BP8 of the chip CP are moved inward towards the center of the chip bonding area 100, so that the bumps BP3 and BP8 of the chip CP can respectively bond to the third pin 232 and the third input pin 234 with a third predetermined pitch PX3 and a third predetermined input pitch PX8. It should be noted that after the thermoforming process, the pins and bumps in other areas of the chip bonding area 100 will also be bonded in the same way. Figure 8 The shown is a ground alignment joint.

[0050] In summary, since the chip bonding area 100 of the flexible dielectric substrate FS will undergo significant expansion or contraction due to high temperature after the thermo-pressing process, the bonding lines 200 formed on the flexible dielectric substrate FS will have a preset compensation value to adjust the position and spacing of the pins before the thermo-pressing process, so that the pins after the thermo-pressing process can be aligned with the bump positions of the chip for bonding. For example, if it is estimated that the chip bonding area 100 will shrink after the thermo-pressing process, the pin spacing of the bonding lines 200 will be set to be greater than the bump spacing of the corresponding chip CP, so that the pins will move inward towards the center due to the shrinkage of the flexible dielectric substrate FS, thus aligning and bonding with the corresponding bumps. However, since the line layout density varies in different areas of the flexible circuit board 10, especially for flexible circuit boards 10 with upper-layer lines UC and lower-layer lines DC, different positions in the chip bonding area 100 may experience different degrees of expansion or contraction after the thermo-pressing process, resulting in unequal offsets of the pins of the bonding lines 200. If the pins of all bonding lines 200 are pre-adjusted with the same compensation value, the unequal offsets generated after the thermoforming process may cause some pins to be centered on the bonding bumps, while others may be outside the bump bonding range. Therefore, this embodiment divides the chip bonding area 100 into regions and pre-sets different compensation values ​​for the pin spacing of the bonding lines 200 in each region. As a result, the problem of pin misalignment due to unequal pin offsets caused by inconsistent expansion or contraction in different regions of the chip bonding area 100 is improved, and the yield of the internal pin bonding process can be effectively improved.

Claims

1. A flexible circuit board for supporting a chip having multiple bumps, comprising: A flexible dielectric substrate, wherein the upper surface of the flexible dielectric substrate has a chip bonding region, and the chip bonding region includes a central region, two first variant regions and two outer regions, wherein the central region, the two first variant regions and the two outer regions are arranged along a long side of the chip bonding region, the central region is located between the two first variant regions, and the two first variant regions and the central region are located between the two outer regions. as well as A bonding line, formed on the upper surface of the flexible dielectric substrate and located within the chip bonding region, for correspondingly bonding the bumps of the chip, the bonding line comprising: At least one first line group is located in the central area, each first line group includes a plurality of first pins arranged adjacent to each other along the long side, and the bumps corresponding to the engagement of two adjacent first pins have a first predetermined spacing, the first spacing between two adjacent first pins being equal to the first predetermined spacing multiplied by a first compensation value. Multiple second line groups are located in the two first variation regions, and each second line group includes multiple second pins arranged adjacently along the long side, for correspondingly engaging the bumps of two adjacent second pins with a second predetermined spacing, the second spacing between two adjacent second pins being equal to the second predetermined spacing multiplied by a second compensation value. as well as Multiple third line groups are located in the two outer regions, and each third line group includes multiple third pins arranged adjacently along the long side, for correspondingly engaging the bumps of two adjacent third pins with a third predetermined spacing, the third spacing between two adjacent third pins being equal to the third predetermined spacing multiplied by a third compensation value, wherein the second compensation value is not equal to the first compensation value.

2. The flexible circuit board according to claim 1, wherein the third compensation value is equal to or not equal to the first compensation value.

3. The flexible circuit board according to claim 1, wherein the chip bonding area further includes two second variation areas located between the two outer areas and the two first variation areas, and the bonding circuit further includes a plurality of fourth circuit groups located between the two second variation areas, and each of the fourth circuit groups includes a plurality of fourth pins arranged adjacently along the long side, for correspondingly bonding the bumps of two adjacent fourth pins having a fourth predetermined spacing, the fourth spacing between two adjacent fourth pins being equal to the fourth predetermined spacing multiplied by a fourth compensation value, wherein the fourth compensation value is not equal to the first compensation value, the second compensation value and the third compensation value.

4. The flexible circuit board according to claim 3, wherein the chip bonding area further includes two third variation areas located between the two first variation areas and the two second variation areas, and the bonding circuit further includes a plurality of fifth line groups located between the two third variation areas, and each fifth line group includes a plurality of fifth pins arranged adjacently along the long side, and the bumps corresponding to the bonding of two adjacent fifth pins have a fifth predetermined spacing, wherein the fifth spacing between two adjacent fifth pins is equal to the fifth predetermined spacing multiplied by a fifth compensation value, wherein the fifth compensation value is not equal to the second compensation value and the fourth compensation value.

5. The flexible circuit board according to claim 3, wherein the second compensation value is greater than the fourth compensation value, and the fourth compensation value is greater than the first compensation value.

6. The flexible circuit board according to claim 1, further comprising: The lower layer circuitry is formed on the lower surface of the flexible dielectric substrate; as well as Multiple conductive vias penetrate the flexible dielectric substrate and electrically connect the bonding lines to the underlying circuitry.

7. The flexible circuit board according to claim 1, wherein the first pin includes a plurality of first outer row pins, a plurality of first inner row pins and a plurality of first pads, the second pin includes a plurality of second outer row pins, a plurality of second inner row pins and a plurality of second pads, the third pin includes a plurality of third outer row pins, a plurality of third inner row pins and a plurality of third pads, the first inner row pins, the second inner row pins and the third inner row pins are respectively farther away from the long side than the first outer row pins, the second outer row pins and the third outer row pins, the first outer row pins, the second outer row pins and the third outer row pins extend outward from the chip bonding area through the long side, and the first inner row pins, the second inner row pins and the third inner row pins extend in the chip bonding area in a direction away from the long side and are respectively connected to the first pads, the second pads and the third pads.

8. The flexible circuit board according to claim 7, further comprising: The lower layer circuit is formed on the lower surface of the flexible dielectric substrate. The lower layer circuit includes a plurality of lower layer pins and a plurality of lower layer pads. The lower layer pins are respectively connected to the lower layer pads, and the lower layer pads correspond to the first pad, the second pad and the third pad respectively. as well as Multiple conductive vias penetrate the flexible dielectric substrate and respectively connect the first pad, the second pad, and the third pad located on the upper surface to the lower pad located on the lower surface.

9. The flexible circuit board according to claim 1, wherein the plurality of first predetermined spacings corresponding to each first circuit group are equal or unequal to each other, the plurality of second predetermined spacings corresponding to each second circuit group are equal or unequal to each other, and the plurality of third predetermined spacings corresponding to each third circuit group are equal or unequal to each other.

10. The flexible circuit board according to claim 1, wherein the bonding circuitry further comprises: Multiple first input pins are located in the central area. The first input pins are arranged adjacent to each other along the other long side of the chip bonding area relative to the long side. The bumps that correspondingly bond two adjacent first input pins have a first predetermined input spacing. The first input spacing between two adjacent first input pins is equal to the first predetermined input spacing multiplied by the first compensation value. A plurality of second input pins are respectively located in the two first variation regions. The second input pins are arranged adjacently along the other long side, and the bumps corresponding to the engagement of two adjacent second input pins have a second predetermined input spacing. The second input spacing between two adjacent second input pins is equal to the second predetermined input spacing multiplied by the second compensation value. Multiple third input pins are located in the two outer regions respectively. The third input pins are arranged adjacently along the other long side to correspond to the bumps of two adjacent third input pins having a third predetermined input spacing. The third input spacing between two adjacent third input pins is equal to the third predetermined input spacing multiplied by the third compensation value.

11. A method for manufacturing a thin-film flip-chip packaging structure, comprising: Provides a flexible circuit board as described in any one of claims 1 to 10; as well as A thermo-pressing process is performed to place the chip in the chip bonding area, wherein the flexible circuit substrate shrinks due to heat, so that the bumps of the chip are respectively bonded to the first pin, the second pin and the third pin of the flexible circuit substrate at the first predetermined spacing, the second predetermined spacing and the third predetermined spacing.

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