Method of manufacturing a semiconductor structure and semiconductor structure
By forming wavy trenches within the substrate and then forming transistors within the substrate, the problem of insufficient 3D DRAM performance is solved, avoiding the use of IGZO and Superlattice technologies, and achieving higher performance and lower defect rate.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-09-21
- Publication Date
- 2026-06-05
AI Technical Summary
The performance of existing 3D DRAM has not yet reached its optimal level, mainly due to the difficulty in controlling the uniformity of IGZO materials and the numerous interface defects caused by Superlattice technology.
By forming a first trench and a second trench with wavy sidewalls in the substrate, transistors are formed in the substrate using Bosch technology, avoiding the use of IGZO and Superlattice technology, and forming word lines and source/drain layers that protrude from the trench.
It reduces defects in semiconductor structures, improves performance, simplifies manufacturing processes, and lowers costs.
Smart Images
Figure CN117794236B_ABST
Abstract
Description
Technical Field
[0001] This disclosure pertains to the field of semiconductors, specifically relating to a method for manufacturing a semiconductor structure and the semiconductor structure itself. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that primarily works by using the amount of charge stored in a capacitor to represent whether a stored binary bit is 1 or 0.
[0003] 3DDRAM is a structure that stacks multiple layers of memory cells. It has a high degree of integration and a larger capacity per unit area, which helps to reduce the cost per unit area. However, the performance of 3DDRAM still needs to be improved. Summary of the Invention
[0004] This disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure, which at least helps to improve the performance of the semiconductor structure.
[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for manufacturing a semiconductor structure, wherein the method includes: providing a substrate, forming a first trench and a second trench in the substrate, both having a depth direction in a first direction; the first trench includes a plurality of first sub-trenches arranged in the first direction, the second trench includes a plurality of second sub-trenches arranged in the first direction, and the sidewalls of the first sub-trench and the second sub-trench are both convex; forming a word line protruding away from the first trench at the junction of adjacent first sub-trenches; forming a first source / drain layer on the sidewall of the first sub-trench; forming a second source / drain layer protruding away from the second trench at the junction of adjacent second sub-trenches; the second source / drain layer and the word line are both located between the first trench and the second trench, and the second source / drain layer and the word line are disposed opposite to each other.
[0006] According to some embodiments of this disclosure, another aspect of this disclosure provides a semiconductor structure, the semiconductor structure comprising: a substrate having a first trench and a second trench therein, both having a depth direction in a first direction; the first trench including a plurality of first sub-trenches arranged in the first direction, the second trench including a plurality of second sub-trenches arranged in the first direction, and the sidewalls of the first sub-trench and the second sub-trench both being convex; a word line protruding away from the first trench at the junction of adjacent first sub-trenches; a first source / drain layer on the sidewall of the first sub-trench; a second source / drain layer protruding away from the second trench at the junction of adjacent second sub-trenches; the second source / drain layer and the word line are both located between the first trench and the second trench, and the second source / drain layer and the word line are disposed opposite to each other.
[0007] The technical solutions provided in this disclosure have at least the following advantages:
[0008] A first trench and a second trench are formed within a substrate. The first trench includes multiple first sub-trenches, and the second trench includes multiple second sub-trenches. The sidewalls of both the first and second sub-trenches are convex. A word line convex away from the first trench is formed at the boundary of adjacent first sub-trenches. A first source / drain layer is formed on the sidewall of the first sub-trench. A second source / drain layer convex away from the second trench is formed at the boundary of adjacent second sub-trenches. In other words, transistors are formed within the substrate based on the wavy sidewalls of the first and second trenches, thus avoiding the use of IGZO and Superlattice technologies to form transistors. This helps reduce defects in the semiconductor structure and improves its performance. Attached Figure Description
[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0010] Figure 1(a), Figures 1(b) to 27(a) Figure 27(b) shows a schematic diagram of the structure corresponding to each step in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;
[0011] Figure 28 A partially enlarged view of the semiconductor structure shown in Figure 27(a) is shown. Detailed Implementation
[0012] As the background technology shows, the performance of 3D DRAM still needs improvement. Analysis reveals that the main reasons are as follows: 3D DRAM mainly includes two types. The first type is based on indium gallium zinc oxide (IGZO) material, forming a 3D DRAM with a vertical annular channel device structure (CAA). However, the uniformity of IGZO material is difficult to control, resulting in numerous defects. The second type is based on superlattice technology, forming a structure composed of alternating layers of different materials, namely alternating layers of silicon and germanium-silicon. However, depositing multiple layers of silicon and germanium-silicon causes numerous interface defects.
[0013] This disclosure provides a method for manufacturing a semiconductor structure, including: forming a first trench and a second trench in a substrate, wherein the first trench includes a plurality of first sub-trenches, and the second trench includes a plurality of second sub-trenches, and the sidewalls of both the first and second sub-trenches are convex. A word line convex away from the first trench is formed at the boundary of adjacent first sub-trenches; a first source / drain layer is formed on the sidewall of the first sub-trench; and a second source / drain layer convex away from the second trench is formed at the boundary of adjacent second sub-trenches. That is, a transistor is formed in the substrate based on the wavy sidewalls of the first and second trenches, thereby avoiding the use of IGZO and Superlattice technologies to form transistors, reducing defects in the semiconductor structure, and improving the performance of the semiconductor structure.
[0014] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0015] As shown in Figure 1(a), Figures 1(b) to 27(a) As shown in Figure 27(b), another embodiment of this disclosure provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, for ease of description and to clearly illustrate the steps of the semiconductor structure fabrication method, Figure 1(a), Figures 1(b) to 27(a) Figures 27 and 27(b) are schematic diagrams of partial structures of semiconductor structures.
[0016] refer to Figures 1(a) to 1(b)Figure 1(b) is a top view of the semiconductor structure shown in Figure 1(a). A substrate 1 is provided, and a first trench 2 is formed in the substrate 1. The depth direction of the first trench 2 is a first direction X; the first trench 2 includes a plurality of first sub-trenches 20 arranged in the first direction X, and the sidewalls of the first sub-trenches 20 are all convex. That is, the sidewalls of the first trench 2 are wavy.
[0017] Specifically, the first trench 2 is formed using a Bosch process. The Bosch process involves alternating etching and passivation steps. First, isotropic etching is used to form a first sub-trench 20; a passivation layer is formed on the inner wall of the first sub-trench 20; the passivation layer at the bottom of the first sub-trench 20 is removed; and isotropic etching is used to form another first sub-trench 20. This etching and passivation process is repeated to form multiple first sub-trenches 20 to constitute the first trench 2.
[0018] In some embodiments, the substrate 1 can be made of monocrystalline silicon. Monocrystalline silicon offers material stability, and its defects are easier to control compared to IGZO layers and alternating layers of silicon and germanium-silicon, thus helping to ensure the performance of the semiconductor structure. Furthermore, based on monocrystalline silicon, the etching gas used in the Bosch process can be sulfur hexafluoride, and the passivation gas can be octafluorocyclobutane.
[0019] Furthermore, the substrate 1 may contain doped ions, and the type of doped ions in the substrate 1 may be opposite to the type of doped ions in the subsequently formed first source / drain layer 61 and second source / drain layer 62 (refer to FIG. 27(a)).
[0020] In some embodiments, the depth h of the first sub-trench 20 in the first direction X is 1µm to 2µm. This depth h facilitates the subsequent formation of a first source / drain layer 61 of suitable size (see reference). Figure 24 The first sub-trench 20 protrudes approximately tens of nanometers from the substrate 1, facilitating the subsequent formation of the hole 22 (see reference). Figure 5 ).
[0021] refer to Figures 2(a) to 2(b) Figure 2(b) is a top view of the semiconductor structure shown in Figure 2(a). A first isolation film 21 is formed on the sidewall of the first trench 2. The first isolation film 21 located at the junction of adjacent first sub-trench 20 protrudes into the first sub-trench 20. That is, since the sidewall of the first trench 2 has a wavy shape, the first isolation film 21 formed on the sidewall of the first trench 2 also has a wavy shape.
[0022] For example, an isotropic deposition process or a thermal oxidation method is used to form a silicon oxide film as the first isolation film 21. In the second direction Y, the thickness of the first isolation film 21 can be 20 nm to 50 nm. It should be noted that when the thickness of the first isolation film 21 is within the above range, it facilitates the retention of the first isolation film 21 located on the sidewall of the first sub-trench 20 when removing the first isolation film 21 at the junction of adjacent first sub-trench 20s. That is, if the thickness of the first isolation film 21 is too large, it is difficult to expose the substrate 1 located at the junction of adjacent first sub-trench 20s; if the thickness of the first isolation film 21 is too small, it may be possible to remove all of the first isolation films 21 at the same time.
[0023] In addition, a portion of the first isolation film 21 may also cover the upper surface of the substrate 1, and this portion of the first isolation film 21 will be removed subsequently.
[0024] refer to Figures 3(a) to 3(b) Figure 3(b) is a top view of the semiconductor structure shown in Figure 3(a). Using the substrate 1 itself as a mask, a portion of the first isolation film 21 located at the junction of adjacent first sub-trenches 20 is etched along the first direction X. That is, an anisotropic etching process is used to cut the protruding first isolation film 21 at the junction of adjacent first sub-trenches 20 flat, thereby making the first isolation film 21 at this location thinner.
[0025] refer to Figure 4 An isotropic etching process is used to remove the remaining first isolation film 21 located at the junction of adjacent first sub-trench 20, so as to expose the substrate 1 located at the junction of adjacent first sub-trench 20. The top view of the semiconductor structure does not change in this step, and can be referred to Figure 3(b).
[0026] In other words, after anisotropic etching, the first isolation film 21 at the junction of adjacent first sub-trench 20 is thinner than the first isolation film 21 on the sidewall of the first sub-trench 20; in the isotropic etching process, the first isolation film 21 at the junction of adjacent first sub-trench 20 will be removed more quickly, thereby exposing a certain width of substrate 1.
[0027] In the first direction X, the width L of the exposed substrate 1 at the junction of adjacent first sub-trench 20 is 20 nm to 50 nm. It should be noted that when the width of the exposed substrate 1 is within the above range, it is beneficial to form holes 22 of appropriate size in the future, that is, to avoid the inner diameter of the holes 22 being too small or the interconnection of adjacent holes 22.
[0028] At this point, based on Figures 3(a) to 3(b) as well as Figure 4 The steps shown can remove the first isolation film 21 located at the junction of adjacent first sub-trench 20 to expose the substrate 1 located at the junction of adjacent first sub-trench 20.
[0029] refer to Figure 5 The substrate 1 exposed by the first insulating film 21 is etched to form holes 22. The top view of the semiconductor structure remains unchanged in this step, as shown in Figure 3(b).
[0030] For example, isotropic etching is performed on the exposed substrate 1 to further open the substrate 1 and form a hole 22. The depth of the hole 22 in the second direction Y can be 100 nm to 200 nm. It should be noted that if the depth of the hole 22 is too small, it may be difficult to provide sufficient filling space for the word line 32, thereby increasing the resistance of the word line 32; if the depth of the hole 22 is too large, defects such as pores may be generated in the word line 32. When the depth of the hole 22 is within the above range, it facilitates subsequent filling of the word line 32, ensures that the word line 32 has appropriate dimensions, reduces defects within the word line 32, and thus improves the performance of the semiconductor structure.
[0031] At this point, based on Figures 3(a) to 3(b) , Figure 4 as well as Figure 5 The steps shown can form a hole 22 protruding away from the first trench 2 at the junction of adjacent first sub-trenches 20. That is, the first isolation membrane 21 can serve as a mask layer for forming the hole 22, and is used to control the position and size of the hole 22.
[0032] refer to Figure 6 A gate dielectric layer 31 is formed on the inner wall of the hole 22. The top view of the semiconductor structure remains unchanged during this step, as shown in Figure 3(b). For example, a thermal oxidation process is used to form silicon oxide on the inner wall of the hole 22 as the gate dielectric layer 31 of the transistor. In other embodiments, an atomic layer deposition process can be used to deposit a high dielectric constant material on the inner wall of the hole 22 as the gate dielectric layer 31.
[0033] refer to Figures 7(a) to 7(b) Figure 7(b) is a top view of the semiconductor structure shown in Figure 7(a), in which initial word lines 321 are formed on the sidewalls of the first trench 2 and within the holes 22. For example, tungsten and titanium nitride are deposited as the initial word lines 321 using an isotropic deposition process.
[0034] refer to Figures 8(a) to 8(b) Figure 8(b) is a top view of the semiconductor structure shown in Figure 8(a). An isotropic etching process is used to remove a portion of the initial word line 321 located on the sidewalls of the first trench 2 and within the hole 22. The remaining initial word line 321 within the hole 22 serves as the word line 32. The word line 32 serves as the gate of the transistor, and the gate dielectric layer 31 also covers the word line 32. Specifically, the gate dielectric layer 31 covers the side of the word line 32 away from the interior of the first trench 2.
[0035] At this point, based on Figures 7(a) to 7(b) as well as Figures 8(a) to 8(b) The steps shown can form a character line 32 protruding away from the first groove 2 at the junction of adjacent first sub-grooves 20, and the character line 32 extends along the third direction Z.
[0036] refer to Figures 9(a) to 9(b) Figure 9(b) is a top view of the semiconductor structure shown in Figure 9(a), in which an initial insulating layer 331 is formed within the hole 22 and on the sidewalls of the first sub-trench 20. For example, titanium nitride is deposited using an isotropic deposition process as the initial insulating layer 331 to seal the hole 22. The material of the initial insulating layer 331 can be different from the material of the first isolation film 21, thereby avoiding the removal of the insulating layer 331 during the subsequent removal of the first isolation film 21.
[0037] refer to Figures 10(a) to 10(b) Figure 10(b) is a top view of the semiconductor structure shown in Figure 10(a). Using the substrate 1 itself as a mask, the initial insulating layer 331 located on the sidewall of the first sub-trench 20 is etched along the first direction X. The remaining initial insulating layer 331 serves as the insulating layer 33. The sidewall of the insulating layer 33 is flush with the opening of the hole 22. The gate dielectric layer 31 also covers the surface of the insulating layer 33.
[0038] At this point, based on Figures 9(a) to 9(b) as well as Figures 10(a) to 10(b) The steps shown allow for the formation of an insulating layer 33 within the hole 22, located on the side of the word line 32 facing the first trench 2. It should be noted that the purpose of forming the insulating layer 33 is primarily twofold: first, to isolate the word line 32 from the subsequently formed capacitor plate 72 (refer to Figure 26(a)) to prevent short circuits; second, the insulating layer 33 can be separated from the subsequently formed first source / drain layer 61 (refer to Figure 26(a)) in the first direction X. Figure 24 ( ) Directly opposite, that is, reduce the direct opposite area between word line 32 and the first source / drain layer 61, thereby reducing the risk of leakage current.
[0039] refer to Figures 11(a) to 11(b) Figure 11(b) is a top view of the semiconductor structure shown in Figure 11(a). After forming the word line 32, the structure further includes filling the first trench 2 with a sacrificial layer 22. The sacrificial layer 22 can protect the first trench 2 from contamination in subsequent steps such as forming the second trench 5, the second source / drain layer 62, the metal silicide layer 63, and the bit line 64, thereby ensuring the performance of the semiconductor structure.
[0040] For example, silicon oxide is deposited in the first trench 2 as a sacrificial layer 22. After silicon oxide deposition, a planarization process can be performed to smooth the upper surface of the substrate 1 and the upper surface of the sacrificial layer 22. In some embodiments, the material of the sacrificial layer 22 can be the same as the material of the first isolation film 21, so that the sacrificial layer 22 and the first isolation film 21 can be removed using the same process step, thereby simplifying the manufacturing process.
[0041] refer to Figure 12 , Figure 12 In a top view, a portion of the substrate 1 and a portion of the sacrificial layer 22 are removed to form a plurality of spaced isolation trenches 4, which extend in the second direction Y and are arranged in the third direction Z.
[0042] For example, a mask is formed on the substrate 1 and the sacrificial layer 22, and the substrate 1 and the sacrificial layer 22 are etched using the mask. It should be noted that the word lines 32 cannot be cut during the etching process.
[0043] refer to Figure 13 , Figure 13 In a top view, multiple spaced isolation structures 41 are formed; the multiple isolation structures 41 extend along the second direction Y and are arranged in the third direction Z. The isolation structures 41 cover multiple word lines 32, that is, the isolation structures 41 do not truncate the word lines 32. In addition, the isolation structures 41 also divide the sacrificial layer 22 into multiple parts.
[0044] For example, silicon nitride is filled into the isolation trench 4 to serve as an isolation structure 41. Subsequently, a planarization process is performed to grind the substrate 1, the sacrificial layer 22, and the upper surface of the isolation structure 41. In some embodiments, the material of the isolation structure 41 may be different from the material of the sacrificial layer 22, thereby avoiding the consumption of the isolation structure 41 during the subsequent removal of the sacrificial layer 22.
[0045] refer to Figures 14(a) to 14(b) Figure 14(b) is a top view of the semiconductor structure shown in Figure 14(a). After the isolation structure 41 is formed, a second trench 5 is formed in the substrate 1. The depth direction of the second trench 5 is the first direction X. The second trench 5 includes a plurality of second sub-trenches 50 arranged in the first direction X. The sidewalls of the second sub-trenches 50 are convex. That is, the second trench 5 also has wavy sidewalls. The isolation structure 41 also spans the first trench 2 and the second trench 5.
[0046] Specifically, the second groove 5 is formed using Bosch technology. For details on the specific formation process of the second groove 5, please refer to the detailed description of the first groove 2.
[0047] It should be noted that the materials of the isolation structure 41 and the substrate 1 may be different, so the isolation structure 41 may not be removed during the etching of the substrate 1 to form the second trench 5.
[0048] In other embodiments, a second trench 5 extending in the third direction Z can be formed first, followed by the formation of an isolation structure 41 extending in the second direction Y to divide the second trench 5 into multiple sections. For example, a first trench 2 and a second trench 5 can be formed in the same process step; then, sacrificial material is filled into the second trench 5; subsequently, a first isolation membrane 21, a letter line 32, an insulating layer 33, and other structures are formed in the first trench 2; and then, the isolation structure 41 is formed to span the first trench 2 and the second trench 5. Since the first trench 2 and the second trench 5 can be integrated in the same process step, the manufacturing process is simplified.
[0049] refer to Figures 15(a) to 15(b) Figure 15(b) is a top view of the semiconductor structure shown in Figure 15(a). An initial second isolation film 511 is formed on the sidewall of the second trench 5. The second isolation film 51 located at the junction of adjacent second sub-trench 50 protrudes towards the interior of the second sub-trench 50. That is, since the sidewall of the second trench 5 has a wavy shape, the initial second isolation film 511 formed on the sidewall of the second trench 5 also has a wavy shape.
[0050] For example, an isotropic deposition process is used to form a silicon nitride film as an initial second isolation film 511.
[0051] refer to Figures 16(a) to 16(b) Figure 16(b) is a top view of the semiconductor structure shown in Figure 16(a). Using the substrate 1 itself as a mask, a portion of the initial second isolation film 511 located at the junction of adjacent second sub-trenches 50 is etched along the first direction X. That is, an anisotropic etching process is used to cut the protruding second isolation film 51 at the junction of adjacent second sub-trenches 50 flat, thereby making the second isolation film 51 at this location thinner.
[0052] refer to Figure 17 An isotropic etching process is used to remove the remaining initial second isolation film 511 located at the junction of adjacent second sub-trenches 50, thereby exposing the substrate 1 located at the junction of adjacent second sub-trenches 50. The remaining initial second isolation film 511 serves as the second isolation film 51. In other words, in the isotropic etching process, the thinner initial second isolation film 511 at the junction of adjacent second sub-trenches 50 is removed more quickly, thus exposing a certain width of the substrate 1. The top view of the semiconductor structure remains unchanged in this step, as shown in Figure 16(b).
[0053] At this point, based on Figures 16(a) to 16(b) as well as Figure 17 The steps shown can remove the initial second isolation film 511 located at the junction of adjacent second sub-trench 50 to expose the substrate 1 located at the junction of adjacent second sub-trench 50.
[0054] refer to Figure 18The substrate 1 exposed by the second isolation film 51 is doped to form a second source / drain layer 62. For example, n-type dopant ions are implanted into the substrate 1 using plasma doping to form the second source / drain layer 62. The top view of the semiconductor structure remains unchanged in this step, as shown in Figure 16(b).
[0055] The second source / drain layer 62 and the word line 32 are both located between the first trench 2 and the second trench 5, and the second source / drain layer 62 is disposed opposite to the word line 32. The second source / drain layer 62 is also in contact with the gate dielectric layer 31.
[0056] Furthermore, the second source / drain layers 62 arranged adjacent to each other in the third direction Z are separated by the isolation structure 41 to avoid mutual interference. The second source / drain layers 62 arranged in the first direction X are separated by the second isolation membrane 51 to avoid interconnection.
[0057] At this point, based on Figures 16(a) to 16(b) , Figure 17 as well as Figure 18 The steps shown allow for the formation of a second source / drain layer 62 protruding away from the second trench 5 at the junction of adjacent second sub-trenches 50. In other words, the second isolation membrane 51 can serve as a mask for forming the second source / drain layer 62, thereby preventing adjacent second source / drain layers 62 from interconnecting in the first direction X.
[0058] refer to Figure 19 A portion of the second source / drain layer 62 near the interior of the second trench 5 is removed to form a contact port 52. For example, isotropic etching is used to remove the portion of the second source / drain layer 62 exposed by the second isolation film 51 to increase the exposed area of the second source / drain layer 62. The top view of the semiconductor structure remains unchanged during this step, as shown in Figure 16(b).
[0059] refer to Figure 20 A metal silicide layer 63 is formed in the contact port 52. That is, a metal silicide layer 63 is formed in contact with the second source / drain layer 62, and the metal silicide layer 63 is located on the side of the second source / drain layer 62 closer to the interior of the second trench 5. For example, a metal layer is first deposited in the contact port 52, and the metal layer is annealed to cause the metal layer to react with the second source / drain layer 62 to generate the metal silicide layer 63.
[0060] The metal silicide layer 63 can reduce the contact resistance between the subsequently formed bit line 64 and the second source / drain layer 62, thereby improving the electrical performance of the semiconductor structure. In some embodiments, the metal silicide layer 63 may not be formed.
[0061] It should be noted that the contact port 52 can increase the contact area between the metal silicide layer 63 and the second source / drain layer 62, thereby reducing the contact resistance. In some embodiments, the metal silicide layer 63 may only adhere to the inner wall of the contact port 52 without completely filling it; that is, the subsequently formed bit line 64 may also fill the contact port 52, which helps to increase the filling space of the bit line 64 and increase the contact area between the bit line 64 and the metal silicide layer 63. In other embodiments, the metal silicide layer 63 may also completely fill the contact port 52.
[0062] refer to Figures 21(a) to 21(b) Multiple bit lines 64 are formed to fill the second trench 5. The bit lines 64 extend along the first direction X and are electrically connected to the second source / drain layers 62, that is, each bit line 64 is electrically connected to multiple second source / drain layers 62 in the first direction X. Two adjacent bit lines 64 arranged in the third direction Z are separated by the isolation structure 41. The bit lines 64 are also in contact with the metal silicide layer 63.
[0063] For example, metals such as tungsten and titanium nitride are deposited in the second trench 5 to serve as bit lines 64. After the metals are deposited, they are polished and ground flat.
[0064] refer to Figures 22(a) to 22(b) The bit line 64 is etched back and a third isolation film 52 is formed to seal the top of the second trench 5. The third isolation film 52 can protect the bit line 64 from contamination and oxidation.
[0065] refer to Figures 23(a) to 23(b) After forming bit line 64, sacrificial layer 22 is removed. In addition, the first isolation membrane 21 located on the sidewall of the first sub-trench 20 is also removed, thereby exposing the sidewall of the first sub-trench 20.
[0066] For example, a wet etching process is used to remove the sacrificial layer 22 and the first isolation film 21.
[0067] refer to Figure 24 After removing the sacrificial layer 22, a first source / drain layer 61 is formed on the sidewall of the first sub-trench 20. The first source / drain layer 61 is also in contact with the gate dielectric layer 31. Specifically, the sidewall of the first sub-trench 20 is doped to form the first source / drain layer 61. For example, n-type dopant ions are implanted into the substrate 1 exposed in the first trench 2 using a plasma doping process.
[0068] It should be noted that the first source / drain layer 61 has a shallow doping depth in the second direction Y, which allows the first source / drain layer 61 and the word line 32 to be staggered in the first direction X, avoiding the formation of an overlap region between them, or reducing the overlap area between them, thereby avoiding leakage between the first source / drain layer 61 and the word line 32.
[0069] In addition, the first source-drain layers 61 arranged adjacent to each other on the third direction Z are separated by the isolation structure 41 to avoid mutual interference between adjacent first source-drain layers 61.
[0070] refer to Figures 25(a) to 25(b) An initial dielectric layer 711 is formed on the sidewalls of the first trench 2 and the upper surface of the substrate 1, and the initial dielectric layer 711 also covers the first source / drain layer 61. For example, a high dielectric constant material is deposited as the initial dielectric layer 711. A high dielectric constant material is beneficial for improving capacitance.
[0071] refer to Figures 26(a) to 26(b) Remove the initial dielectric layer 711 located on the upper surface of the substrate 1, and use the initial dielectric layer 711 on the sidewall of the first trench 2 as the dielectric layer 71.
[0072] Continue to refer to Figures 26(a) to 26(b) Multiple capacitor plates 72 are formed to fill the first trench 2, and the capacitor plates 72 are also covered by a dielectric layer 71; the multiple capacitor plates 72 are arranged in the third direction Z and extend in the first direction X. The capacitor plates 72 arranged adjacently in the third direction Z are separated by an isolation structure 41.
[0073] In other words, the first source / drain layer 61, the capacitor plate 72, and the dielectric layer 71 constitute a capacitor, which is connected to the transistor formed by the first source / drain layer 61, the second source / drain layer 62, and the word line 32. It is understandable that since the first source / drain layer 61 also serves as a capacitor plate, it is advantageous to eliminate the need for an electrical connection structure between the first source / drain layer 61 and the capacitor, thus simplifying the manufacturing process.
[0074] For example, the first trench 2 is filled with metals such as tungsten and titanium nitride as capacitor plates 72, and then the capacitor plates 72 and the upper surface of the substrate 1 are polished.
[0075] refer to Figures 27(a) to 27(b) The capacitor plate 72 is etched back, and a fourth isolation film 23 is deposited to seal the top of the first trench 2. The fourth isolation film 23 can protect the capacitor plate 72. For example, the material of the fourth isolation film 23 can be silicon nitride.
[0076] At this point, based on Figures 1(a) to 27(b)The steps shown can complete the front-end manufacturing of 3D DRAM. It is worth noting that performing the process steps in the aforementioned order helps reduce contamination of the semiconductor structure and reduces impurity residue. In other embodiments, the order of the process steps can also be adjusted. For example, the second trench 5 can be formed first, and the second source / drain layer 62, metal silicide layer 63, and bit line 64 can be formed based on the wavy shape of the second trench 5; then, the first trench 2 can be formed, and the word line 32, dielectric layer 71, and capacitor plate 72 can be formed based on the wavy shape of the first trench 2. Alternatively, the first trench 2, word line 32, first source / drain layer 61, dielectric layer 71, and capacitor plate 72 can be formed first, followed by the formation of the second trench 5, second source / drain layer 62, and bit line 64.
[0077] In summary, the embodiments disclosed herein employ Bosch processes to form a first trench 2 and a second trench 5 with wavy shapes. Word lines 32 and a first source / drain layer 61 are formed based on the wavy first trench 2, and a second source / drain layer 62 is formed based on the wavy second trench 5. Therefore, transistors can be formed within the silicon substrate 1, avoiding the use of IGZO and Superlattice technologies, thereby reducing defects within the semiconductor structure and improving its performance.
[0078] like Figures 27(a) to 27(b) , Figure 28 As shown, one embodiment of this disclosure provides a semiconductor structure. This semiconductor structure can be manufactured using the manufacturing method provided in the foregoing embodiments. Detailed description of this semiconductor structure can be found in the foregoing embodiments, and will not be repeated here.
[0079] The semiconductor structure includes: a substrate 1, which has a first trench 2 and a second trench 5, both of which have a depth direction of a first direction X; the first trench 2 includes a plurality of first sub-trenches 20 arranged in the first direction X, and the second trench 5 includes a plurality of second sub-trenches 50 arranged in the first direction X, and the sidewalls of the first sub-trenches 20 and the second sub-trenches 50 are both convex; a word line 32 protruding away from the first trench 2 is provided at the junction of adjacent first sub-trenches 20; a first source / drain layer 61 is provided on the sidewall of the first sub-trench 20; a second source / drain layer 62 protruding away from the second trench 5 is provided at the junction of adjacent second sub-trenches 50; the second source / drain layer 62 and the word line 32 are both located between the first trench 2 and the second trench 5, and the second source / drain layer 62 and the word line 32 are disposed opposite to each other.
[0080] The semiconductor structure will be explained in detail below.
[0081] First, it should be noted that the semiconductor structure has a first direction X, a second direction Y, and a third direction Z, and these three directions are not the same. For example, the first direction X is perpendicular to the second direction Y and the third direction Z, and the second direction Y is perpendicular to the third direction Z. In some embodiments, the semiconductor structure can be a Dynamic Random Access Memory (DRAM).
[0082] The semiconductor structure also includes a gate dielectric layer 31, which covers the side of the word line 32 away from the interior of the first trench 2, and is in contact with the first source / drain layer 61 and the second source / drain layer 62. That is, the first source / drain layer 61, the second source / drain layer 62, the word line 32, and the gate dielectric layer 31 can be used to form a transistor.
[0083] The semiconductor structure further includes: a plurality of capacitor plates 72 filling the first trench 2; the plurality of capacitor plates 72 are spaced apart in the third direction Z and extend along the first direction X. The semiconductor structure also includes: a dielectric layer 71 located on the sidewall of the first trench 2, the dielectric layer 71 being located between the first source / drain layer 61 and the capacitor plates 72. That is, the first source / drain layer 61, the dielectric layer 71, and the capacitor plates 72 constitute a capacitor. The capacitor and the transistor can form a basic memory cell.
[0084] refer to Figure 28 , Figure 28 As shown in the enlarged view of Figure 27(a), when an enable voltage is supplied to word line 32, two channels are formed, meaning current flows between the first source / drain layer 61 and the second source / drain layer 62 on both the upper and lower sides of word line 32. When the transistor is turned on, the capacitor can store or release charge.
[0085] Referring again to Figure 27(a), since the upper and lower transistors share a first source-drain layer 61, adjacent transistors can be switched off simultaneously to prevent read / write errors. In some embodiments, the transistors include an isolation transistor and active transistors, which are alternately arranged in the first direction X. A normally off voltage is supplied to the isolation transistor to isolate the two active transistors. In other words, an isolation transistor is provided between the two active transistors, thereby increasing the distance between the active transistors, and the isolation transistor is in a normally off state, thus isolating the two active transistors and preventing mutual interference between adjacent active transistors.
[0086] Referring to Figure 27(b), the first trench 2 and the second trench 5 are arranged in the second direction Y, and both extend along the third direction Z. In some embodiments, there are multiple first trenches 2 and multiple second trenches 5, and the first trenches 2 and the second trenches 5 are arranged alternately in the second direction Y, which is beneficial to increasing the number of transistors and capacitors, thereby improving the storage capacity.
[0087] In some embodiments, reference Figures 27(a) to 27(b) Multiple first source / drain layers 61 are spaced apart in the third direction Z; multiple second source / drain layers 62 are spaced apart in the third direction Z; and word lines 32 extend along the third direction Z. That is, multiple transistors can be arranged in the third direction Z, and word lines 32 can serve as gates for the multiple transistors arranged in the third direction Z.
[0088] The semiconductor structure also includes multiple bit lines 64 filling the second trench 5. These bit lines 64 are spaced apart in the third direction Z and extend along the first direction X. The bit lines 64 are electrically connected to the second source / drain layers 62. In other words, the bit lines 64 are electrically connected to the multiple second source / drain layers 62 arranged in the first direction X. The bit lines 64 are also electrically connected to peripheral circuitry and are used to read stored data from memory cells or write data to memory cells.
[0089] Furthermore, the semiconductor structure also includes isolation structures 41, a plurality of which extend along the second direction Y and are arranged in the third direction Z; the isolation structures 41 span the first trench 2 and the second trench 5. That is, the isolation structures 41 are used to isolate the plurality of transistors arranged in the third direction Z, but do not truncate the word lines 32. Specifically, the first source-drain layers 61 arranged adjacent to each other in the third direction Z are separated by the isolation structures 41, and the second source-drain layers 62 arranged adjacent to each other in the third direction Z are separated by the isolation structures 41. In addition, the isolation structures 41 are also used to isolate the bit lines 64 adjacent to each other in the third direction Z, and the capacitor plates 72 adjacent to each other in the third direction Z.
[0090] In summary, the semiconductor structure provided in this disclosure has 3D stacked transistors and capacitors, which constitute a memory cell. In the first direction X, interference between adjacent memory cells can be avoided by not simultaneously activating adjacent memory cells. In the third direction Z, adjacent memory cells are separated by an isolation structure.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided in which a first trench and a second trench are formed, and the depth direction of both trenches is the first direction. The first trench includes a plurality of first sub-grooves arranged in the first direction, and the second trench includes a plurality of second sub-grooves arranged in the first direction, and the sidewalls of the first sub-grooves and the second sub-grooves are both convex. A letter line protruding away from the first groove is formed at the junction of adjacent first sub-grooves; A first source / drain layer is formed on the sidewall of the first sub-trench; A second source / drain layer protruding away from the second trench is formed at the junction of adjacent second sub-trenches; the second source / drain layer and the word line are both located between the first trench and the second trench, and the second source / drain layer and the word line are disposed opposite to each other.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Before forming the word lines, the following is also included: A hole protruding away from the first trench is formed at the junction of adjacent first sub-grooves; A gate dielectric layer is formed on the inner wall of the hole, the gate dielectric layer covers the word line and is in contact with the first source / drain layer and the second source / drain layer.
3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The steps for forming the hole include: A first isolation membrane is formed on the sidewall of the first trench, and the first isolation membrane located at the junction of adjacent first sub-trenches protrudes into the interior of the first sub-trench. Remove the first isolation membrane located at the junction of adjacent first sub-trenches to expose the substrate located at the junction of the adjacent first sub-trenches; The substrate exposed by the first insulating film is etched to form the holes.
4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, Removing the first isolation membrane located at the junction of adjacent first sub-trenches to expose the substrate located at the junction of the adjacent first sub-trenches; including: Using the substrate itself as a mask, a portion of the first isolation film located at the junction of adjacent first sub-trenches is etched along the first direction; An isotropic etching process is used to remove the remaining first isolation film located at the junction of adjacent first sub-trenches, so as to expose the substrate located at the junction of the adjacent first sub-trenches.
5. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, Also includes: An insulating layer is formed inside the hole, the insulating layer being located on the side of the letter line facing the first groove; The gate dielectric layer also covers the surface of the insulating layer.
6. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The steps for forming the word lines include: Initial letter lines are formed on the sidewalls of the first trench and within the holes; An isotropic etching process is used to remove a portion of the initial word lines located on the sidewall of the first trench and within the hole, with the remaining initial word lines within the hole serving as the word lines.
7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The first groove and the second groove are arranged in a second direction and both extend along a third direction; the second direction is perpendicular to the third direction and both are perpendicular to the first direction; The letter line extends along the third direction; The manufacturing method further includes: forming a plurality of spaced-apart isolation structures; the plurality of isolation structures extending along a second direction and arranged upwards on the third direction; The isolation structure spans the first trench and the second trench; the isolation structure covers multiple word lines; The first source / drain layer, which is arranged adjacent to the third party upwards, is separated by the isolation structure; The second source / drain layer, which is arranged adjacent to the third party upwards, is separated by the isolation structure.
8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, It also includes: forming a plurality of bit lines that fill the second trench, the bit lines extending along the first direction; the bit lines being electrically connected to the second source / drain layer; The two bit lines arranged adjacent to each other in the third direction are separated by the isolation structure.
9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, After forming the word line, the method further includes: filling the first trench with a sacrificial layer; After the sacrificial layer is formed, the second trench is formed; After the second trench is formed, the isolation structure is formed, and the isolation structure further divides the sacrificial layer into multiple parts; After the isolation structure is formed, the second source / drain layer and the bit line are formed; After the bit lines are formed, the sacrificial layer is removed; After removing the sacrificial layer, the sidewalls of the first sub-trench are doped to form the first source / drain layer.
10. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, After the isolation structure is formed, it also includes: A dielectric layer is formed on the sidewall of the first trench, and the dielectric layer also covers the first source / drain layer; A plurality of capacitor plates are formed to fill the first trench, and the capacitor plates are also covered by the dielectric layer; the capacitor plates arranged adjacent to each other in the third direction are separated by the isolation structure.
11. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The steps for forming the second source / drain layer include: An initial second isolation membrane is formed on the sidewall of the second trench, and the second isolation membrane located at the junction of adjacent second sub-trenches protrudes into the interior of the second sub-trench; Remove the initial second isolation film located at the junction of adjacent second sub-trenches to expose the substrate located at the junction of the adjacent second sub-trenches; the remaining initial second isolation film serves as the second isolation film; The substrate exposed by the second isolation film is doped to form the second source / drain layer.
12. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Also includes: A metal silicide layer is formed in contact with the second source / drain layer, and the metal silicide layer is located on the side of the second source / drain layer closer to the interior of the second trench.
13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that, Before forming the metal silicide layer, the method further includes: Remove a portion of the second source / drain layer near the interior of the second trench to form a contact port; The metal silicide layer is formed in the contact port.
14. A semiconductor structure, characterized in that, include: A substrate having a first trench and a second trench, both of which have a depth direction in the first direction; The first trench includes a plurality of first sub-grooves arranged in the first direction, and the second trench includes a plurality of second sub-grooves arranged in the first direction, and the sidewalls of the first sub-grooves and the second sub-grooves are both convex. The junction of adjacent first sub-grooves has a character line protruding away from the first groove; The sidewall of the first sub-trench has a first source / drain layer; The boundary between adjacent second sub-grooves has a second source / drain layer that protrudes away from the second groove; the second source / drain layer and the word line are both located between the first groove and the second groove, and the second source / drain layer and the word line are disposed opposite to each other.
15. The semiconductor structure according to claim 14, characterized in that, Also includes: A gate dielectric layer covers the side of the word line away from the interior of the first trench, and the gate dielectric layer is also in contact with the first source / drain layer and the second source / drain layer.
16. The semiconductor structure according to claim 14, characterized in that, Also includes: Multiple bit lines fill the second trench, and the multiple bit lines are spaced apart in a third direction and extend along the first direction; The third direction is perpendicular to the first direction; the bit line is electrically connected to the second source / drain layer. The letter line extends along the third direction; Multiple first source-drain layers are arranged at intervals above the third party; multiple second source-drain layers are arranged at intervals above the third party.
17. The semiconductor structure according to claim 14, characterized in that, Also includes: Multiple capacitor plates filling the first trench; The plurality of capacitor plates are arranged at intervals in a third-direction upward direction and extend along the first direction; The third direction is perpendicular to the first direction; The semiconductor structure further includes a dielectric layer located on the sidewall of the first trench, the dielectric layer being located between the first source / drain layer and the capacitor plate.