Memory system, control method, and server

Abstract

The application relates to the computer technical field and discloses a memory system, a control method and a server, the system comprising: a CPU and an FPGA acceleration card, the CPU and the FPGA acceleration card both supporting a CXL protocol; the CPU and the FPGA acceleration card being connected through a PCIe interface supporting the CXL protocol; the CPU being configured with a plurality of local memory strips through a memory strip slot; the FPGA acceleration card being configured with a plurality of extended memory strips through a memory connection component or a memory connector; and the FPGA acceleration card being used for receiving memory data sent by the CPU, and performing logical calculation on the memory data according to the attribute characteristics of the memory data based on the extended memory strips to obtain target memory data. The system provided by the above scheme realizes expansion of the memory capacity of the server by additionally arranging the FPGA acceleration card, reduces the difficulty of expansion of the memory capacity of the server, and improves the overall performance and response speed of the server.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a memory system, control method, and server. Background Technology

[0002] Currently, in scenarios involving large-scale, high-speed computing, the server's memory capacity determines the number of tasks and the amount of data the server can process simultaneously. Larger memory capacity provides greater data processing capabilities, enabling the server to run more applications and handle more complex tasks concurrently, improving overall performance and response speed. Therefore, expanding server memory capacity has become a hot research topic.

[0003] In related technologies, server memory capacity expansion is typically achieved by connecting a CXL switch to the CPU and then connecting the memory module to the CXL switch. However, CXL switches are still under development and cannot be mass-produced, and their high complexity increases server development costs. Therefore, there is an urgent need for a server memory system that can expand server memory capacity, which is of great significance for improving the overall performance and response speed of servers. Summary of the Invention

[0004] This application provides a memory system, control method, and server to address the shortcomings of related technologies, such as the difficulty in expanding server memory capacity.

[0005] The first aspect of this application provides a memory system, including: a CPU and an FPGA acceleration card, wherein both the CPU and the FPGA acceleration card support the CXL protocol;

[0006] Both the CPU and the FPGA accelerator card are equipped with PCIe interfaces that support the CXL protocol.

[0007] The CPU and FPGA accelerator card are connected via a PCIe interface supporting the CXL protocol. The FPGA accelerator card is connected to the gold finger slot of the PCIe interface supporting the CXL protocol via the gold finger plug-in of the PCIe interface supporting the CXL protocol. The gold finger adopts the PCIe 5.0 interface protocol.

[0008] The CPU is configured with several local memory modules via memory module slots;

[0009] The FPGA accelerator card is configured with several expansion memory modules via memory connection components or memory connectors;

[0010] The FPGA acceleration card is used to receive memory data sent by the CPU, and based on the extended memory module, performs logical calculations on the memory data according to the attribute characteristics of the memory data to obtain the target memory data.

[0011] In one optional implementation, the FPGA acceleration card includes: a main control chip;

[0012] The main control chip is used to, upon receiving the memory data, if the memory data is general data, select a first target extended memory module based on the current space occupancy rate of each extended memory module;

[0013] The memory data is saved as data to be calculated to the first target extended memory module;

[0014] Extract the data to be calculated from the first target extended memory module, and perform corresponding logical calculations on the data to be calculated to obtain the target memory data;

[0015] The delay requirement for general data is lower than the preset delay standard.

[0016] In one optional implementation, the FPGA acceleration card includes: a main control chip;

[0017] The main control chip is used to, upon receiving the memory data, perform logical calculations directly on the memory data if the memory data is urgent data, to obtain the target memory data;

[0018] The delay requirement for the emergency data is higher than the preset delay standard.

[0019] In one optional implementation, the main control chip includes: a protocol logic analyzer;

[0020] The protocol logic analyzer is used to determine the latency characteristic value of the memory data based on the protocol type and data type represented by the attribute characteristics of the memory data; and to determine whether the memory data is urgent data based on the latency characteristic value of the memory data.

[0021] Specifically, when the latency characteristic value of the memory data is not lower than a preset emergency threshold, the memory data is determined to be emergency data; when the latency characteristic value of the memory data is lower than the preset emergency threshold, the memory data is determined to be general data.

[0022] In one alternative implementation, the FPGA accelerator card is configured with several extended memory modules via a memory connection component;

[0023] The FPGA acceleration card is also used for:

[0024] Based on the current remaining capacity of each of the aforementioned extended memory modules, select the second target extended memory module;

[0025] The target memory data is saved to the corresponding second target extended memory module via the memory connection component;

[0026] The target memory data is memory data that has undergone logical calculation.

[0027] In one optional implementation, the FPGA accelerator card is configured with several extended memory modules via a memory connection component, the memory connection component including: a hard disk connector and a memory connector;

[0028] The hard disk connector is used to connect to the FPGA acceleration card. The hard disk connector supports the PCIe protocol. The hard disk connector and the FPGA acceleration card are connected by physical lines.

[0029] The memory connector is used to connect an expansion memory module, which is connected to the memory connector via gold fingers.

[0030] In one alternative implementation, the FPGA accelerator card includes:

[0031] A hard disk connection interface, wherein the hard disk connector is connected to the FPGA accelerator card through the hard disk connection interface;

[0032] The hard disk connection interface is soldered to the FPGA acceleration card, and the hard disk connection interface supports the PCIe protocol.

[0033] In one optional implementation, a plurality of data transmission lines are provided between the hard disk connector and the memory connector, and the data transmission links are used to transmit the memory data, target memory data, FPGA accelerator card signals and extended memory status information.

[0034] In one optional implementation, the data transmission line includes:

[0035] The PCIe x4 line is used to transmit the memory data and the target memory data.

[0036] In one optional implementation, the data transmission line includes:

[0037] A clock signal line is used to transmit the clock signal generated by the clock generator on the FPGA accelerator card to the extended memory module.

[0038] The FPGA accelerator card signal includes the clock signal.

[0039] In one optional implementation, the data transmission line includes:

[0040] The status transmission line is used to transmit the status information of the extended memory module to the FPGA acceleration card. The status information of the extended memory module includes memory manufacturer information, operating frequency, operating voltage, speed and capacitance.

[0041] In one alternative implementation, the FPGA accelerator card is configured with several expansion memory modules via memory connectors;

[0042] The memory connector is soldered to the FPGA accelerator card, and the expansion memory module is connected to the memory connector via gold finger plug-in.

[0043] In one alternative implementation, the system further includes: from the CPU;

[0044] The CPU and the CPU are connected via a UPI line;

[0045] The CPU shares the FPGA acceleration card with the CPU through the UPI line.

[0046] In one alternative implementation, the system further includes: from the CPU;

[0047] The CPU and the CPU are connected via a memory exchanger;

[0048] The CPU is connected to the FPGA acceleration card via the memory switch.

[0049] In one alternative implementation, the system further includes: from the CPU and from the FPGA acceleration card;

[0050] The slave CPU is connected to the CPU via a memory exchange, and the slave CPU is connected to the uplink port of the memory exchange.

[0051] The FPGA accelerator cards are connected to each other via the memory switch, and the FPGA accelerator cards are connected to the downlink port of the memory switch.

[0052] The slave CPU is connected to the CPU via the memory switch and shares the FPGA accelerator card and the slave FPGA accelerator card.

[0053] In one alternative implementation, the system further includes: an FPGA acceleration card;

[0054] The FPGA acceleration card is connected to the FPGA acceleration card via a memory switch, and the CPU is connected to the uplink port of the memory switch.

[0055] The FPGA accelerator card is connected to the downstream port of the memory switch.

[0056] In one alternative implementation, the FPGA accelerator card includes:

[0057] The optical communication module is used to receive remote data sent by a remote CPU.

[0058] The FPGA acceleration card is also used to perform logical calculations on the remote data based on the extended memory module to obtain the target remote data.

[0059] In one alternative implementation, the FPGA accelerator card includes:

[0060] A complex programmable logic device is used to control and manage the power supply, monitor the overall status information of the FPGA accelerator card, and send the overall status information to the host BMC.

[0061] A second aspect of this application provides a memory system control method, comprising:

[0062] Get memory data;

[0063] The memory data is sent to the local memory module or FPGA acceleration card;

[0064] The FPGA acceleration card is configured with several extended memory modules via a memory connection component.

[0065] A third aspect of this application provides a server comprising: a memory system as described in the first aspect above and various possible designs of the first aspect.

[0066] The technical solution of this application has the following advantages:

[0067] This application provides a memory system, control method, and server. The system includes a CPU and an FPGA accelerator card, both supporting the CXL protocol. Both the CPU and FPGA accelerator card have PCIe interfaces supporting the CXL protocol. The CPU and FPGA accelerator card are connected via these CXL protocol PCIe interfaces. The FPGA accelerator card is pluggably connected to the CPU's CXL protocol PCIe interface gold finger slot via a gold finger connector using the PCIe 5.0 interface protocol. The CPU is configured with several local memory modules via memory slots. The FPGA accelerator card is configured with several extended memory modules via memory connection components or memory connectors. The FPGA accelerator card receives memory data sent by the CPU and performs logical calculations on the memory data based on the attribute characteristics of the memory data according to the extended memory modules to obtain the target memory data. The system provided by the above solution expands the server's memory capacity by adding an FPGA accelerator card, reducing the difficulty of expanding the server's memory capacity and improving the overall performance and response speed of the server. Attached Figure Description

[0068] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0069] Figure 1 A schematic diagram of an exemplary memory system provided for embodiments of this application;

[0070] Figure 2 This is a schematic diagram of the memory data processing flow provided in the embodiments of this application;

[0071] Figure 3 A schematic diagram of the structure of an exemplary FPGA accelerator card provided in the embodiments of this application;

[0072] Figure 4 A flowchart illustrating the memory system control method provided in an embodiment of this application;

[0073] Figure 5 This is a schematic diagram illustrating the interaction process between the CPU and the FPGA accelerator card provided in an embodiment of this application.

[0074] Figure 6 This is a schematic diagram of the server structure provided in an embodiment of this application.

[0075] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0076] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0077] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. In the following descriptions of embodiments, "a plurality of" means two or more, unless otherwise explicitly defined.

[0078] With the rapid development of AI technology, data centers are placing increasingly higher demands on computing power. Therefore, we need to optimize computing power supply, strengthen the construction of computing infrastructure, and coordinate the scheduling of computing resources to continuously improve utilization efficiency. The most critical infrastructure is the server. A server is essentially a high-performance computer, characterized by high-speed computing power, long-term stability, and powerful data throughput. It is indispensable in industries such as the internet, finance, telecommunications, energy, and healthcare. A server mainly consists of a CPU, memory, hard drive, network interface card (NIC), power supply, and chassis. The server's memory capacity determines the number of tasks and the amount of data it can process simultaneously. Larger memory capacity provides greater data processing capabilities, enabling the server to run more applications and handle more complex tasks concurrently, improving overall performance and response speed. With the development of CXL technology, mainstream manufacturers' CPUs and FPGAs have begun to support the CXL protocol, which allows for memory expansion. In related technologies, memory capacity expansion is typically achieved by connecting a CXL switch to the CPU and then connecting the memory module to the CXL switch. However, CXL switches are currently still under development, cannot be mass-produced, and are quite complex, increasing the development cost of servers.

[0079] To address the aforementioned issues, this application provides a memory system, control method, and server. The system includes a CPU and an FPGA accelerator card, both supporting the CXL protocol. Both the CPU and FPGA accelerator card have PCIe interfaces supporting the CXL protocol. The CPU and FPGA accelerator card are connected via these CXL protocol PCIe interfaces. The FPGA accelerator card is pluggably connected to the CPU's CXL protocol PCIe interface's gold finger slot via a gold finger connector using the PCIe 5.0 interface protocol. The CPU is configured with several local memory modules via memory slots. The FPGA accelerator card is configured with several extended memory modules via memory connection components or memory connectors. The FPGA accelerator card receives memory data sent by the CPU and performs logical calculations on the memory data based on the attribute characteristics of the memory data according to the extended memory modules to obtain the target memory data. The system provided by this solution expands the server's memory capacity by adding an FPGA accelerator card, reducing the difficulty of expanding the server's memory capacity and improving the server's overall performance and response speed.

[0080] The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0081] This application provides a memory system for expanding the memory capacity of a server. The memory system includes a CPU and an FPGA accelerator card.

[0082] Both the CPU and FPGA accelerator card support the CXL protocol; both the CPU and FPGA accelerator card are equipped with PCIe interfaces supporting the CXL protocol; the CPU and FPGA accelerator card are connected through the PCIe interfaces supporting the CXL protocol, and the FPGA accelerator card is connected to the gold finger slot of the CPU's PCIe interface supporting the CXL protocol via a gold finger plug-in connector for the CXL protocol-supported PCIe interface, with the gold fingers using the PCIe 5.0 interface protocol; the CPU is configured with several local memory modules through memory slots; the FPGA accelerator card is configured with several extended memory modules through memory connection components or memory connectors; the FPGA accelerator card is used to receive memory data sent by the CPU, and based on the extended memory modules, performs logical calculations on the memory data according to the attribute characteristics of the memory data to obtain the target memory data.

[0083] The FPGA accelerator card includes a main control chip, which performs logical calculations on the memory data. The main control chip of the FPGA accelerator card is the FPGA chip, responsible for accelerated computing and communication. After receiving the memory data, the main control chip can perform logical calculations such as data compression, data transcoding, and searching to convert the obtained memory data into target memory data.

[0084] It should be noted that the Compute Express Link (CXL) protocol is a brand-new high-speed interconnect technology standard that allows CPUs to expand memory capacity.

[0085] For example, such as Figure 1 The diagram shows an exemplary memory system provided in this embodiment of the application. The CPU supports local 8-way memory (DDR5_CH1 to DDR5_CH8) and supports the CXL protocol. The FPGA accelerator card also supports the CXL protocol. The CXL protocol is physically identical to PCIe Gen5.0, therefore the FPGA accelerator card can be connected to the CPU's PCIe interface slot that supports the CXL protocol via its PCIe 5.0 interface contacts. The FPGA accelerator card has four memory slots, allowing for the configuration of four memory modules (E3.S CXL memory).

[0086] Specifically, in one embodiment, the main control chip, upon receiving the memory data, if the memory data is general data, then selects a first target extended memory module based on the current space occupancy rate of each extended memory module; saves the memory data as data to be calculated to the first target extended memory module; extracts the data to be calculated from the first target extended memory module; and performs corresponding logical calculations on the data to be calculated to obtain the target memory data. The latency requirement for the general data is lower than a preset latency standard.

[0087] It should be noted that the computing unit (CPU) and memory are two separate units. When logical calculations need to be performed on memory data, the CPU typically reads the corresponding memory data from memory according to instructions, performs the calculations and processing on the CPU, and then stores the resulting target data back into memory.

[0088] Specifically, when an FPGA accelerator card is configured with multiple extended memory modules, in order to balance the load of the extended memory modules, several extended memory modules with smaller current space occupancy rates can be selected as the first target extended memory modules based on their current space occupancy rates.

[0089] Specifically, in the FPGA accelerator card provided in this application embodiment, its main control chip has the same computing function as the host CPU, that is, the main control chip can perform corresponding logical calculations on memory data to obtain target memory data.

[0090] Accordingly, in one embodiment, after receiving the memory data, if the memory data is urgent data, the main control chip directly performs logical calculations on the memory data to obtain the target memory data. The latency requirement for the urgent data is higher than a preset latency standard.

[0091] It's important to note that CPU access to local memory (DDR5_CH1~DDR5_CH8) is faster than accessing remote extended memory (E3.S CXL memory). This is because accessing remote memory requires traversing the FPGA accelerator card, and there's a latency in performing data input and computation simultaneously while reading data. Larger-scale AI computations, such as multiply-accumulate cascading, require significantly more memory, which the CPU's local memory cannot meet. Therefore, some memory data needs to be offloaded to E3.S CXL memory (extended memory).

[0092] To address the aforementioned technical issues, when the main control chip determines that the received memory data is urgent, it directly performs logical calculations on the memory data, omitting the step of saving the memory data as data to be calculated to the extended memory module, thereby reducing data processing latency.

[0093] Specifically, in one embodiment, the main control chip includes: a protocol logic analyzer; the protocol logic analyzer is used to determine whether the memory data is urgent data based on the attribute characteristics of the memory data.

[0094] Specifically, the protocol logic analyzer can be configured in software on the main control chip.

[0095] Specifically, in one embodiment, the protocol logic analyzer can determine the latency characteristic value of the memory data based on the attribute characteristics of the memory data; and determine whether the memory data is urgent data based on the latency characteristic value of the memory data.

[0096] Among them, such as Figure 2The diagram illustrates the memory data processing flow provided in this embodiment. The CPU sends memory data to the FPGA acceleration card via the gold fingers. The FPGA acceleration card first calculates the latency characteristic value of the memory data based on the protocol logic analyzer. Then, it determines whether the memory data is low-latency urgent data based on the latency characteristic value. If so, it directly performs logic calculation processing on the memory data; otherwise, it first saves it as data to be calculated to the extended memory module, and then performs logic calculation processing. The data processing flows for urgent data and general data are actually parallel processes that do not affect each other.

[0097] Specifically, in one embodiment, the protocol logic analyzer determines the latency characteristic value of the memory data based on the protocol type and data type represented by the attribute characteristics of the memory data.

[0098] The protocol logic analyzer's calculation logic for the latency characteristic value of memory data is shown in the following table:

[0099]

[0100] Here, Flag is the latency characteristic value of memory data. Data types are divided into M1, M2, M3...Mm, and protocol types are divided into N1, N2, N3...Nn. Data types are at least text, image, and video. If the protocol type used by the memory data is N1 and the data type is M1, then the corresponding latency characteristic value is F11. If the protocol type used by the memory data is Nn and the data type is Mm, then the corresponding latency characteristic value is Fnm. Then, according to different latency characteristic values, it enters the corresponding logical IP core for corresponding processing.

[0101] Specifically, in one embodiment, the protocol logic analyzer determines that the memory data is urgent data when the latency characteristic value of the memory data is not lower than a preset urgent threshold.

[0102] Specifically, several delay characteristic values ​​can be pre-selected as an emergency feature set, such as selecting F11, F21, and F33 to construct the emergency feature set. When the delay characteristic value of the received memory data to be logically calculated is F21, the memory data is determined to be emergency data; when the delay characteristic value of the received memory data to be logically calculated is Fn2, the memory data is determined to be general data.

[0103] It should be noted that the FPGA accelerator card provided in this application embodiment fully cooperates with the storage during the data access process, so as to adopt better caching strategies and data consistency strategies during the computing process and obtain better data storage performance. For example, data enters the FPGA accelerator card for data compression, searching, video file transcoding and other processing, and then enters the CXL extended memory, thereby realizing an integrated storage and computing system device.

[0104] Based on the above embodiments, such as Figure 1 As shown, in one embodiment, when the FPGA accelerator card is configured with several extended memory modules via a memory connection component, the FPGA accelerator card selects a second target extended memory module based on the current remaining capacity of each extended memory module; the target memory data is then saved to the corresponding second target extended memory module via the memory connection component, so that the CPU can subsequently read the target memory data from the extended memory module. The target memory data is memory data that has undergone logical calculations.

[0105] Specifically, when the FPGA accelerator card is configured with multiple extended memory modules, to further ensure that the extended memory modules maintain a balanced load, several extended memory modules with smaller current remaining capacities can be selected as the second target extended memory modules based on their current remaining capacity. The selection logic for the first target extended memory module and the second target extended memory module are two independent logics, meaning that an extended memory module can be both the first target extended memory module and the second target extended memory module.

[0106] Among them, such as Figure 1 As shown, the memory connection components include a hard disk connector (MCIO CONN x16) and a memory connector (U.2CONN). The hard disk connector is used to connect the FPGA accelerator card, supports the PCIe protocol, and is physically connected to the FPGA accelerator card. The memory connector is used to connect an expansion memory module, which is connected to the memory connector via gold fingers.

[0107] It should be noted that the memory connector is connected to the expansion memory module, and there is a one-to-one correspondence between the memory connector and the expansion memory module (E3.S CXL memory). One hard disk connector can correspond to two or more memory connectors.

[0108] It needs to be further explained that, such as Figure 1 As shown, the MCIO CONN x16 actually connects two extended memory modules, which then branch into two x8 modules. Therefore, the memory connector (U.2CONN) can specifically use the GEN-Z2C connector.

[0109] Specifically, in one embodiment, the FPGA accelerator card includes a hard disk connection interface (MCIO CONN x16-PCIe5.0 / CXL), and the hard disk connector is connected to the FPGA accelerator card through the hard disk connection interface.

[0110] Specifically, the FPGA accelerator card outputs memory data to the hard drive connector in the form of a high-speed signal through the hard drive connection interface.

[0111] The MCIO CONN x16 hard drive interface in the FPGA accelerator card is a high-speed connector that supports PCIe Gen5.0 and CXL protocol communication, enabling hard drive or memory expansion. When used for NVMe SSD hard drive expansion, the MCIO CONN x16 communicates with the gold fingers using the PCIe Gen5.0 protocol; when used for memory expansion, the MCIO CONN x16 communicates with the gold fingers using the CXL protocol.

[0112] Specifically, in one embodiment, a plurality of data transmission lines are provided between the hard disk connector and the memory connector. These data transmission lines are used to transmit the memory data, target memory data, FPGA accelerator card signals, and extended memory status information.

[0113] The data transmission lines include PCIe x4 lines for transmitting the memory data and target memory data. It also includes a clock signal line for transmitting the clock signal generated by the clock generator on the FPGA accelerator card to the extended memory module; the FPGA accelerator card signal includes the clock signal. Furthermore, it includes a status transmission line for transmitting the extended memory status information of the extended memory module to the FPGA accelerator card; the extended memory status information includes memory manufacturer information, operating frequency, operating voltage, speed, and capacitance.

[0114] Specifically, such as Figure 1 As shown, the data transmission lines between the hard disk connector and the memory connector include PCIe x4 lines, REFCLK lines (clock signal lines), and SMBus lines (status transmission lines). Among them, the PCIe x4 lines are used to transmit memory data, the REFCLK lines are used to transmit clock signals, and the SMBus lines are used to transmit corresponding status signal parameters according to actual needs. SMBus is actually a bus connected to the CPLD on the FPGA accelerator card and is used to transmit extended memory status information to the FPGA accelerator card so that the FPGA accelerator card can apply extended memory according to the obtained extended memory status information.

[0115] Based on the above embodiments, in order to further simplify the system structure, as an implementable approach, in one embodiment, the FPGA accelerator card is directly configured with several expansion memory modules through a memory connector; the memory connector is soldered to the FPGA accelerator card, and the expansion memory modules are connected to the memory connector through gold finger plug-in.

[0116] Specifically, to further improve the flexibility of system deployment and reduce system development costs, the memory connector can be directly soldered to the FPGA accelerator card, and then the expansion memory module can be connected to the FPGA accelerator card through gold finger plug-in.

[0117] Based on the above embodiments, for multi-processor (multi-CPU) application scenarios, as an implementable approach, in one embodiment, the system further includes: from the CPU.

[0118] The slave CPU is connected to the CPU via a UPI line; the slave CPU shares the FPGA acceleration card with the CPU via the UPI line.

[0119] It should be noted that UPI refers to Intel's Ultra Path Interconnect, also known as Hyper Path Interconnect. UPI is a peer-to-peer interconnect technology designed by Intel for its multiprocessor systems.

[0120] Specifically, in one embodiment, the slave CPU can also be connected to the CPU via a memory exchange; the slave CPU shares the FPGA acceleration card with the CPU via the memory exchange.

[0121] The memory switch needs to support the CXL protocol; the memory switch is called a CXL switch.

[0122] Specifically, in one embodiment, to further expand system memory resources, the system may include, in addition to the CPU, an FPGA accelerator card.

[0123] The slave CPU is connected to the CPU via a memory exchange, and the slave CPU is connected to the CPU via the uplink port of the memory exchange; the slave FPGA accelerator card is connected to the FPGA accelerator card via the memory exchange, and the slave FPGA accelerator card is connected to the FPGA accelerator card via the downlink port of the memory exchange; the slave CPU shares the FPGA accelerator card and the slave FPGA accelerator card with the CPU via the memory exchange.

[0124] Specifically, in one embodiment, when the system includes a CPU and two or more FPGA accelerator cards, the slave FPGA accelerator card is connected to the FPGA accelerator card via a memory exchange, the CPU is connected to the uplink port of the memory exchange, and the slave FPGA accelerator card is connected to the FPGA accelerator card via the downlink port of the memory exchange.

[0125] Specifically, the specific connection methods between the CPU, the main CPU, the slave FPGA accelerator card, the main FPGA accelerator card, and the memory exchanger can be set according to the actual situation, and this application embodiment does not limit them.

[0126] Based on the above embodiments, to further enrich the functionality of the FPGA accelerator card and improve the overall performance of the server, such as... Figure 3 The diagram shown is a schematic of an exemplary FPGA accelerator card provided in an embodiment of this application. As an implementable approach, in one embodiment, the FPGA accelerator card includes: an optical communication module (QSFP28_1, QSFP28_2) for receiving remote data sent by a remote CPU; the FPGA accelerator card is also used to perform logical calculations on the remote data based on the extended memory module to obtain target remote data.

[0127] Specifically, the remote CPU can send remote data to the optical communication module of the FPGA accelerator card based on optical communication devices such as optical switches.

[0128] Specifically, in one embodiment, the FPGA accelerator card includes complex programmable logic devices for controlling and managing power.

[0129] The complex programmable logic device is also used to monitor the overall status information of the FPGA accelerator card and send the overall status information to the host BMC.

[0130] It should be noted that the CPLD is responsible for controlling power timing and GPIO communication, and also acts as the BMC (Browser Control Center) of the FPGA accelerator card, managing and monitoring overall board power consumption, temperature, and alarm information. This information is exchanged with the CPU board via SMBUS communication through the PCIe x16 connector. The CPLD also communicates with the FPGA primarily through I2C and GPIO, obtaining the current FPGA status and information about the source and decomposition of data entering the FPGA.

[0131] Specifically, the complex programmable logic device (CPLD) controls and manages the power supply, and also acts as the BMC of the FPGA accelerator card, managing and monitoring the overall board status information such as power consumption, temperature, and alarms. At the same time, it communicates with the host BMC on the host side (CPU) through SMBUS to send the overall board status information to the host BMC.

[0132] Specifically, in one embodiment, the FPGA acceleration card includes: a board status indicator (LED).

[0133] The overall board status indicator is used to report the overall board status information of the local FPGA accelerator card in different lighting modes, such as a red light when the temperature is too high and a yellow light when the power consumption is too high.

[0134] Specifically, in one embodiment, the FPGA acceleration card includes a clock generator and flash memory. For example... Figure 3 As shown, the FPGA acceleration card also includes functional components such as a clock buffer (CLK Buffer), other ICs, JTAG, and FANCONN.

[0135] It should be noted that the FPGA accelerator card is based on the FPGA chip, and functional components such as clock generator and flash memory are added to the FPGA chip to build the FPGA accelerator card. The specific components added can be set according to actual needs, and this application embodiment does not limit them.

[0136] Flash and Clock Generator are essential components on the FPGA board. Flash is a necessary peripheral component of the FPGA, i.e., it is standard equipment, to ensure that the FPGA can function properly. The clock signal generated by the Clock Generator is transmitted to the CXL memory through the clock signal line, and it is a necessary signal for the operation of the CXL memory.

[0137] The memory system provided in this application includes: a CPU and an FPGA accelerator card, both of which support the CXL protocol; both the CPU and the FPGA accelerator card are equipped with PCIe interfaces supporting the CXL protocol; the CPU and the FPGA accelerator card are connected through the PCIe interfaces supporting the CXL protocol, and the FPGA accelerator card is pluggably connected to the gold finger slot of the CPU's PCIe interface supporting the CXL protocol through the gold finger of the PCIe interface supporting the CXL protocol, wherein the gold finger adopts the PCIe 5.0 interface protocol; the CPU is configured with several local memory modules through memory module slots; the FPGA accelerator card is configured with several extended memory modules through memory connection components or memory connectors, and the FPGA accelerator card is used to receive memory data sent by the CPU, and to perform logical calculations on the memory data according to the attribute characteristics of the memory data based on the extended memory modules, to obtain the target memory data. The system provided by the above solution expands the server's memory capacity by adding an FPGA accelerator card, reducing the difficulty of expanding the server's memory capacity and improving the overall performance and response speed of the server. Furthermore, by using an FPGA accelerator card to expand CXL memory while simultaneously performing logical calculations on the memory data, an in-memory computing effect can be achieved. Using this FPGA accelerator card to implement in-memory computing CXL memory expansion not only increases the memory capacity of the CPU but also accelerates computing, allowing data reading and calculation to be performed simultaneously, reducing CPU computing costs, and thus improving the overall performance of the system.

[0138] This application provides a memory system control method for processing memory data. The execution subject of this application embodiment is an electronic device, such as a server, desktop computer, laptop computer, tablet computer, and other electronic devices that can process memory data.

[0139] like Figure 4 The diagram shown is a flowchart illustrating a memory system control method provided in an embodiment of this application. The method includes:

[0140] Step 501: Obtain memory data;

[0141] Step 502: Send the memory data to the local memory module or FPGA acceleration card.

[0142] The FPGA acceleration card is configured with several extended memory modules via a memory connection component.

[0143] For example, such as Figure 5The diagram illustrates the interaction process between the CPU and the FPGA accelerator card according to an embodiment of this application. The CPU acquires memory data and, if it determines that the memory data will be processed based on extended memory, sends the memory data to the FPGA accelerator card. The FPGA accelerator card, based on the extended memory module and the attribute characteristics of the memory data, determines the appropriate processing method for the memory data and obtains the target memory data. For example, if the memory data is general data, it is saved as data to be calculated to the extended memory module. The data to be calculated is extracted from the extended memory module, and corresponding logical calculations are performed on the data to be calculated to obtain the target memory data. If the memory data is urgent data, logical calculations are performed directly on the memory data to obtain the target memory data. Finally, the target memory data is saved to the extended memory module, and the CPU reads the target memory data by accessing the extended memory module.

[0144] Regarding the memory system control method in this embodiment, the specific ways in which each module performs operations have been described in detail in the embodiments related to the system, and will not be elaborated here.

[0145] The memory system control method provided in this application is used to control the memory system provided in the above embodiments. Its implementation method and principle are the same, and will not be described again.

[0146] This application provides a server for executing the memory system control method provided in the above embodiments.

[0147] like Figure 6 The diagram shown is a structural schematic of a server provided in an embodiment of this application. The server includes the memory system provided in the above embodiment.

[0148] The server provided in this application embodiment is used to deploy the memory system provided in the above embodiment, so as to perform memory data processing by controlling the memory system. Its implementation method and principle are the same, and will not be described again.

[0149] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the system can be divided into different functional modules to complete all or part of the functions described above.

[0150] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A memory system, characterized by, The application relates to a CPU and FPGA acceleration card supporting a CXL protocol. The CPU and FPGA acceleration card are both provided with a PCIe interface supporting the CXL protocol. The CPU and FPGA acceleration card are connected through the PCIe interface supporting the CXL protocol, the FPGA acceleration card is connected to the PCIe interface supporting the CXL protocol of the CPU through the gold finger plug of the PCIe interface supporting the CXL protocol, and the gold finger adopts a PCIe 5.0 interface protocol. The CPU is provided with a plurality of local memory strips through a memory strip slot. The FPGA acceleration card is provided with a plurality of extended memory strips through a memory connection component or a memory connector. The FPGA acceleration card is used for receiving memory data sent by the CPU, and performing logical calculation on the memory data based on the attribute characteristics of the extended memory strips to obtain target memory data. The memory connection component comprises a hard disk connector and a memory connector. The hard disk connector is used for connecting the FPGA acceleration card, the hard disk connector supports the PCIe protocol, and the hard disk connector and the FPGA acceleration card are connected through a physical line. The memory connector is used for connecting the extended memory strip, and the extended memory strip is connected to the memory connector through the gold finger plug. A plurality of data transmission lines are arranged between the hard disk connector and the memory connector. The data transmission link is used for transmitting the memory data, target memory data, FPGA acceleration card signals and extended memory state information. The FPGA acceleration card comprises a master control chip.

2. The system of claim 1, wherein, The master control chip is used for screening a first target extended memory strip according to the current space occupancy of each extended memory strip if the memory data is general data after receiving the memory data. The memory data is saved as to-be-calculated data in the first target extended memory strip. To-be-calculated data is extracted from the first target extended memory strip, and corresponding logical calculation is performed on the to-be-calculated data to obtain target memory data. The delay requirement of the general data is lower than a preset delay standard. The FPGA acceleration card comprises a master control chip.

3. The system of claim 1, wherein, The master control chip is used for directly performing logical calculation on the memory data to obtain target memory data if the memory data is emergency data after receiving the memory data. The delay requirement of the emergency data is higher than a preset delay standard. The master control chip comprises a protocol logic analyzer.

4. The system of claim 2 or 3, wherein, The protocol logic analyzer is used for determining the delay characteristic value of the memory data according to the protocol type and data type represented by the attribute characteristics of the memory data, and judging whether the memory data is emergency data according to the delay characteristic value of the memory data. When the delay characteristic value of the memory data is not lower than a preset emergency threshold, the memory data is determined to be emergency data; and when the delay characteristic value of the memory data is lower than the preset emergency threshold, the memory data is determined to be general data. ​ 5. The system of claim 1, wherein, In the case that the FPGA acceleration card configures a plurality of extended memory bars through the memory connection component; The FPGA acceleration card is further configured to: According to the current remaining capacity of each extended memory bar, a second target extended memory bar is screened; The target memory data is saved to the corresponding second target extended memory bar through the memory connection component; The target memory data is memory data after logical calculation.

6. The system of claim 1, wherein, The FPGA acceleration card comprises: A hard disk connection interface, the hard disk connector connects the FPGA acceleration card through the hard disk connection interface; The hard disk connection interface is welded to the FPGA acceleration card, and the hard disk connection interface supports the PCIe protocol.

7. The system of claim 1, wherein, The data transmission line comprises: A PCIe x4 line for transmitting the memory data and the target memory data.

8. The system of claim 7, wherein, The data transmission line comprises: A clock signal line for transmitting a clock signal generated by a clock generator on the FPGA acceleration card to the extended memory bar; The FPGA acceleration card signal comprises the clock signal.

9. The system of claim 6, wherein, The data transmission line comprises: A state transmission line for transmitting extended memory state information of the extended memory bar to the FPGA acceleration card, the extended memory state information comprising memory manufacturer information, working frequency, working voltage, speed and capacitance.

10. The system of claim 1, wherein, In the case that the FPGA acceleration card configures a plurality of extended memory bars through the memory connector; The memory connector is welded to the FPGA acceleration card, and the extended memory bar is connected to the memory connector through a gold finger plug.

11. The system of claim 1, wherein, The system further comprises a slave CPU; The slave CPU is connected to the CPU through a UPI line; The slave CPU shares the FPGA acceleration card with the CPU through the UPI line.

12. The system of claim 1, wherein, The system further comprises a slave CPU; The slave CPU is connected to the CPU through a memory switch; The slave CPU shares the FPGA acceleration card with the CPU through the memory switch connection.

13. The system of claim 1, wherein, The system further comprises a slave CPU and a slave FPGA acceleration card; The slave CPU is connected to the CPU through a memory switch, and the slave CPU is connected to the uplink port of the memory switch; The slave FPGA acceleration card is connected to the FPGA acceleration card through the memory switch, and the slave FPGA acceleration card is connected to the downlink port of the memory switch; The slave CPU shares the FPGA acceleration card and the slave FPGA acceleration card with the CPU through the memory switch connection.

14. The system of claim 1, wherein, The system further comprises a slave FPGA acceleration card; The slave FPGA acceleration card is connected to the FPGA acceleration card through a memory switch, and the CPU is connected to the uplink port of the memory switch; The slave FPGA acceleration card is connected to the FPGA acceleration card through the downlink port of the memory switch.

15. The system of claim 1, wherein, The FPGA acceleration card comprises: An optical communication module for receiving remote data sent by a remote CPU; The FPGA acceleration card is also used for performing logical calculation on the remote data based on the extended memory bank to obtain target remote data.

16. The system of claim 1, wherein, The FPGA acceleration card comprises: A complex programmable logic device is used for controlling and managing power supply, monitoring whole-board state information of the FPGA acceleration card, and sending the whole-board state information to a host BMC.

17. A memory system control method characterized by comprising: Comprise: Obtaining memory data; Sending the memory data to a local memory bank or an FPGA acceleration card; The FPGA acceleration card is configured with a plurality of extended memory banks through a memory connection component; the memory connection component comprises a hard disk connector and a memory connector; The hard disk connector is used for connecting the FPGA acceleration card, the hard disk connector supports a PCIe protocol, and the hard disk connector and the FPGA acceleration card are connected through a physical line; The memory connector is used for connecting the extended memory bank, and the extended memory bank is connected to the memory connector through a gold finger plug; A plurality of data transmission lines are arranged between the hard disk connector and the memory connector; The data transmission link is used for transmitting the memory data, target memory data, FPGA acceleration card signals and extended memory state information.

18. A server, comprising: Comprise: The memory system according to any one of claims 1 to 16.

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