An on-chip bus with adjustable bit width and channels

Abstract

The present invention belongs to the technical field of on-chip buses, and specifically relates to an on-chip bus with adjustable bit width and channels. The present invention adopts a shared bus interconnection to realize parallel communication, which saves more hardware resources than parallel communication interconnection methods such as crossbar interconnection and point-to-point interconnection. The present invention adopts a bus design with adjustable bit width and channels, and the data channel uses 4 bits as the minimum transmission unit. On the basis of the original shared bus interconnection, it realizes the simultaneous reading and writing of data of multiple pairs of master and slave machines at the same time, thereby improving the bus transmission efficiency. The present invention designs an arbitrator design dedicated to a bus with adjustable bit width and channels. On the basis of a traditional arbitration algorithm, a transmission unit allocation module is added to form an efficient on-chip bus architecture. The present invention designs a host adapter module and a slave adapter module, which are used to connect an actual host, an actual slave and an interconnection module. The bus timing is simplified through these two modules, thereby reducing the development difficulty of the actual host and the actual slave.

Description

Technical Field

[0001] The invention belongs to the technical field of on-chip buses, and in particular relates to an on-chip bus with adjustable bit width and channels. Background Art

[0002] In SoC design, the on-chip bus plays a vital role. Under the same set of bus standards, the interfaces of each module are unified, and the data communication between modules adopts the same set of standards, which reduces the design complexity and shortens the design cycle of the entire SoC. At the same time, compared with the cross-connection between IP cores, the on-chip bus has the advantages of low power consumption, flexible use, less hardware resources, and support for multiple groups of hosts and slaves for data transmission. It is currently an effective way to realize the interconnection between various IP cores in the SOC system. The bus protocol and bus interconnection are important components of the bus. The bus protocol defines the transmission timing, bus signals, application scenarios, etc. of the on-chip bus, while the bus interconnection defines the connection method between the master and slave. The design of these two determines the data transmission efficiency of the entire SOC system.

[0003] The AXI bus uses five channels for communication in the protocol, among which the separation of read and write channels enables the AXI bus to support full-duplex communication, which greatly improves the transmission efficiency of the AXI bus. At the same time, the AXI bus also supports transmission modes such as out-of-order transmission, outstanding transmission, and burst transmission. These transmission modes expand the application scenarios of the AXI bus and also improve the transmission efficiency of the AXI bus. In the interconnection design, the AXI bus often uses Crossbar (cross switch) type interconnection and point-to-point type interconnection to realize parallel communication of multiple groups of hosts and slaves. In this way, the transmission efficiency of the bus is greatly improved. However, when facing a system with a large number of hosts and slaves, the Crossbar structure and the point-to-point structure have the problems of many communication nodes and high resource consumption, which restricts the use of the AXI bus in compact, low-power SoC systems. When the AXI bus uses a shared interconnection, due to the characteristics of the shared interconnection itself, it can greatly reduce the resource overhead of the bus system, but the problem that the shared interconnection only supports one pair of master-slave communication at the same time also restricts the use of the AXI bus in SoC systems.

[0004] The AHB bus uses three channels for communication in the protocol. The design of the read and write channels is not separated, which makes the AHB bus unable to support full-duplex channels, which has a certain impact on the transmission efficiency of the AHB bus. In the interconnection design, the AHB bus adopts a shared bus interconnection method, which only allows a pair of master and slave machines to communicate at the same time. It is widely used in many low-bandwidth SoCs. However, due to the use of a shared bus interconnection method, the AHB bus cannot support parallel communication, which limits the communication efficiency of the AHB bus. At the same time, when facing a transmission scenario with narrow transmission, the AHB bus uses a selection signal for identification. Regardless of the transmission bit width, all data channels will be occupied for transmission, which causes a waste of data channels and further reduces the communication efficiency of the bus.

[0005] The APB bus protocol is mainly used for connections between low-bandwidth peripherals. It is generally used as a configuration interface for low-speed IP in SoC design. It is generally used in conjunction with the AHB bus in SoC design. In the application scenario of multiple hosts and multiple slaves, the APB bus bandwidth is low and is not suitable for use as the main bus in SoC.

[0006] In some heterogeneous SoC designs, the on-chip bus only plays the role of parameter configuration and instruction transmission. The data transmission time on the bus is much shorter than the data calculation time in the computing core. In this case, the bus is required to be simple, flexible and configurable. However, in order to pursue faster transmission efficiency and larger bus bandwidth, traditional bus protocols often introduce pipelines, out-of-order transmission, cross-connection structures, etc. into the bus design. These methods can greatly improve the bus transmission rate, but they will also greatly increase the resource consumption of the bus. Summary of the invention

[0007] In view of the above problems, the present invention proposes an on-chip bus with adjustable bit width and channels.

[0008] The technical solution of the present invention is:

[0009] An on-chip bus with adjustable bit width and channel comprises a host adapter, an arbitrator, an interconnection module and a slave adapter; the interconnection module comprises a bidirectional data channel, an address channel, a control information channel and a response channel, wherein the data transmission bit width in the bidirectional data channel is adjustable from 4 bits to 32 bits; the host adapter is respectively connected to the host, the interconnection module and the arbitrator, the host adapter allocates the data transmission bit width according to the host control signal and the arbitration information, and then establishes the data path of the host adapter and the slave adapter in a handshake transmission mode through the interconnection module; the slave adapter is respectively connected to the interconnection module and the slave; the arbitrator performs arbitration by setting a transmission unit allocation module in the arbitrator, the arbitration information sent by the host adapter comprises the state of the state machine in the host adapter, the data transmission width and the arbitration request, and the arbitrator dynamically allocates the address channel, the control information channel and the bidirectional data channel through the transmission unit allocation module according to the current channel occupancy.

[0010] Furthermore, the bidirectional data channel includes a 32-bit write data channel and a 32-bit read data channel, the address channel is 32 bits, the control information channel is 32 bits, and the response channel is 8 bits; the write data channel is defined as a transmission unit with every 4 bits, thereby defining the write data channel as 8 write data channel transmission units and numbering them respectively, and similarly performing the same operation on the read data channel, thereby obtaining 8 independent bidirectional data transmission units, and establishing data paths for multiple pairs of host adapters and slave adapters at the same time.

[0011] Furthermore, the arbitrator is connected to all the host adapters and arbitrates the arbitration request of each host adapter respectively, and the arbitration return information is the allocation status of 8 bidirectional data transmission units.

[0012] Furthermore, during the data transmission process, the host adapter reads and writes data from the allocated data transmission unit according to the arbitration information, and the slave adapter also reads and writes data from the allocated data transmission unit according to the arbitration information.

[0013] The beneficial effects of the present invention are as follows: 1) The present invention adopts a shared bus interconnection to realize parallel communication, which saves more hardware resources than parallel communication interconnection methods such as crossbar interconnection and point-to-point interconnection. 2) The present invention adopts a bus design with adjustable bit width and channel, and the data channel uses 4 bits as the minimum transmission unit. On the basis of the original shared bus interconnection, it realizes the simultaneous reading and writing of data of multiple pairs of master and slave machines at the same time, thereby improving the bus transmission efficiency. 3) The present invention designs an arbitrator design specifically for a bus with adjustable bit width and channel. On the basis of the traditional arbitration algorithm, a transmission unit allocation module is added to form an efficient on-chip bus architecture. 4) The present invention designs a host adapter module and a slave adapter module for connecting an actual host, an actual slave and an interconnection module. The bus timing is simplified by these two modules, thereby reducing the development difficulty of the actual host and the actual slave. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 An on-chip bus for a traditional shared bus architecture;

[0015] Figure 2 An on-chip bus architecture with adjustable bit width and channels;

[0016] Figure 3 A schematic diagram of a host adapter proposed by the present invention;

[0017] Figure 4 A schematic diagram of a bus control signal with adjustable bit width and channels proposed by the present invention;

[0018] Figure 5 A structural diagram of an arbiter module with adjustable bit width and channels proposed by the present invention;

[0019] Figure 6 A schematic diagram of a slave adapter proposed by the present invention;

[0020] Figure 7 A data transmission flow chart of an on-chip bus architecture with adjustable bit width and channels proposed by the present invention;

[0021] Figure 8 It is a timing diagram of the actual host-side and bus-side write operation interface in a host adapter proposed by the present invention;

[0022] Fig. 9 A timing diagram of an actual slave-end and bus-end write operation interface in a slave adapter proposed by the present invention;

[0023] Fig.10 It is a timing diagram of the actual host-side and bus-side read operation interface in a host adapter proposed by the present invention;

[0024] Fig.11The present invention provides a timing diagram of the actual slave-end and bus-end read operation interface in a slave adapter. DETAILED DESCRIPTION

[0025] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0026] Figure 1 The invention discloses an on-chip bus of a traditional shared bus architecture. Under this architecture, the arbitrator is responsible for selecting the host according to the arbitration algorithm. The host transmits the address information, control information and write data to the address channel, control information channel and write data channel shared by the slave end through the selection of the multiplexer. The slave decides whether to read the information on the shared channel according to the chip select signal. Similarly, the read data sent by the slave also needs to be transmitted to the shared read data channel of the host end through the selection of the multiplexer. Through the access link established by this architecture, only one pair of master-slave machines can communicate at the same time, and other master-slave machines must wait for the previous pair of master-slave machines to complete the communication. This method is still widely used in SOC design due to its advantages such as low resource overhead, simple structure and easy implementation. Compared with the on-chip bus of the traditional shared bus architecture, the present invention adopts the design of bit width and channel separation to enable the shared bus architecture to support parallel communication.

[0027] Figure 2The present invention proposes an on-chip bus architecture with adjustable bit width and channel, and the system includes: a host adapter, an arbiter, an interconnection module, and a slave adapter. In this architecture, a 32-bit bidirectional data transmission channel, a 32-bit address transmission channel, a 32-bit control information transmission channel, and an 8-bit response channel constitute all the transmission channels of the bus. The 32-bit bidirectional data transmission channel is composed of a 32-bit write data channel and a 32-bit read data channel. In the write data channel, every 4 bits is a minimum transmission unit, and the write data channel is finally subdivided into 8 write data channel transmission units, and the 8 write data channel transmission units are numbered 0-7. The same operation is performed on the read data channel and numbered 0-7. Finally, the write data and read data channel transmission units with the same number are transformed into a group of bidirectional transmission units, totaling 8 groups of bidirectional transmission units. When the bidirectional transmission unit is working, only one direction of the transmission unit will work at the same time. On a macro level, the 64-bit data channel is represented as a 32-bit bidirectional data transmission channel. The 32-bit address transmission channel, 32-bit control information transmission channel and 8-bit response channel all pass through the interconnection module and establish the path between the host adapter and the slave adapter by handshaking. Only one pair of master-slave adapters can communicate with the above three channels at the same time. However, since the address information transmission, control information transmission and response signal transmission only occupy a small part of the entire read and write process during the read and write process, it does not affect the efficiency of the entire read and write transmission process. The address channel, control information channel, bidirectional data channel and response channel realize channel transmission through the handshake protocol. At the same time, the architecture also defines the bus signal to realize bus operation, as shown in Table 1:

[0028] Table 1 Bus interface signals

[0029]

[0030]

[0031]

[0032] Figure 3This is a schematic diagram of a host adapter proposed by the present invention. The host adapter flexibly allocates the data transmission bit width and transmission unit according to the actual host control information and arbitration information. The bit width of the data channel is adjustable within 32 bits, and the data path between the host adapter and the slave adapter is established through the interconnection module and the handshake transmission method. Due to the independent transmission of 8 bidirectional data transmission units, the path can establish multiple pairs of host adapter and slave adapter data paths at the same time. At the same time, the host adapter acts as a transfer bridge between the host-side interface and the bus-side interface, defines the host-side interface, uses the basic handshake protocol to simplify the bus timing, and transmits address information, control information, read and write data, and necessary control signals, as shown in Table 2:

[0033] Table 2 Host interface signals

[0034]

[0035]

[0036] Figure 4 The present invention provides a bus control signal schematic diagram with adjustable bit width and channel. The 32-bit signal represents the control signal in the control channel, wherein the [0] bit is a read / write flag, 1'b1 is for write, and 1'b0 is for read; the [1] bit represents the single instruction mode. In the single instruction mode, the actual host may not send write data, and only use the [31:26] bits in the 32-bit control signal to transmit instruction information. In this mode, the [6:2] bits need to be set to 5'b0, and the [11:7] bits need to be set to 5'b4; the [6:2] bits represent the burst transmission length, and the possible values ​​are 5'd0 to 5'd31. It should be noted that the actual burst transmission length is 100, ... The input length is [6:2]+1; bits [11:7] represent the burst transmission width, which supports a maximum of 32 bits and a minimum of 4 bits. Only integer multiples of 4 can be transmitted, so the value of bits [11:7] can only be 4 or integer multiples of 4; bits [13:12] are burst types, and possible values ​​are 2'b00\2'b01\2'b10\2'b11; bits [17:14] are host IDs, which are used to identify the host. Different hosts have different IDs; bits [25:18] are reserved for transmission unit selection. These 8 bits are reserved for host operations; bits [31:26] are reserved for command transmission.

[0037] Figure 5The present invention proposes a structural diagram of an arbiter module suitable for adjustable bit width and channels. The arbiter module is connected to all host adapters to arbitrate arbitration requests of each host adapter. Since the traditional arbitration method can only authorize channels as a whole, in order to realize the allocation of each data transmission unit and address and control channels, the arbiter module introduces a transmission unit allocation module based on the traditional arbitration method. The transmission unit allocation module allocates transmission units according to the actual occupancy of the data transmission units.

[0038] Figure 6 This is a schematic diagram of a slave adapter proposed by the present invention. The slave adapter connects the actual slave and the interconnection module, and receives and sends data to the corresponding data transmission unit according to the control information. At the same time, the slave adapter serves as a transfer bridge between the slave-side interface and the bus-side interface, defines the slave-side interface, uses a basic handshake protocol to simplify the bus timing, and transmits address information, control information, read and write data, and necessary control signals, as shown in Table 3:

[0039] Table 3 Slave interface signals

[0040]

[0041] Figure 7 The data transmission process of the on-chip bus system with adjustable bit width and channel includes the following working steps:

[0042] Step 1: The actual host determines the read / write slave address and control information according to the read / write request, and the control information includes data transmission mode, data transmission length, data transmission width, and host ID. If it is a write process, the actual host is ready to send write data; if it is a read process, the actual host is ready to receive read data.

[0043] Step 2: The actual host transmits the address and control information to the host adapter through the corresponding interface using the handshake protocol, waits for the host adapter to complete arbitration and sends the address and control information to the corresponding slave adapter through the bus interface.

[0044] Step 3: The host adapter sends arbitration information to the arbitrator, which includes the state of the host adapter state machine, data transmission width, arbitration request, and the arbitrator dynamically allocates address channels, control information channels, and bidirectional data channels according to the channel occupancy.

[0045] Step 4. After receiving the return information from the arbitrator, the host adapter writes the arbitration return information into the control information. The arbitration return information is the allocation of 8 data transmission units, and uses the handshake protocol to transmit the address and control information to the corresponding slave adapter through the corresponding channel to complete the address and control information transmission. At the same time, the host adapter releases the address and control information channel.

[0046] Step 5. After completing the address and control information transmission, start data transmission. If it is a write process, the actual host sends the first write data to the host adapter. On the host adapter side, 32 bits of data are sent from a specific data transmission unit according to the write data width and arbitration information, waiting for the write data to be sent to the corresponding slave adapter through the bus interface. On the slave adapter side, according to the arbitration information in the control information, N scattered 4 bits of data are received from the specific data transmission unit, and spliced ​​into 32 bits of data in sequence starting from the low bit. Finally, according to the transmission type, the address and control information of this write data and the write data itself are sent to the actual slave. After completing the first write data transmission, the remaining write data is transmitted according to the same process; if it is a read process, on the slave adapter side, The address and control information of the first read data are sent to the actual slave, and the actual slave is waiting to return the corresponding read data. After the slave adapter receives the 32-bit read data, it sends the 32-bit data from the specific data transmission unit according to the arbitration information, and waits for the read data to be sent to the corresponding host adapter through the bus interface. At the host adapter end, N scattered 4-bit data are received from the specific data transmission unit according to the arbitration information, and are spliced ​​into 32-bit data in sequence starting from the low bit, and finally the 32-bit data is sent to the actual host. After completing the first read data, the remaining read data is transmitted in the same way.

[0047] Step 6: After completing all read and write data transmission processes, the slave adapter returns a response signal through the corresponding channel, and the corresponding host adapter receives the response signal through handshake.

[0048] Example

[0049] The present invention is finally implemented by simulation on the VCS platform to verify the reading and writing process of the bus. The following is a description of the reading and writing process.

[0050] During the write process, the signal timing diagram at the host adapter side refers to Figure 8It should be noted that the prefix m of the bus port represents the host in the bus system. During the transmission, the actual host sends a write request at T2 according to the actual transmission requirements, and pulls up the mi_req signal, transmits the write address (mi_addr) and the control information (mi_control) to the corresponding host adapter. In this embodiment, the write address (mi_addr) is set to 0x1000_0000, and the control information (mi_control) is set to 0x44D, that is: do not use the single instruction mode; the Burst length is 4; 4 data are transmitted; the Burst width is 8 bits; the Burst type is address unchanged transmission; the host ID is 1. After receiving the request signal, the host adapter returns the mi_ack signal at T3, and completes the handshake transmission of the mi_req signal and the mi_ack signal at T4. After that, the host adapter sends an arbitration request to the arbitrator, and pulls up the m_mbi_grant_req signal at T4 and passes the m_mbi_data_size signal, waiting for the arbitration return signal (m_mbi_grant and m_mbi_grant_valid). After the arbitrator completes the arbitration, it returns the arbitration signal (m_mbi_grant and m_mbi_grant_valid) to the host adapter at T5. The host adapter writes the arbitration return information (00000011) into the corresponding bit width of the control information, and sends the address (m_mbi_addr) and control information (m_mbi_control) to the interconnection module through the bus interface at T6. The address and control information in the interconnection module are selected by the multiplexer, and the address and control information of the selected host adapter are sent to the shared channel of the address and control information.

[0051] During the writing process, refer to the signal timing diagram of the slave adapter end Fig. 9It should be noted that the prefix s of the bus port represents the slave in the bus system. During the transmission, after the corresponding slave adapter receives the chip select signal (s_mbi_sel) at time T2, it receives the address (s_mbi_addr) and control information (s_mbi_control) from the shared channel, and completes the handshake transmission of the address and control channels at time T4. Then the host adapter starts to receive the first write data from the actual host through the handshake protocol at time T5. The slave converter receives the write data from the shared data channel of the No. 0 (s_mbi_port0_wdata) and No. 1 (s_mbi_port1_wdata) transmission units according to the [25:18] bit information in the control information (s_mbi_control), and splices the two scattered 4-bit write data into 32-bit write data in sequence. Finally, the slave adapter sends the address (si_addr), control information (si_control) and write data (si_wdata) to the actual slave at time T6 according to the Burst type, completing a write data transmission. After completing a write data transmission, the host adapter receives the next write data from the actual host. Since the present invention adopts burst transmission, it is not necessary to resend the address and control information when sending the second write data, but directly send the write data. After the slave adapter receives the write data, it sends the address, control information, and write data to the actual slave according to the Burst type to complete the second write data reception. After the write data is sent 4 times in this way, the write data process is completed. The slave adapter returns the response data at time T15, and sends the response data to the shared channel through the interconnection module. The host adapter receives the response signal, decodes the response signal, and sends the write data completion signal to the actual host to complete the entire write data process.

[0052] During the read process, the signal timing diagram at the host adapter side refers to Fig.10 , the actual host sends a read request (mi_req), read address (mi_addr) and control information (mi_contr) to the corresponding host adapter at time T2 according to the actual transmission needs. Similar to the write process, in this example, the read address is set to 0x1000_0000, and the control information is set to 0x440C, specifically: do not use single instruction mode; Burst length is 4; transmit 4 data; Burst width is 8 bits; Burst type is address unchanged transmission; host ID is 1. On the host adapter side, the sending of address and control information in the read process is the same as the write process, and is sent through the address channel and control information channel.

[0053] During the read process, the signal timing diagram at the host adapter side refers to Fig.11. At the slave adapter end, after receiving the address (s_mbi_addr) and control information (s_mbi_control) at T2, the slave adapter sends the si_r_req signal, read address (si_addr) and control information (si_contr) to the actual slave at T4, and waits for the actual slave to return the si_r_ack signal and read data (si_rdata). After receiving the read data at T5, the slave adapter splits the lower 8 bits of the 32-bit read data into two 4-bit data according to the information of the [25:18] bits in the control information (s_mbi_control), and sends the read data to the shared channel of the interconnection module through the No. 0 (s_mbi_port0_rdata) and No. 1 (s_mbi_port0_rdata) transmission units at T6, waiting for the corresponding host adapter to receive the read data. The host adapter receives two 4-bit read data from transmission units 0 and 1 according to the arbitration information, and combines the two 4-bit data into 32-bit read data from the low bit, and finally sends the 32-bit read data to the actual host through the handshake protocol to complete a read data transmission. The slave adapter starts the second read data transmission, repeating the previous process, and transmits the 4 read data through transmission units 0 and 1 on the bus. After completing the read data transmission, the slave adapter starts to return the response signal and transmits the response data to the host adapter through the shared response channel to complete the entire read process.

Claims

1. An on-chip bus with adjustable bit width and channels, characterized in that: It comprises a host adapter, an arbitrator, an interconnection module and a slave adapter; the interconnection module comprises a bidirectional data channel, an address channel, a control information channel and a response channel, wherein the data transmission bit width in the bidirectional data channel is adjustable from 4 bits to 32 bits; the host adapter is connected to the host, the interconnection module and the arbitrator respectively, the host adapter allocates the data transmission bit width according to the host control signal and the arbitration information, and then establishes the data path between the host adapter and the slave adapter in a handshake transmission manner through the interconnection module; the slave adapter is connected to the interconnection module and the slave respectively; the method for the arbitrator to arbitrate is to set a transmission unit allocation module in the arbitrator, the arbitration information sent by the host adapter comprises the state of the state machine in the host adapter, the data transmission width and the arbitration request, and the arbitrator dynamically allocates the address channel, the control information channel and the bidirectional data channel through the transmission unit allocation module according to the current channel occupancy; The bidirectional data channel includes a 32-bit write data channel and a 32-bit read data channel, the address channel is 32 bits, the control information channel is 32 bits, and the response channel is 8 bits; the write data channel is defined as a transmission unit with every 4 bits, so that the write data channel is defined as 8 write data channel transmission units and numbered respectively, and the same operation is performed on the read data channel, thereby obtaining 8 independent bidirectional data transmission units, and establishing data paths for multiple pairs of host adapters and slave adapters at the same time.

2. The on-chip bus with adjustable bit width and channels according to claim 1, characterized in that: The arbitrator is connected to all host adapters and arbitrates the arbitration request of each host adapter respectively. The arbitration return information is the allocation status of 8 bidirectional data transmission units.

3. The on-chip bus with adjustable bit width and channels according to claim 2, characterized in that: During the data transmission process, the host adapter reads and writes data from the allocated data transmission unit according to the arbitration information, and the slave adapter also reads and writes data from the allocated data transmission unit according to the arbitration information.

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