Imaging system capable of selective readout for visible-infrared image capture

Abstract

An imaging system capable of selective readout for visible-infrared image capture. An imaging system includes a sensor die and a logic die. The sensor die includes a plurality of pixels arranged in a number of rows and a number of columns, the plurality of pixels arranged in a number of rows and a number of columns and including at least a first pixel and a second pixel positioned in a first row included in the rows. The sensor die includes a first transfer control line associated with the first row, the first transfer control line coupled to both a first transfer gate of the first pixel and a second transfer gate of the second pixel. The logic die includes a first storage capacitor associated with the first pixel and a second storage capacitor associated with the second pixel, a first storage control line coupled to a first storage gate associated with the first pixel, and a second storage control line coupled to a second storage gate associated with the second pixel.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to image sensors, and in particular, but not exclusively, to CMOS image sensors and their applications. BACKGROUND

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of sub-devices, it is desirable to enhance the functionality, performance metrics, etc. of the image sensors in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through device architecture design as well as image acquisition processing.

[0003] A typical image sensor operates in response to image light reflected from an external scene incident on the image sensor. The image sensor includes an array of pixels having a photosensitive element (e.g., a photodiode) that absorbs a portion of the incident image light and generates image charge upon absorption of the image light. The image charge photo-generated by a pixel can be measured as an analog output image signal on a column bitline that varies in accordance with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out from the column bitline as an analog image signal and converted to a digital value to produce a digital image (i.e., image data) representative of the external scene. SUMMARY

[0004] Embodiments of the present disclosure provide an imaging system comprising: a sensor wafer including: a plurality of pixels arranged in a number of rows and a number of columns, the plurality of pixels including at least a first pixel and a second pixel positioned in a first row included in the rows, wherein each pixel included in the plurality of pixels includes a respective photodiode configured to accumulate image charge in response to incident light; and a first transfer control line associated with the first row, wherein the first transfer control line is coupled to both a first transfer gate of the first pixel and a second transfer gate of the second pixel; and a logic wafer coupled to the sensor wafer, the logic wafer including: a plurality of storage capacitors, each storage capacitor associated with a respective one of the plurality of pixels of the sensor wafer, wherein the plurality of storage capacitors includes a first storage capacitor associated with the first pixel and a second storage capacitor associated with the second pixel; a first storage control line coupled to a first storage gate associated with the first pixel, wherein the first storage gate is included in a first storage transistor coupled to the first storage capacitor; and a second storage control line coupled to a second storage gate associated with the second pixel, and wherein the second storage gate is included in a second storage transistor coupled to the second storage capacitor.

[0005] Another embodiment of the disclosure provides a logic wafer for an imaging system, the logic wafer comprising: a plurality of storage capacitors, each storage capacitor configured to store an image signal associated with a respective one of a plurality of pixels, wherein the plurality of storage capacitors includes a first storage capacitor associated with a first pixel included in a first row of the plurality of pixels and a second storage capacitor associated with a second pixel included in the first row of the plurality of pixels; a first storage control line coupled to a first storage gate associated with the first pixel, wherein the first storage gate is included in a first storage transistor coupled to the first storage capacitor; and a second storage control line coupled to a second storage gate associated with the second pixel, and wherein the second storage gate is included in a second storage transistor coupled to the second storage capacitor. BRIEF DESCRIPTION OF DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein the like reference numerals refer to like elements unless otherwise specified. Not all elements of each figure are necessary for understanding the inventive principles, and not all elements of each figure are shown in order not to obscure such principles. The figures are not drawn to scale, emphasis instead being placed upon illustrating the principles of the described implementations.

[0007] Figure 1A An example imaging system including a sensor wafer and a logic wafer providing selective readout for visible-infrared image capture is illustrated in accordance with the teachings of this disclosure.

[0008] Figure 1B A cross-sectional view of a sensor wafer included in an imaging system in accordance with the teachings of this disclosure is illustrated. Figure 1A

[0009] Figure 1C A top view of a sensor wafer included in an imaging system in accordance with the teachings of this disclosure is illustrated. Figure 1A

[0010] Figure 1D An example pixel circuit for an individual pixel included in the imaging system illustrated in Figure 1A

[0011] Figure 1E An example pixel control line arrangement for the sensor wafer illustrated in Figure 1A

[0012] Figure 1F An example pixel control line arrangement for the sensor wafer illustrated in Figure 1A ​​​​An example pixel control line arrangement of a logic die illustrated in the middle.

[0013] Figure 2A An example operational method for an imaging system that can be selectively read out for visible-infrared image capture is illustrated in accordance with the teachings of this disclosure.

[0014] Figure 2B An example timing diagram for capturing visible-infrared image frames via selective readout during short and long exposure periods is illustrated in accordance with the teachings of this disclosure.

[0015] Figure 3A An example pixel cell circuit diagram of a sensor die is illustrated in accordance with the teachings of this disclosure.

[0016] Figure 3B An example pixel cell circuit diagram of a logic die is illustrated in accordance with the teachings of this disclosure.

[0017] Figure 3C to 3D An example operational method for an imaging system that can be selectively read out for visible-infrared image capture is illustrated in accordance with the teachings of this disclosure.

[0018] Figure 4 An example pixel control line arrangement of a logic die illustrated in the middle.

[0019] Figure 5A An example pixel circuit for an imaging system is illustrated in accordance with the teachings of this disclosure.

[0020] Figure 5B An example timing diagram for capturing image frames representing an external scene via selective readout during long and short exposure periods of the image frames is illustrated in accordance with the teachings of this disclosure. Figure 5A An example pixel control line arrangement of a sensor die of an imaging system illustrated in the middle.

[0021] Figure 5C An example timing diagram for capturing visible-infrared image frames via selective readout during short and long exposure periods is illustrated in accordance with the teachings of this disclosure. Figure 5A An example pixel control line arrangement of a logic die illustrated in the middle.

[0022] Figure 5D An example timing diagram for capturing image frames representing an external scene via selective readout during long and short exposure periods of the image frames is illustrated in accordance with the teachings of this disclosure.

[0023] Figure 6 A block diagram of an imaging system that can be selectively read out for visible-infrared image capture is illustrated in accordance with the teachings of this disclosure. DETAILED DESCRIPTION

[0024] Embodiments of apparatuses, systems, and methods related to image sensors that can be selectively read out for visible-infrared image capture are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the technology described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring aspects of the specific aspects.

[0025] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearance of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0026] Throughout this specification, several technical terms are used. Such terms are to take on their ordinary meaning in the art unless otherwise specifically defined herein or the context of their use clearly dictates otherwise. It should be noted that throughout this document, element names and notations can be used interchangeably (e.g., Si for silicon); however, both have the same meaning.

[0027] Embodiments of imaging systems and methods thereof that can be selectively read out for visible-infrared image capture are described herein. In some embodiments, individual image sensors, which can have a stacked chip approach, are used to capture visible images (e.g., color) and non-visible images (e.g., near-infrared, infrared, short-wave infrared, far-infrared, or other frequency ranges outside the visible spectrum of electromagnetic radiation) of an external scene. This can be accomplished, at least in part, by an image sensor architecture that provides selective readout to storage nodes of the image sensor. Specifically, image frames can be captured using a plurality of exposure periods, including a long exposure period associated with visible image light and a short exposure period associated with non-visible image light (e.g., near-infrared, infrared, short-wave infrared, far-infrared, or other frequency ranges outside the visible spectrum of electromagnetic radiation). In some embodiments, storage control lines associated with the storage nodes can be configured to provide independent readout to the storage nodes even when individual storage nodes are associated with a common row, such that each image frame captured by the image sensor can include image data associated with both the long exposure period and the short exposure period.

[0028] Advantageously, when capturing a given image frame with an image sensor or imaging system in conjunction with selective readout to a storage node, the long and short exposure periods allow for a reduction in cross-talk between visible and non-visible image data. In some embodiments, the duration of the short exposure period can be tailored based on the time taken for the non-visible light source to illuminate the external scene (or more specifically, the total time for the non-visible light to illuminate the external scene and reflect back onto the image sensor or imaging system), which can then be used to increase the duration of the long exposure period. In other words, the duration ratio of the long exposure period relative to the short exposure period can be increased to avoid sacrificing the sensitivity of the visible image data while maintaining a sufficient duration of the short exposure period to produce non-visible image data. It should be appreciated that the non-visible image data can be used to produce an illuminated image that does not interfere with the human eye or vision, a depth map of the external scene, and / or determine a distance of one or more pixels from the external scene. Thus, by reducing the duration of the short exposure period, the effect of ambient light on the non-visible image data can be reduced or otherwise mitigated. Still further, the increased ratio between the long and short exposure periods mitigates the blurring of flicker present in the external scene. This is particularly useful during video capture where image frames are captured consecutively and the non-visible image of the external scene is desired for each of the image frames.

[0029] While most of the embodiments described herein are discussed in the context of capturing image frames that include visible and non-visible image data, it should be appreciated that other embodiments can capture image frames with only visible image data and / or only non-visible image data over multiple exposure periods. In particular, the particular embodiments described herein can be used to capture a high dynamic range of visible or non-visible images using multiple exposure periods.

[0030] Figure 1A An example imaging system 100 including a sensor die 101 and a logic die 151 that provide for selective readout for visible-infrared image capture in accordance with the teachings of this disclosure is illustrated. The sensor die 101 includes a plurality of pixels 105, drivers 111, and an input / output (I / O) interface 109. The logic die 151 includes pixel circuitry 153, column circuitry 155, a v-scan 157, an I / O interface 159, and control circuitry 161. In the illustrated embodiment, the imaging system 100 includes a stacked complementary metal-oxide-semiconductor (CMOS) image sensor formed at least in part by the sensor die 101 (e.g., a first die) and the logic die 151 (e.g., a second die) stacked and coupled together (e.g., electrically and / or physically) in a stacked-chip arrangement. It should be appreciated that while the illustrated embodiment includes a stacked-chip arrangement, other embodiments can include a monolithic CMOS image sensor formed on a single die. In the illustrated embodiment, the sensor die 101 includes a plurality of pixels 105, drivers 111, and an I / O interface 109. The logic die 151 includes pixel circuitry 153, column circuitry 155, a v-scan 157, an I / O interface 159, and control circuitry 161. In the illustrated embodiment, the sensor die 101 and the logic die 151 are stacked in a stacked-chip arrangement. In other embodiments, the sensor die 101 and the logic die 151 can be formed on a single die. Figure 1AThe sensor die 101 and the logic die 151 are illustrated in the middle, but the stacked chip approach of the imaging system 100 can include additional dies that can be integrated into the stacked chip approach. Additionally, it should be appreciated that Figure 1A The views presented in the middle can omit particular elements of the imaging system 100 to avoid obscuring details of the disclosure (e.g., as Figure 6 The light source illustrated in the middle that emits electromagnetic radiation toward an external scene, Figure 6 Other components illustrated in the middle and / or other components not explicitly illustrated). In other words, not all elements of the imaging system 100 can be labeled, illustrated, or otherwise shown within Figure 1A It is further appreciated that, in some embodiments, the imaging system 100 can not necessarily include all of the elements shown.

[0031] Figure 1A The stacked chip approach illustrated in the middle distributes components of the imaging system 100 across multiple dies. Specifically, the sensor die 101 includes light-sensitive elements (e.g., photodiodes, pinned photodiodes, etc.) included in the plurality of pixels 105, while the logic die 151 includes pixel circuitry 153 associated with the plurality of pixels 105 (see, e.g., Figure 1D In other words, the logic die 151 offloads at least a portion of the circuitry associated with the plurality of pixels 105 of the sensor die 101, which advantageously provides additional space on the sensor die 101. The plurality of pixels 105 can be coupled to the pixel circuitry 153 through one or more hybrid bonds, through-silicon vias, combinations thereof, or other suitable circuit coupling techniques. In some embodiments, the space saved on the sensor die 101 by offloading circuitry to the logic die 151 can be repurposed to increase the size of individual photodiodes included in the plurality of pixels 105 to allow for increased pixel size, density, sensitivity, combinations thereof, and the like. Additionally or alternatively, functionality of the imaging system 100 can be facilitated because the logic die 151 can have space for additional components or circuitry that can not otherwise fit on an individual die or substrate containing both the plurality of pixels 105 and the pixel circuitry 153 without affecting performance and / or functionality of the imaging system 100.

[0032] In the illustrated embodiment, imaging system 100 includes a sensor wafer 101 and a logic wafer 151 coupled to sensor wafer 101. Sensor wafer 101 includes a plurality of pixels 105 including individual pixels arranged in a number of rows (e.g., R1, R2, R3,... RY) and a number of columns (e.g., C1, C2, C3,... CX) to form a pixel array. The plurality of pixels 105 can include any number of pixels, including at least a first pixel and a second pixel. In the same or other embodiments, the plurality of pixels 105 can further include a third pixel and a fourth pixel. Collectively, the first pixel, the second pixel, the third pixel, and the fourth pixel can form a minimum repeating unit of sensor wafer 101, or more specifically, the plurality of pixels 105. In some embodiments, the first pixel and the second pixel share a first common row (e.g., each of the first pixel and the second pixel can be arranged in a respective one of a number of rows, such as R1, R2, R3, or any other of the rows included therein). In the same or other embodiments, the third pixel and the fourth pixel share a second common row different from the first common row (e.g., each of the third pixel and the fourth pixel can be arranged in a respective one of a number of rows, such as R1, R2, R3, or any other of the rows included therein other than the first common row). In some embodiments, the first pixel and the second pixel are adjacent such that there are no intervening pixels between the first pixel and the second pixel along the first common row. In the same or other embodiments, the third pixel and the fourth pixel are adjacent such that there are no intervening pixels between the third pixel and the fourth pixel along the second common row. In the same or other embodiments, the first common row and the second common row are adjacent such that there are no intervening rows in the rows between the first common row and the second common row.

[0033] As discussed above, each given pixel included in the plurality of pixels 105 can include a single or multiple photosensitive elements (e.g., one or more photodiodes) configured to generate a response to incident light (e.g., accumulate photo-generated image charges), which can be transferred to a corresponding floating diffusion region associated with the given pixel. In some embodiments, the plurality of pixels 105 of the sensor die 101 are operated in response to a global shutter signal. In other words, in response to the global shutter signal, accumulated image charges can be transferred from respective photodiode regions included in the plurality of pixels 105 to corresponding floating diffusion regions. In some embodiments, the pixel circuitry 153 includes a plurality of storage nodes (e.g., one or more reset storage capacitors and one or more storage capacitors to read out the levels of the floating diffusion regions after reset and photo-carrier accumulation, respectively) each associated with one or more pixels included in the plurality of pixels 105. In some embodiments, the plurality of storage nodes are configured to store image signal levels and reset signal levels for each of the plurality of pixels 105, respectively. In some embodiments, the logic die 151 can operate on a row-by-row basis. In other words, image data can be generated based on the plurality of storage nodes of the logic die 151 read out on a row-by-row basis, as opposed to being read out simultaneously from the global shutter signal of the sensor die 101. It should be appreciated that, in some embodiments, the pixel circuitry 153 is configured to provide selective readout from the plurality of storage nodes, facilitating capturing image frames for multiple exposure periods. Advantageously, this approach allows for the benefits of global shuttering (e.g., mitigated rolling shutter artifacts) while still maintaining the low noise benefits facilitated by row-by-row readout from the plurality of storage nodes.

[0034] As Figure 1A illustrated in FIG. 1, the sensor die 101 and the logic die 151 include various analog and / or digital support circuitry for the imaging system 100. In some embodiments, the support circuitry includes, but is not limited to, row and column decoders and drivers (e.g., the drivers 111), analog signal processing chains, digital imaging processing blocks, memory, timing and control circuitry (e.g., the control circuitry 161), input / output (I / O) interfaces (e.g., the I / O interfaces 109 and 159), a vertical scanner (e.g., the v-scan 157), sample-and-hold circuitry, amplifiers, analog-to-digital converter circuitry (e.g., the column circuitry 155), digital processors, and any other embodiments of logic circuitry suitable for the functionality of the imaging system 100.

[0035] Figure 1B illustrates a cross-sectional view 100-A of the sensor die 101 included in the imaging system 100 of Figure 1A FIG. 1, in accordance with the teachings of this disclosure. More specifically, the cross-sectional view 100-A is shown to include a plurality of pixels 105, a plurality of storage nodes 107, and a plurality of column circuitry 155, as described above. Figure 1AA portion of a cross-section of a row of pixels (e.g., a first row) included in a pixel array formed by the plurality of pixels 105 illustrated in the middle. Referring back to Figure 1B The plurality of pixels 105 includes a plurality of photodiodes 104 formed in a semiconductor material 102 (e.g., a silicon wafer or substrate, a silicon-germanium alloy, germanium, a silicon carbide alloy, an indium gallium arsenide alloy, any other alloy formed from a group III-V compound, other semiconductor materials or alloys, combinations thereof, or a bulk substrate, corresponding to or otherwise included in the sensor wafer 101), a plurality of color filters 106 (e.g., red, green, blue, infrared, clear, transparent, cyan, magenta, yellow, black, or any other color filter to filter visible or non-visible light that would otherwise be incident on an optically aligned photodiode included in the plurality of photodiodes 104), and a plurality of microlenses 108. In some embodiments, each pixel (e.g., the first pixel 105-1, the second pixel 105-2, or any other unlabeled individual pixel included in the plurality of pixels 105) includes an optically aligned stack of at least one of the plurality of photodiodes 104, at least one of the plurality of color filters 106, and at least one of the plurality of microlenses 108. As illustrated, the plurality of color filters 106 is disposed between the plurality of photodiodes 104 and the plurality of microlenses 108. It should be appreciated that view 100-A illustrates an individual row included in a pixel array formed by the plurality of pixels 105, each of which can have "N" elements. In other words, each of the number of rows can have N photodiodes included in the plurality of photodiodes 104, N color filters included in the plurality of color filters 106, and N microlenses included in the plurality of microlenses 108, where N corresponds to an integer greater than 2. Thus, photodiode 104-N, color filter 106-N, and microlens 108-N each correspond to the Nth element within the row illustrated in view 100-A. Thus, in the illustrated embodiment, there is a one-to-one correspondence between photodiodes included in the plurality of photodiodes 104, color filters included in the plurality of color filters 106, and microlenses included in the plurality of microlenses 108. However, in other embodiments, there can be a correspondence other than one-to-one. In one embodiment, an individual microlens can be optically aligned with (e.g., share) more than one color filter included in the plurality of color filters 106 and / or more than one photodiode included in the plurality of photodiodes 104.

[0036] In the illustrated embodiment, a first pixel 105-1, comprising a plurality of pixels 105, includes a first photodiode 104-1 included in a plurality of photodiodes 104 disposed in a first portion 102-1 of semiconductor material 102, a first color filter 106-1 (e.g., a blue color filter) included in a plurality of color filters 106, and a first microlens 108-1 included in a plurality of microlenses 108. As illustrated, the first photodiode 104-1, the first color filter 106-1, and the first microlens 108-1 are optically aligned with each other to form the first pixel 105-1. Adjacent to the first pixel 105-1 is a second pixel 105-2 (e.g., no intervening pixel between the first pixel 105-1 and the second pixel 102-2). The second pixel includes a second photodiode 104-2 contained in a plurality of photodiodes 104 disposed in a second portion 102-2 of semiconductor material 102, a second color filter 106-2 contained in a plurality of color filters 106 (e.g., an infrared or "IR" filter), and a second microlens 108-2 contained in a plurality of microlenses 108. It should be understood that in some embodiments, the IR filter (e.g., the second color filter 106-2 contained in the plurality of color filters 106 or any other IR filter) may correspond to a clear or transparent color filter that allows the transmission of near-infrared, infrared, or far-infrared light (e.g., light with wavelengths between 800 nm and 3000 nm). Therefore, it should be understood that in some embodiments, the IR filters included in the plurality of color filters 106 may not attenuate light within the visible range of the electromagnetic spectrum (e.g., approximately 300 nm to 800 nm). In other embodiments, the IR filters included in the plurality of color filters 106 attenuate incident light outside the infrared range of the electromagnetic spectrum (e.g., approximately 800 nm to 3000 nm) (e.g., via reflection, diffraction, absorption, or other means). It should be understood that color filters associated with the visible range of the electromagnetic spectrum (e.g., red, green, blue, or others) may attenuate incident light outside a specified color (e.g., a blue color filter attenuates visible light outside the region corresponding to the visible range of the electromagnetic spectrum of blue, a green color filter attenuates visible light outside the region corresponding to the visible range of the electromagnetic spectrum of green, etc.).

[0037] As discussed above, Figure 1A The imaging system 100 illustrated in the figure Figure 1BThe cross-sectional view 100-A illustrated in FIG. 1 A can not include all elements to avoid obscuring certain aspects of the disclosure. In some embodiments, the imaging system 100 can further include one or more doped semiconductor regions to form a plurality of photodiodes 104 (e.g., one or more photodiodes, pinned photodiodes, etc.), form isolation structures (e.g., shallow trench isolation structures disposed between adjacent photodiodes included in the plurality of photodiodes 104, deep trench isolation structures, etc.), metal grid structures (e.g., one or more metal structures disposed between adjacent color filters included in the plurality of color filters 106), an attenuation layer, an anti-reflective film, a filter, or other components in the semiconductor material 102.

[0038] Figure 1C FIG. 1 B illustrates a top view 100-B of a sensor wafer 101 included in an imaging system in accordance with the teachings of this disclosure. More specifically, the top view 100-B illustrates a pixel array formed by a plurality of pixels 105 illustrated in FIG. 1 A. Referring back to FIG. 1 A, the view 100-B illustrates the plurality of pixels 105 arranged in a number of rows (e.g., R1, R2, R3,... RY) and a number of columns (e.g., C1, C2, C3,... CY). The rows (e.g., R1, R2, R3, etc.) can be represented by the view 100-A illustrated in FIG. 1 A. For example, a cross-sectional view of the row “R2” illustrated in FIG. 1 A can correspond to the view 100-A illustrated in FIG. 1 A. Referring back to FIG. 1 A, the view 100-B illustrates the plurality of pixels 105 arranged in a number of columns (e.g., C1, C2, C3,... CY). The columns (e.g., C1, C2, C3, etc.) can be represented by the view 100-A illustrated in FIG. 1 A. For example, a cross-sectional view of the column “C2” illustrated in FIG. 1 A can correspond to the view 100-A illustrated in FIG. 1 A. Figure 1A Figure 1A Figure 1C Figure 1B Figure 1C Figure 1B Figure 1C Figure 1C Figure 1B Figure 1B ​​​​​​​​​The illustrated embodiment shows a first pixel (e.g., 105-B), a second pixel (e.g., 105-IR), a third pixel (e.g., 105-R), and a fourth pixel (e.g., 105-G). In the illustrated embodiment, the first pixel (e.g., 105-B), the second pixel (e.g., 105-IR), the third pixel (e.g., 105-R), and the fourth pixel (e.g., 105-G) are adjacent to each other to form in the imaging system (e.g., Figure 1A The first pixel unit (e.g., pixel unit 110) is included in a plurality of pixel units of the imaging system 100 illustrated herein. It should be understood that in some embodiments, different color filters included in a plurality of color filters 106 (e.g., 106-B, 106-IR, 106-R, and / or 106-G) may have different spectral responses to various wavelengths of light within the electromagnetic spectrum. In one embodiment, a second pixel (e.g., 105-IR) of the first pixel unit (e.g., pixel unit 110) is more sensitive to a first wavelength (e.g., one or more discrete wavelengths contained in the infrared range of the electromagnetic spectrum, such as any wavelength between 800 nm and 3000 nm) than the first pixel (e.g., 105-B, 105-G, and / or 105-R). In other words, the second transmittance of the first wavelength of the corresponding color filter (e.g., an IR color filter) included in the plurality of color filters 106 of the second pixel is greater than the first transmittance of the first wavelength of the corresponding color filter (e.g., a red, green, and / or blue color filter) included in the plurality of color filters 106 of the first pixel.

[0039] Figure 1D Diagram illustrating the use of the teachings of this disclosure. Figure 1A The illustration shows an example pixel circuit 150 for individual pixels 105-N included in the plurality of pixels 105 of the imaging system. More specifically, Figure 1DThe schematic diagram illustrated in FIG. illustrates pixel 105-N and associated pixel circuitry 153-N. For discussion purposes, the portion of circuitry included in pixel circuitry 153 that is associated with pixel 105-N and that is located in or on logic die 151 is referred to as pixel circuitry 153-N. However, it should be understood that in the illustrated embodiment, pixel 105-N also includes circuitry located on sensor die 101. Thus, as discussed in embodiments herein, the term "pixel" includes at least one photodiode included in a plurality of photodiodes and can further include circuitry, control lines, etc. associated with the at least one photodiode. In some embodiments, the at least one photodiode, circuitry, control lines are all located on or in a common substrate (e.g., sensor die 101). In the same or other embodiments, circuitry and control lines can be distributed across multiple substrates (e.g., sensor die 101 and logic die 151). Further, it should be understood that Figure 1D The circuit diagrams illustrated in FIG. are not necessarily meant to imply a particular physical location of elements within or on sensor die 101 and / or logic die 151.

[0040] As Figure 1D As illustrated in FIG., pixel 105-N includes photodiode 104-N (e.g., a pinned photodiode), transfer transistor TX including transfer gate 112, floating diffusion region 114, reset transistor RST1 including first reset gate 116, source follower transistor SF1, and select transistor SEL including select gate 118, each of which is disposed in, on, or otherwise included in sensor die 101. Pixel circuitry 153-N associated with pixel 105-N includes current source 122 including transistor CS and transistor CSW, second reset transistor RST2 including second reset gate 128, reset storage transistor SSW R , reset storage capacitor C R , storage transistor SSW S , storage capacitor C S , row select transistor RS including row select gate 134, and second source follower transistor SF2, each of which is disposed in, on, or otherwise included in logic die 151. As illustrated, reset storage transistor SSW R , reset storage gate 130, reset storage capacitor C R , storage transistor SSW S , storage gate 132, and storage capacitor C SA storage node 124 associated with the pixel 105-N is formed. Note that the sensor die 101 can be coupled to the logic die 151 on a per-pixel basis via a plurality of interconnects (hybrid pads, through-silicon vias, or other suitable circuit coupling technology) including the interconnect 120. In other words, each pixel (e.g., Figure 1A An individual pixel of the plurality of pixels 105 illustrated in FIG. 1A, such as the pixel 153-N illustrated in FIG. 1B, is individually coupled to associated pixel circuitry (e.g., Figure 1D A portion of the pixel circuitry 153 associated with an individual pixel of the plurality of pixels 105 illustrated in FIG. 1A, such as the pixel circuitry 153-N illustrated in FIG. 1B. The circuitry of the pixel 105-N included in the sensor die 101 is electrically coupled to the pixel circuitry 153-N via the interconnect 120. Figure 1D Figure 1A A portion of the pixel circuitry 153 associated with an individual pixel of the plurality of pixels 105 illustrated in FIG. 1A, such as the pixel circuitry 153-N illustrated in FIG. 1B. The circuitry of the pixel 105-N included in the sensor die 101 is electrically coupled to the pixel circuitry 153-N via the interconnect 120. Figure 1D

[0041] As illustrated, a transfer transistor TX is coupled between the photodiode 104-N and a floating diffusion region 114. The floating diffusion region 114 is coupled between the transfer transistor TX, a reset transistor RST1, and a source follower transistor SF1. The source follower transistor SF1 is coupled between the floating diffusion region 114 and a select transistor SEL. The floating diffusion region 114 is coupled to a gate of the source follower transistor SF1. The interconnect 120 is coupled between the floating diffusion region 114 and a storage node 124 (e.g., indirectly via the source follower transistor SF1 and the select transistor SEL). The storage node 124 is further coupled between the interconnect 120 and a second source follower transistor SF2. A reset storage transistor SSW R is coupled between the reset storage capacitor C R and the second reset transistor RST2. The storage capacitor SSW S is coupled between the storage capacitor C S and the second reset transistor RST2. The second source follower transistor SF2 is coupled between a row select transistor RS and the storage node 124. The row select transistor RS is coupled between a bit line and the storage node 124.

[0042] It should be appreciated that in the illustrated embodiment, each transistor (e.g., the transfer transistor TX, the reset transistor RST1, the select transistor SEL, the transistor CS, the transistor CSW, the reset storage transistor SSW R , the storage transistor SSW S ​​The gate terminals of the row select transistor RS (e.g., transfer gate 112, first reset gate 116, select gate 118, second reset gate 128, unmarked gate of transistor CS, unmarked gate of transistor CSW, reset storage gate 130, storage gate 132, and row select gate 134) may be coupled to one or more control lines (e.g., see [link to relevant documentation]). Figure 1E and Figure 1F This is used to control the operation of the imaging system 100. Specifically, the control line may be coupled to a controller, a control circuit system (e.g., see...). Figure 1A The control circuitry 161 illustrated herein, or other circuitry not explicitly illustrated, controls the operation of the imaging system 100. In some embodiments, common elements along a common row may share control lines. In the same or other embodiments, according to embodiments of this disclosure, specific elements may be configured to have individual control lines to provide selective readout.

[0043] In some embodiments, included Figure 1A Each of the multiple pixels 105 illustrated in the diagram has Figure 1D The corresponding pixel circuit system is illustrated in the diagram. Therefore, each pixel contained in the plurality of pixels 105 is associated with a plurality of storage nodes (not illustrated but contained in...). Figure 1A Individual storage nodes in the pixel circuit system 153 illustrated in the figure are associated (e.g., Figure 1D The storage node 124 illustrated herein is associated with an individual pixel among a plurality of pixels 105 corresponding to pixels 105-N. Therefore, the logic chip 151 includes a plurality of storage capacitors (e.g., a storage capacitor C for each pixel contained in the plurality of pixels 105). S Each storage capacitor is associated with a corresponding pixel in a plurality of pixels 105 of the sensor chip 101. The plurality of storage capacitors includes a first storage capacitor associated with a first pixel and a second storage capacitor associated with a second pixel (e.g., the first and second storage capacitors included in the plurality of storage capacitors are respectively associated with corresponding pixels in the plurality of pixels 105). Figure 1B The pixels 105-1 and 105-2 illustrated herein are associated with or otherwise electrically coupled to each other. Similarly, the logic chip 151 includes a plurality of reset storage capacitors (e.g., a reset storage capacitor C for each pixel included in the plurality of pixels 105). R At least one of the plurality of pixels 105 in the sensor chip 101, each reset storage capacitor is associated with a corresponding pixel in the plurality of pixels 105 of the sensor chip 101. The plurality of reset storage capacitors include those associated with the first pixel (e.g., Figure 1B The first reset storage capacitor associated with pixel 105-1 (illustrated in the figure) and the second pixel (e.g., Figure 1B The second reset storage capacitor is associated with pixel 105-2 as illustrated in the diagram.

[0044] During the capture of a given image frame representing an external scene (e.g., a first image frame included in a plurality of image frames), in response to a transfer signal applied (e.g., asserted) to transfer gate 112 (e.g., via a transfer control line) to turn on transfer transistor TX, image charge accumulated by photodiodes 104-N during an exposure cycle (e.g., a short exposure cycle, a long exposure cycle, or others) associated with the given image frame can be transferred to floating diffusion regions 114. In some embodiments, the transfer signal may cause image charge accumulated in each of the plurality of photodiodes 104 to be simultaneously transferred to a corresponding floating diffusion region associated with a plurality of pixels 105. Source follower transistor SF1 is coupled to photodiodes 104-N to generate an image signal (e.g., a long exposure image signal, a short exposure image signal, or others, depending on the exposure cycle associated with the given image frame being read out) in response to image charge accumulated by photodiodes 104-N during an exposure cycle (e.g., a long exposure cycle, a short exposure cycle, or other exposure cycles). In the illustrated embodiment, the image signal is read out to storage node 124, or more specifically, via storage transistor SSW. S Read out to the corresponding storage capacitor C S In the same or other embodiments, the reset transistor RST1 can be used to reset the charge in the floating diffusion region 114 and, as appropriate, the charge in the photodiode 104-N (e.g., reset to VDD or another suitable predetermined potential). During the reset, a reset signal (e.g., a long exposure reset signal, a short exposure reset signal, or others, depending on the exposure period associated with the given image frame being read out) can be read out and stored in the corresponding reset storage capacitor C. R In some embodiments, for each pixel included in a plurality of pixels 105, a reset signal (e.g., correlated double sampling) may be subtracted from the image signal to produce image data corresponding to or otherwise representing an image frame. In the same or other embodiments, current source 122, in conjunction with reset transistor RST2, may be used to discharge a capacitor (e.g., a reset storage capacitor C). R and / or storage capacitor C S The image signal and reset signal can be read out on a row-by-row basis to the column circuitry (e.g., via a row select transistor, or via a row select signal applied to row select gate 134) using a row select transistor. Figure 1A The diagram illustrates the bit lines of the column circuit 155 to generate image data. It should be understood that additional details related to the operation of the imaging system 100 have been omitted, which will be discussed in more detail in subsequent chapters.

[0045] Figure 1E Diagram illustrating the use of the teachings of this disclosure. Figure 1A An exemplary pixel control line arrangement 152 of the pixel unit (e.g., pixel unit 110) of the sensor chip 101 illustrated herein. As previously discussed, the illustrated pixel unit 110 includes red (105-R), green (105-G), blue (105-B), and infrared (105-IR) pixels included in a plurality of pixels 105, each pixel having as shown in the figure. Figure 1D The corresponding circuit system is illustrated in the diagram. As illustrated, blue pixel 105-B (e.g., the first pixel) and infrared pixel 105-IR (e.g., the second pixel) are arranged in row "n" (e.g., the first row). Red pixel 105-R (e.g., the third pixel) and green pixel 105-G (e.g., the fourth pixel) are arranged in row "n+1" (e.g., the second row), which is different from row "n". It should be understood that the first row and the second row are adjacent to each other (e.g., there is no intervening row between the first row and the second row). Each pixel contained in pixel unit 110 has its own corresponding circuit system instance on sensor chip 101 (e.g., see [reference]). Figure 1D This is controlled by a corresponding control line with an appropriate label name. For example... Figure 1E As illustrated in the diagram, the control line arrangement 152 includes a first reset control line RST1(n)154, a first transfer control line TX(n)156, a first selection control line SEL(n)158, a second reset control line RST1(n+1)160, a second transfer control line TX(n+1)162, and a second selection control line SEL(n+1)164. Figure 1E The general format of the control line names illustrated in the diagram indicates the coupled gate, followed by the associated row. For example, the label "TX(n)" for control line TX(n) 156 indicates that control line TX(n) 156 can be coupled to the transfer gate of each pixel associated with row n (e.g., Figure 1D The transfer gate 112 illustrated in the figure, the label "RST1(n)" on the first reset control line RST1(n) 154 indicates that the first reset control line RST1(n) 154 can be coupled to the first reset gate of each pixel associated with row n (e.g., Figure 1D The first reset gate 116 is illustrated in the diagram. Connection nodes, indicated by black circles, indicate connections to designated circuit elements associated with the corresponding pixels. For example, if in one or more pixels (e.g., as shown in the diagram)... Figure 1EA connection node exists on control line TX(n) 156 if the control line TX(n) 156 is coupled to the transfer gate of each of the one or more pixels (i.e., the transfer gate 112 of both the pixel 105-B and the pixel 105-R). It should be appreciated that when a connection node is omitted for a corresponding control line as it passes through an associated pixel, then the corresponding control line is not coupled to the specified circuit element.

[0046] Thus, in the illustrated embodiment, a first reset control line RST1(n) 154 is electrically coupled to a first reset gate 116 of a reset transistor RST1 included in each of a first pixel 105-B and a second pixel 105-IR. A first transfer control line TX(n) 156 and a first select control line SEL(n) 158 are also located along row n (e.g., the first row), which are each coupled to a transfer transistor (e.g., Figure 1D (e.g., the transfer gate 112) of the pixel 105-B (e.g., the first pixel), the pixel 105-IR (e.g., the second pixel), and optionally additional pixels (not illustrated) that can be included in row n. Figure 1D (e.g., the select gate 118) of the pixel 105-B (e.g., the first pixel), the pixel 105-IR (e.g., the second pixel), and optionally additional pixels (not illustrated) that can be included in row n. Figure 1D (e.g., the select gate 118) of the pixel 105-B (e.g., the first pixel), the pixel 105-IR (e.g., the second pixel), and optionally additional pixels (not illustrated) that can be included in row n. Figure 1D (e.g., the select gate 118) of the pixel 105-B (e.g., the first pixel), the pixel 105-IR (e.g., the second pixel), and optionally additional pixels (not illustrated) that can be included in row n. Figure 1D (e.g., the select gate 118) of the pixel 105-B (e.g., the first pixel), the pixel 105-IR (e.g., the second pixel), and optionally additional pixels (not illustrated) that can be included in row n.

[0047] Similarly, a row n+1 (e.g., the second row) that includes a third pixel 105-R, a fourth pixel 105-G, and optionally additional pixels (not illustrated) includes a second reset control line RST1 160(n+1), a second transfer control line TX(n+1) 162, and a second select control line SEL(n+1) 164, which are each coupled to respective gates (e.g., transfer gates, first reset gates, and select gates, such as the transfer gate 112, the first reset gate 116, and the select gate 118 illustrated in Figure 1E (e.g., the transfer gate 112, the first reset gate 116, and the select gate 118 illustrated in Figure 1D (e.g., the transfer gate 112, the first reset gate 116, and the select gate 118 illustrated in

[0048] In some embodiments, adjacent control lines included in each set of control lines associated with a given row (e.g., the first reset control line RST1(n) 154, the first transfer control line TX(n) 156, and the first selection control line SEL(n) 158, each associated with row n) may be separated from each other by a common separation distance (e.g., Figure 1E The separation distance 166 is illustrated in the figure. In the same or other embodiments, the control lines of adjacent rows (e.g., rows n and n+1) may be symmetrical about axis 168 (e.g., the first sensor chip control line group containing the first reset control line RST1(n) 154, the first transfer control line TX(n) 156, and the first selection control line SEL(n) 158 of row n is symmetrical about axis 168 with the second sensor chip control line group containing the second reset control line RST1(n+1) 160, the second transfer control line TX(n+1) 162, and the second selection control line SEL(n+1) 164 of row n+1). It should be understood that in the illustrated embodiment, the connection nodes are aligned across a common column. However, in other embodiments, the connection nodes may not be aligned across a common column.

[0049] Figure 1F Diagrammatic illustration based on the teachings of this disclosure and Figure 1A An exemplary pixel control line arrangement 172 of the pixel circuit system (e.g., pixel circuit system 153-N) on the logic chip 151 associated with the pixel unit (e.g., pixel unit 110) illustrated herein. More specifically, Figure 1F The control lines illustrated in the diagram supplement Figure 1E The control lines illustrated in the diagram are coupled to a control circuit system (e.g., Figure 1A The control circuit system 161 illustrated in the figure), the series circuit system (e.g., Figure 1A The illustrated circuitry 155 and / or other circuitry systems are used to control the operation of pixel units (e.g., pixel unit 110), or more specifically, to control... Figure 1A The operation of the imaging system 100 is illustrated in the figure. As previously discussed, pixel unit 110 includes red (105-R), green (105-G), blue (105-B), and infrared (105-IR) pixels. Each pixel contained in pixel unit 110 has its own corresponding circuit system instance on sensor chip 101 and logic chip 151, such as... Figure 1D The diagram in the image illustrates this. Therefore, refer back to the reference. Figure 1FExamples of pixel circuit systems 153-N in pixel unit 110 are labeled as 153-R, 153-G, 153-B, and 153-IR, respectively. Therefore, for pixel unit 110, pixel circuit system 153-R of logic chip 151 is associated with pixel 105-R of sensor chip 101, pixel circuit system 153-G of logic chip 151 is associated with pixel 105-G of sensor chip 101, pixel circuit system 153-B of logic chip 151 is associated with pixel 105-B, and pixel circuit system 153-IR is associated with pixel 105-IR.

[0050] like Figure 1F As illustrated in the diagram, the control line arrangement 172 includes a first storage control line SSW_S(n)174, a second storage control line SSW_IR_S(n)178, a first reset storage control line SSW_R(n)176, a second reset storage control line SSW_IR_R(n)180, a second reset control line RST2(n)182, a row selection control line RS(n)184, a control line CSW(n)186, and a control line CS(n)188, each associated with a row n (e.g., the first row). Similarly, for row n+1 (e.g., the second row), there are a third memory control line SSW_S(n+1)175, a third reset memory line SSW_R(n+1)177, a control line SSW_IR_S(n+1)179, a control line SSW_IR_R(n+1)181, a second reset control line RST2(n+1)183, a row selection control line RS(n+1)185, a control line CSW(n+1)186, and a control line CS(n+1)189.

[0051] Figure 1F The general format of the control line names illustrated in the diagram is similar to Figure 1E The general format is as follows, where the name indicates the coupled gate that subsequently follows the associated row. For example, the label "SSW_R(n)" on the first reset memory control line SSW_R(n)176 indicates that the first reset memory control line SSW_R(n)176 can be coupled to the reset memory gate of each pixel associated with row n (e.g., Figure 1D The reset memory gate 130 illustrated in the figure, the label “SSW_S(n)” on the first memory control line SSW_S(n) 174 indicates that the first memory control line SSW_S(n) 174 can be coupled to the first memory gate of each pixel associated with row n (e.g., Figure 1D The first storage gate 132, etc., is illustrated in the diagram. Connection nodes, indicated by black circles, indicate connections to designated circuit elements associated with corresponding pixels. For example, if in one or more pixels (e.g., such as...) Figure 1FThe presence of a connection node in the pixel circuitry of 153-B) illustrated in the middle on the first storage control line SSW S(n) 174, then the first storage control line SSW S(n) 174 is coupled to the storage gate included in the pixel circuitry of each of the one or more pixels. It will be appreciated that when a connection node is omitted from a corresponding control line as it passes through an associated pixel, then the corresponding control line is not coupled to the specified circuit element.

[0052] It will be appreciated that, Figure 1F The control line arrangement 172 illustrated in the middle is similar to the control line arrangement 152 illustrated in the middle, except that, Figure 1E One difference between the control line arrangement 152 illustrated in the middle and the control line arrangement 172 illustrated in the middle is that, Figure 1F Additional control lines are included to provide selective readout, facilitating operation to capture visible-infrared image frames with multiple exposure periods. Specifically, since infrared data from a short exposure period will be used in conjunction with color image data from a long exposure period to produce an image frame, visible pixels (e.g., 105-B) illustrated in the middle or other color pixels such as 105-G or 105-R in embodiments with different color filter arrangements, and non-visible pixels (e.g., 105-IR) illustrated in the middle) are included in the same row. Figure 1A Figure 1A The row containing both color pixels (e.g., 105-B) illustrated in the middle or other color pixels such as 105-G or 105-R in embodiments with different color filter arrangements, and non-visible pixels (e.g., 105-IR) illustrated in the middle) includes additional control lines to provide selective readout between color pixels and non-visible pixels (e.g., row n). To maintain control line symmetry and reduce or otherwise mitigate noise during readout, dummy control lines that are not coupled to any pixels are also included in rows that do not contain non-visible pixels (e.g., row n+1).

[0053] ​Thus, in the illustrated embodiment, the first reset storage control line SSW R(n) 176 is coupled to the reset storage gate included in the pixel circuitry of each visible pixel in row n (e.g., the pixel circuitry 153-B of pixel 105-B), while the second reset storage control line SSW IR R(n) 180 is coupled to the reset storage gate included in the pixel circuitry of each invisible pixel (e.g., the pixel circuitry 153-IR of pixel 105-IR). Similarly, the first storage control line SSW S(n) 174 is coupled to the storage gate included in the pixel circuitry of each visible pixel in row n (e.g., the pixel circuitry 153-B of pixel 105-B), while the second storage control line SSW IR S(n) 178 is coupled to the storage gate included in the pixel circuitry of each invisible pixel in row n (e.g., the pixel circuitry 153-IR of pixel 105-IR). Note that in the illustrated embodiment, row n+1 is not associated with any invisible pixels. Thus, the third storage control line SSW S(n+1) 175 and the third reset storage line SSW R(n+1) 177 are coupled to the storage gate and reset gate, respectively, included in the pixel circuitry of each visible pixel included in row n+1 (e.g., the pixel circuitry 153-R and 153-G). To maintain control line symmetry and mitigate noise during readout, there are control line SSW IR S(n+1) 179 and control line SSW IR R(n+1) 181 for row n+1, but not connected to the pixel circuitry of the pixels associated with row n+1, which is represented by the lack of a connection node along the control lines. In other words, control line SSW IR S(n+1) 179 and control line SSW IR R(n+1) 181 are dummy control lines. In particular, control line SSW IR S(n+1) 179 corresponds to a dummy storage control line and control line SSW IR R(n+1) 181 corresponds to a dummy reset storage control line.

[0054] The following details then describe the overall relationship between the control lines when viewed in the context of the pixel circuitry 153-B, 153-IR, 153-R, and 153-G, which are represented by different instances of the pixel circuitry 153-N as illustrated by Figure 1D Figure 1F The first storage control line SSW S(n) 174 is coupled to a first storage gate associated with a first pixel (e.g., the storage gate 132 included in the pixel circuitry 153-B associated with pixel 105-B). The first storage gate (e.g., the storage gate 132 included in the pixel circuitry 153-B) is included in a first storage capacitor (e.g., the storage capacitor C S ​The first storage transistor (e.g., the storage transistor SSW included in the pixel circuit system 153-B) S The second storage control line SSW_IR_S(n)178 is coupled to a second storage gate associated with the second pixel (e.g., storage gate 132 included in pixel circuitry 153-IR associated with pixel 105-IR). The second storage gate (e.g., storage gate 132 included in pixel circuitry 153-IR) is included in a second storage capacitor (e.g., storage capacitor C included in pixel circuitry 153-IR) coupled to a second storage capacitor. S The second storage transistor (e.g., the storage transistor SSW included in the pixel circuit system 153-IR) S In ) . For example Figure 1F As illustrated in the diagram, the first storage control line SSW_S(n) 174 is separated from the second storage control line SSW_IR_S(n) 178 to direct the signal to the first storage capacitor (e.g., the storage capacitor C included in the pixel circuit system 153-B). S ) or a second storage capacitor (e.g., the storage capacitor C included in the pixel circuit system 153-IR). S At least one of them provides selective readout. Logic chip 151 further includes a third memory control line SSW_S(n+1) 175 coupled to a third memory gate associated with a third pixel (e.g., memory gate 132 included in pixel circuit system 153-R associated with pixel 105-R) and a fourth memory gate associated with a fourth pixel (e.g., memory gate 132 included in pixel circuit system 153-G associated with pixel 105-G). The third memory gate (e.g., memory gate 132 included in pixel circuit system 153-R) is included in a third memory capacitor (e.g., memory capacitor C included in pixel circuit system 153-R). S The third storage transistor (e.g., the storage transistor SSW included in the pixel circuit system 153-R) S The fourth storage gate (e.g., storage gate 132 included in pixel circuit system 153-G) is included in the fourth storage capacitor (e.g., storage capacitor C included in pixel circuit system 153-G). S The fourth storage transistor (e.g., the storage transistor SSW included in the pixel circuit system 153-G) S) near the third storage control line SSW S(n+1) 175. As illustrated, the dummy storage control line (e.g., control line SSW IR S(n+1) 179) is not connected to any gate, including the first, second, third, and fourth storage gates associated with the first, second, third, and fourth pixels. In Figure 1F In the illustrated embodiment, the dummy storage control line (e.g., control line SSW IR S(n+1) 179) is positioned to maintain control line symmetry of the logic die 151 such that a first separation distance 191 between the first storage control line SSW S(n) 174 and the second storage control line SSW IR S(n) 178 is equal to a second separation distance 193 between the third storage control line SSW S(n+1) 175 and the dummy storage control line (e.g., control line SSW IR S(n+1) 179).

[0055] It should be appreciated that a dummy control line (e.g., dummy storage control line SSW IR S(n+1) 179, dummy storage reset control line SSW IR R(n+1) 181, or other dummy control lines described in various embodiments of the present disclosure) can be biased to a predetermined value (e.g., a preset voltage level). In some embodiments, the predetermined value of the bias corresponds to a logic low (e.g., a ground or negative bias voltage, such as -1.4V) of one or more nearby control lines. In some embodiments, the predetermined value applied to the dummy control line corresponds to a logic low of a neighboring control line (i.e., not one of the dummy control lines). For example, the predetermined value of the bias applied to the dummy storage control line SSW IR S(n+1) 179 and / or the dummy storage reset control line SSW IR R(n+1) 181 can correspond to a logic low value of the control line SSW S(n+1) 175 and / or the third reset storage line SSW R(n+1) 177 to provide physical and electrical symmetry (e.g., when the active control line is at a logic low).

[0056] In the illustrated embodiment, the logic die 151 control lines of the pixel cell 110 further include a reset storage control line SSW R(n) 176 coupled to a first reset storage gate associated with the first pixel (e.g., a reset storage gate 130 included in the pixel circuitry 153-B associated with the pixel 105-B). The first reset storage gate (e.g., the reset storage gate 130 included in the pixel circuitry 153-B) is included in a first reset storage capacitor (e.g., the reset storage capacitor C RThe first reset storage transistor (e.g., the storage transistor SSW included in the pixel circuit system 153-B) R The second reset storage control line SSW_IR_R(n)180 is coupled to a second storage gate associated with the second pixel (e.g., the reset storage gate 130 included in pixel circuitry 153-IR associated with pixel 105-IR). The second reset storage gate (e.g., the reset storage gate 130 included in pixel circuitry 153-IR) is included in a second reset storage capacitor (e.g., the reset storage capacitor C included in pixel circuitry 153-IR). R The second storage transistor (e.g., the reset storage transistor SSW included in the pixel circuit system 153-IR) R In ) . For example Figure 1F As illustrated in the diagram, the first reset storage control line SSW_R(n) 176 is separated from the second reset storage control line SSW_IR_R(n) 180 to direct the data to the first reset storage capacitor (e.g., the reset storage capacitor C included in the pixel circuit system 153-B). R ) or a second reset storage capacitor (e.g., the storage capacitor C included in the pixel circuit system 153-IR). R At least one of them provides selective readout.

[0057] In the same or other embodiments, the control lines of the logic chip 151 associated with adjacent rows (e.g., row n and row n+1) may be symmetrical about axis 195 (e.g., the first group of logic chip control lines including the first memory control line SSW_S(n) 174, the second memory control line SSW_IR_S(n) 178, the first reset memory control line SSW_R(n) 176, and the second reset memory control line SSW_IR_R(n+1) 180 of row n is symmetrical about axis 195 with the second group of logic chip control lines including the third memory control line SSW_S(n+1) 175, the third reset memory line SSW_R(n+1) 177, the control line SSW_IR_S(n+1) 179, and the control line SSW_IR_R(n+1) 181 of row n+1). It should be understood that in the illustrated embodiment, the connection nodes are aligned across a common column. However, in other embodiments, the connection nodes may not be aligned across a common column.

[0058] Figure 1E Control line layout 152 and Figure 1F The control line arrangement 172 is only illustrated for individual pixel units 110, which may be one of a plurality of pixel units included in a plurality of pixel units (e.g., such as...). Figure 1Aillustrated in FIG. 1). Thus, it should be appreciated that additional pixels and associated pixel circuitry can be included in row n and row n+1. In other words, in some embodiments of the disclosure, there can be more than two columns. Additionally, there can be additional rows above and / or below the pixel cells 110 (e.g., as illustrated in FIG. 2). Thus, the specific number of pixel cells, rows, and / or columns explicitly illustrated is not intended to be limiting and any number of pixel cells, rows, and / or columns can be included in various embodiments of the disclosure. Moreover, it should be appreciated that different color filter patterns or arrangements can be utilized (e.g., infrared pixels can be adjacent to any of red, green, or blue pixels or other visible pixels). However, in most embodiments, it should be appreciated that control line symmetry can be maintained to provide the advantages discussed herein. Figure 1A

[0059] Figure 2A illustrated in FIG. 1) according to the teachings of this disclosure. The method 200 can include blocks 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, 226, and 228. It should be appreciated that several of the blocks of the method 200 including blocks 202-228 can occur in any order and even in parallel. Additionally, several blocks can be added to or removed from the method 200 according to the teachings of this disclosure. It should be appreciated that the method 200 represents one possible implementation for operating an imaging system (e.g., the imaging system 100 illustrated in FIG. 1) according to the teachings of this disclosure. Additionally, it should be appreciated that the method 200 is not limited to only operating the imaging system 100 illustrated in FIG. 1, but rather the method 200 can be applicable to operating other embodiments of imaging systems and / or image sensors. As Figures 1A to 1F Figures 1A to 1F Figure 2A

[0060] ​​​​During the method 200, image frames with multiple exposure periods are captured with selective readout. Specifically, a first image frame includes a long exposure period and a short exposure period. The duration of the short exposure period (i.e., short exposure duration) is less than the duration of the long exposure period (i.e., long exposure duration). In some embodiments, the short exposure period is configured to occur after the long exposure period. In some embodiments, the short exposure period is used to produce non-visible (e.g., near-infrared, infrared, or far-infrared) image data of the external or object scene, while the long exposure period is used to produce visible (e.g., red, green, blue, or other combination to represent the visible range of the electromagnetic spectrum) image data of the external scene.

[0061] Block 202 illustrates the beginning or initiation of the method 200, where the capture of one or more image frames with multiple exposure durations (e.g., one or more image frames that image an external scene with visible and infrared image signals) will occur. The initiation can occur in response to a user input (e.g., a user pressing or otherwise contacting a physical or virtual trigger), an event condition trigger (e.g., a vehicle shifting into reverse, a turn signal being activated), or other.

[0062] Block 204 shows resetting a plurality of photodiodes (e.g., the plurality of photodiodes 104 included in the plurality of pixels 105 illustrated in FIG. 1). Figures 1A to 1F The plurality of photodiodes can be reset in response to an assertion of a reset signal (e.g., for each pixel included in the plurality of pixels 105 of the imaging system 100 illustrated in FIG. 1, as illustrated in FIG. 2) applied to the transfer gate 112 of the transfer transistor TX and the reset gate 116 of the reset transistor RST1. The appropriate signal causes charge to be placed across the plurality of photodiodes to provide a predetermined potential (e.g., VDD or other appropriate predetermined potential illustrated in FIG. 1) and allow image charge to accumulate during the long exposure period. The reset signal can be applied via appropriate control lines (e.g., RST1(n) 154, RST1(n+1) 160, TX(n) 156, and TX(n+1) 162, as illustrated in FIG. 1, to turn on the reset transistor RST1 and the transfer transistor TX). Figure 1A Figure 1D The reset signal can be applied via appropriate control lines (e.g., RST1(n) 154, RST1(n+1) 160, TX(n) 156, and TX(n+1) 162, as illustrated in FIG. 1, to turn on the reset transistor RST1 and the transfer transistor TX). Figure 1D Figure 1E Block 206 illustrates beginning the long exposure period of the image frame. During the long exposure period, image charge accumulates in the plurality of photodiodes in response to incident light from the external scene (e.g., from block 204). The accumulated image charge represents the external scene and has a magnitude based on the intensity of light incident on a given photodiode included in the plurality of photodiodes.

[0063] Block 208 illustrates beginning the short exposure period of the image frame. During the short exposure period, image charge accumulates in the plurality of photodiodes in response to incident light from the external scene (e.g., from block 206). The accumulated image charge represents the external scene and has a magnitude based on the intensity of light incident on a given photodiode included in the plurality of photodiodes.

[0064] ​​Box 208 shows the results by targeting multiple pixels (e.g., Figures 1A to 1F Each pixel contained in the plurality of pixels 105 (illustrated in the figure) corresponds to a floating diffusion region (e.g., Figure 1D The first floating diffusion reset of an image frame (e.g., a first image frame) is performed by resetting the floating diffusion region 114 (illustrated in the figure), wherein the plurality of pixels includes a first pixel, a second pixel, a third pixel, and a fourth pixel (e.g., ...). Figures 1C to 1F The illustration shows pixels 105-B, 105-IR, 105-R, and 105-G. The first floating diffusion reset can be achieved by resetting the reset gate of each pixel contained within the plurality of pixels (e.g., ...). Figure 1D The reset transistor RST1 illustrated in the diagram is initiated by an assertion or by otherwise applying a pulse, which in turn activates (e.g., turns on) the source follower transistor (e.g., ...). Figure 1D The source follower transistor SF1 illustrated in the figure allows the long exposure reset signal of each of multiple pixels to be read out (e.g., Figure 1D The reset level of the floating diffusion region 114 illustrated in the diagram). This can be achieved via an appropriate control line (e.g., Figure 1E The RST1(n) 154 and RST1(n+1) 160 illustrated in the diagram apply pulses to the reset gate of each pixel. Therefore, in response to the first floating diffusion reset and using an appropriate configuration (e.g., applying a selection signal to the select gate 118 to turn on the select transistor SEL (e.g., the first select control line SEL(n) 158, the second select control line SEL(n+1) 164 to turn on the corresponding select transistor SEL), pulses are applied from the corresponding floating diffusion region (e.g., ...). Figure 1D The long exposure reset signal, illustrated in the figure, for the floating diffusion region 114 of each of the plurality of pixels, is read out to a reset storage capacitor associated with each of the plurality of pixels (e.g., a first reset storage capacitor associated with a first pixel, a second reset storage capacitor associated with a second pixel, a third reset storage capacitor associated with a third pixel, a fourth reset storage capacitor associated with a fourth pixel, etc.). In some embodiments, the reset storage capacitor is part of a storage node included in a pixel circuit system on a logic wafer (e.g., included in...). Figure 1D The reset storage capacitor C in storage node 124 illustrated in the figure. R In some embodiments, the reset storage gate of each pixel included in a plurality of pixels (e.g., Figure 1D The reset storage transistor SSW illustrated in the figure. Ron the reset storage gate 130) to facilitate readout of the long-exposure reset signal.

[0065] Block 210 illustrates transferring first image charges accumulated during a long-exposure period of an image frame (e.g., a first image frame) to respective floating diffusion regions of a plurality of pixels (e.g., floating diffusion regions 114 for each of a first pixel (e.g., 105-B), a second pixel (e.g., 105-IR), a third pixel (e.g., 105-R), a fourth pixel (e.g., 105-G), etc., as illustrated in FIG. 1). Figures 1C to 1F In some embodiments, a transfer control line signal (e.g., a first transfer control line signal) associated with the plurality of pixels (e.g., one or more of a first pixel, a second pixel, a third pixel, a fourth pixel, or others) is asserted (e.g., applied to TX(n) 156 and TX(n+1) 162 as illustrated in FIG. 1) to transfer the first image charges accumulated during the long-exposure period (e.g., the first image charges accumulated during the long-exposure period of the first image frame can be transferred to respective floating diffusion regions of one or more of the first pixel, the second pixel, the third pixel, the fourth pixel, etc.). Figure 1E In some embodiments, a transfer control line signal (e.g., a first transfer control line signal) associated with the plurality of pixels (e.g., one or more of a first pixel, a second pixel, a third pixel, a fourth pixel, or others) is asserted (e.g., applied to TX(n) 156 and TX(n+1) 162 as illustrated in FIG. 1) to transfer the first image charges accumulated during the long-exposure period (e.g., the first image charges accumulated during the long-exposure period of the first image frame can be transferred to respective floating diffusion regions of one or more of the first pixel, the second pixel, the third pixel, the fourth pixel, etc.). Figure 1D In some embodiments, a transfer control line signal (e.g., a first transfer control line signal) associated with the plurality of pixels (e.g., one or more of a first pixel, a second pixel, a third pixel, a fourth pixel, or others) is asserted (e.g., applied to TX(n) 156 and TX(n+1) 162 as illustrated in FIG. 1) to transfer the first image charges accumulated during the long-exposure period (e.g., the first image charges accumulated during the long-exposure period of the first image frame can be transferred to respective floating diffusion regions of one or more of the first pixel, the second pixel, the third pixel, the fourth pixel, etc.).

[0066] Block 212 shows reading out the long-exposure image signals from the respective floating diffusion regions to respective storage capacitors (e.g., a first storage capacitor associated with the first pixel and a second storage capacitor associated with the second pixel) included in storage nodes for each pixel included in the plurality of pixels (e.g., storage nodes 116 as illustrated in FIG. 1). Figure 1D S More specifically, a corresponding source follower transistor (e.g., source follower transistor 118 as illustrated in FIG. 1) is enabled when the long-exposure image signal is transferred to the respective floating diffusion region (e.g., floating diffusion region 114 as illustrated in FIG. 1). Figure 1D Figure 1D ​​The source follower transistor SF1, as illustrated in the diagram, is then turned on and, with appropriate configuration (e.g., a select signal is applied to select gate 118 to turn on select transistor SEL and to storage gate 132 to turn on storage transistor SSW), S Storage control line signals, such as Figure 1D (Illustrated in the figure), this indicates that the amount of charge stored in the corresponding floating diffusion region of the sensor chip will be stored in the storage capacitor of the logic chip. In some embodiments, individual control line signals (e.g., a first storage control line signal and a second storage control line signal) will be asserted or otherwise applied simultaneously to the appropriate storage control lines (e.g., the first storage control line SSW_S(n)174 and the second storage control line SSW_IR_S(n)178) to turn on along the common row (e.g., as shown in the figure). Figures 1A to 1F The diagram illustrates the associated storage transistors (e.g., the first row containing the first pixel 105-B and the second pixel 105-IR) of different pixels with different orientations. Figure 1D The storage transistor SSW illustrated in the figure S In the same or other embodiments, individual memory line control signals will be asserted or otherwise applied to the appropriate control line (e.g., Figure 1F The third storage control line SSW_S(n+1)175, as illustrated in the diagram, is coupled to a common row (e.g., as shown in the diagram). Figures 1A to 1F The illustration shows all the pixels in the second row (including the third pixel 105-R and the fourth pixel 105-G).

[0067] Box 214 illustrates the short exposure period for the start of the image frame. In some embodiments, the short exposure period may begin in response to resetting multiple photodiodes. In other words, during box 214, multiple photodiodes may be reset (e.g., to...). Figure 2A (As illustrated in block 204 of the diagram). Multiple photodiodes can accumulate image charge representing an external scene and have a magnitude based on the light intensity incident on a given photodiode included in the multiple photodiodes during a short exposure period.

[0068] Box 216 illustrates a pulse that emits electromagnetic radiation of a first spectrum during a short exposure period of an image (e.g., a first image frame). The emission of electromagnetic radiation of the first spectrum is synchronized with the short exposure period. It should be understood that, in order to mitigate crosstalk between the short exposure period of the image frame and the long exposure period of subsequent image frames, the pulse duration is less than the short exposure duration of the short exposure period of the image frame. In some embodiments, the pulse duration is less than one-tenth of the duration of the long exposure period, which allows for the capture of invisible images during the short exposure period with minimal impact on visible images captured during the long exposure period. The short exposure duration of the short exposure period can be configured based on the amount of time required to capture electromagnetic radiation of the first spectrum reflected from an external scene. It should be understood that the electromagnetic radiation of the first spectrum includes a first wavelength, which is in the infrared range of the electromagnetic spectrum (e.g., from near-infrared to far-infrared, such as 800 nm to 3000 nm). The electromagnetic radiation of the first spectrum can be generated by a light source, wherein the light source can be a component external to the image sensor. During a short exposure period, multiple photodiodes accumulate image charge in response to pulses of electromagnetic radiation of a first spectrum reflected from one or more objects in an external scene and incident on the multiple photodiodes. This image charge can be used to generate an illuminated image that does not interfere with the human eye (i.e., an invisible image based on pulses of electromagnetic radiation of a first spectrum outside the visible light range) and / or depth or distance information associated with the external scene (e.g., the distance or depth of one or more pixels contained in a plurality of pixels to one or more objects contained in the external scene). In some embodiments, time-of-flight information and / or phase difference information can be calculated based on the image charge accumulated during the short exposure period.

[0069] Box 218 illustrates how multiple pixels (e.g., Figures 1A to 1F Each pixel contained in the plurality of pixels 105 (illustrated in the figure) corresponds to a floating diffusion region (e.g., Figure 1D The floating diffusion region 114 illustrated in the figure is reset to perform a second floating diffusion reset of the image frame (e.g., the first image frame), the plurality of pixels including the first pixel, the second pixel, the third pixel, and the fourth pixel (e.g., ... Figures 1C to 1F (Pixels 105-B, 105-IR, 105-R, and 105-G are illustrated in the diagram).

[0070] In contrast to block 208, where the long exposure reset signal for each pixel is read out to the associated reset storage capacitor, in block 218, selective readout is performed to store the long exposure reset signal along with the visible pixels (e.g., ...). Figure 1A The first part of the pixel unit 110 (105-B, 105-R, and 105-G) illustrated in the figure is associated with the long exposure reset signal and the invisible pixel (e.g., Figure 1AThe second portion associated with the pixel cell 110 illustrated in FIG. 1 15-IR) will be replaced with a corresponding short exposure reset signal. For example, in the case of the pixel cell 110 illustrated in FIG. Figures 1A to 1F In the case of the pixel cell 110 illustrated in FIG. 1 15-IR), in response to the second floating diffusion reset, a short exposure reset signal from a corresponding one of the floating diffusion regions (e.g., the floating diffusion region 114 of the pixel 105-IR) is read out to a second reset storage capacitor (e.g., the reset storage capacitor C R ) associated with the second pixel. This is accomplished, at least in part, by pulsing (i.e., asserting a signal to) the reset storage gate 130 of the reset storage transistor SSW R of the invisible pixel (e.g., the pixel 105-IR) to turn on the reset storage transistor SSW R of the invisible pixel while not turning on the reset storage transistor SSW R .

[0071] Block 220 shows transferring second image charge accumulated during a short exposure period of an image frame (e.g., a first image frame) to respective floating diffusion regions of a plurality of pixels (e.g., the floating diffusion region 114 for each of a first pixel (e.g., 105-B), a second pixel (e.g., 105-IR), a third pixel (e.g., 105-R), a fourth pixel (e.g., 105-G), etc., as illustrated in FIG. Figures 1C to 1F In some embodiments, a transfer control line signal (e.g., a first transfer control line signal) associated with the plurality of pixels (e.g., one or more of the first pixel, the second pixel, the third pixel, the fourth pixel, or others) is asserted (e.g., applied to TX(n) 156 and TX(n+1) 162 illustrated in FIG. Figure 1E In some embodiments, the transfer control line signal corresponds to a pulse applied to a transfer gate of each of the plurality of pixels (e.g., the transfer gate 112 of the transfer transistor TX as illustrated in FIG. Figure 1D In the same or other embodiments, the transfer control line signal is applied simultaneously to the transfer gate of each of the plurality of pixels. In some embodiments, the start of block 220 corresponds to the end of a short exposure period of an image frame being captured (e.g., the first image frame).

[0072] Box 222 illustrates the selective readout of short-exposure image signals from corresponding floating diffusion regions to corresponding storage capacitors (e.g., when the second pixel corresponds to an invisible pixel (e.g.)). Figure 1A When pixel 105-IR of pixel unit 110 (illustrated in the figure) is used, the second storage capacitor associated with the second pixel is used. More specifically, the short exposure image signal can be read out to the storage capacitor associated with each invisible pixel (e.g., an infrared pixel) to overwrite or otherwise replace a previously stored long exposure image signal (e.g., see box 212). In contrast, the long exposure image signal associated with a visible pixel contained in the plurality of pixels is not replaced or otherwise read out to the associated storage capacitor contained in the visible pixel. In some embodiments, the readout of the short exposure signal is achieved by asserting an appropriate storage control line signal (e.g., asserting a second storage control line signal instead of a first storage control line signal to initiate the readout of the short exposure image signal to the second storage capacitor and replace the previously stored signal associated with the long exposure period of the first image frame). For example, in Figure 1F In this case, this can be achieved by directing the second storage control line SSW_IR_S(n)178 (and... Figure 1E This is achieved by applying a pulse (as illustrated in the diagram, associated with 105-IR), instead of applying a pulse to the first memory control line SSW_S(n)174 (as shown in the diagram). Figure 1E (As illustrated in the diagram, 105-B is associated with) or the third memory control line SSW_S(n+1)175 (and) Figure 1E The 105-R and 105-G pulses are illustrated in the diagram.

[0073] Box 224 illustrates the process of storing data from multiple storage capacitors (e.g., for each of multiple pixels, such as...). Figure 1D The storage capacitor C illustrated in the figure S ) and multiple reset capacitors (e.g., for each of the multiple pixels) Figure 1D The reset storage capacitor C illustrated in the figure R The stored charge signal is read from the image to generate image data corresponding to or otherwise representing an image frame (e.g., a first image frame). It should be understood that additional processing may be performed to generate the image frame (e.g., de-mosaicing, smoothing, etc.). In some embodiments, this is done via column circuitry (e.g., Figure 1A The column circuit 155 illustrated in the figure reads out the stored charge signal. The column circuit may include an analog-to-digital converter, sample-and-hold circuitry, or otherwise determine the storage node for each pixel contained in a plurality of pixels (e.g., ...). Figure 1Dthe state of each capacitor contained in the storage node 124) illustrated in the middle. Specifically, for a given pixel, the storage capacitor stores a signal level and the reset storage capacitor stores a reset level, which are read out (e.g., via Figure 1D the second source follower transistor SF2) illustrated in the middle to a bit line, which in turn reaches a column circuit that converts the signal level minus the reset level into a digital value (e.g., image data). For example, in one embodiment, from the first storage capacitor and the second storage capacitor (e.g., associated with the first pixel (e.g., Figures 1E to 1F the storage capacitor C S ) reads out the stored charge signal to generate at least a portion of image data for an image frame (e.g., a first image frame) based on a corresponding one of a long exposure image signal associated with a first pixel (e.g., Figures 1A to 1F the pixel 105-B) illustrated in the middle and a short exposure image signal associated with a second pixel (e.g., Figures 1A to 1F the pixel 105-IR) illustrated in the middle. In the same or another embodiment, the image data for the first image frame is based on a first difference between a corresponding one of the long exposure image signal associated with the first pixel and a corresponding one of the long exposure reset signal associated with the first pixel, and a second difference between the short exposure image signal and the short exposure reset signal. In some embodiments, the readout of the stored charge signal is done on a row-by-row basis to generate the image data, which can occur during the capture of a next image frame.

[0074] If additional image frames are to be captured, block 226 returns to block 204 and the method 200 continues to capture a next image frame. If no additional image frames are needed, block 226 proceeds to block 228 and the method 200 ends or otherwise terminates.

[0075] Figure 2B illustrates an example timing diagram 250 for capturing image frames (e.g., a first image frame 221 and a second image frame 223) representative of an external scene via selective readout during long and short exposure periods of an image frame (e.g., a long exposure period 225 and a short exposure period 227 of the first image frame 227) in accordance with the teachings of this disclosure. The timing diagram 250 provides an overview of the method 200 illustrated in the middle being performed by an image sensor or imaging system (e.g., Figure 2A the imaging system 100 and Figure 1A the imaging system 100 and Figures 1A to 1FThe illustration shows the visual representation of the exposure and readout of an exemplary photodiode in multiple rows of the associated structure. As discussed in the previous embodiments, the multiple pixels include visible (e.g., red, green, blue) and invisible (e.g., infrared) pixels. During the long exposure period 225, the photodiode (e.g., ... Figure 1D The PD 104-N diagram illustrates the accumulation of image charge. Then, to end the long exposure cycle, the accumulated image charge is read out to the floating diffusion region (e.g., corresponding to...). Figure 1D The floating diffusion region 114 is illustrated in the diagram. Then, all storage switches for visible and invisible pixels (e.g., Figure 1D The storage transistor SSW illustrated in the figure S For each pixel contained in multiple pixels, by applying a pulse to, for example Figure 1F The storage control lines (SSW_S(n)174, SSW_IR_S(n)178, and SSW_S(n+1)175, as illustrated in the diagram) are turned on to read the long exposure image signal to a storage capacitor (e.g., ...) associated with each of the multiple pixels. Figure 1D The storage capacitor C illustrated in the figure S Shortly thereafter, a short exposure cycle 227 begins, during which light source 241 emits electromagnetic radiation pulses (e.g., light with wavelengths between 800 nm and 3000 nm) towards the external scene captured by the image sensor, and charge is accumulated in the photodiodes of each of the multiple pixels. Then, to end the short exposure cycle, the accumulated image charge is read out to the floating diffusion region (e.g., Figure 1D The floating diffusion region 114 illustrated in the figure is activated only for reading out short-exposure image signals (e.g., the storage switch associated with invisible pixels is activated to read out short-exposure image signals). Figure 1D The storage transistor SSW illustrated in the figure S By applying pulses to the storage control line of invisible pixels, for example Figure 1F The diagram illustrates SSW_IR_S(n)178 instead of SSW_S(n)174. When reading out a short-exposure image signal, each short-exposure image signal contained in the short-exposure image signal replaces the corresponding one in the long-exposure image signal (e.g., generated in response to image light reflected from an external scene incident on the image sensor during the long-exposure period 225). Thereafter, the next image frame (e.g., the second image frame 223) begins and a rolling readout 231 of the stored charge signal is performed to generate image data for the first image frame 221. In other words, the readout of the stored charge signal to generate image data is completed on a line-by-line basis.

[0076] Figure 3A and Figure 3BCircuitry for pixel cells on sensor die 301 and logic die 351 according to the teachings of this disclosure is illustrated, respectively. It should be appreciated that Figure 3A and Figure 3B The circuit diagrams illustrated in Figures 1A to 1F The imaging system 100 illustrated in Figure 3A Circuitry 300 for pixel cells on sensor die 301 is illustrated, including a blue pixel (e.g., photodiode PD B associated with a first pixel in a first row), an infrared pixel (e.g., photodiode PD IR associated with a second pixel in the first row), a red pixel (e.g., photodiode PD R associated with a third pixel in a second row), and a green pixel (e.g., photodiode PD G associated with a fourth pixel in the second row). It should be appreciated that circuitry 300 is similar in many respects to the circuitry of sensor die 101 illustrated in Figure 1D to avoid obscuring the disclosure, particular elements (e.g., gates of individual transistors, source follower transistors, etc.) are not labeled in Figure 3A The circuitry of sensor die 101 illustrated in Figure 1D The circuitry of sensor die 101 illustrated in Figure 3A One difference between the circuitry of sensor die 101 illustrated in Figure 3A As illustrated in Figure 3A Control lines (e.g., RST1 354 and SEL 358) are also illustrated as being coupled to control pixels of multiple rows (e.g., RST1 354 can be used to simultaneously reset floating diffusion regions FD 1 and FD 2 and photodiodes PD B, PD IR, PD R, and PD G in conjunction with appropriate signals or pulses on transfer control lines TX(n) 356 and TX(n+1) 362). In other embodiments, separate control lines can be provided for each row and function (e.g., first and second reset and select control lines for the first and second rows).

[0077] Now for reference Figure 3B The diagram illustrates the pixel circuitry system 353 on or within the logic chip 351 for the pixel unit, which in many respects is similar to... Figure 1D The pixel circuitry system 153-N on or within the logic chip 151 is illustrated in the diagram. Specifically, each photodiode is coupled to a corresponding memory node (e.g., memory node 324-B and a node containing...). Figure 3A The blue pixels of PD_B are associated with storage node 324-IR and contain Figure 3A The infrared pixels of PD_IR are associated with storage node 324-R and contain Figure 3A The red pixels of PD_R are associated with the storage node 324-G, and the storage node 324-G is associated with the red pixels of PD_R. Figure 3A (Associated with the green pixels of PD_G). It should be understood that the pixel circuit system 353 is similar in many ways to Figure 1D The pixel circuit system 153-N of the logic chip 151 illustrated herein has been expanded to represent a full pixel unit. For example, separate control lines exist for memory nodes that share a row with visible pixels (e.g., infrared and blue pixels in the second row) to provide selective readout to the appropriate memory node (e.g., SSW_IR_S(n)378 and SSW_IR_R(n)380 are coupled to memory node 324-IR, while SSW_S(n)374 and SSW_R(n)376 are coupled to memory node 324-B). In contrast, control lines for memory nodes associated with rows of only visible pixels (e.g., red and green pixels in the second row) are shared (e.g., SSW_S(n+1)375 and SSW_R(n+1)377 are coupled to memory nodes 324-R and 324-G). It should be understood that the lines coupled to... Figure 3B The control lines of the pixel circuit system 353 illustrated in the diagram can functionally be connected to... Figure 1F The control lines illustrated in the diagram are similar or otherwise analogous. In other words, Figure 3B SSW_S(n)374 can correspond to or be similar to Figure 1F The first storage control line is SSW_S(n)174. Figure 3B SSW_IR_S(n)378 can correspond to or be similar to Figure 1F The second storage control line is SSW_IR_S(n)178. Figure 3B SSW_R(n)376 can correspond to or be similar to Figure 1F The first reset memory control line is SSW_R(n)176. Figure 3B SSW_IR_R(n)380 can correspond to or be similar to Figure 1F The second reset memory control line is SSW_IR_R(n)180. Figure 3B RST2(n)382 can correspond to or be similar to Figure 1F Control line RST2(n)182, Figure 3B RS(n)384 can correspond to or be similar to Figure 1F The row selection control line RS(n)184, Figure 3B CSW(n)386 can correspond to or be similar to Figure 1F Control line CSW(n)186, Figure 3B CS(n)388 can correspond to or be similar to Figure 1F The control line CS(n)188, Figure 3B SSW_S(n)374 can correspond to or be similar to Figure 1F The third storage control line SSW_S(n+1)175, and Figure 3B SSW_R(n+1)377 can correspond to or be similar to Figure 1F The third reset memory line is SSW_R(n+1)177.

[0078] Figure 3C to 3D The illustration illustrates an exemplary operating method 350 for an imaging system according to the teachings of this disclosure (i.e., Figure 3C The above diagram illustrates 350-1 and Figure 3D As illustrated in 350-2 above, the imaging system can selectively read out for visible-infrared image capture. Method 350 can be implemented by an imaging system having a pixel unit circuit system distributed across sensor wafers and logic wafers, such as... Figure 3A and Figure 3B The diagrams in the text illustrate (e.g., Figure 3A The sensor chip 301 illustrated in the figure and Figure 3B The logic chip 351 illustrated in the figure is shown. Method 350 includes blocks 303, 305, 307, 309, 311, 313, 315, 317, 319, 321, 323, 325, 327, 329, 331, and 333. It should be understood that the blocks of method 350 including blocks 303 to 333 can occur in any order and even in parallel. Furthermore, according to the teachings of this disclosure, blocks can be added to or removed from method 350. It should be understood that method 350 represents a possible embodiment for operating an imaging system having, for example, […]. Figure 3A and Figure 3B The pixel unit circuit system illustrated in the figure spans the distribution of sensor chips and logic chips (e.g., Figure 3A The sensor chip 301 illustrated in the figure and Figure 3B (The logic chip 351 illustrated in the diagram). Furthermore, it should be understood that method 350 is not limited to... Figures 3A to 3BThe imaging system illustrated herein is not the only one; method 350 can be applied to control the operation of other embodiments of the imaging system and / or image sensor. Figure 3C and Figure 3D As illustrated in the diagram, each loop of method 350 (e.g., a set of boxes 305 to 329) may represent capturing an individual image frame representing the external scene. It should be understood that multiple image frames (e.g., a first image frame, a second image frame, etc.) may be captured to generate a video of the external scene.

[0079] Figure 3C Box 303 illustrates the start or initiation of method 350, wherein the capture of one or more image frames having multiple exposure durations will occur (e.g., one or more image frames imaging an external scene using visible and infrared image signals). In some embodiments, box 303 may be associated with... Figure 2A The boxes 202 illustrated in the diagram are similar and may contain the same or similar features.

[0080] Figure 3C Box 305 shows multiple photodiodes (e.g., Figure 3A The diagram illustrates PD_B, PD_IR, PD_R, ​​and PD_G. Reset is possible in response to a reset signal (e.g., applied to...). Figure 3A The pulses of the control lines RST1354, TX(n)356, and TX(n+1)362 illustrated in the diagram are used to reset the plurality of photodiodes to provide a predetermined potential (e.g., Figure 3A (as illustrated in the diagram, VDD or other suitable predetermined potential) and allows image charge to accumulate during long exposure cycles. In some embodiments, block 305 may be connected to... Figure 2A The boxes 204 illustrated in the diagram are similar and may contain the same or similar features.

[0081] Figure 3C Box 307 illustrates the long exposure period of the starting image frame. During the long exposure period, image charge (e.g., from box 307) accumulates in the multiple photodiodes in response to their reset. The accumulated image charge represents the external scene and has a magnitude based on the light intensity incident on a given photodiode included in the multiple photodiodes. In some embodiments, box 307 may be associated with... Figure 2A The boxes 202 illustrated in the diagram are similar and may contain the same or similar features.

[0082] Figure 3C Box 309 illustrates the performance of a floating diffusion reset of an image frame (e.g., a first image frame) and the selective readout of a reset storage capacitor to a first group of pixels. In a shared floating diffusion region (e.g., as... Figure 3AIn the illustrated embodiment, where each floating diffusion region is shared by two adjacent pixels in the same column, the first group of pixels is supplemented by a second group of pixels, and the first and second groups of pixels together cover multiple pixels (e.g., each pixel unit formed by multiple pixels). For example, in the illustrated embodiment, the first group of pixels corresponds to pixels associated with PD_R and PD_G (e.g., row n+1) and the second group of pixels corresponds to pixels associated with PD_B and PD_IR (e.g., row n), and the pixels together cover as shown in the illustration. Figure 3A The diagram illustrates multiple pixels. However, it should be understood that, depending on the specific layout or arrangement of the multiple pixels, different schemes may be used to share the floating diffusion region (e.g., PD_IR in the same row as any of PD_R, ​​PD_G, or PD_B).

[0083] The shared floating diffusion region (e.g., RST1 354 and TX(n+1) 362 for the first group of pixels) can be controlled by asserting appropriate control lines (e.g., RST1 354 and TX(n+1) 362 for the first group of pixels) or by otherwise applying pulses. Figure 3A The FD_1 and FD_2 diagrams illustrate the process. After resetting the floating diffusion region, it can be immediately reset by adjusting the appropriate control lines (e.g., in the case of the first group of pixels). Figure 3A SEL 358 and Figure 3B Assertions are made on SSW_R(n+1)377) or pulses are applied in other ways to selectively read the reset level of the floating diffusion region to the corresponding reset storage capacitor (e.g., in the case of the first group of pixels, assertions are made on TX(n+1) to separately read the reset level of the floating diffusion region to the corresponding reset storage capacitor). Figure 3A The reset levels of FD_1 and FD_2 illustrated in the diagram are read out. Figure 3B The diagram illustrates R_C R and G_C R ).

[0084] Figure 3C The diagram in box 311 illustrates the selective transfer of image charge accumulated during long exposure cycles to storage capacitors (e.g., ...) of the first group of pixels. Figure 3B The R_C of the first group of pixels illustrated in the diagram S and G_CS S In one embodiment, during a long exposure cycle... Figure 3A The image charges accumulated in PD_R and PD_G are transferred to floating diffusion regions FD_1 and FD_2, respectively (e.g., by adjusting the image charge in PD_R and PD_G). Figure 3A The diagram illustrates TX(n+1)362, which is asserted or otherwise pulsed and then asserted on the appropriate control line (e.g., to...). Figure 3A The diagram illustrates SEL 358 and Figure 3BThe SSW_S(n+1)375 pulse (illustrated in the diagram) reads out the long-exposure image signal representing the image charge to the appropriate storage capacitor (e.g., Figure 3B The diagram illustrates R_C S and G_C S )).

[0085] Figure 3C Box 313 illustrates the implementation of a float diffusion reset for an image frame (e.g., the first image frame) and a reset for a second group of pixels (e.g., with...). Figure 3A Selective readout of the reset storage capacitors of the pixels associated with PD_B and PD_IR (illustrated in the diagram). The shared floating diffusion region (e.g., ...) can be selectively read out by asserting or otherwise pulsed on appropriate control lines (e.g., RST1 354 and TX(n) 356 of the second group of pixels). Figure 3A The FD_1 and FD_2 diagrams illustrate the process. After resetting the floating diffusion region, it can be immediately reset by adjusting the appropriate control lines (e.g., in the case of the second group of pixels). Figure 3A SEL 358, Figure 3B Assertions are made on SSW_R(n)376 and SSW_IR_R(n)380, or pulses are applied in other ways to selectively read the reset level of the floating diffusion region to the corresponding reset storage capacitor (e.g., in the case of the second group of pixels, assertions are made on TX(n) to respectively read the reset level of the floating diffusion region to the corresponding reset storage capacitor). Figure 3A The reset levels of FD_1 and FD_2 illustrated in the diagram are read out. Figure 3B The diagram illustrates B_C R and IR_C R ).

[0086] Figure 3C The diagram in box 315 illustrates the selective transfer of image charge accumulated during long exposure cycles to storage capacitors (e.g., ...) of the second set of pixels. Figure 3B The second group of pixels, B_C, is illustrated in the diagram. S and IR_C S In one embodiment, during a long exposure cycle... Figure 3A The image charges accumulated in PD_B and PD_IR are transferred to floating diffusion regions FD_1 and FD_2, respectively (e.g., by adjusting the image charge concentration in PD_B and PD_IR). Figure 3A The diagram illustrates TX(n)356, which is used to assert or otherwise apply a pulse and then assert through the appropriate control line (e.g., to...). Figure 3A The diagram illustrates SEL 358 and Figure 3BThe SSW_S(n)374 and SSW_IR_S(n)378 illustrated in the figure apply pulses) to read out the long exposure image signal representing the image charge to the appropriate storage capacitor (e.g., Figure 3B The diagram illustrates B_C S and IR_C S )).

[0087] It should be understood that in some embodiments, Figure 3C The boxes 309 and 313 of method 350 illustrated in the figure can collectively correspond to Figure 2A The blocks 208 of the method 200 illustrated herein may contain the same or similar features. Additionally, in the same or other embodiments, Figure 3C The boxes 311 and 315 of method 350 illustrated in the figure can collectively correspond to Figure 2A The method 200 illustrated in the figure includes boxes 210 and 212, all of which may contain the same or similar features. (Return to Reference) Figure 3C Box 315 continues through "A" to Figure 3D Box 317 in the above diagram.

[0088] Figure 3D Block 317 illustrates the short exposure period for the start of the image frame. In some embodiments, the short exposure period may begin in response to a reset of multiple photodiodes. In other words, during block 317, multiple photodiodes may be reset (e.g., to...). Figure 3C (As illustrated in block 305 of the diagram). Multiple photodiodes can accumulate image charge representing an external scene and have a magnitude based on the intensity of light incident on a given photodiode included in the plurality of photodiodes during a short exposure period. In some embodiments, block 317 may be related to... Figure 2A The boxes 214 illustrated in the figure are similar and may contain the same or similar features.

[0089] Figure 3DBlock 319 illustrates a pulse (e.g., through a light source) emitting electromagnetic radiation of a first spectrum during a short exposure period of an image (e.g., a first image frame). In some embodiments, the light source may be contained within the image sensor, while in other embodiments, the light source may be positioned externally to the image sensor. It should be understood that, to mitigate crosstalk between the short exposure period of an image frame and the long exposure period of subsequent image frames, the pulse duration is less than the short exposure duration of the short exposure period of the image frame. In some embodiments, the pulse duration is less than one-tenth of the duration of the long exposure period, which allows for the capture of an invisible image during the short exposure period with minimal impact on the visible image captured during the long exposure period. It should be understood that the electromagnetic radiation of the first spectrum includes a first wavelength, which may be in the infrared range of the electromagnetic spectrum (e.g., from near-infrared to far-infrared, such as 800 nm to 3000 nm). During a short exposure cycle, the plurality of photodiodes accumulate image charge in response to pulses of electromagnetic radiation of a first spectrum reflected from one or more objects in an external scene and incident on the plurality of photodiodes. This image charge can be used to generate an illuminated image that does not interfere with the human eye (e.g., an invisible image based on electromagnetic radiation outside the visible spectrum), or to generate depth or distance information associated with an external scene (e.g., the distance or depth of one or more pixels contained in a plurality of pixels to the external scene). In some embodiments, time-of-flight information and / or phase difference information can be calculated based on the image charge accumulated during the short exposure cycle. In some embodiments, block 319 may be related to... Figure 2A The boxes 216 illustrated in the figure are similar and may contain the same or similar features.

[0090] Figure 3D Box 321 illustrates the performance of a floating diffusion reset without reading the reset storage capacitor to the first group of pixels. In other words, the floating diffusion regions (e.g., FD_1 and FD_2) can be reset, but the reset level of the floating diffusion regions will not be determined because the visible pixels (e.g., with...) Figure 3A The pixels associated with PD_R and PD_G (as illustrated in the diagram) do not require a short exposure reset signal because... Figures 3A to 3D The illustrated embodiment utilizes infrared pixels (e.g., with...) Figure 3A The short exposure image and reset signal are determined by the pixels associated with PD_IR (illustrated in the diagram). The reset of the floating diffusion region can be achieved by asserting appropriate control lines (e.g., applied to...). Figure 3A The diagram above illustrates RST1 354, not... Figure 3B This is achieved by using the pulse of SSW_R(n+1)377 as illustrated in the diagram.

[0091] Figure 3DBox 323 illustrates the selective transfer of image charge accumulated during the short exposure cycle of an image frame (e.g., the first image frame) to the floating diffusion region, rather than to the storage capacitors of the first set of pixels (e.g., ...). Figure 3B The diagram illustrates R_C S and G_CS S Similar to box 321, in the illustrated embodiment, a short-exposure image signal of the first set of pixels (or more specifically, the visible pixels) is not required. This can be achieved by asserting (e.g., applying to) appropriate control lines. Figure 3A The above diagram illustrates TX(n+1)362 and RST1 354, rather than being applied to... Figure 3B The pulse of SSW_S(n+1)375 illustrated above is used to perform selective transfer.

[0092] Figure 3D The diagram for box 325 illustrates one or more invisible pixels (e.g., with...). Figure 3A The diagram illustrates the floating diffusion reset of the pixels associated with PD_IR and the reset of the storage capacitor (e.g., for one or more invisible pixels in the second group of pixels) for one or more of the pixels in the second group of pixels. Figure 3B The diagram illustrates IR_C R Selective short-exposure reset signal readout. The second group of pixels (per pixel unit) contains both visible and invisible pixels, but only pixels sensitive to emitted electromagnetic radiation (e.g., infrared pixels corresponding to invisible pixels) require a short-exposure image signal. Therefore, short-exposure reset and image signals are obtained for invisible pixels, while maintaining the previously obtained long-exposure reset and image signals (e.g., in...). Figure 3C During the period illustrated in boxes 309, 311, 313, and 315. Assertions can be made by applying appropriate control lines (e.g., applied to). Figure 3A The diagrams illustrate RST1 354 and SEL 358, and Figure 3B The diagram illustrates SSW_IR_R(n)380 instead of being applied to Figure 3B The pulse of SSW_R(n)376, as illustrated in the diagram, is used to reset the floating diffusion region and read out the short exposure reset signal.

[0093] Figure 3D Box 327 shows one or more invisible pixels (e.g., with...) Figure 3AThe PD_IR associated pixels, as illustrated in the diagram, perform selective transfer of image charge accumulated during the short exposure period of an image frame (e.g., the first image frame) to the floating diffusion region and readout of the short exposure image signal to the storage capacitor for one or more invisible pixels. As previously discussed, it is desirable to include the short exposure image signal of the invisible pixels in the second set of pixels while maintaining the long exposure image signal of the visible pixels. This can be achieved by asserting appropriate control lines (e.g., applied to...). Figure 3A The above diagram illustrates TX(n)362 and SEL 358, and Figure 3B The diagram illustrates SSW_IR_S(n)378, not applied to... Figure 3B The pulses of SSW_S(n)374 illustrated above are used to perform selective transfer and readout. It should be understood that selective readout and reset result in the loss of long-exposure image signals associated with invisible pixels (e.g., stored in...). Figure 3B The diagram illustrates IR_C S The charge in the image is replaced by the corresponding short-exposure image signal.

[0094] It should be understood that in some embodiments, Figure 3C The boxes 321 and 325 of method 350 illustrated in the figure can collectively correspond to Figure 2A The blocks 218 of the method 200 illustrated herein may contain the same or similar features. Additionally, in the same or other embodiments, Figure 3C The boxes 323 and 327 of method 350 illustrated in the figure can collectively correspond to Figure 2A The method 200 illustrated in the figure includes boxes 220 and 222, all of which may contain the same or similar features.

[0095] Figure 3D The diagram in box 329 illustrates how multiple storage capacitors (e.g., from each of multiple pixels) are accessed through the following operations. Figure 3B The storage capacitor R_C is illustrated in the diagram. S B_C S G_C S and IR_C S ) and multiple reset capacitors for each of the multiple pixels (e.g., Figure 3B The reset storage capacitor R_C is illustrated in the diagram. R B_C R G_C R and IR_C R Read out the stored charge signal to generate image data corresponding to or otherwise representing an image frame (e.g., a first image frame); assert the appropriate control lines (applied to at the appropriate time). Figure 3Bthe SSW_R(n+1) 377, SSW_S(n+1) 375, SSW_R(n) 376, SSW_S(n) 374, SSW_IR_R(n) 380, or SSW_IR_S(n) 378, and RS(n) 384 to read out the stored charge signal to a bit line, which in turn reaches a column circuit that converts the signal level minus the reset level into a digital value (e.g., image data). It should be appreciated that in some embodiments, reading out the stored charge signal can be performed on a row-by-row basis (e.g., while multiple photodiodes are accumulating image charges for a subsequent image frame). In some embodiments, block 329 can be similar to and can include the same or similar features as block 224 illustrated in Figure 2A

[0096] If additional image frames are to be captured, block 331 returns to block 305 via "B" and method 350 continues to capture the next image frame. If no additional image frames are needed, block 331 proceeds to block 333 and method 350 ends or otherwise terminates.

[0097] Figure 4 An example pixel control line arrangement 400 for a logic die 451 in accordance with the teachings of this disclosure is illustrated. It should be appreciated that the control line arrangement 400 illustrating a plurality of pixel cells 410 (e.g., a first pixel cell 410-1 and a second pixel cell 410-2) can have circuitry similar to that described in various embodiments of this disclosure (e.g., the distributed circuitry arrangement illustrated in Figure 1D Figure 3A and / or Figure 3B may incorporate various methods of this disclosure (e.g., the method 200 illustrated in Figure 2A and / or Figure 3C and Figure 3D method 350 illustrated in). Thus, Figure 4 The control line arrangement 400 illustrated in shows control line traces for rows n, n+1, n+2, and n+3, including SSW_R, SSW_S, SSW_IR, and SSW_IR_S, with similar naming of control lines having similar functionality as described in embodiments of this disclosure. The control line arrangement 400 also includes an "other" overlay label that provides a representation of a set of control lines that can otherwise exist that are not explicitly illustrated (e.g., CS(n), CSW(n), RS(n), and RST2(n) for other (n), etc.).

[0098] As Figure 4 ​​In the illustrated embodiment, some rows contain only visible pixels (e.g., row n+1 and row n+3), while other rows contain visible and non-visible pixels (e.g., row n and row n+2). However, in the illustrated embodiment, it can not be desirable to obtain a short exposure image and a reset signal for each infrared pixel (e.g., pixels labeled IR1 and IR2). For example, a lower resolution non-visible image of the external scene (e.g., an image based on infrared light or other non-visible electromagnetic radiation) can be acceptable, which can free up every other infrared pixel (e.g., IR1 or IR2) for purposes other than generating a short exposure image signal. Thus, in some embodiments, IR1 or IR2 can be used to generate a calibration image signal for visible color pixels (e.g., red, green, and blue pixels) during a long exposure period. For example, infrared pixel IR1 (a first type of infrared pixel) can be configured to store image signals captured during a short exposure period and a reset signal to capture emitted non-visible light without interference from nearby visible color pixels (e.g., red, green, and blue pixels), and infrared pixel IR2 (a second type of infrared pixel) can be configured to store an image and a reset signal captured during a long exposure period simultaneously with other visible color pixels for pixel calibration purposes, reducing color cross-talk between the infrared pixel and nearby visible color pixels. In some embodiments, IR1 and IR2 pixels can be structurally identical. However, in other embodiments, IR1 and IR2 pixels can differ from one another (e.g., via a color filter or other component) depending on their intended function. In one embodiment, a color filter associated with an IR2 pixel can block or otherwise attenuate visible light to generate a reference signal that can be subtracted from a long exposure image signal associated with nearby visible pixels (e.g., to mitigate the effects of ambient infrared light affecting the long exposure image signal). In other embodiments, a color filter of an IR2 pixel can block all light to generate a black reference signal to be subtracted from a long exposure image signal.

[0099] It should be appreciated that in the illustrated embodiment, infrared pixels IR1 and IR2 are coupled differently to control lines (e.g., SSW_R(n), SSW_S(n), SSW_IR_S(n), etc.), which need not be the same on a row-by-row basis (e.g., the connections of the control lines for row n need not be the same as the connections of the control lines for row n+1). For example, for pixels in a given row (e.g., row n, which includes two blue (B) pixels, an IR1 pixel, and an IR2 pixel of a sensor wafer, with a first B pixel adjacent to IR2 and a second B pixel adjacent to IR1 and IR2), the control lines are coupled to the pixel circuitry of the pixels in a particular manner. Each of the pixels can include a corresponding storage capacitor, a reset storage capacitor, a storage gate, a storage transistor, a reset storage gate, a reset storage transistor, etc., as appropriate for the pixel type (e.g., B, IR1, IR2). For example, the pixel circuitry for the IR1 pixel can include a storage capacitor Cstg, a reset storage capacitor CstgR, a storage gate Gstg, a storage transistor Tstg, a reset storage gate GstgR, and a reset storage transistor TstgR. The pixel circuitry for the IR2 pixel can include a storage capacitor Cstg, a reset storage capacitor CstgR, a storage gate Gstg, a storage transistor Tstg, a reset storage gate GstgR, and a reset storage transistor TstgR. The pixel circuitry for the first B pixel can include a storage capacitor Cstg, a reset storage capacitor CstgR, a storage gate Gstg, a storage transistor Tstg, a reset storage gate GstgR, and a reset storage transistor TstgR. The pixel circuitry for the second B pixel can include a storage capacitor Cstg, a reset storage capacitor CstgR, a storage gate Gstg, a storage transistor Tstg, a reset storage gate GstgR, and a reset storage transistor TstgR. Figure 1DAs illustrated, this means that for a given row illustrated in Figure 4 each pixel has corresponding pixel circuitry (e.g., at least four storage capacitors in row n, at least four storage gates in row n, etc.). In the context of Figure 1D returning reference to Figure 4 , the storage control line SSW_S(n) is coupled to the storage gates of the blue pixels in row n and the IR1 pixels in row n, but not to the storage gates of the IR2 pixels of row n. Separate control lines for reading out the IR2 pixels in row n (e.g., via SSW_IR_S(n)) allow for selective storage of image signals with respect to the blue pixels and IR1 pixels in row n. The same applies to reset operations (e.g., via SSW_R and SSW_IR_R). Additionally, it should be appreciated that in the illustrated embodiment, the connections of the IR1 and IR2 pixels are alternating. For example, in row n+2, IR1 is located in the same column as IR2 in row n. It should further be appreciated that in some embodiments, for the convenience of row readout, the IR1 and IR2 pixels can be alternately disposed on a row basis in the pixel array. For example, one or more first visible color pixels (e.g., red, green, blue, or other color) and first non-visible pixels (e.g., first infrared or IR1 pixels) that share control lines (e.g., via SSW_R(n) and SSW_S(n) for simultaneous readout and reset of the first visible color pixels and first non-visible color pixels) are arranged in a first common row, while one or more second visible color pixels (e.g., red, green, blue, or other color) and second non-visible pixels (e.g., second infrared or IR2 pixels) that can be read out and reset independently of one another (e.g., separate control lines (e.g., SSW_IR_R(n) and SSW_IR_S(n)) read out and reset the IR2 pixels independent of the second visible color pixels) are arranged in a second common row, where the first common row and the second common row are alternately arranged in the pixel array.

[0100] Thus, in the illustrated embodiment, there are generally two types of adjacent pair of pixel connections. A first pair of pixels along a common row that includes visible (e.g., red, green, blue, or other color) and non-visible pixels (e.g., infrared) that can be read out and reset independently of one another (i.e., separate control lines (e.g., SSW_IR_R(n) and SSW_IR_S(n)) read out and reset the IR2 pixels of row n independent of the B and IR1 pixels of row n), and a second pair of pixels along a common row that includes visible (e.g., red, green, blue, or other color) and non-visible pixels (e.g., infrared) that cannot be read out and reset independently of one another (i.e., shared control lines (e.g., SSW_R(n) and SSW_S(n)) simultaneously read out and reset the B pixels and IR1 pixels of row n). Then, as with Figure 2A, Figure 3C and / or Figure 3D the operation discussed is implemented. For example, in an image frame having a short exposure period and a long exposure period, image charges during the short exposure period can be stored (e.g., via control lines associated with IR2), while also storing image charges during the long exposure period of the image frame (e.g., control lines associated with R, G, B, and IR1 pixels).

[0101] In one embodiment, the operations include transferring first image charges accumulated during a long exposure period of a first image frame to respective floating diffusion regions of the first, second, third, and fourth pixels, reading out long exposure image signals from the respective floating diffusion regions to respective storage capacitors (e.g., first, second, third, and fourth storage capacitors associated with the first, second, third, and fourth pixels, respectively), and reading out storage charge signals from the first, second, third, and fourth storage capacitors to generate image data for the first image frame such that the image data is based on corresponding ones of long exposure image signals associated with the first, third, and fourth pixels (e.g., red, green, blue, and / or IR1 pixels) and a short exposure image signal associated with the second pixel (e.g., an IR2 pixel). This can be accomplished by asserting the first, second, and third storage control line signals after the long exposure period of the first image frame to initiate reading out the long exposure image signals, and asserting the second storage control line signal, but not the first and third storage control lines, to initiate reading out the short exposure image signal to the second storage capacitor and replacing the previous stored signal associated with the long exposure period of the first image frame. When the first, third, and fourth pixels are distributed across more than one row, the first storage control line signal can be applied to SSW_S(n), the second storage control line signal can be applied to SSW_IR_S(n), and the third storage control line signal is applied to SSW_S(n+1) or some other SSW_S control line on a different row than row n.

[0102] Figure 5A FIG. illustrates example pixel circuitry 550 for individual pixels 505-N included in an imaging system, in accordance with the teachings of this disclosure. More specifically, Figure 5A The pixel circuitry 550 illustrated in FIG. is distributed across at least the sensor wafer 501 and the logic wafer 551, with the circuitry for the pixels 505-N located on the sensor wafer 501 and the pixel circuitry 553-N located on the logic wafer 551. The pixel circuitry 550 is similar in many respects to the pixel circuitry 150 illustrated in FIG.. Figure 1D The pixel circuitry 550 illustrated in FIG. is distributed across at least the sensor wafer 501 and the logic wafer 551, with the circuitry for the pixels 505-N located on the sensor wafer 501 and the pixel circuitry 553-N located on the logic wafer 551. The pixel circuitry 550 is similar in many respects to the pixel circuitry 150 illustrated in FIG.. Figure 5APixel circuit 550 includes similarly labeled elements (e.g., VDD, RST1, FD, TX, PD, SF1, SEL, RST2, CSW, CS, RS, SF2, CSW, CS, and bit line) that can operate in similar manners or otherwise include the same features as described with respect to Figure 1D In other words, pixel circuit 550 can be one possible implementation of imaging system 100 illustrated in Figure 1A Thus, pixel circuit 550 can be implemented in various embodiments of the present disclosure.

[0103] Figure 1D One difference between pixel circuit 150 of Figure 5A and pixel circuit 550 of Figure 1D is that pixel circuitry 553-N of pixel 505-N includes a set of at least four capacitors (e.g., C RL , C SL , C RS , C SS ). In other words, instead of each pixel having only one storage node as illustrated in pixel circuit 150 of Figure 1D , each pixel in pixel circuit 550 includes at least two storage nodes to capture an image frame using multiple exposure periods (e.g., long exposure node 524-L and short exposure node 524-S). Thus, a first pixel included in the plurality of pixels (e.g., a first instance of pixel circuit 550) includes a first set of four capacitors each associated with the first pixel, including a first storage capacitor (e.g., a first instance of C SL or C SS ), and a second pixel included in the plurality of pixels (e.g., a second instance of pixel circuit 550) includes a second set of four capacitors each associated with the second pixel, including a second storage capacitor (e.g., a second instance of C SL or C SS ). In some embodiments, the number of storage nodes per pixel matches the number of exposure periods per image frame (e.g., short exposure storage node 524-S for short exposure periods, and long exposure node 524-L for long exposure periods), which can be advantageous for certain pixel layouts. For example, in one embodiment, each pixel cell can be formed from visible pixels (e.g., a red pixel, a blue pixel, and two green pixels). In the same or other embodiments, the color filter of one or more of the visible pixels can permit sufficient transmission of infrared light such that a short exposure image signal associated with the emitted infrared light can still be captured.

[0104] Figure 5B FIG. 2 illustrates an example pixel control line arrangement 252 of sensor die 201 of the imaging system illustrated in Figure 5A FIG. 1, in accordance with the teachings of this disclosure.Figure 5B The pixel control line arrangement 552 illustrated in the diagram is similar to Figure 1E The pixel control line arrangement 152 illustrated in the figure may include the same or similar features. One difference lies in the pixel layout of individual pixel units. Pixel units include red pixels (e.g., pixels labeled R), blue pixels (e.g., pixels labeled B), and two green pixels (e.g., pixels labeled G1 and G2), which may be arranged based on a Bayer pattern, but do not include infrared pixels. In other words, for a given pixel unit, neighboring pixels are different visible color pixels (e.g., G1 and R are different visible color pixels, G2 and B are different visible color pixels, etc.). It should be understood that, according to embodiments of this disclosure, control lines (e.g., RST1, TX, and SEL) may be used respectively to apply pulses to the coupled circuit elements (e.g., ...) of the pixel. Figure 5B The SEL control line is operable to control Figure 5A (SEL transistor illustrated in the figure). In the same or other embodiments, the control lines of adjacent rows (e.g., row n and row n+1) may be symmetrical about axis 568.

[0105] Figure 5C Diagrammatic explanation based on the teachings of this disclosure Figure 5A The illustration shows an example pixel control line arrangement 572 for the logic chip 551. Figure 5B The pixel control line arrangement illustrated in Figure 572 is similar to Figure 1F The pixel control line arrangement 172 illustrated in the diagram may include the same or similar features. One difference is that, instead of having dummy control lines (e.g., Figure 1F The control lines SSW_IR_S(n+1)179 and SSW_IR_R(n+1)181 illustrated in the diagram exist as individual control lines coupled to each capacitor contained in each of the multiple memory nodes (e.g., Figure 5C SSW_R(n)_LONG, SSW(S(n)_LONG, SSW_R(n)_SHORT, and SSW_S(n)_SHORT are respectively coupled to Figure 5A The capacitor C illustrated in the figure RL C SL C RS and C SS), to generate the image and reset signals for each exposure period (e.g., long exposure period and short exposure period) without having to replace any previously stored signals (e.g., the short exposure image and reset signals can be obtained without replacing the long exposure image and reset signals). Since the capacitor of each pixel (e.g., a set of four capacitors collectively included in the long exposure storage node 524-L and the short exposure storage node 524-S) is controlled on a row-by-row basis (e.g., row n, row n+1, etc.), each storage control line (e.g., a first storage control line corresponding to SSW S(n)_LONG or SSW S(n)_SHORT) is coupled to multiple transistor gates (e.g., for each pixel in a given row, to the gates of the Figure 5A SSW SL or SSW SS transistor associated with the gate).

[0106] Figure 5C The control line arrangement 572 of the logic die 551 is also similar in many respects to the control line arrangement 172 of Figure 1F . For example, the control lines of the logic die 551 associated with adjacent rows (e.g., row n and row n+1) can be symmetric about the axis 595. In the same or other embodiments, the control lines are positioned to maintain control line symmetry of the logic die 551 such that a first separation distance 591 between the control line SSW S(n)_LONG and the control line SSW S(n)_SHORT is equal to a second separation distance 593 between the control line SSW S(n+1)_LONG and the control line SSW S(n+1)_SHORT.

[0107] It should be appreciated that the operation of controlling an imaging system having pixel cell circuitry, layout, and control line arrangements as illustrated in Figures 5A to 5C is similar to the operation of the method 200 illustrated in Figure 2A . One difference is that, instead of performing selective readout (e.g., blocks 218-222), the short exposure image and reset signals for each pixel are also stored or otherwise read out, such that the image signals for each pixel include both the short exposure image signals and the long exposure image signals and the reset signals include both the short exposure reset signals and the long exposure reset signals.

[0108] Figure 5DAn exemplary timing diagram 580 illustrates, according to the teachings of this disclosure, the selective readout of image frames representing an external scene (e.g., first image frame 581 and second image frame 583) during long and short exposure periods (e.g., long exposure period 5811 and short exposure period 5813 of the first image frame 581). The short exposure period has a duration shorter than the long exposure period. Timing diagram 580 provides information from an image sensor or imaging system (e.g., Figure 1A The imaging system 100 illustrated in the figure and Figures 5A to 5C The illustration shows a visual representation of the exposure and readout of multiple rows of exemplary photodiodes (as illustrated in the diagram). As discussed in previous embodiments, the multiple pixels include visible color pixels (e.g., such as...). Figure 5B and Figure 5C The color filter arrangement shown indicates red, green, and blue. Before the long exposure period 5811, the photodiodes (e.g., of each visible color pixel) are pulsed by applying pulses to the corresponding reset control line RST1 and transfer control line TX. Figure 5A The diagram illustrates the PD and the floating diffusion region (e.g., Figure 5A The corresponding floating diffusion region (FD) illustrated in the diagram is reset. During the long exposure period 5811, the photodiode (e.g., in each of the visible pixels) is reset. Figure 5A The image charge is accumulated by the PD (PD) illustrated in the diagram. Then, in order to end the long exposure cycle, the floating diffusion region is reset by applying a pulse to the corresponding reset control line RST1, wherein the reset is performed by applying a pulse to the corresponding reset storage control line (e.g., as shown in the diagram). Figure 5C The diagram illustrates that pulses are applied to SSW_R(n)_LONG and SSW_R(n+1)_LONG to read the reset signal to the reset storage capacitor C associated with the long exposure. RL (like Figure 5A (Illustrated in the diagram) to turn on the reset storage transistor SSW, which is contained in each of the multiple pixels. RL This allows the reset signal to be read out to the reset storage capacitor associated with each of the multiple pixels (e.g., Figure 5A The reset storage capacitor C illustrated in the figure RL Subsequently, the accumulated image charge is read out into the floating diffusion region (e.g., Figure 5A The corresponding floating diffusion region FD is illustrated in the diagram. Then, for each pixel contained in multiple pixels, by directing the data to the storage control line (e.g., as shown in the diagram), Figure 5C The diagram illustrates that pulses are applied to the SSW_S(n)_LONG and SSW_S(n+1)_LONG transistors (e.g., with...). Figure 5AThe diagram illustrates the long exposure-related storage transistor SSW. SL ) is turned on to read out the long exposure image signal to the image storage capacitor (e.g., ) associated with each of the multiple pixels. Figure 5A The storage capacitor C illustrated in the figure SL Shortly thereafter, a short exposure cycle 5813 begins, during which light source 241 emits electromagnetic radiation pulses (e.g., light with wavelengths between 800 nm and 3000 nm, or light otherwise corresponding to invisible light or electromagnetic radiation) toward the external scene captured by the image sensor, and charge is accumulated in the photodiodes of each of the multiple pixels. Then, to end the short exposure cycle, the floating diffusion region (e.g., Figure 5A The floating diffusion region (FD) illustrated in the diagram is reset, wherein the reset is achieved via a corresponding reset storage control line (e.g., as shown in the diagram). Figure 5C The diagram illustrates how pulses are applied to SSW_R(n)_SHORT and SSW_R(n+1)_SHORT to read the reset signal. Figure 5A The diagram illustrates the reset storage capacitor C associated with short exposure. RS This turns on the storage transistor SSW contained in each of the multiple pixels. RS To read the reset signal to a reset storage capacitor associated with each of the multiple pixels (e.g., Figure 5A The reset storage capacitor C illustrated in the figure RS Subsequently, the accumulated image charge is read out into the floating diffusion region (e.g., Figure 5A The floating diffusion region (FD) illustrated in the diagram, in which the storage transistors associated with the short exposure in each pixel are activated to read out the short exposure image signal (e.g., Figure 5A The storage transistor SSW illustrated in the figure SS via, for example Figure 5C The storage control lines such as SSW_S(n)_SHORT, as illustrated in the diagram, are pulsed. Then, the next image frame (e.g., the second image frame 583) begins and a rolling readout of the stored charge signal is performed to generate image data for the first image frame 581. In other words, the readout of the stored charge signal to generate image data is completed on a line-by-line basis.

[0109] Figure 6 This is a functional block diagram of an imaging system 600 capable of selective readout for visible-infrared image capture, based on the teachings of this disclosure. The imaging system 600 is implementable. Figure 2A Method 250 illustrated in the diagram Figure 3A and Figure 3B Method 350 and / or illustrated in the figure Figure 5Bone possible system of the method 550 illustrated in FIG. 6. Thus, it should be appreciated that, in accordance with the teachings of the present disclosure, an imaging system 600 can have corresponding or otherwise similar components to those illustrated in Figures 1A to 1F the imaging system 100 illustrated in FIG. 1, Figure 1D , Figure 3A , Figure 3B , Figure 5A the circuitry illustrated in FIG. 6, Figure 1E , Figure 1F , Figure 3A , Figure 3B , Figure 4 , Figure 5B , Figure 5C the control line arrangement illustrated in FIG. 6, or combinations thereof. As illustrated, the imaging system 600 includes a sensor wafer 601 coupled to a logic wafer 651, optics 615, a light source 617, and optics 619. The sensor wafer 601 includes a semiconductor material 631 (e.g., silicon or a wafer), a plurality of photodiodes 633, a plurality of color filters 635 (e.g., red, green, blue, infrared, or other color filters arranged over the plurality of photodiodes 633 to form one or more pixel cells), and a plurality of microlenses 637 arranged to focus portions of incident light 698 onto individual photodiodes included in the plurality of photodiodes 633. The light source 617 is optically coupled to the optics 619 (e.g., one or more optical components such as one or more lenses, filters, or other elements) and is operable to emit electromagnetic radiation of a first spectrum (e.g., infrared light including a first wavelength between 800 nm and 3000 nm) toward an external scene 603, which electromagnetic radiation of the first spectrum can then be reflected as incident light 698 (e.g., during a short exposure period).

[0110] The logic die 651 at least partially functions as a controller 610 that includes logic and / or circuitry to control operation of various components of the imaging system 600, e.g., during pre-, post-, and in-situ stages of image and / or video acquisition. The controller 610 can be implemented as hardware logic (e.g., application specific integrated circuitry, field programmable gate array, system on a chip, etc.), software / firmware logic executing on a general purpose microcontroller or microprocessor, or a combination of hardware and software / firmware logic. In one embodiment, the controller 610 includes a processor 612 coupled to a memory 614 that stores instructions executed by the controller 610 or otherwise by one or more components of the imaging system 600. The instructions, when executed, can cause the imaging system 600 to perform operations associated with various functional modules, logic blocks, or circuitry of the imaging system 600, including any of the control circuitry 616, readout circuitry 618, functional logic 620, components of the sensor die 601, optics 615 (e.g., an objective having one or more optical components that can be adjusted to provide variable focus), and any other elements of the imaging system 600 (illustrated or otherwise), or a combination thereof.

[0111] The memory 614 is a non-transitory machine-accessible (e.g., computer-readable) medium that can include, but is not limited to, volatile (e.g., RAM) or non-volatile (e.g., ROM) storage systems that are accessible / readable by the controller 610. In some embodiments, a machine that has access to the non-transitory machine-accessible medium corresponds to the imaging system 600, including the logic die 651 coupled to the sensor die 601. In the same or other embodiments, the non-transitory machine-accessible storage medium corresponds to on-chip memory (e.g., the memory 614 and / or the functional logic 620) of a machine (e.g., the imaging system 600 or components thereof) to capture visible-infrared images via selective readout.

[0112] Control circuitry 616 can control operational characteristics of imaging system 600 (e.g., exposure duration, when to capture digital images or video, etc.). Control circuitry 616 can further control operation of light source 617 in accordance with imaging operations of the pixel cells formed by the plurality of photodiodes 633. Readout circuitry 618 reads or otherwise samples analog signals from individual photodiodes (e.g., reads out electrical signals generated by each of the plurality of photodiodes 633 representing image charges generated in response to incident light to generate phase detection signals, reads out image signals to capture image frames or video, etc.) and can include amplification circuitry, analog-to-digital (ADC) circuitry, image buffers, or others. In the illustrated embodiment, readout circuitry 618 is included in controller 610, but in other embodiments, readout circuitry 618 can be separate from controller 610. Functional logic 680 is coupled to readout circuitry 618 to receive electrical signals, in response generate phase detection signals, generate images in response to receiving image signals or data, etc. In some embodiments, electrical signals or image signals can be stored as phase detection signals or image data, respectively, and can be manipulated by functional logic 420 to perform operations (e.g., compute expected image signals, grade image signals, demosaic image data, apply post-image effects such as cropping, rotation, red-eye removal, adjust brightness, adjust contrast, detect presence of occlusions, or others).

[0113] It should be appreciated that the imaging systems discussed herein (e.g., Figures 1A to 1F the imaging system 100 and Figure 6The imaging system 600 illustrated in the middle can be fabricated by semiconductor device processing and microfabrication techniques known to those skilled in the art. In one embodiment, fabrication of the imaging system 600 can include providing a semiconductor material (e.g., a silicon wafer having a front side and a back side), forming a mask or template (e.g., formed from solidified photoresist) on the front side of the semiconductor material via photolithography to provide a plurality of exposed regions of the front side of the semiconductor material, doping the exposed portions of the semiconductor material (e.g., via ion implantation, chemical vapor deposition, physical vapor deposition, etc.) to form a plurality of photodiodes 635 extending from the front side of the semiconductor material into the semiconductor material, removing the mask or template (e.g., by dissolving the solidified photoresist with a solvent), and planarizing the front side of the semiconductor material (e.g., via chemical mechanical planarization or polishing). In the same or another embodiment, photolithography can similarly be used to form the plurality of color filters 635 and the plurality of microlenses 637 (e.g., individual or shared microlenses, which can be polymer-based microlenses having a target shape and size formed from a master mold or template). It should be appreciated that the described techniques are merely illustrative and not exhaustive, and other techniques can be utilized to fabricate one or more components of various embodiments of the present disclosure.

[0114] The processes explained above can employ software and / or hardware. The described techniques can constitute machine-executable instructions embodied within tangible or non-transitory machine (e.g., computer) readable storage media used in operation of the machine. Such machine-executable instructions can be used to program computing devices (e.g., controller 610 of FIG. 6) to implement processes described herein. Figure 6 The processes explained above can be implemented using software and / or hardware. The software comprises machine executable instructions 620 stored on machine- readable storage medium 630 (e.g., non-transitory storage medium) at a computing device (e.g., controller 610 of FIG. 6). These instructions 620 represent an embodiment of a technical solution to a problem in the art and are used to program the machine (e.g., controller 610) to implement a process described herein. The instructions 620 can be provided on the machine-readable storage medium 630 by embedding them in the machine-readable storage medium 630 (e.g., recording them on the machine-readable storage medium 630), by writing them to the machine-readable storage medium 630 (e.g., downloading them onto the machine-readable storage medium 630), or by any other method of encoding the machine- executable instructions 620 on the machine-readable storage medium 630.

[0115] Tangible machine-readable storage media includes any mechanism that provides (i.e., stores) information in a non-transitory form accessible by a machine (e.g., a computer, network device, personal digital assistant, manufacturing tool, any device with a set of one or more processors, etc.). For example, machine-readable storage media includes recordable / non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).

[0116] The above description of illustrated embodiments of the application, including what is described in the abstract, is not intended to be exhaustive or to limit the application to the precise forms disclosed. While specific embodiments of, and examples for, the application are described herein for illustrative purposes, various modifications are possible within the scope of the application, as those skilled in the relevant art will recognize.

[0117] These modifications can be made in light of the above detailed description. The terms used in the following claims should not be construed to limit the application to the specific examples disclosed in the specification and the claims are to be accorded the full scope consistent with the principles of patent law.

Claims

1. An imaging system comprising: a sensor wafer including: a plurality of pixels arranged in a number of rows and a number of columns, the plurality of pixels including at least a first pixel and a second pixel positioned in a first row included in the rows, wherein each pixel included in the plurality of pixels includes a respective photodiode configured to accumulate image charge in response to incident light; and a first transfer control line associated with the first row, wherein the first transfer control line is coupled to both a first transfer gate of the first pixel and a second transfer gate of the second pixel; and a logic wafer coupled to the sensor wafer, the logic wafer including: a plurality of storage capacitors, each storage capacitor associated with a respective one of the plurality of pixels of the sensor wafer, wherein the plurality of storage capacitors includes a first storage capacitor associated with the first pixel and a second storage capacitor associated with the second pixel; a first storage control line coupled to a first storage gate associated with the first pixel, wherein the first storage gate is included in a first storage transistor coupled to the first storage capacitor; and a second storage control line coupled to a second storage gate associated with the second pixel, and wherein the second storage gate is included in a second storage transistor coupled to the second storage capacitor.

2. The imaging system of claim 1, wherein the first storage control line is separate from the second storage control line to provide selective readout to at least one of the first storage capacitor or the second storage capacitor.

3. The imaging system of claim 2, wherein the first pixel is a visible color pixel and the second pixel is an infrared pixel adjacent to the visible color pixel.

4. The imaging system of claim 1, wherein the sensor wafer includes a floating diffusion region coupled to the respective photodiodes of the first pixel and the second pixel via the first transfer gate and the second transfer gate to selectively read out the image charge from the first pixel and the second pixel.

5. The imaging system of claim 1, wherein the plurality of pixels included in the sensor wafer further include a third pixel and a fourth pixel positioned in a second row included in the row, wherein, the second row adjacent to the first row such that the first pixel, the second pixel, a third pixel, and a fourth pixel form a first pixel cell included in a plurality of pixel cells of the imaging system, wherein the plurality of storage capacitors included in the logic wafer includes a third storage capacitor associated with the third pixel and a fourth storage capacitor associated with the fourth pixel, and wherein the logic wafer further includes: a third storage control line coupled to both a third storage gate associated with the third pixel and a fourth storage gate associated with the fourth pixel, wherein the third storage gate is included in a third storage transistor coupled to the third storage capacitor, wherein the fourth storage gate is included in a fourth storage transistor coupled to the fourth storage capacitor.

6. The imaging system of claim 5, wherein the first pixel cell is similar to a minimum repeat unit of the imaging system.

7. The imaging system of claim 5, wherein the logic wafer further includes a dummy storage control line positioned proximate to the third storage control line, wherein the dummy storage control line is not connected to any gate, including the first, second, third, and fourth storage gates associated with the first, second, third, or fourth pixels.

8. The imaging system of claim 7, wherein, During operation of the imaging system, the dummy storage control line is biased to a predetermined value corresponding to a logic low of the third storage control line.

9. The imaging system of claim 7, wherein the dummy storage control line is positioned to maintain a control line symmetry of the logic wafer such that a first separation distance between the first and second storage control lines is equal to a second separation distance between the third storage control line and the dummy storage control line.

10. The imaging system of claim 1, wherein the logic wafer further includes: a plurality of reset storage capacitors including a first reset storage capacitor associated with the first pixel and a second reset storage capacitor associated with the second pixel; a first reset storage control line coupled to a first reset storage gate associated with the first pixel, wherein the first reset storage gate is included in a first reset storage transistor coupled to the first reset storage capacitor; and a second reset storage control line coupled to a second reset storage gate associated with the second pixel, and wherein the second reset storage gate is included in a second reset storage transistor coupled to the second reset storage capacitor, and wherein the first and second reset storage control lines are separate to provide selective readout to at least one of the first or second reset storage capacitors.

11. The imaging system of claim 1, wherein the logic wafer further includes a reset transistor associated with the first pixel, the reset transistor coupled between the first storage transistor of the logic wafer and a floating diffusion region included in the first pixel of the sensor wafer.

12. The imaging system of claim 1, wherein the first and second pixels are different visible color pixels adjacent to each other.

13. The imaging system of claim 12, wherein the logic wafer further includes: a first set of four capacitors including the first storage capacitor, each associated with the first pixel; and a second set of four capacitors including the second storage capacitor, each associated with the second pixel. a second set of four capacitors including the second storage capacitor, each associated with the second pixel, wherein the first storage control line is further coupled to a transistor gate associated with a capacitor included in the second set of four capacitors other than the second storage capacitor, and wherein the second storage control line is further coupled to a transistor gate associated with a capacitor included in the first set of four storage capacitors other than the first storage capacitor.

14. The imaging system of claim 1, further comprising a light source adapted to emit electromagnetic radiation of a first spectrum during a short exposure period of an image frame capture operation, the first spectrum including at least a first wavelength, and wherein the second pixel is more sensitive to the first wavelength than the first pixel.

15. A logic die for an imaging system, the logic die comprising: a plurality of storage capacitors, each storage capacitor configured to store an image signal associated with a respective one of a plurality of pixels, wherein the plurality of storage capacitors includes a first storage capacitor associated with a first pixel included in a first row of the plurality of pixels and a second storage capacitor associated with a second pixel included in the first row of the plurality of pixels, wherein the plurality of pixels is coupled to the logic die by an interconnect; a first storage control line coupled to a first storage gate associated with the first pixel, wherein the first storage gate is included in a first storage transistor coupled to the first storage capacitor; and a second storage control line coupled to a second storage gate associated with the second pixel, and wherein the second storage gate is included in a second storage transistor coupled to the second storage capacitor.

16. The logic die of claim 15, wherein the first storage control line is separate from the second storage control line to provide selective readout to at least one of the first storage capacitor or the second storage capacitor.

17. The logic die of claim 15, further comprising a third storage control line coupled to both a third storage gate associated with a third pixel included in the plurality of pixels and a fourth storage gate associated with a fourth pixel included in the plurality of pixels, wherein the third pixel and the fourth pixel are located in a second row of the plurality of pixels adjacent to the first row, wherein the third storage gate is included in a third storage transistor coupled to a third storage capacitor included in the plurality of storage capacitors, and wherein the fourth storage gate is included in a fourth storage transistor coupled to a fourth storage capacitor included in the plurality of storage capacitors.

18. The logic die of claim 17, further comprising a dummy storage control line positioned proximate to the third storage control line, wherein the dummy storage control line is not connected to any gate, including the first, second, third, and fourth storage gates associated with the first, second, third, and fourth pixels.

19. The logic die of claim 18, wherein the dummy storage control line is positioned to maintain a control line symmetry of the logic die, such that a first separation distance between the first storage control line and the second storage control line is equal to a second separation distance between the third storage control line and the dummy storage control line.

20. The logic die of claim 15, wherein the plurality of storage capacitors further comprises a third storage capacitor associated with a third pixel included in the first row of the plurality of pixels, wherein the first pixel is a visible color pixel, the second pixel is a first infrared pixel adjacent to the first pixel, and the third pixel is a second infrared pixel, wherein the first storage control line is further coupled to a third storage gate associated with the third pixel, and wherein the third storage gate is included in a third storage transistor coupled to the third storage capacitor.

21. The logic die of claim 15, further comprising: a third storage capacitor associated with a third pixel and a fourth storage capacitor associated with a fourth pixel; and a third storage control line coupled to a third storage gate associated with the third pixel and a fourth storage gate associated with the fourth pixel, wherein the third storage gate is included in a third storage transistor coupled to the third storage capacitor, and wherein the fourth storage gate is included in a fourth storage transistor coupled to the fourth storage capacitor.

22. The logic die of claim 21, wherein the first and third pixels are visible color pixels, wherein the second and fourth pixels are infrared pixels, wherein the second pixel is adjacent to the first pixel, and wherein the fourth pixel is adjacent to the third pixel.

23. The logic die of claim 22, wherein the third and fourth pixels are included in the first row of the plurality of pixels, and wherein the third storage control line is the first storage control line separate from the second storage control line to provide selective readout to the second storage capacitor by the first storage control line relative to the first, third, and fourth storage capacitors.

24. The logic die of claim 23, wherein the first and third storage capacitors are included in a first row of the plurality of storage capacitors, and wherein the second and fourth storage capacitors are included in a second row of the plurality of storage capacitors.

25. The logic die of claim 24, wherein the first and third storage capacitors are included in a first column of the plurality of storage capacitors, and wherein the second and fourth storage capacitors are included in a second column of the plurality of storage capacitors.

26. The logic die of claim 25, wherein the first and third storage capacitors are included in a first column of the plurality of storage capacitors, and wherein the second and fourth storage capacitors are included in a second column of the plurality of storage capacitors.

27. The logic die of claim 26, wherein the first and third storage capacitors are included in a first column of the plurality of storage capacitors, and wherein the second and fourth storage capacitors are included in a second column of the plurality of storage capacitors.

28. The logic die of claim 27, wherein the first and third storage capacitors are included in a first column of the plurality of storage capacitors, and wherein the second and fourth storage capacitors are included in a second column of the plurality of storage capacitors.

29. The logic die of claim 28, wherein the first and third storage capacitors are included in a first column of the plurality of storage capacitors, and wherein the second and fourth storage capacitors are included in a second column of the plurality of storage capacitors.

30. The logic die of claim 29, wherein the first and third storage capacitors are included in a first column of the plurality of storage capacitors, and wherein the second and fourth storage capacitors are included in a second column of the plurality of storage capacitors.

Images