A testable design method for chip

Abstract

The present application discloses a testable design method for a chip, and relates to the field of chips. The testable design method optimizes and designs a resource module at at least one predetermined position inside a chip as a dual-mode resource module based on the module infrastructure of the resource module, and designs a chip containing the dual-mode resource module inside. Then, a direct path from the input end to the output end formed by the dual-mode resource module when it is in a direct working mode can be used to construct a test path between a test input and output port and a resource module to be tested without affecting the test coverage. The testable design method improves the testability of the chip, ensures the test requirements of the resource modules in the chip, meets the test requirements of the chip and improves the test efficiency.

Description

Technical Field

[0001] The present application relates to the field of chips, and in particular to a testable design method for chips. Background Art

[0002] With the development of electronic technology, various chips are widely used in many fields such as communication, control, video, information processing, consumer electronics, Internet, automobile, and aerospace. Various chips such as FPGA contain a large number of resource modules. These resource modules can be interconnected with other resource modules through direct connection or built-in interconnection resources. In the design process of the chip, in order to ensure the accuracy of the chip function, it is often necessary to perform functional testing on the resource modules inside the chip. At this time, it is necessary to connect the test input port to the input end of the resource module to be tested, and connect the output end of the resource module to be tested to the test output port to form a test path. Then, the test vector is input into the test input port and sent to the resource module via the test path. The test result obtained will also reach the test output port via the test path to achieve output. By analyzing the test result, the functional test of the resource module to be tested can be realized.

[0003] However, as the resource scale of chips gradually expands and the functional complexity gradually increases, it is easy to have insufficient interfaces for interconnected resources or crowded connections between interconnected resources. These problems will make it impossible to form the required test paths, and it will be impossible to complete the functional testing of the resource modules to be tested, making it difficult to meet the testing requirements and even affecting the design process and functional reliability of the entire chip. Summary of the invention

[0004] In view of the above problems and technical requirements, this application proposes a testable design method for a chip. The technical solution of this application is as follows:

[0005] A testable design method for a chip, the testable design method comprising:

[0006] For a resource module at at least one predetermined position inside the chip, the resource module is optimized and designed as a dual-mode resource module based on the module infrastructure of the resource module, so as to obtain a chip including the dual-mode resource module inside;

[0007] Any dual-mode resource module forms a module infrastructure when in the basic working mode, and forms a direct path from the input end to the output end when in the direct working mode and is used to construct a test path between the test input and output ports and the resource module to be tested.

[0008] A further technical solution is to use a dual-mode resource module in a direct working mode to construct a test path between a test input and output port and a resource module to be tested, including:

[0009] When it is determined that a test path from the test input / output port to the resource module to be tested cannot be formed through the wiring resources inside the chip, at least one dual-mode resource module inside the control chip is switched to a direct working mode, and the dual-mode resource module switched to the direct working mode forms a direct path from the input end to the output end internally, and transmits the signal obtained from the input end to the output end unchanged;

[0010] The connection resources inside the chip are used to form a test path from the test input and output port to the resource module to be tested via a direct path inside at least one dual-mode resource module.

[0011] A further technical solution is to optimize and design the resource module into a dual-mode resource module based on the module infrastructure of the resource module, including:

[0012] The input end of the module infrastructure of the resource module is connected to the input end of the dual-mode resource module, the output end of the module infrastructure of the resource module is connected to one input end of the newly added two-input multiplexer, the other input end of the two-input multiplexer is connected to the input end of the dual-mode resource module, the output end of the two-input multiplexer is connected to the output end of the dual-mode resource module, and the control end of the two-input multiplexer is led out as the mode switching end of the dual-mode resource module. The dual-mode resource module is optimized and designed, and the dual-mode resource module switches between the basic working mode and the direct working mode according to the mode switching signal received by the mode switching end.

[0013] A further technical solution is to optimize and design the resource module into a dual-mode resource module based on the module infrastructure of the resource module, including:

[0014] A direct working mode is added to the module general function table corresponding to the module infrastructure of the resource module to update the module general function table, and a dual-mode resource module is obtained by optimizing the design according to the updated module general function table. The dual-mode resource module switches between the basic working mode and the direct working mode according to the module configuration signal.

[0015] A further technical solution is that the testable design method further includes: optimizing the design of all resource modules inside the chip into dual-mode resource modules, or optimizing the design of some resource modules inside the chip into dual-mode resource modules.

[0016] A further technical solution is that, in a test path formed by a through path inside at least one dual-mode resource module:

[0017] A vector input path between the test input port and the input end of the resource module to be tested passes through a through path inside at least one dual-mode resource module;

[0018] and / or,

[0019] The result output path from the output end of the resource module to be tested to the test output port passes through a direct path inside at least one dual-mode resource module.

[0020] A further technical solution is that any dual-mode resource module passed by the formed test path is arranged adjacent to the resource module to be tested, or is separated from other resource modules.

[0021] Its further technical solution is that for any dual-mode resource module that is switched to the pass-through working mode and connected in the test path, all input ports or part of the input ports of the dual-mode resource module are connected in the test path, and all output ports or part of the output ports of the dual-mode resource module are connected in the test path.

[0022] The beneficial technical effects of this application are:

[0023] The present application discloses a testable design method for a chip. The testable design method optimizes the resource module inside the chip into a dual-mode resource module in terms of circuit structure. Then, when constructing a test path, when it is impossible to directly use the connection resources to construct the test path, the direct path inside the dual-mode resource module is used to construct the test path without affecting the test coverage. This testable design method that combines module structure optimization with test method optimization improves the testability of the chip, ensures the test requirements of the resource modules in the chip, meets the test requirements of the chip and improves the test efficiency.

[0024] The method provides two different methods for designing a dual-mode resource module, wherein the method of adding a bypass structure based on the module infrastructure is easy to implement without redesigning the resource module, and the working mode switching is flexible.

[0025] This method can optimize the design of resource modules in only some locations inside the chip as dual-mode resource modules, or optimize the design of all resource modules as dual-mode resource modules. Increasing the number of dual-mode resource modules inside the chip can further flexibly construct the required test paths, which is beneficial to improving the testability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a structural diagram of a dual-mode resource module designed in one embodiment of the present application.

[0027] Figure 2 The diagram is a schematic diagram of forming a test path through a through path inside a dual-mode resource module in an example.

[0028] Figure 3 is a schematic diagram of forming a test path through a direct path inside a dual-mode resource module in another example.

[0029] Figure 4 is a schematic diagram of forming a test path through a direct path inside a dual-mode resource module in another example. DETAILED DESCRIPTION

[0030] The specific implementation of the present application is further described below in conjunction with the accompanying drawings.

[0031] The present application discloses a testable design method for a chip, which is targeted at various types of chips currently in the mainstream. The chip includes a large number of resource modules and connection resources arranged in a predetermined manner. The current traditional practice is to design the resource module according to the module infrastructure required by the resource module arranged at each position when designing the chip, so that the resource module can achieve a basic working mode that matches the module infrastructure. The module infrastructure of each resource module is designed according to actual needs.

[0032] The testable design method disclosed in the present application is an optimization design method based on the existing traditional practice. When implementing the testable design method of the present application, for a resource module at at least one predetermined position inside the chip, the resource module is optimized and designed as a dual-mode resource module based on the module infrastructure of the resource module, so that the dual-mode resource module has not only a basic working mode that matches the module infrastructure, but also a direct working mode that transmits the signal obtained from the input end to the output end unchanged. That is, the present application upgrades at least one resource module inside the chip to add a direct working mode on the basis of keeping the module infrastructure unchanged. Thus, a chip containing a dual-mode resource module is designed.

[0033] This application provides two implementation methods to upgrade and optimize a resource module into a dual-mode resource module:

[0034] 1. One approach is to add a direct working mode to the module general function table corresponding to the module basic structure of the resource module to update the module general function table, and optimize the design according to the updated module general function table to obtain a dual-mode resource module. The dual-mode resource module switches between the basic working mode and the direct working mode according to the module configuration signal. This approach is equivalent to redesigning the resource module, which has a great impact on the chip design process and has a high implementation cost.

[0035] 2. Another approach is to Figure 1As shown, the input end of the module infrastructure of the resource module is connected to the input end Pin of the dual-mode resource module, the output end of the module infrastructure of the resource module is connected to an input end of the newly added two-input multiplexer MUX2, and the other input end of the two-input multiplexer MUX2 is connected to the input end Pin of the dual-mode resource module. The output end of the two-input multiplexer MUX2 is connected to the output end Pout of the dual-mode resource module. The control end of the two-input multiplexer MUX2 is led out as the mode switching end Ctrl of the dual-mode resource module, so as to optimize the design to obtain the dual-mode resource module. Then, the dual-mode resource module can switch between the basic working mode and the direct working mode according to the mode switching signal received by the mode switching end Ctrl, and the dual-mode resource module can be switched to the desired working mode by inputting the corresponding mode switching signal: when MUX2 selects the input end Pin of the dual-mode resource module, the direct working mode is realized, and the signal of the input end is transmitted to the output end unchanged; when MUX2 selects the output end of the module infrastructure, the basic working mode is realized, and the signal of the input end is converted according to the function designed by the module infrastructure and outputted from the output end.

[0036] The second approach does not require redesigning the resource module. It only requires adding a bypass structure to the original module infrastructure structure. This is equivalent to optimizing the existing resource module. The implementation difficulty is much lower than the first approach, so it is a more commonly used approach.

[0037] Regardless of which of the above methods is used to optimize and upgrade each resource module to a dual-mode resource module, one approach is to optimize and design all resource modules inside the chip as dual-mode resource modules. Alternatively, some resource modules inside the chip are optimized and designed as dual-mode resource modules, while other resource modules are still designed as traditional methods and have basic working modes. When only some resource modules inside the chip are optimized and designed as dual-mode resource modules, the arrangement positions of the dual-mode resource modules are designed according to actual needs, and multiple dual-mode resource modules can be arranged adjacent to each other or evenly distributed in different positions. In actual implementation, in order to make the chip more testable, all resource modules inside the chip are generally optimized and designed as dual-mode resource modules.

[0038] Based on this optimized design of the resource modules in the chip, any dual-mode resource module in the chip forms a module infrastructure when in the basic working mode, and the dual-mode resource module forms a direct path from the input end to the output end when in the direct working mode and is used to construct a test path between the test input and output ports and the resource module to be tested, so that the chip containing the dual-mode resource module can be more testable than the traditional chip. The following embodiment introduces a method for constructing a test path between the test input and output ports and the resource module to be tested using a dual-mode resource module in the direct working mode:

[0039] As mentioned in the background technology section, insufficient interfaces of interconnected resources or crowded connections between interconnected resources may result in the inability to directly use connection resources to form a test path from the input and output ports to the resource module to be tested. In order to solve this problem, the present application uses dual-mode resource modules within the chip to indirectly form a test path from the input and output ports to the resource module to be tested.

[0040] When it is determined that a test path from the test input-output ports Testin and Testout to the resource module M1 to be tested cannot be formed through the wiring resources inside the chip, at least one dual-mode resource module inside the control chip is switched to a through-mode operation mode. The dual-mode resource module switched to the through-mode operation mode forms a through-path from the input end to the output end internally, and transmits the signal obtained from the input end to the output end unchanged. In this way, a test path from the test input-output ports Testin and Testout to the resource module M1 to be tested via a through-path inside at least one dual-mode resource module can be formed by utilizing the wiring resources inside the chip.

[0041] The test path from the test input and output ports Testin and Testout to the resource module M1 to be tested that needs to be formed includes: a vector input path from the test input port Testin to the input end of the resource module M1 to be tested, and a result output path from the output end of the resource module M1 to be tested to the test output port Testout. The test input and output ports Testin and Testout are connected to a test controller, and the test controller writes a test vector to the resource module M1 to be tested via the test input port Testin via the vector input path, and then reads the test result of the resource module M1 to be tested via the test output port Testout via the result output path, thereby completing the test of the resource module M1 to be tested. The test controller is located inside the chip or outside the chip.

[0042] Then in the test path formed by the direct path inside at least one dual-mode resource module: the vector input path between the test input port Testin and the input end of the resource module to be tested M1 passes through the direct path inside at least one dual-mode resource module, and / or the result output path from the output end of the resource module to be tested to the test output port Testout passes through the direct path inside at least one dual-mode resource module.

[0043] That is, both the vector input path and the result output path can pass through the direct path inside the dual-mode resource module, such as Figure 2 Taking this case as an example, the vector input path passes through the direct paths inside the two dual-mode resource modules M2 and M3, and the result output path passes through the direct path inside the dual-mode resource module M4. Alternatively, only the vector input path passes through the direct path inside the dual-mode resource module, and the result output path does not pass through any dual-mode resource module. Figure 3 Taking this case as an example, the vector input path passes through a direct path inside a dual-mode resource module M5, and the result output path is directly implemented using the connection resources. Alternatively, only the result output path passes through the direct path inside the dual-mode resource module, and the vector input path does not pass through any dual-mode resource module. Figure 4 Taking this case as an example, the result output path is realized by directly using the connection resources through the through path inside the two dual-mode resource modules M6 and M7 and the vector input path.

[0044] In traditional chips, although it is theoretically possible to Figure 2-Figure 4 As shown, the path is formed through other resource modules, but due to the function of the module infrastructure of the resource module passed through, the path cannot meet the test coverage requirement and cannot actually form a test path. Figure 3 Taking this structure as an example, in a conventional chip, when the test input port Testin is connected to the resource module M1 to be tested through the module infrastructure of the resource module M5, a value is written to the module infrastructure of the resource module M5 through the test input port Testin, and then the output of the module infrastructure of the resource module M5 is used as the input of the resource module M1 to be tested. However, since the module infrastructure of the resource module M5 is fixed according to the chip design requirements, the output of the module infrastructure of the resource module M5 cannot cover all vector values, that is, when the module infrastructure of the resource module M5 has N output ports, the module infrastructure of the resource module M5 is often unable to output all 2 through the output port due to the limitation of the module infrastructure designed for the resource module M5. NDifferent values ​​are provided to the resource module M1 to be tested, which is a common and inevitable defect. This situation leads to that when the input of the resource module M1 to be tested requires a specific test vector, it is very likely that the module infrastructure of the resource module M5 cannot output the test vector, and thus cannot provide the test vector to the resource module M1 to be tested for testing, resulting in incomplete test coverage of the resource module M1 to be tested.

[0045] Likewise, please combine Figure 2 In the result output path part, when the output end of the resource module M1 to be tested is connected to the test output port Testout via the module infrastructure of the resource module M4, the test result of the resource module M1 to be tested must pass through the output of the module infrastructure of the resource module M4 before reaching the test output port Testout. Similarly, affected by the function of the module infrastructure of the resource module M4, the module infrastructure of the resource module M4 may not be able to output the value of the test result, resulting in the inability to output the test result to the test output port Testout, which will also damage the test coverage of the resource module M1 to be tested.

[0046] The above example only takes the case where the vector input path and the result output path only pass through one other resource module. When passing through more resource modules, due to the functions of each resource module, the above limitations will be more obvious, resulting in a very low test coverage of the resource module M1 to be tested. This is also the reason why the current chip cannot form a test path through other resource modules.

[0047] The present application optimizes the chip design so that the test path is formed not by using common resource modules, but by using dual-mode resource modules switched to the direct working mode. Figure 2-Figure 4 As shown, since what is passed through is a direct path within the dual-mode resource module rather than the module infrastructure, each dual-mode resource module passed through can transmit the value received at the input end to the output end unchanged without being restricted by the function of the module infrastructure. This ensures the correct transmission of test vectors and test results, thereby truly forming a test path that does not affect test coverage.

[0048] By Figure 2-Figure 4It can be seen from the examples that the present application is very flexible in forming a test path using the dual-mode resource modules inside the chip. There are many different combinations of the number of dual-mode resource modules that the vector input path and the result output path pass through. Not only is the number of dual-mode resource modules that pass through flexible, but the choice of the arrangement position of the dual-mode resource modules that pass through is also very flexible. It only needs to ensure that the required test path can be formed. Any dual-mode resource module that the formed test path passes through is arranged adjacent to the resource module to be tested, or separated by other resource modules, such as Figure 2 In the example, the dual-mode resource module M3 is arranged adjacent to the resource module to be tested M1, and the dual-mode resource module M1 and the resource module to be tested M4 are separated by other resource modules. Figure 2 It only shows the logical path connection relationship, and does not represent the relative arrangement positions between resource modules. When the vector input path passes through multiple dual-mode resource modules, any two dual-mode resource modules are arranged adjacent to each other or separated by other resource modules, such as Figure 1 In the example, the dual-module resource module M2 and the dual-module resource module M3 can be arranged adjacent to or separated by other resource modules. When the result output path passes through multiple dual-mode resource modules, any two dual-mode resource modules are arranged adjacent to or separated by other resource modules, such as Figure 3 In the embodiment, the dual-module resource module M6 and the dual-module resource module M7 can be arranged adjacent to each other or separated by other resource modules.

[0049] In addition, for any dual-mode resource module that is switched to the pass-through working mode and connected to the test path, all or part of the input ports of the dual-mode resource module are connected to the test path, and all or part of the output ports of the dual-mode resource module are connected to the test path. The unused input ports and / or output ports can be set to 1 or 0 at will without affecting the test process.

[0050] The above is only a preferred embodiment of the present application, and the present application is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present application should be considered to be included in the protection scope of the present application.

Claims

1. A testable design method for a chip, It is characterized in that The testable design method includes: The chip includes resource modules and connection resources arranged in a predetermined manner. For a resource module at at least one predetermined position in the chip, the resource module is optimized and designed as a dual-mode resource module based on the module infrastructure of the resource module, so as to obtain a chip including the dual-mode resource module; Any dual-mode resource module forms a module infrastructure when it is in the basic working mode, and the dual-mode resource module forms a direct path from the input end to the output end when it is in the direct working mode; when it is determined that the test path from the test input and output port to the resource module to be tested cannot be formed through the wiring resources inside the chip, at least one dual-mode resource module inside the chip is controlled to switch to the direct working mode, and the dual-mode resource module switched to the direct working mode forms a direct path from the input end to the output end internally, and transmits the signal obtained from the input end to the output end unchanged, and uses the wiring resources inside the chip to form a test path from the test input and output port to the resource module to be tested via the direct path inside the at least one dual-mode resource module; In the test path formed via the direct path inside the at least one dual-mode resource module: the vector input path between the test input port and the input end of the resource module to be tested passes through the direct path inside at least one dual-mode resource module; and / or, the result output path from the output end of the resource module to be tested to the test output port passes through the direct path inside at least one dual-mode resource module.

2. The testable design method according to claim 1, It is characterized in that Optimizing and designing the resource module into a dual-mode resource module based on the module infrastructure of the resource module includes: The input end of the module infrastructure of the resource module is connected to the input end of the dual-mode resource module, the output end of the module infrastructure of the resource module is connected to one input end of a newly added two-input multiplexer, the other input end of the two-input multiplexer is connected to the input end of the dual-mode resource module, the output end of the two-input multiplexer is connected to the output end of the dual-mode resource module, and the control end of the two-input multiplexer is led out as the mode switching end of the dual-mode resource module. The dual-mode resource module is obtained by optimized design. The dual-mode resource module switches between the basic working mode and the direct working mode according to the mode switching signal received by the mode switching end.

3. The testable design method according to claim 1, It is characterized in that Optimizing and designing the resource module into a dual-mode resource module based on the module infrastructure of the resource module includes: A direct working mode is added to the module total function table corresponding to the module infrastructure of the resource module to update the module total function table, and a dual-mode resource module is obtained by optimizing the design according to the updated module total function table. The dual-mode resource module switches between the basic working mode and the direct working mode according to the module configuration signal.

4. The testable design method according to claim 1, It is characterized in that The testable design method further includes: optimizing and designing all resource modules inside the chip as dual-mode resource modules, or optimizing and designing some resource modules inside the chip as dual-mode resource modules.

5. The testable design method according to claim 1, It is characterized in that Any dual-mode resource module passed by the formed test path is arranged adjacent to the resource module to be tested, or is separated from other resource modules.

6. The testable design method according to claim 1, It is characterized in that For any dual-mode resource module that is switched to the pass-through working mode and connected in the test path, all or part of the input ports of the dual-mode resource module are connected in the test path, and all or part of the output ports of the dual-mode resource module are connected in the test path.

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