Array substrate row driving circuit and display panel

Abstract

The present application provides an array substrate row driver circuit and a display panel. The array substrate row driver circuit includes a pre-charging unit, a first pull-up unit, a first pull-down unit, and a first pull-down control unit. A preset charging unit outputs a reference high-level signal from a first reference signal end to a first node under the control of an n-p-th level first gate driver signal or an n+p-th level first gate driver signal. The first pull-down control unit can output a reverse scan control signal to a second node and a forward scan control signal to a first node under the control of a second clock signal. Thus, the array substrate row driver circuit can have both forward and reverse scan functions, simplify the circuit structure in the gate driver module, simplify the circuit structure of the array substrate row driver circuit, reduce the area occupied by the non-display area, and achieve a narrow frame of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate row driving circuit and a display panel. Background Art

[0002] The gate-driver on array (GOA) technology integrates the gate driver circuit on the array substrate of the display panel, thereby eliminating the gate driver integrated circuit part and reducing product costs in terms of both material cost and manufacturing process.

[0003] Since the display panel needs to have the functions of forward scanning and reverse scanning in some applications, the GOA is required to be able to perform both forward scanning from top to bottom and reverse scanning from bottom to top.

[0004] However, during the implementation process, the inventors found that the GOA in the related art has at least the following problems: the circuit structure in the GOA is complex, and the GOA occupies a large area of the non-display area of the display panel, which is not conducive to achieving a narrow frame of the display panel. Summary of the Invention

[0005] The present application provides an array substrate row driving circuit, which can solve the technical problem that the array substrate row driving circuit occupies a large area of the non-display area of the display panel.

[0006] In a first aspect, the present application provides an array substrate row driving circuit, comprising a cascaded multi-stage gate driving module, wherein the n-th stage gate driving module comprises:

[0007] a pre-charging unit, the pre-charging unit being electrically connected to an np-th level first gate driving signal output terminal of an np-th level gate driving module, an n+p-th level first gate driving signal output terminal of an n+p-th level gate driving module, a first reference signal terminal, and a first node of the n-th level gate driving module, the pre-charging unit being configured to output a reference high-level signal from the first reference signal terminal to the first node under control of the np-th level first gate driving signal from the np-th level first gate driving signal output terminal or the n+p-th level first gate driving signal from the n+p-th level first gate driving signal output terminal;

[0008] a first pull-up unit, the first pull-up unit being electrically connected to the first node, the first clock signal terminal, and the n-stage first gate driving signal output terminal of the n-stage gate driving module, the first pull-up unit being configured to output the n-stage first gate driving signal to the n-stage first gate driving signal output terminal under the control of the first clock signal of the first clock signal terminal and the potential of the first node;

[0009] a first pull-down unit, the first pull-down unit being electrically connected to the first node, the n-th stage first gate driving signal output terminal, the second reference signal terminal, and the second node of the n-th stage gate driving module, the first pull-down unit being configured to output a reference low-level signal of the second reference signal terminal to the first node and the n-th stage first gate driving signal output terminal based on a potential of the second node;

[0010] a first pull-down control unit, the first pull-down control unit being electrically connected to the second clock signal terminal, the forward scan control signal terminal, the reverse scan control signal terminal, the first node, and the second node, the first pull-down control unit being configured to output the forward scan control signal of the forward scan control signal terminal to the second node and output the reverse scan control signal of the reverse scan control signal terminal to the first node under the control of the second clock signal of the second clock signal terminal;

[0011] Wherein, n and p are integers greater than 0, and n is greater than p.

[0012] In the array substrate row driving circuit provided in the present application, the pre-charging unit includes a first transistor and a second transistor, the gate of the first transistor is electrically connected to the first gate driving signal output terminal of the np-th stage, the source of the first transistor is electrically connected to the first reference signal terminal, the drain of the first transistor is electrically connected to the first node, the gate of the second transistor is electrically connected to the first gate driving signal output terminal of the n+p-th stage, the source of the second transistor is electrically connected to the first reference signal terminal, and the drain of the second transistor is electrically connected to the first node;

[0013] The first pull-up unit includes a third transistor, a gate of the third transistor is electrically connected to the first node, a source of the third transistor is electrically connected to the first clock signal terminal, and a drain of the third transistor is electrically connected to the n-th stage first gate drive signal output terminal;

[0014] The first pull-down unit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is electrically connected to the second node, the source of the fourth transistor is electrically connected to the second reference signal terminal, the drain of the fourth transistor is electrically connected to the first node, the gate of the fifth transistor is electrically connected to the second node, the source of the fifth transistor is electrically connected to the second reference signal terminal, and the drain of the fifth transistor is electrically connected to the n-th stage first gate driving signal output terminal;

[0015] The first pull-down control unit includes a sixth transistor and a seventh transistor, the gate of the sixth transistor is electrically connected to the second clock signal end, the source of the sixth transistor is electrically connected to the reverse scan control signal end, the drain of the sixth transistor is electrically connected to the first node, the gate of the seventh transistor is electrically connected to the second clock signal end, the source of the seventh transistor is electrically connected to the forward scan control signal end, and the drain of the seventh transistor is electrically connected to the second node.

[0016] In the array substrate row driving circuit provided in the present application, the n-th stage gate driving module further includes a feedback unit, the feedback unit being electrically connected to the first node, the second node, and the second reference signal terminal, and the feedback unit being configured to output the reference low-level signal to the second node based on the potential of the first node;

[0017] The n-th stage gate driving module further includes a voltage stabilizing unit, the voltage stabilizing unit being electrically connected to the first reference signal terminal, the first node, and the first pull-up unit, and the voltage stabilizing unit being configured to maintain the potential of the first node based on the reference high-level signal;

[0018] The n-th stage gate driving module further includes a first storage unit, one end of the first storage unit is electrically connected to the first node, the other end of the first storage unit is electrically connected to the second reference signal end, and the first storage unit is used to store the potential of the first node;

[0019] The n-th stage gate driving module further includes a second storage unit, one end of the second storage unit is electrically connected to the second node, the other end of the second storage unit is electrically connected to the second reference signal end, and the second storage unit is used to store the potential of the second node;

[0020] The n-th level gate drive module also includes a first global control unit, which is electrically connected to the first global control signal terminal and the n-th level first gate drive signal output terminal, and the first global control unit is used to pull up the potential of the n-th level first gate drive signal output terminal under the control of the first global control signal of the first global control signal terminal.

[0021] In the array substrate row driving circuit provided in the present application, the n-th level gate driving module also includes a second pull-down control unit, which is electrically connected to the n-th level first gate driving signal output terminal, the n+p-th level first gate driving signal output terminal, the forward scan control signal terminal, the reverse scan control signal terminal, the second reference signal terminal and the n-th level pull-down signal output terminal. The second pull-down control unit is used to output the reference low-level signal to the n-th level pull-down signal output terminal under the control of the n-th level first gate driving signal and the reverse scan control signal, or to output the reference low-level signal to the n-th level pull-down signal output terminal under the control of the n+p-th level first gate driving signal and the forward scan control signal.

[0022] In the array substrate row driving circuit provided in the present application, the second pull-down control unit includes a first control signal receiving subunit, a second control signal receiving subunit and a pull-down output subunit;

[0023] The first control signal receiving subunit is electrically connected to the n-th stage first gate driving signal output terminal, the reverse scan control signal terminal and the pull-down output subunit;

[0024] The second control signal receiving subunit is electrically connected to the n+pth stage first gate driving signal output terminal, the forward scanning control signal terminal and the pull-down output subunit;

[0025] The pull-down output subunit is also electrically connected to the second reference signal terminal and the n-th stage pull-down signal output terminal.

[0026] In the array substrate row driving circuit provided in the present application, the first control signal receiving sub-unit includes an eighth transistor, the gate of the eighth transistor is electrically connected to the n-th stage first gate driving signal output terminal, the source of the eighth transistor is electrically connected to the reverse scan control signal terminal, and the drain of the eighth transistor is electrically connected to the pull-down output sub-unit;

[0027] The second control signal receiving sub-unit includes a ninth transistor, a gate of the ninth transistor being electrically connected to the n+p-th stage first gate driving signal output terminal, a source of the ninth transistor being electrically connected to the forward scan control signal terminal, and a drain of the ninth transistor being electrically connected to the pull-down output sub-unit;

[0028] The pull-down output subunit includes a tenth transistor, the gate of the tenth transistor is electrically connected to the first control signal receiving subunit and the second control signal receiving subunit, the source of the tenth transistor is electrically connected to the second reference signal terminal, and the drain of the tenth transistor is electrically connected to the n-th level pull-down output signal terminal.

[0029] In the array substrate row driving circuit provided in the present application, the n-th stage gate driving module further includes a second pull-up unit and a second pull-down unit;

[0030] The second pull-up unit is electrically connected to the third clock signal terminal, the first node, and the n-stage second gate driving signal output terminal of the n-stage gate driving module, and the second pull-up unit is configured to output the n-stage second gate driving signal to the n-stage second gate driving signal output terminal under the control of the third clock signal of the third clock signal terminal and the potential of the first node;

[0031] The second pull-down unit is electrically connected to the second node, the second reference signal terminal and the n-th level second gate drive signal output terminal, and the second pull-down unit is used to output the reference low-level signal to the n-th level second gate drive signal output terminal based on the potential of the second node.

[0032] In the array substrate row driving circuit provided in the present application, the second pull-up unit includes a fourteenth transistor, a gate of the fourteenth transistor is electrically connected to the first node, a source of the fourteenth transistor is electrically connected to the third clock signal terminal, and a drain of the fourteenth transistor is electrically connected to the n-th stage second gate driving signal output terminal;

[0033] The second pull-down unit includes a fifteenth transistor, a gate of the fifteenth transistor is electrically connected to the second node, a source of the fifteenth transistor is electrically connected to the second reference signal terminal, and a drain of the fifteenth transistor is electrically connected to the n-th level second gate drive signal output terminal.

[0034] In the array substrate row driving circuit provided in the present application, the end time point of the first clock signal received as a high-level signal by the first pull-up unit is earlier than or equal to the start time point of the third clock signal received as a high-level signal by the second pull-up unit.

[0035] In the array substrate row driving circuit provided in the present application, the starting time point of the first clock signal received as a high-level signal by the first pull-up unit is earlier than the starting time point of the third clock signal received as a high-level signal by the second pull-up unit, and the ending time point of the first clock signal received as a high-level signal by the first pull-up unit is later than the starting time point of the third clock signal received as a high-level signal by the second pull-up unit.

[0036] In a second aspect, the present application further provides a display panel, comprising the array substrate row driving circuit described above, wherein the array substrate row driving circuit is located in a non-display area of the display panel;

[0037] Multiple scan lines, multiple scan lines are located in the display area of the display panel, the qth scan line is electrically connected to the qth first gate drive signal output terminal of the array substrate row drive circuit, and the qth scan line is also electrically connected to the q-1th pull-down output terminal of the array substrate row drive circuit, wherein q is an integer greater than or equal to 2.

[0038] Furthermore, in the display panel provided in the present application, the head end of the qth scan line is electrically connected to the qth first gate drive signal output terminal, and the tail end of the qth scan line is electrically connected to the q-1th pull-down output terminal.

[0039] The present application further provides a display panel, comprising the two array substrate row driving circuits described above, wherein the first array substrate row driving circuit is located in a first non-display area of the display panel, and the second array substrate row driving circuit is located in a second non-display area of the display panel, and the first non-display area and the second non-display area are located on opposite sides of a display area of the display panel;

[0040] A plurality of scan lines, wherein the plurality of scan lines are located in the display area;

[0041] Among them, the 2q-1th scan line is electrically connected to the qth first gate drive signal output terminal of the first array substrate row driving circuit, and the 2q-1th scan line is also electrically connected to the q-1th pull-down output terminal of the second array substrate row driving circuit, and the 2qth scan line is electrically connected to the qth first gate drive signal output terminal of the second array substrate row driving circuit, and the 2qth scan line is also electrically connected to the qth pull-down output terminal of the first array substrate row driving circuit, wherein q is an integer greater than or equal to 1.

[0042] Furthermore, in the display panel provided in the present application, along the extension direction of the scan line, the first non-display area and the second non-display area are located on opposite sides of the display area;

[0043] The head end of the 2q-1th scan line is electrically connected to the qth level gate drive signal output terminal of the first array substrate row driving circuit, the tail end of the 2q-1th scan line is electrically connected to the q-1th level pull-down output terminal of the second array substrate row driving circuit, the head end of the 2qth scan line is electrically connected to the qth level gate drive signal output terminal of the second array substrate row driving circuit, and the tail end of the 2qth scan line is electrically connected to the qth level pull-down output terminal of the first array substrate row driving circuit.

[0044] Furthermore, in the display panel provided in the present application, the first scan line is electrically connected to the first-level gate drive signal output terminal of the first array substrate row driving circuit, and the first scan line is also electrically connected to the virtual output terminal, which is the zero-level pull-down output terminal of the second array substrate row driving circuit.

[0045] Furthermore, in the display panel provided in the present application, in the final-stage gate driving module electrically connected to the last scan line, the n+p-th stage first gate driving signal output terminal electrically connected to the second pull-down control unit is the first reference signal terminal;

[0046] The final gate driving module is the final gate driving unit of the first array substrate row driving circuit or the final gate driving unit of the second array substrate row driving circuit.

[0047] The present application also provides a display panel, comprising the array substrate row driving circuit described above, wherein the array substrate row driving circuit is located in a non-display area of the display panel;

[0048] a plurality of first scan lines, the plurality of first scan lines being located in a display area of the display panel, the plurality of first scan lines corresponding one-to-one to and electrically connected to the multi-stage first gate drive signal output terminals of the array substrate row drive circuit;

[0049] A plurality of second scan lines are provided, the plurality of second scan lines are located in the display area, and the plurality of second scan lines correspond one-to-one to and are electrically connected to the multi-stage second gate drive signal output terminals of the array substrate row drive circuit.

[0050] Furthermore, in the display panel provided in the present application, the first scan lines and the second scan lines are alternately located in the display area;

[0051] The rth first scan line is electrically connected to the rth first gate drive signal output terminal of the array substrate row drive circuit, and the rth second scan line is electrically connected to the rth second gate drive signal output terminal, where r is an integer greater than or equal to 1.

[0052] Furthermore, in the display panel provided in the present application, the display panel includes the two array substrate row driving circuits described above, wherein the first array substrate row driving circuit is located in a first non-display area of the non-display area, and the second array substrate row driving circuit is located in a second non-display area of the non-display area, and the first non-display area and the second non-display area are located on opposite sides of the display area;

[0053] The rth first scan line is electrically connected to the rth stage first gate driving signal output terminal of the first array substrate row driving circuit and the rth stage first gate driving signal output terminal of the second array substrate row driving circuit;

[0054] The rth second scan line is electrically connected to the rth stage second gate driving signal output terminal of the first array substrate row driving circuit and the rth stage second gate driving signal output terminal of the second array substrate row driving circuit.

[0055] Furthermore, in the display panel provided in the present application, along the extension direction of the first scan line, the first non-display area and the second non-display area are located on opposite sides of the display area;

[0056] The rth first scan line has a leading end electrically connected to the rth first gate drive signal output terminal of the first array substrate row driver circuit, and the rth first scan line has a trailing end electrically connected to the rth first gate drive signal output terminal of the second array substrate row driver circuit;

[0057] The head end of the rth second scan line is electrically connected to the rth second gate drive signal output terminal of the first array substrate row driving circuit, and the tail end of the rth second scan line is electrically connected to the rth second gate drive signal output terminal of the second array substrate row driving circuit.

[0058] The array substrate row driving circuit provided in the present application provides a pre-charging unit electrically connected to the np-th level first gate driving signal output terminal, the n+p-th level first gate driving signal output terminal, the first reference signal terminal, and the first node in the n-th level gate driving module, and a first pull-down control unit electrically connected to the second clock signal terminal, the forward scan control signal terminal, the reverse scan control signal terminal, the first node, and the second node. Thus, the pre-charging unit can output a reference high-level signal from the first reference signal terminal to the first node under the control of the np-th level first gate driving signal or the n+p-th level first gate driving signal. The first pull-down control unit can output a reverse scan control signal to the second node and a forward scan control signal to the first node under the control of the second clock signal. Thus, while the array substrate row driving circuit has both forward scanning and reverse scanning functions, the circuit structure in the gate driving module and the circuit structure of the array substrate row driving circuit are simplified, and the non-display area occupied by the array substrate row driving circuit is reduced, thereby achieving a narrow frame of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 A block diagram of an array substrate row driving circuit provided in an embodiment of the present application;

[0060] Figure 2 for Figure 1 A first block diagram of the n-th stage gate driving module of the array substrate row driving circuit shown;

[0061] Figure 3 for Figure 2 Schematic diagram of a first circuit of the n-th stage gate driving module shown;

[0062] Figure 4 for Figure 2 Schematic diagram of the second circuit of the n-th stage gate driving module shown;

[0063] Figure 5 for Figure 1 A second block diagram of the n-th stage gate driving module of the array substrate row driving circuit shown;

[0064] Figure 6 for Figure 1 A third block diagram of the n-th stage gate driving module of the array substrate row driving circuit shown;

[0065] Figure 7 for Figure 6 A schematic diagram of a circuit of the n-th stage gate driving module shown;

[0066] Figure 8 A first schematic diagram of a display panel provided in an embodiment of the present application;

[0067] Figure 9 A second schematic diagram of a display panel provided in an embodiment of the present application;

[0068] Figure 10 A third schematic diagram of a display panel provided in an embodiment of the present application;

[0069] Figure 11 A fourth schematic diagram of a display panel provided in an embodiment of the present application;

[0070] Figure 12 A schematic diagram of a circuit of a final-stage gate drive module;

[0071] Figure 13a for Figure 10 A schematic diagram of a circuit of the display panel shown;

[0072] Figure 13b for Figure 13a Schematic diagram of the driving timing of the display panel shown;

[0073] Figure 14 for Figure 1 A fourth block diagram of the n-th stage gate driving module of the array substrate row driving circuit shown;

[0074] Figure 15 for Figure 14 A schematic diagram of a circuit of the n-th stage gate driving module shown;

[0075] Figure 16 for Figure 14 The first timing diagram of the array substrate row driving circuit shown;

[0076] Figure 17 for Figure 14 The second timing diagram of the array substrate row driving circuit shown;

[0077] Figure 18 A fifth schematic diagram of a display panel provided in an embodiment of the present application;

[0078] Figure 19 This is a sixth schematic diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0079] The following will describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. The described embodiments are only used to explain the ideas created by the present invention and should not be regarded as limiting the scope of protection of this application.

[0080] The transistors used in the embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are interchangeable, in the embodiments of the present application, in order to distinguish the two poles of the transistor other than the gate, one of the poles is called the source and the other is called the drain. According to the form in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end is the source, and the signal output end is the drain. In addition, when the transistors used in the embodiments of the present application are P-type transistors, they are turned on when the gate is at a low level and cut off when the gate is at a high level. When the transistors used in the embodiments of the present application are N-type transistors, they are turned on when the gate is at a high level and cut off when the gate is at a low level.

[0081] like Figure 1 As shown, the array substrate row driving circuit 1000 includes a cascade of multiple gate driving modules 100. Each gate driving module 100 is electrically connected to a first reference signal terminal VGH, a second reference signal terminal VGL, a first clock signal terminal CKa, a second clock signal terminal CKb, a forward scan control signal terminal U2D, and a reverse scan control signal terminal D2U.

[0082] The first gate drive signal output terminal of the primary gate drive module 100 is configured to provide a first gate drive signal to a scan line in the display area AA of the display panel. The pixel unit electrically connected to the scan line is turned on or off based on the received gate drive signal, thereby controlling the start and end time of charging for the pixel unit, as well as the charging duration.

[0083] In any stage of the gate driving module 100 , the first clock signal at the first clock signal terminal CKa is different from the second clock signal at the second clock signal terminal CKb.

[0084] like Figure 2 As shown, in some embodiments provided in this application, the n-th stage gate driving module 100 of the array substrate row driving circuit 1000 includes a pre-charging unit 10 , a first pull-up unit 21 , a first pull-down unit 31 and a first pull-down control unit 41 .

[0085] The pre-charging unit 10 is electrically connected to the np-th stage first gate driving signal output terminal G1(np) of the np-th stage gate driving module 100, the n+p-th stage first gate driving signal output terminal G1(n+p), the first reference signal terminal VGH, and the first node Q(n) of the n-th stage gate driving module 100.

[0086] The pre-charging unit 10 is used to output the reference high-level signal of the first reference signal terminal VGH to the first node Q(n) under the control of the np-th level first gate driving signal of the np-th level first gate driving signal output terminal G1(np) or the n+p-th level first gate driving signal of the n+p-th level first gate driving signal output terminal G1(n+p), so as to pull up the potential of the first node Q(n) and pre-charge the first node Q(n).

[0087] Wherein, n and p are both integers greater than 0, and n is greater than p.

[0088] The first pull-up unit 21 is electrically connected to the first node Q(n), the first clock signal terminal CKa, and the n-th stage first gate driving signal output terminal G1 (n) of the n-th stage gate driving module 100 .

[0089] The first node Q(n) is a node of a line between the pre-charging unit 10 and the first pull-up unit 21 .

[0090] The first pull-up unit 21 is used to output the nth stage first gate driving signal to the nth stage first gate driving signal output terminal G1 (n) under the control of the first clock signal of the first clock signal terminal CKa and the potential of the first node Q(n).

[0091] The first pull-down unit 31 is electrically connected to the first node Q(n), the n-th stage first gate driving signal output terminal G1 (n), the second reference signal terminal VGL, and the second node P(n) of the n-th stage gate driving module 100 .

[0092] The second node P(n) is a node of the line between the first pull-down unit 31 and the first pull-down control unit 41 .

[0093] The first pull-down unit 31 is used to output the reference low-level signal of the second reference signal terminal VGL to the first node Q(n) and the n-th level first gate drive signal output terminal G1(n) based on the potential of the second node P(n), so as to pull down the potential of the first node Q(n) and the potential of the n-th level first gate drive signal output terminal G1(n).

[0094] The first pull-down control unit 41 is electrically connected to the second clock signal terminal CKb, the forward scan control signal terminal U2D, the reverse scan control signal terminal D2U, the first node Q(n), and the second node P(n).

[0095] The first pull-down control unit 41 is used to output the forward scan control signal of the forward scan control signal terminal U2D to the second node P(n) and output the reverse scan control signal of the reverse scan control signal terminal D2U to the first node Q(n) under the control of the second clock signal of the second clock signal terminal CKb.

[0096] It should be noted that in the array substrate row driver circuit 1000, a start signal can be set to replace the first gate drive signal of the pn-th stage in the first-stage gate driver module 100 through the p-th-stage gate driver module 100. Similarly, a start signal or another signal can be set to replace the first gate drive signal of the n+p-th stage gate driver module 100 in the last-stage gate driver module 100 through the p-th-last-stage gate driver module 100. Aside from the aforementioned differences, the circuit structure and signal connections of the first and second p-stage gate driver modules 100 are identical to those of the other stages of the gate driver modules 100.

[0097] In the array substrate row driver circuit provided in this embodiment, a pre-charging unit electrically connected to the np-th level first gate driver signal output terminal, the n+p-th level first gate driver signal output terminal, the first reference signal terminal, and the first node, and a first pull-down control unit electrically connected to the second clock signal terminal, the forward scan control signal terminal, the reverse scan control signal terminal, the first node, and the second node are provided in the n-th level gate driver module. Thus, the pre-charging unit can output a reference high-level signal from the first reference signal terminal to the first node under the control of the np-th level first gate driver signal or the n+p-th level first gate driver signal. The first pull-down control unit can output the reverse scan control signal to the second node and the forward scan control signal to the first node under the control of the second clock signal. Thus, while the array substrate row driver circuit has both forward scan and reverse scan functions, the circuit structure in the gate driver module and the circuit structure of the array substrate row driver circuit are simplified, and the non-display area occupied by the array substrate row driver circuit is reduced, thereby achieving a narrow frame of the display panel.

[0098] In some embodiments provided in this application, specifically, Figure 3 As shown, the pre-charging unit 10 includes a first transistor T1 and a second transistor T2.

[0099] The gate of the first transistor T1 is electrically connected to the np-th stage first gate driving signal output terminal G1(np), the source of the first transistor T1 is electrically connected to the first reference signal terminal VGH, and the drain of the first transistor T1 is electrically connected to the first node Q(n).

[0100] The gate of the second transistor T2 is electrically connected to the n+p-th stage first gate driving signal output terminal G1(n+p), the source of the second transistor T2 is electrically connected to the first reference signal terminal VGH, and the drain of the second transistor T2 is electrically connected to the first node Q(n).

[0101] In this embodiment, when the first transistor T1 is in the on state based on the np-th level first gate drive signal output by the np-th level first gate drive signal output terminal G1(np), the reference high-level signal of the first reference signal terminal VGH is output to the first node Q(n), so as to pull up the potential of the first node Q(n) to realize pre-charging of the first node Q(n).

[0102] Similarly, when the second transistor T2 is in the on state based on the n+p-th level first gate drive signal output by the n+p-th level first gate drive signal output terminal G1(n+p), the reference high-level signal of the first reference signal terminal VGH is output to the first node Q(n), thereby pre-charging the first node Q(n).

[0103] In some embodiments provided in this application, Figure 3 As shown, the first pull-up unit 21 includes a third transistor T3.

[0104] The gate of the third transistor T3 is electrically connected to the first node Q(n), the source of the third transistor T3 is electrically connected to the first clock signal terminal CKa, and the drain of the third transistor T3 is electrically connected to the n-th stage first gate driving signal output terminal G1(n).

[0105] In this embodiment, when the third transistor T3 is in the on state based on the potential of the first node Q(n), the first clock signal of the first clock signal terminal CK1 is output to the n-th level first gate drive signal output terminal G1(n), so that whether the n-th level first gate drive signal is high or low depends on whether the first clock signal is high or low when the third transistor T3 is turned on.

[0106] In some embodiments provided in this application, specifically, Figure 3 As shown, the first pull-down unit 31 includes a fourth transistor T4 and a fifth transistor T5.

[0107] The gate of the fourth transistor T4 is electrically connected to the second node P(n), the source of the fourth transistor T4 is electrically connected to the second reference signal terminal VGL, the drain of the fourth transistor T4 is electrically connected to the first node Q(n), the gate of the fifth transistor T5 is electrically connected to the second node P(n), the source of the fifth transistor T5 is electrically connected to the second reference signal terminal VGL, and the drain of the fifth transistor T5 is electrically connected to the n-th level first gate drive signal output terminal G1(n).

[0108] In some embodiments provided in this application, specifically, Figure 3 As shown, the first pull-down control unit 41 includes a sixth transistor T6 and a seventh transistor T7.

[0109] The gate of the sixth transistor T6 is electrically connected to the second clock signal terminal CKb, the source of the sixth transistor T6 is electrically connected to the reverse scan control signal terminal D2U, the drain of the sixth transistor T6 is electrically connected to the first node Q(n), the gate of the seventh transistor T7 is electrically connected to the second clock signal terminal CKb, the source of the seventh transistor T7 is electrically connected to the forward scan control signal terminal U2D, and the drain of the seventh transistor T7 is electrically connected to the second node P(n).

[0110] In this embodiment, if the array substrate row driver circuit 1000 performs forward scanning, then in the n-stage gate driver module 100, the seventh transistor T7 is turned on, and the seventh transistor T7 provides a forward scanning control signal to the second node P(n), thereby turning on the first pull-down unit 31 and controlling the voltage of the n-stage first gate driver signal outputted from the n-stage first gate driver signal output terminal G1(n) to be a constant low-level signal. Similarly, if the array substrate row driver circuit 1000 performs reverse scanning, then in the n-stage gate driver module 100, the sixth transistor T6 is turned on, and the sixth transistor T6 provides a reverse scanning control signal to the first node Q(n), thereby pulling up the potential of the first node Q(n), and further turning on the first pull-up unit 21 and controlling the n-stage first gate driver signal outputted from the n-stage first gate driver signal output terminal G1(n) to be a low-level first clock signal.

[0111] Furthermore, in some embodiments provided in this application, Figure 4 As shown, Figure 4 and Figure 2 、 Figure 3 The difference is that the n-th stage gate driving module 100 further includes a feedback unit 50 .

[0112] The feedback unit 50 is electrically connected to the first node Q(n), the second node P(n) and the second reference signal terminal VGL. The feedback unit 50 is configured to output a reference low-level signal to the second node P(n) according to the potential of the first node Q(n).

[0113] When the potential of the first node Q(n) is high, the feedback unit 50 maintains the first pull-down unit 31 in a closed state, thereby preventing the first pull-down unit 31 from accidentally pulling the potential of the first node Q(n) down while the pre-charging unit 10 pulls up the potential of the first node Q(n).

[0114] Specifically, the feedback unit 50 includes an eleventh transistor T11 having a gate electrically connected to the first node Q(n), a source electrically connected to the second reference signal terminal VGL, and a drain electrically connected to the second node P(n).

[0115] In this embodiment, the on-state and off-state of the eleventh transistor T11 depend on the potential of the first node Q(n). When the eleventh transistor T11 is turned on, the potential of the second node P(n) is a low potential, and the first pull-down unit 31 is in the off state based on the second node P(n) being a low potential.

[0116] Furthermore, in some embodiments provided in this application, Figure 4 As shown, the n-th stage gate driving module 100 further includes a voltage stabilizing unit 60 .

[0117] The voltage stabilizing unit 60 is electrically connected to the first reference signal terminal VGH, the first node Q(n), and the first pull-up unit 21 . The voltage stabilizing unit 60 is configured to maintain the potential of the first node Q(n) based on the reference high-level signal.

[0118] Specifically, the voltage stabilizing unit 60 includes a twelfth transistor T12 , a gate of which is electrically connected to the first reference signal terminal VGH, a source of which is electrically connected to the first node Q(n), and a drain of which is electrically connected to the first pull-up unit 21 .

[0119] The twelfth transistor T12 is an N-type transistor and is therefore in a normally-on state. Due to the normally-on state of the twelfth transistor T12, the potential at the gate of the third transistor T3 in the first pull-up unit 21 does not flow back to the first node Q(n).

[0120] Furthermore, in some embodiments provided in this application, Figure 4 As shown, the n-th stage gate driving module 100 further includes a first storage unit 71 .

[0121] One end of the first storage unit 71 is electrically connected to the first node Q(n), and the other end of the first storage unit 71 is electrically connected to the second reference signal terminal VGL. The first storage unit 71 is used to store the potential of the first node Q(n).

[0122] Specifically, such as Figure 5 As shown, the first storage unit 71 includes a first capacitor C1. A first plate of the first capacitor C1 is electrically connected to the first node Q(n), and a second plate of the first capacitor C1 is electrically connected to the second reference signal terminal VGL.

[0123] Furthermore, in some embodiments provided in this application, Figure 4 As shown, the n-th stage gate driving module 100 further includes a second storage unit 72 .

[0124] One end of the second storage unit 72 is electrically connected to the second node P(n), and the other end of the second storage unit 72 is electrically connected to the second reference signal terminal VGL. The second storage unit 72 is used to store the potential of the second node P(n).

[0125] Specifically, such as Figure 5 As shown, the second storage unit 72 includes a second capacitor C2. A first plate of the second capacitor C2 is electrically connected to the second node P(n), and a second plate of the second capacitor is electrically connected to the second reference signal terminal VGL.

[0126] Furthermore, in some embodiments provided in this application, Figure 4 As shown, the n-th stage gate driving module 100 further includes a first global control unit 81 .

[0127] The first global control unit 81 is electrically connected to the first global control signal terminal gas1 and the n-th stage first gate drive signal output terminal G1(n). The first global control unit 81 is used to pull up the potential of the n-th stage first gate drive signal output terminal G1(n) under the control of the first global control signal of the first global control signal terminal gas1.

[0128] Specifically, such as Figure 4 As shown, the first global control unit 81 further includes a thirteenth transistor T13. The gate and source of the thirteenth transistor T13 are both electrically connected to the first global control signal terminal gas1, and the drain of the thirteenth transistor T13 is electrically connected to the n-th stage first gate drive signal output terminal G1(n). The first global control units 81 of all gate drive modules 100 are simultaneously turned on based on the first global control signal.

[0129] Furthermore, in some embodiments provided in this application, Figure 5 As shown, Figure 5 and Figures 2 to 4 The difference between the two is that the n-th stage gate driving module 100 further includes a second pull-down control unit 42 .

[0130] The second pull-down control unit 42 is electrically connected to the n-th stage first gate drive signal output terminal G1(n), the n+p-th stage first gate drive signal output terminal G1(n+p), the forward scan control signal terminal U2D, the reverse scan control signal terminal D2U, the second reference signal terminal VGL and the n-th stage pull-down output signal terminal D(n).

[0131] The second pull-down control unit 42 is used to output a reference low-level signal to the n-th level pull-down output signal terminal D(n) under the control of the n-th level first gate drive signal and the reverse scan control signal, or to output a reference low-level signal to the n-th level pull-down output signal terminal D(n) under the control of the n+p-th level first gate drive signal and the forward scan control signal.

[0132] In this embodiment, when the n-th level first gate drive signal output terminal G1(n) of the n-th level gate drive module 100 outputs the n-th level first gate drive signal, if the array substrate row drive circuit is in reverse scanning at this time, the second pull-down control unit 42 of the n-th level gate drive module 100 also outputs a reference low-level signal to the n-th level pull-down output terminal D(n) based on the n-th level first gate drive signal; if the array substrate row drive circuit is in forward scanning at this time, the second pull-down control unit 42 of the np-th level gate drive module 100 also outputs a reference low-level signal to the np-th level pull-down output terminal D(np) based on the n-th level first gate drive signal.

[0133] Specifically, such as Figure 6 As shown, the second pull-down control unit 42 includes a first control signal receiving subunit 421 , a second control signal receiving subunit 422 and a pull-down output subunit 423 .

[0134] The first control signal receiving subunit 421 is electrically connected to the n-th stage first gate drive signal output terminal G1(n), the reverse scan control signal terminal D2U, and the pull-down output subunit 423. The first control signal receiving subunit 421 is configured to output the reverse scan control signal to the pull-down output subunit 423 under the control of the n-th stage first gate drive signal.

[0135] The second control signal receiving subunit 422 is electrically connected to the n+p-th stage first gate drive signal output terminal G1(n+p), the forward scan control signal terminal U2D, and the pull-down output subunit 423. The second control signal receiving subunit 422 is configured to output the forward scan control signal to the pull-down output subunit 423 under the control of the n+p-th stage first gate drive signal.

[0136] The pull-down output subunit 423 is also electrically connected to the second reference signal terminal VGL and the n-th pull-down output signal terminal D(n). The pull-down output subunit 423 is configured to output a reference low-level signal to the n-th pull-down output terminal in response to a received forward scan control signal or a received reverse scan control signal, thereby pulling down the potential at the n-th pull-down output signal terminal D(n).

[0137] Specific, combined Figure 7 as well as Figure 6As shown, in some embodiments of the present application, the first control signal receiving subunit 421 includes an eighth transistor T8.

[0138] The gate of the eighth transistor T8 is electrically connected to the n-th stage first gate driving signal output terminal G1(n), the source of the eighth transistor T8 is electrically connected to the reverse scan control signal terminal D2U, and the drain of the eighth transistor T8 is electrically connected to the pull-down output sub-unit 423.

[0139] Specific, combined Figure 7 as well as Figure 6 As shown, in some embodiments of the present application, the second control signal receiving subunit 422 includes a ninth transistor T9.

[0140] The gate of the ninth transistor T9 is electrically connected to the n-th stage first gate driving signal output terminal G1(n), the source of the ninth transistor T9 is electrically connected to the forward scan control signal terminal U2D, and the drain of the ninth transistor T9 is electrically connected to the pull-down output sub-unit 423.

[0141] Specific, combined Figure 7 as well as Figure 6 As shown, in some embodiments of the present application, the pull-down output subunit 423 includes a tenth transistor T10.

[0142] The gate of the tenth transistor T10 is electrically connected to the first control signal receiving subunit 421 and the second control signal receiving subunit 422, the source of the tenth transistor T10 is electrically connected to the second reference signal terminal VGL, and the drain of the tenth transistor T10 is electrically connected to the n-th stage pull-down output signal terminal D(n).

[0143] Accordingly, some embodiments of the present application further provide a display panel. The display panel includes: Figures 5 to 7 Any one of the array substrate row driving circuits 1000 and a plurality of scan lines is shown.

[0144] Specifically, such as Figure 8 As shown, the display panel 2000 has a display area AA and a non-display area NA excluding the display area AA. The display panel 2000 includes an array substrate row driver circuit 1000 and a plurality of scan lines SL. The array substrate row driver circuit 1000 is located in the non-display area NA, and the plurality of scan lines SL are located in the display area AA.

[0145] The display panel 2000 also includes a plurality of pixel units, which are arrayed in the display area AA. A row of pixel units is electrically connected to a scan line SL, and a column of pixel units is electrically connected to a data line DL, so that each pixel unit is electrically connected to a scan line SL and a data line DL. A pixel unit is in an on state or an off state based on a received gate drive signal. When the gate drive signal is in the on state, the pixel unit is charged according to the data signal transmitted by the data line DL, so that the gate drive signal transmitted by the scan line SL can control the starting time, the ending time and the charging duration of the pixel unit.

[0146] The plurality of scan lines SL correspond one-to-one to and are electrically connected to the multi-stage first gate driving signal output terminals of the array substrate row driving circuit 1000 .

[0147] The qth scan line SL_q is electrically connected to the qth first gate driving signal output terminal G1(q) of the qth gate driving module 100 of the array substrate row driving circuit 1000, and the qth scan line SL_q is also electrically connected to the q-1th pull-down output terminal D(q-1) of the q-1th gate driving module 100 of the array substrate row driving circuit 1000. q is an integer greater than or equal to 2.

[0148] In the display panel 2000 provided in this embodiment, the qth scan line SL_q is electrically connected to the qth first gate drive signal output terminal G1(q), and the qth first gate drive signal output by the qth first gate drive signal output terminal G1(q) controls the starting time and charging duration of the row pixel unit electrically connected to the qth scan line SL_q. In addition, the qth scan line SL_q is electrically connected to the q-1th pull-down output signal terminal D(q-1), and the reference low-level signal output by the q-1th pull-down output terminal D(q-1) pulls down the potential on the qth scan line SL_q, thereby reducing the pull-down delay on the qth scan line SL_q (the pull-down delay refers to the delay for the first gate drive signal to switch from a high level to a low level), avoiding the problem of mischarging of the pixel unit electrically connected to the qth scan line SL_q, and improving the charging rate of the pixel unit.

[0149] Further, such as Figure 9 As shown, Figure 9 and Figure 8 The difference is that the head end of the qth scan line SL_q is electrically connected to the qth stage first gate driving signal output terminal G1(q), and the tail end of the qth scan line SL_q is electrically connected to the q-1th stage pull-down output terminal D(q-1).

[0150] In this embodiment, the starting end of the qth scan line SL_q refers to the end close to the non-display area NA where the array substrate row driving circuit 1000 is located, and the tail end of the qth scan line SL_q refers to the end away from the non-display area NA where the array substrate row driving circuit 1000 is located.

[0151] For medium-sized display panels or even large-sized display panels, when the scan line SL is unilaterally driven based on the array substrate row driving circuit 1000, the length of the scan line SL is relatively long. In the process of the first gate driving signal being transmitted from the head end of the scan line SL to the tail end of the scan line SL, the pixel unit electrically connected to the tail end of the scan line SL receives the first gate driving signal switched from a high level to a low level later than the pixel unit electrically connected to the head end of the scan line SL receives the first gate driving signal switched from a high level to a low level. As a result, the multiple pixel units electrically connected to the same scan line SL have different charging durations due to their different distances from the head end of the scan line SL, so that some pixel units in a row of pixel units are at risk of mischarging, which in turn causes the image displayed by the display panel to have bright and dark patterns along the pixel row direction.

[0152] To solve this problem, the present embodiment proposes to electrically connect the tail end of the qth scan line SL_q to the q-1th pull-down output signal terminal D(q-1), so that after the qth scan line SL_q is scanned, the q+1th scan line SL_q+1 receives the q+1th first gate drive signal from the q+1th first gate drive signal output terminal G1(q+1) and starts scanning. At the same time, the second pull-down control unit 42 of the qth gate drive module 100 also receives the q+1th first gate drive signal from the q+1th first gate drive signal output terminal G1(q+1) and outputs a reference low-level signal to the qth pull-down output signal terminal D(q).

[0153] Furthermore, the tail end of the qth scan line SL_q receives a reference low-level signal provided by the qth-level pull-down output signal terminal D(q), and the voltage of the first gate drive signal near the tail end of the qth scan line SL_q is pulled down to the voltage of the reference low-level signal, thereby achieving that the charging duration of multiple pixel units electrically connected to the same scan line SL is close to or the same, reducing the pull-down delay of the scan line, reducing the risk of mischarging of some pixel units in a row of pixel units, reducing the problem of uneven brightness of the picture displayed by the display panel along the pixel direction, and improving the display uniformity of the display panel.

[0154] It is worth mentioning that in Figure 9 as well as Figure 8In any of the display panels 2000 shown, the first scan line is not electrically connected to any stage of pull-down output terminal.

[0155] like Figure 10 As shown, in some other embodiments provided in this application, the display panel 2000 includes two Figures 8 and 9 Any one of the array substrate row driving circuits 1000 and a plurality of scan lines SL is shown.

[0156] The first array substrate row driver circuit 1000a is located in the first non-display area NA1 of the display panel 2000, and the second array substrate row driver circuit 1000b is located in the second non-display area NA2 of the display panel 2000. The first non-display area NA1 and the second non-display area NA2 are located on different sides of the display area AA of the display panel 2000. Multiple scan lines SL are located in the display area AA. The multiple scan lines SL correspond one-to-one to and are electrically connected to multiple rows of pixel units.

[0157] Among the plurality of scan lines SL, the 2q-1th scan line SL_(2q-1) is electrically connected to the qth first gate drive signal output terminal G1a(q) of the first array substrate row driver circuit 1000a, and the 2q-1th scan line SL_(2q-1) is also electrically connected to the q-1th pull-down output terminal Db(q-1) of the second array substrate row driver circuit 1000b. The 2qth scan line SL_(2q) is electrically connected to the qth first gate drive signal output terminal G1b(q) of the second array substrate row driver circuit 1000b, and the 2qth scan line SL_(2q) is also electrically connected to the qth pull-down output terminal Da(q) of the first array substrate row driver circuit 1000a. q is an integer greater than or equal to 1.

[0158] In this embodiment, the odd-numbered scan lines SL of the display panel 2000 receive a first gate drive signal provided by the first array substrate row drive circuit 1000a, and the even-numbered scan lines SL of the display panel receive a gate drive signal provided by the second array substrate row drive circuit 1000b, so that the odd-numbered scan lines SL charge the odd-numbered row pixel units pixel under the control of the first array substrate row drive circuit 1000a, and the even-numbered scan lines charge the even-numbered row pixel units pixel under the control of the second array substrate row drive circuit 1000b.

[0159] Furthermore, in this embodiment, the odd-numbered scan lines SL receive the reference low-level signal output by the second array substrate row driver circuit 1000b. Thus, under the control of the second array substrate row driver circuit 1000b, the potential on the odd-numbered scan lines SL is rapidly pulled down to the potential of the reference low-level signal. This reduces the pull-down delay of the first gate drive signal on the odd-numbered scan lines SL, thereby reducing the risk of mischarging of the pixels in the odd-numbered rows. The even-numbered scan lines SL receive the reference low-level signal output by the first array substrate row driver circuit 1000a. Thus, under the control of the first array substrate row driver circuit 1000a, the potential on the even-numbered scan lines SL is rapidly pulled down to the potential of the reference low-level signal. This reduces the pull-down delay of the first gate drive signal on the even-numbered scan lines SL, thereby reducing the risk of mischarging of the pixels in the even-numbered rows.

[0160] Furthermore, in some embodiments provided in this application, Figure 10 As shown, along the extension direction d1 of the scan lines SL, the first non-display area NA1 and the second non-display area NA2 are located on opposite sides of the display area AA. Specifically, the extension direction d1 of the scan lines SL is the pixel row direction, and the arrangement direction d2 of the multiple scan lines SL in the display area AA is the pixel column direction.

[0161] Among them, the head end of the 2q-1th scan line SL_(2q-1) is electrically connected to the q-th gate drive signal output terminal G1a(q) of the first array substrate row driving circuit 1000a, and the tail end of the 2q-1th scan line SL_(2q-1) is electrically connected to the q-1th pull-down output terminal Db(q-1) of the second array substrate row driving circuit 1000b.

[0162] Among them, the starting end of the 2q-1th scan line SL_(2q-1) refers to the end of the 2q-1th scan line SL_(2q-1) close to the first non-display area NA1, and the tail end of the 2q-1th scan line SL_(2q-1) refers to the end of the 2q-1th scan line SL_(2q-1) close to the second non-display area NA2.

[0163] Among them, the head end of the 2qth scan line SL_(2q) is electrically connected to the qth gate drive signal output terminal G1b(q) of the second array substrate row driving circuit 1000b, and the tail end of the 2qth scan line SL_(2q) is electrically connected to the qth pull-down output terminal D(q) of the first array substrate row driving circuit 1000a.

[0164] The beginning of the 2qth scan line SL_(2q) refers to the end of the 2qth scan line SL_(2q) close to the second non-display area NA2, and the end of the 2qth scan line SL_(2q) refers to the end of the 2qth scan line SL_(2q) close to the first non-display area NA1.

[0165] In this embodiment, based on electrically connecting the head end of the 2q-1th scan line SL_(2q-1) to the qth gate drive signal output terminal G1a(q) of the first array substrate row drive circuit 1000a, the connection line between the qth gate drive module 100 of the first array substrate row drive circuit 1000a and the 2q-1th scan line SL_(2q-1) is shortened, thereby shortening the transmission time of the first gate drive signal from the qth gate drive signal output terminal G1a(q) of the first array substrate row drive circuit 1000a to the 2q-1th scan line SL_(2q-1).

[0166] In this embodiment, based on the electrical connection between the tail end of the 2q-1th scan line SL_(2q-1) and the q-1th level pull-down output signal terminal Db(q-1) of the second array substrate row driving circuit 1000b, the connection line between the q-1th level gate driving module 100 of the second array substrate row driving circuit 1000b and the 2q-1th scan line SL_(2q-1) is shortened, thereby shortening the transmission time of the reference low-level signal from the q-1th level pull-down output terminal Db(q-1) of the second array substrate row driving circuit 1000b to the 2q-1th scan line SL_(2q-1), reducing the pull-down delay of the first gate driving signal on the 2q-1th scan line SL_(2q-1), further reducing the risk of mischarging, and further improving the display uniformity of the display panel.

[0167] It is worth mentioning that in this embodiment, based on the fact that an array substrate row driving circuit (1000a, 1000b) is provided on both sides of the display area AA, and the electrical connection relationship between the scan line SL and the first array substrate row driving circuit 1000a and the second array substrate row driving circuit 1000b, the display panel 2000 adopts an interlace driving architecture.

[0168] Furthermore, in some embodiments provided in this application, Figure 11 As shown, the first scan line SL_1 is electrically connected to the first-stage gate drive signal output terminal G1a(1) of the first array substrate row driver circuit 1000a. The first scan line SL_1 is also electrically connected to the dummy output terminal Dummy located in the second non-display area NA2. The dummy output terminal Dummy is the zero-stage pull-down output terminal of the second array substrate row driver circuit 1000b.

[0169] In this embodiment, since the smallest pull-down output terminal in the second array substrate row driving circuit 1000b is the first pull-down output terminal Db(1), a pull-down output terminal smaller than the first pull-down output terminal Db(1) does not exist, and therefore a dummy output terminal Dummy is provided to be electrically connected to the first scan line SL_1.

[0170] Furthermore, in some embodiments provided in this application, Figure 11 as well as Figure 12 As shown, in the final gate driving module 100 electrically connected to the last scan line SL_(last), the n+1th first gate driving signal output terminal G1(n+1) electrically connected to the second pull-down control unit 42 is the second reference signal terminal VGL.

[0171] In this embodiment, since the maximum-level pull-down output signal terminal in the second array substrate row driving circuit 1000b is the final-stage gate driving signal output terminal G1b(last) of the final-stage gate driving module 100, a first gate driving signal output terminal larger than the final-stage gate driving signal output terminal G1b(last) does not exist. Therefore, in the final-stage gate driving module 100, the pre-charging unit 10 that should be electrically connected to the n+2-th-level first gate driving signal output terminal G1(n+2) and the second pull-down control unit 42 are controlled to be electrically connected to the second reference signal terminal VGL.

[0172] The final gate driver module 100 is the last gate driver module 100 in the first array substrate row driver circuit 1000a or the last gate driver module 100 in the second array substrate row driver circuit 1000b. Whether the final gate driver module 100 is located in the first non-display area NA1 or the second non-display area NA2 depends on whether the last scan line SL_(last) is an odd-numbered scan line or an even-numbered scan line.

[0173] The following combination Figure 13a as well as Figure 13b At once Figure 10 For ease of understanding, the display panel 2000 is described as adopting an 8CK architecture and each array substrate row driving circuit has a 4-stage gate driving module 100 as the minimum repeatable unit.

[0174] Specifically, such as Figure 13aAs shown, the display panel 2000 is provided with 8 sub-clock signal terminals, among which the first sub-clock signal terminal CKa1, the second sub-clock signal terminal CKa2, the third sub-clock signal terminal CKa3 and the fourth sub-clock signal terminal CKa4 are electrically connected to the first array substrate row driving circuit 1000a, and the fifth sub-clock signal terminal CKb1, the sixth sub-clock signal terminal CKb2, the seventh sub-clock signal terminal CKb3 and the eighth sub-clock signal terminal CKb4 are electrically connected to the second array substrate row driving circuit 1000b.

[0175] Specifically, such as Figure 13a As shown, in the first array substrate row driving circuit 1000a, the first-stage gate driving module 100, the second-stage gate driving module 100, the third-stage gate driving module 100, and the fourth-stage gate driving module 100 are all electrically connected to the first reference signal terminal VGH, the second reference signal terminal VGL, the forward scan control signal terminal U2D, the reverse scan control signal terminal D2U, and the first global control signal terminal gas1.

[0176] Specifically, such as Figure 13a As shown, in the first array substrate row driving circuit 1000a, each gate driving module 100 includes a pre-charging unit, a first pull-up unit, a first pull-down unit, a first pull-down control unit, a feedback unit, a voltage stabilizing unit, a first storage unit, a second storage unit, a first global reset unit and a second pull-down control unit. Figure 4 as well as Figure 13a As shown, the pre-charging unit 10 includes a first transistor T1 and a second transistor T2, the first pull-up unit 21 includes a third transistor T3, the first pull-down unit 31 includes a fourth transistor T4 and a fifth transistor T5, the first pull-down control unit 41 includes a sixth transistor T6 and a seventh transistor T7, the feedback unit 50 includes an eleventh transistor, the voltage stabilizing unit 60 includes a twelfth transistor T12, and the first global control unit 81 includes a thirteenth transistor T13. Figure 7 as well as Figure 13a As shown, the second pull-down control unit 42 includes an eighth transistor T8 , a ninth transistor T9 and a tenth transistor T10 .

[0177] The difference is that the first-stage gate driving module 100 is electrically connected to the first sub-clock signal terminal CKa1 and the third sub-clock signal terminal CKa3, the second-stage gate driving module 100 is electrically connected to the second sub-clock signal terminal CKa2 and the fourth sub-clock signal terminal CKa4, the third-stage gate driving module 100 is electrically connected to the first sub-clock signal terminal CKa1 and the third sub-clock signal terminal CKa3, and the fourth-stage gate driving module 100 is electrically connected to the second sub-clock signal terminal CKa2 and the fourth sub-clock signal terminal CKa4.

[0178] Specifically, in the first-level gate driving module 100 of the first array substrate row driving circuit 1000a, the gate of the first transistor T1 is electrically connected to the first start signal terminal STV1, the gate of the second transistor T2 is electrically connected to the second-level first gate driving signal output terminal G1a(2) of the first array substrate row driving circuit 1000a, the source of the third transistor T3 is electrically connected to the first sub-clock signal terminal CKa1, the gate of the sixth transistor T6 and the gate of the seventh transistor T7 are both electrically connected to the third sub-clock signal terminal CKa3, the first-level first gate driving signal output terminal G1a(1) is electrically connected to the first scan line SL_1, the gate of the ninth transistor T9 is electrically connected to the second-level first gate driving signal output terminal G1a(2) of the first array substrate row driving circuit 1000a, and the first-level pull-down output signal terminal Da(1) is electrically connected to the second scan line SL_2.

[0179] Specifically, in the second-level gate driving module 100 of the first array substrate row driving circuit 1000a, the gate of the first transistor T1 is electrically connected to the first-level first gate driving signal output terminal G1a(1) of the first array substrate row driving circuit 1000a, the gate of the second transistor T2 is electrically connected to the third-level first gate driving signal output terminal G1a(3) of the first array substrate row driving circuit 1000a, the source of the third transistor T3 is electrically connected to the second sub-clock signal terminal CKa2, the gate of the sixth transistor T6 and the gate of the seventh transistor T7 are electrically connected to the fourth sub-clock signal terminal CKa4, the second-level first gate driving signal output terminal G1a(2) is electrically connected to the third scan line SL_3, the gate of the ninth transistor T9 is electrically connected to the third-level first gate driving signal output terminal G1a(3) of the first array substrate row driving circuit 1000a, and the second-level pull-down output signal terminal Da(2) is electrically connected to the fourth scan line SL_4.

[0180] Specifically, in the third-level gate driving module 100 of the first array substrate row driving circuit 1000a, the gate of the first transistor T1 is electrically connected to the second-level first gate driving signal output terminal G1a(2) of the first array substrate row driving circuit 1000a, the gate of the second transistor T2 is electrically connected to the fourth-level first gate driving signal output terminal G1a(4) of the first array substrate row driving circuit 1000a, the source of the third transistor T3 is electrically connected to the third sub-clock signal terminal CKa3, the gate of the sixth transistor T6 and the gate of the seventh transistor T7 are both electrically connected to the first sub-clock signal terminal CKa1, the third-level first gate driving signal output terminal G1a(3) is electrically connected to the fifth scan line SL_5, the gate of the ninth transistor T9 is electrically connected to the fourth-level first gate driving signal output terminal G1a(4) of the first array substrate row driving circuit 1000a, and the third-level pull-down output signal terminal Da(3) is electrically connected to the sixth scan line SL_6.

[0181] Specifically, in the fourth-level gate driving module 100 of the first array substrate row driving circuit 1000a, the gate of the first transistor T1 is electrically connected to the third-level first gate driving signal output terminal G1a(3) of the first array substrate row driving circuit 1000a, the gate of the second transistor T2 is electrically connected to the fifth-level first gate driving signal output terminal G1a(5) of the first array substrate row driving circuit 1000a, the source of the third transistor T3 is electrically connected to the fourth sub-clock signal terminal CKa4, the gate of the sixth transistor T6 and the gate of the seventh transistor T7 are both electrically connected to the second sub-clock signal terminal CKa2, the fourth-level first gate driving signal output terminal G1a(4) is electrically connected to the seventh scan line SL_7, the second pull-down control unit 42 is electrically connected to the fifth-level first gate driving signal output terminal G1a(5) of the first array substrate row driving circuit 1000a, and the fourth-level pull-down output signal terminal Da(4) is electrically connected to the eighth scan line SL_8.

[0182] Specifically, such as Figure 13a As shown, in the second array substrate row driving circuit 1000b, the first-stage gate driving module 100, the second-stage gate driving module 100, the third-stage gate driving module 100, and the fourth-stage gate driving module 100 are all electrically connected to the first reference signal terminal VGH, the second reference signal terminal VGL, the forward scan control signal terminal U2D, the reverse scan control signal terminal D2U, and the first global control signal terminal gas1.

[0183] The difference is that: the first-level gate driving module 100 is electrically connected to the fifth sub-clock signal terminal CKb1 and the seventh sub-clock signal terminal CKb3, the second-level gate driving module 100 is electrically connected to the sixth sub-clock signal terminal CKb2 and the eighth sub-clock signal terminal CKb4, the third-level gate driving module 100 is electrically connected to the fifth sub-clock signal terminal CKb1 and the seventh sub-clock signal terminal CKb3, and the fourth-level gate driving module 100 is electrically connected to the sixth sub-clock signal terminal CKb2 and the eighth sub-clock signal terminal CKb4.

[0184] Specifically, in the first-level gate driving module 100 of the second array substrate row driving circuit 1000b, the gate of the first transistor T1 is electrically connected to the second start signal terminal STV2, the gate of the second transistor T2 is electrically connected to the second-level first gate driving signal output terminal G1b(2) of the second array substrate row driving circuit 1000b, the source of the third transistor T3 is electrically connected to the fifth sub-clock signal terminal CKb1, the gate of the sixth transistor T6 and the gate of the seventh transistor T7 are both electrically connected to the seventh sub-clock signal terminal CKb3, the first-level first gate driving signal output terminal G1b(1) is electrically connected to the second scan line SL_2, the gate of the ninth transistor T9 is electrically connected to the second-level first gate driving signal output terminal G1b(2) of the second array substrate row driving circuit 1000b, and the first-level pull-down output terminal Db(1) is electrically connected to the third scan line SL_2.

[0185] Specifically, in the second-level gate driving module 100 of the second array substrate row driving circuit 1000b, the gate of the first transistor T1 is electrically connected to the first-level first gate driving signal output terminal G1b(1) of the second array substrate row driving circuit 1000b, the gate of the second transistor T2 is electrically connected to the third-level first gate driving signal output terminal G1b(3) of the second array substrate row driving circuit 1000b, the source of the third transistor T3 is electrically connected to the sixth sub-clock signal terminal CKb2, the gate of the sixth transistor T6 and the gate of the seventh transistor T7 are both electrically connected to the eighth sub-clock signal terminal CKb4, the second-level first gate driving signal output terminal G1b(2) is electrically connected to the fourth scan line SL_4, the gate of the ninth transistor T9 is electrically connected to the third-level first gate driving signal output terminal G1b(3) of the second array substrate row driving circuit 1000b, and the second pull-down output terminal Db(2) is electrically connected to the fourth scan line SL_4.

[0186] Specifically, in the third-level gate driving module 100 of the second array substrate row driving circuit 1000b, the gate of the first transistor T1 is electrically connected to the second-level first gate driving signal output terminal G1a(2) of the second array substrate row driving circuit 1000b, the gate of the second transistor T2 is electrically connected to the fourth-level first gate driving signal output terminal G1a(4) of the second array substrate row driving circuit 1000b, the source of the third transistor T3 is electrically connected to the seventh sub-clock signal terminal CKb3, the gate of the sixth transistor T6 and the gate of the seventh transistor T7 are both electrically connected to the fifth sub-clock signal terminal CKb1, the third-level first gate driving signal output terminal G1b(3) is electrically connected to the sixth scan line SL_6, the gate of the ninth transistor T9 is electrically connected to the fourth-level first gate driving signal output terminal G1b(4) of the second array substrate row driving circuit 1000b, and the third pull-down output terminal Db(3) is electrically connected to the sixth scan line SL_6.

[0187] Specifically, in the fourth-level gate driving module 100 of the second array substrate row driving circuit 1000b, the gate of the first transistor T1 is electrically connected to the third-level first gate driving signal output terminal G1b(3) of the second array substrate row driving circuit 1000b, the gate of the second transistor T2 is electrically connected to the fifth-level first gate driving signal output terminal G1b(5) of the second array substrate row driving circuit 1000b, the source of the third transistor T3 is electrically connected to the eighth sub-clock signal terminal CKb4, the gate of the sixth transistor T6 and the gate of the seventh transistor T7 are both electrically connected to the sixth sub-clock signal terminal CKb2, the fourth-level first gate driving signal output terminal G1b(4) is electrically connected to the eighth scan line SL_8, the gate of the ninth transistor T9 is electrically connected to the fifth-level first gate driving signal output terminal G1b(5) of the second array substrate row driving circuit 1000b, and the fourth pull-down output terminal Db(4) is electrically connected to the eighth scan line SL_8.

[0188] When the display panel performs forward scanning, the first scanning line SL_1 to the eighth scanning line SL_8 scan corresponding pixel rows one by one.

[0189] Specifically, the first transistor T1 of the first-stage gate driving module 100 of the first array substrate row driving circuit 1000a is turned on when the first start signal of the first start signal terminal STV1 is at a high level, and the first node G1a(1) of the first stage is precharged. The third transistor T3 is turned on when the potential of the first node G1a(1) of the first stage is at a high level, and the first sub-clock signal of the first sub-clock signal terminal CKa1 is output to the first-stage first gate driving signal output terminal G1a(1), so that the first scan line SL_1 outputs the first gate driving signal outputted from the first-stage first gate driving signal output terminal G1a(1) to the first scan line SL_1, as shown in FIG. Figure 13b As shown, during the period when the first gate driving signal outputted by the first-stage first gate driving signal output terminal G1a(1) is continuously at a high level, the first scanning line SL_1 charges a row of pixel units.

[0190] After the first-stage gate driving module 100 of the first array substrate row driving circuit 1000a completes precharging based on the first start signal, the first-stage gate driving module 100 of the second array substrate row driving circuit 1000b starts precharging the first node G1b(1) of the first stage based on the second start signal of the second start signal terminal STV2, and the third transistor T3 is turned on when the potential of the first node G1b(1) of the first stage is high, and outputs the fifth sub-clock signal of the fifth sub-clock signal terminal CKb1 to the first-stage first gate driving signal output terminal G1b(1), so that the second scan line SL_2 outputs the first gate driving signal outputted from the first-stage first gate driving signal output terminal G1b(1) to the second scan line SL_2, as shown in FIG. Figure 13b As shown, while the first gate drive signal outputted by the first-stage first gate drive signal output terminal G1b(1) remains at a high level, the second scan line SL_2 charges the second row of pixel units. Furthermore, the start time point of the second scan line SL_2 charging a row of pixel units is later than the end time point of the first scan line SL_1 charging another row of pixel units, thereby achieving row-by-row scanning.

[0191] Among them, while the second-level first gate drive signal output terminal G1a(1) of the first array substrate row drive circuit 1000a outputs the first gate drive signal to the third scan line, this gate drive signal is also output to the gate of the ninth transistor T9 in the first-level gate drive module 100 of the first array substrate row drive circuit 1000a, so that the ninth transistor T9 is turned on, and then controls the tenth transistor T10 to be turned on, and the tenth transistor T10 outputs the reference low-level signal to the second scan line SL_2, so as to reduce the pull-down delay on the second scan line SL_2, and ensure that the second scan line SL_2 stops charging the second row of pixel units during the period when the third scan line SL_3 charges the third row of pixel units.

[0192] Based on the above description, by analogy, during the period when the fourth scan line SL_4 charges the pixel units in the fourth row, the third scan signal SL_3 stops charging the pixel units in the third row; during the period when the fourth scan line SL_4 charges the pixel units in the third row, the third scan signal SL_3 stops charging the pixel units in the third row.

[0193] In some embodiments provided in this application, Figure 14 As shown, compared with Figures 2 to 4 In any one of the above, the n-th stage gate driving module 100 further includes a second pull-up unit 22 and a second pull-down unit 32 .

[0194] The second pull-up unit 22 is electrically connected to the third clock signal terminal CKc, the first node Q(n), and the n-th stage second gate driving signal output terminal G2 (n) of the n-th stage gate driving module 100 .

[0195] The second pull-up unit 22 is used to output the nth stage second gate driving signal to the nth stage second gate driving signal output terminal G2(n) under the control of the third clock signal of the third clock signal terminal CKc and the potential of the first node Q(n).

[0196] Among them, the second pull-down unit 32 is electrically connected to the second node P(n), the second reference signal terminal VGL and the n-th level second gate drive signal output terminal G2(n), and the second pull-down unit 32 is used to output the reference low-level signal to the n-th level second gate drive signal output terminal G2(n) based on the potential of the second node P(n).

[0197] In this embodiment, by adding a second pull-up unit 22 and a second pull-down unit 32, the first-level gate driving module 100 can output two gate driving signals, thereby eliminating half the number of pre-charging units 10 and the first pull-down control unit 41 in the array substrate row driving circuit 1000, which is beneficial to reducing the area occupied by the array substrate row driving circuit 1000 and further realizing a narrow frame of the display panel.

[0198] Specifically, such as Figure 15 As shown, in some embodiments provided herein, the second pull-up unit 22 includes a fourteenth transistor T14, a gate of the fourteenth transistor T14 is electrically connected to the first node Q(n), a source of the fourteenth transistor T14 is electrically connected to the third clock signal terminal CKc, and a drain of the fourteenth transistor T14 is electrically connected to the n-th stage second gate drive signal output terminal G2(n);

[0199] Specifically, such as Figure 15 As shown, in some embodiments provided in the present application, the second pull-down unit 32 includes a fifteenth transistor T15, the gate of the fifteenth transistor T15 is electrically connected to the second node P(n), the source of the fifteenth transistor T15 is electrically connected to the second reference signal terminal VGL, and the drain of the fifteenth transistor T15 is electrically connected to the n-th level second gate drive signal output terminal G2(n).

[0200] Combine Figure 15 as well as Figure 16 As shown, in the 4n-th level gate driving module 100, the first pull-up unit 21 receives the first clock signal (corresponding to Figure 16 The end time of CKa_4 in the second pull-up unit 22 is earlier than or equal to the third clock signal (corresponding to the third clock signal) received as a high level signal by the second pull-up unit 22. Figure 16 The starting time point of CKc_4).

[0201] In this way, the n-th stage gate driving module 100 can output the first gate driving signal as a high level signal to the n-th stage first gate driving signal output terminal G1(n) and the second gate driving signal as a high level signal to the n-th stage second gate driving signal output terminal G2(n) in a time-sharing manner.

[0202] For further information, please refer to Figure 16 as well as Figure 15 In the 4n-th stage gate driving module 100, the first pull-up unit 21 receives the first clock signal (corresponding to Figure 16 The starting time point of CKa_4 in the 4n-1 stage gate driving module 100 is later than or equal to the second clock signal (corresponding to the second clock signal) received by the second pull-up unit 22 as a high level signal. Figure 16 The end point of CKc_3).

[0203] Combine Figure 17 as well as Figure 15 As shown, in the 4n-1th stage gate driving module 100, the first pull-up unit 21 receives the first clock signal (corresponding to Figure 17The starting time point of CKa_3 shown in FIG1 is earlier than the third clock signal (corresponding to the third clock signal) received as a high level signal by the second pull-up unit 22. Figure 17 The starting time point of CKc_3 shown in FIG1 , and the first pull-up unit 21 receives the first clock signal (corresponding to the first clock signal) which is a high level signal. Figure 17 The end point of CKa_3 shown in FIG1 is later than the third clock signal (corresponding to the third clock signal) received as a high level signal by the second pull-up unit 22. Figure 17 The starting time point of CKc_3) shown.

[0204] In this way, in any level of the gate driving module 100, the period during which the first clock signal continues to be a high-level signal and the period during which the third clock signal continues to be a high-level signal partially overlap. Specifically, in the 4n-1 level gate driving module 100, the period during which the 4n-1 level first gate driving signal of the 4n-1 level first gate driving signal output terminal G1 (4n-1) continues to be a high-level signal and the period during which the 4n-1 level second gate driving signal of the 4n-1 level second gate driving signal output terminal G2 (4n-1) continues to be a high-level signal partially overlap, thereby increasing the pre-charge time of the pixel unit.

[0205] Accordingly, some embodiments of the present application further provide a display panel 2000, such as Figure 18 As shown, the display panel 2000 has a display area AA and a non-display area NA except the display area AA. The display panel 2000 includes Figures 14 and 15 Any of the array substrate row driving circuits 1000 , a plurality of first scan lines SL1 , and a plurality of second scan lines SL2 are shown.

[0206] The plurality of first scan lines are located in the display area AA, and the plurality of first scan lines correspond one-to-one to and are electrically connected to the multi-stage first gate drive signal output terminals of the array substrate row driver circuit 1000. The plurality of second scan lines are located in the display area AA, and the plurality of second scan lines correspond one-to-one to and are electrically connected to the multi-stage second gate drive signal output terminals of the array substrate row driver circuit 1000.

[0207] Among them, one Figures 14 and 15 Any of the array substrate row driving circuits 1000 shown is located in the non-display area AA.

[0208] In this embodiment, by setting Figures 14 and 15Any of the array substrate row driver circuits 1000 shown is located in the non-display area AA, and electrically connects the first scan line to the first gate drive signal output terminal and the second scan line to the second gate drive signal output terminal, so that one first scan line and one second scan line share a single-stage gate driver module 100. Compared with the technical solution in the related art in which one scan line is electrically connected to one-stage gate driver module 100, the number of gate driver modules 100 in the array substrate row driver circuit 1000 in this embodiment is half the total number of first scan lines and second scan lines in the display area AA, which is more conducive to achieving a narrow frame of the display panel.

[0209] Furthermore, the display panel 2000 is provided with Figures 14 and 15 Based on any of the array substrate row driving circuits 1000 shown in FIG. 1 , the array substrate row driving circuit 1000 adopts the following Figure 17 As shown in the driving timing, the period during which the first clock signal of each gate driving module 100 is continuously a high-level signal and the period during which the third clock signal is continuously a high-level signal partially overlap, thereby effectively increasing the pre-charging time of the pixel unit and improving the charging rate of the pixel unit.

[0210] Please continue reading Figure 18 ,like Figure 18 As shown, the first scan lines and the second scan lines are alternately located in the display area AA. Exemplarily, the arrangement direction of the plurality of first scan lines and the plurality of second scan lines is the pixel column direction. The pixel column direction is arranged to intersect with the pixel row direction.

[0211] The first first scan line to the last first scan line are sequentially arranged along the pixel column direction, and the first second scan line to the last scan line are sequentially arranged along the pixel column direction.

[0212] The rth first scan line SL1_(r) is electrically connected to the rth first gate drive signal output terminal G1(r) of the array substrate row driver circuit 1000, and the rth second scan line SL2_(r) is electrically connected to the rth second gate drive signal output terminal G2(r). r is an integer greater than or equal to 1.

[0213] The rth first scan line SL1_(r) charges the pixel units in the 2r-1th row, and the rth second scan line SL2_(r) charges the pixel units in the 2rth row.

[0214] In this embodiment, by electrically connecting the rth first scan line SL1_(r) to the rth first gate drive signal output terminal G1(r) and electrically connecting the rth second scan line SL2_(r) to the rth second gate drive signal output terminal G2(r), under the control of the array substrate row drive circuit 1000, the first scan line to the last scan line in the display panel can achieve forward progressive scanning, or, the last scan line to the first scan line in the display panel can achieve reverse progressive scanning.

[0215] Accordingly, some embodiments of the present application further provide a display panel 2000, such as Figure 19 As shown, Figure 19 and Figure 18 、 Figure 17 The difference is that the display panel 2000 includes two Figures 14 and 15 The array substrate row driving circuit 1000 shown in any one of the figures. That is, Figure 18 A display panel with a double-side gate driving architecture is shown.

[0216] The first array substrate row driver circuit 1000a is located in the first non-display area NA1, and the second array substrate row driver circuit 1000b is located in the second non-display area NA2. The first non-display area NA1 and the second non-display area NA2 are located on opposite sides of the display area AA. The plurality of first scan lines and the plurality of second scan lines are both located in the display area AA.

[0217] Among them, the rth first scan line SL1_(r) is electrically connected to the rth first gate drive signal output terminal G1a(r) of the first array substrate row driving circuit 1000a, and the rth first scan line SL1_(r) is also electrically connected to the rth first gate drive signal output terminal G1b(r) of the second array substrate row driving circuit 1000b.

[0218] Among them, the rth second scan line SL2_(r) is electrically connected to the rth second gate drive signal output terminal G2a(r) of the first array substrate row driving circuit 1000a, and the rth second scan line SL1_(r) is also electrically connected to the rth second gate drive signal output terminal G2b(r) of the second array substrate row driving circuit 1000b.

[0219] In the display panel provided in this embodiment, the first array substrate row driving circuit 1000a and the second array substrate row driving circuit 1000b simultaneously output corresponding gate driving signals to the same first scan line SL1 or the same second scan line SL2, thereby reducing the scan signal delay on the same first scan line or the same second scan line and improving the charging rate of the pixel unit.

[0220] Further, such as Figure 19 As shown, Figure 19 and Figure 18 Another difference is that, along the extension direction of the first scan line SL1, the first non-display area NA1 and the second non-display area NA2 are located on opposite sides of the display area AA. As a result, one of the leading end and the trailing end of the first scan line SL1 is close to the first non-display area NA1, and the other of the leading end and the trailing end of the first scan line SL1 is close to the second non-display area NA2.

[0221] Specifically, the rth first scan line SL1_(r) has a leading end adjacent to the first non-display area NA1 and is electrically connected to the rth-stage first gate drive signal output terminal G1a(r) of the first array substrate row driver circuit 1000a. The rth first scan line SL1_(r) has a trailing end adjacent to the second non-display area NA2 and is electrically connected to the rth-stage first gate drive signal output terminal G1b(r) of the second array substrate row driver circuit 1000b.

[0222] In this embodiment, based on electrically connecting one of the head end and the tail end of the rth first scan line SL1_(r) to the rth first gate drive signal output terminal G1a(r) of the first array substrate row driver circuit 1000a, the connection line between the rth level gate driver module 100 of the first array substrate row driver circuit 1000a and the rth first scan line SL1_(r) is shortened, thereby shortening the transmission time of the first gate drive signal from the rth level first gate drive signal output terminal G1a(r) of the first array substrate row driver circuit 1000a to the rth first scan line SL1_(r). Similarly, based on electrically connecting the other of the head end and the tail end of the rth first scan line SL1_(r) to the rth level first gate drive signal output terminal G1b(r) of the second array substrate row driving circuit 1000b, the connection line between the rth level gate driving module 100 of the second array substrate row driving circuit 1000b and the rth first scan line SL1_(r) is shortened, thereby shortening the transmission time of the first gate drive signal from the rth level first gate drive signal output terminal G1b(r) of the second array substrate row driving circuit 1000b to the rth first scan line SL1_(r), thereby improving the charging rate of the 2r-1th row of pixel units electrically connected to the rth first scan line SL1_(r).

[0223] Specifically, the extension direction of the second scan line SL2 is parallel or approximately parallel to the extension direction of the first scan line SL1, the head end of the rth second scan line is close to the first non-display area NA1, the head end of the rth second scan line is electrically connected to the rth level second gate drive signal output terminal of the first array substrate row driving circuit 1000a, the tail end of the rth second scan line is close to the second non-display area NA2, and the tail end of the rth second scan line is electrically connected to the rth level second gate drive signal output terminal of the second array substrate row driving circuit 1000b.

[0224] Similarly, the rth second scan line SL2_(r) is based on a similar connection relationship, thereby shortening the transmission time of the second gate drive signal from the rth level second gate drive signal output terminal G2a(r) of the first array substrate row drive circuit 1000a to the rth second scan line SL2_(r), and shortening the transmission time of the second gate drive signal from the rth level second gate drive signal output terminal G2ab(r) of the second array substrate row drive circuit 1000b to the rth second scan line SL2_(r), thereby improving the charging rate of the 2rth row pixel unit electrically connected to the rth second scan line SL2_(r).

[0225] Of course, the present application may have many other embodiments. Without departing from the spirit and essential points of the present application, technicians familiar with the field may make various corresponding changes and modifications based on the present application, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present application.

Claims

1. An array substrate row driving circuit, characterized in that: The n-th gate driver module includes: a pre-charging unit, the pre-charging unit being electrically connected to an np-th level first gate driving signal output terminal of an np-th level gate driving module, an n+p-th level first gate driving signal output terminal of an n+p-th level gate driving module, a first reference signal terminal, and a first node of the n-th level gate driving module, the pre-charging unit being configured to output a reference high-level signal from the first reference signal terminal to the first node under control of the np-th level first gate driving signal from the np-th level first gate driving signal output terminal or the n+p-th level first gate driving signal from the n+p-th level first gate driving signal output terminal; a first pull-up unit, the first pull-up unit being electrically connected to the first node, the first clock signal terminal, and the n-stage first gate driving signal output terminal of the n-stage gate driving module, the first pull-up unit being configured to output the n-stage first gate driving signal to the n-stage first gate driving signal output terminal under the control of the first clock signal of the first clock signal terminal and the potential of the first node; a first pull-down unit, the first pull-down unit being electrically connected to the first node, the n-th stage first gate driving signal output terminal, the second reference signal terminal, and the second node of the n-th stage gate driving module, the first pull-down unit being configured to output a reference low-level signal of the second reference signal terminal to the first node and the n-th stage first gate driving signal output terminal based on a potential of the second node; a first pull-down control unit, the first pull-down control unit being electrically connected to the second clock signal terminal, the forward scan control signal terminal, the reverse scan control signal terminal, the first node, and the second node, the first pull-down control unit being configured to output the forward scan control signal of the forward scan control signal terminal to the second node and output the reverse scan control signal of the reverse scan control signal terminal to the first node under the control of the second clock signal of the second clock signal terminal; Wherein, n and p are integers greater than 0, and n is greater than p.

2. The array substrate row driving circuit according to claim 1, wherein: The pre-charging unit includes a first transistor and a second transistor, the gate of the first transistor is electrically connected to the first gate driving signal output terminal of the np-th stage, the source of the first transistor is electrically connected to the first reference signal terminal, the drain of the first transistor is electrically connected to the first node, the gate of the second transistor is electrically connected to the first gate driving signal output terminal of the n+p-th stage, the source of the second transistor is electrically connected to the first reference signal terminal, and the drain of the second transistor is electrically connected to the first node; The first pull-up unit includes a third transistor, a gate of the third transistor is electrically connected to the first node, a source of the third transistor is electrically connected to the first clock signal terminal, and a drain of the third transistor is electrically connected to the n-th stage first gate drive signal output terminal; The first pull-down unit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is electrically connected to the second node, the source of the fourth transistor is electrically connected to the second reference signal terminal, the drain of the fourth transistor is electrically connected to the first node, the gate of the fifth transistor is electrically connected to the second node, the source of the fifth transistor is electrically connected to the second reference signal terminal, and the drain of the fifth transistor is electrically connected to the n-th stage first gate driving signal output terminal; The first pull-down control unit includes a sixth transistor and a seventh transistor, the gate of the sixth transistor is electrically connected to the second clock signal end, the source of the sixth transistor is electrically connected to the reverse scan control signal end, the drain of the sixth transistor is electrically connected to the first node, the gate of the seventh transistor is electrically connected to the second clock signal end, the source of the seventh transistor is electrically connected to the forward scan control signal end, and the drain of the seventh transistor is electrically connected to the second node.

3. The array substrate row driving circuit according to claim 1, wherein: The n-th stage gate driving module further includes a feedback unit, the feedback unit being electrically connected to the first node, the second node, and the second reference signal terminal, and the feedback unit being configured to output the reference low-level signal to the second node according to the potential of the first node; The n-th stage gate driving module further includes a voltage stabilizing unit, the voltage stabilizing unit being electrically connected to the first reference signal terminal, the first node, and the first pull-up unit, and the voltage stabilizing unit being configured to maintain the potential of the first node based on the reference high-level signal; The n-th stage gate driving module further includes a first storage unit, one end of the first storage unit is electrically connected to the first node, the other end of the first storage unit is electrically connected to the second reference signal end, and the first storage unit is used to store the potential of the first node; The n-th stage gate driving module further includes a second storage unit, one end of the second storage unit is electrically connected to the second node, the other end of the second storage unit is electrically connected to the second reference signal end, and the second storage unit is used to store the potential of the second node; The n-th level gate drive module also includes a first global control unit, which is electrically connected to the first global control signal terminal and the n-th level first gate drive signal output terminal, and the first global control unit is used to pull up the potential of the n-th level first gate drive signal output terminal under the control of the first global control signal of the first global control signal terminal.

4. The array substrate row driving circuit according to any one of claims 1 to 3, characterized in that: The n-th level gate driving module also includes a second pull-down control unit, which is electrically connected to the n-th level first gate driving signal output terminal, the n+p-th level first gate driving signal output terminal, the forward scan control signal terminal, the reverse scan control signal terminal, the second reference signal terminal and the n-th level pull-down signal output terminal. The second pull-down control unit is used to output the reference low-level signal to the n-th level pull-down signal output terminal under the control of the n-th level first gate driving signal and the reverse scan control signal, or to output the reference low-level signal to the n-th level pull-down signal output terminal under the control of the n+p-th level first gate driving signal and the forward scan control signal.

5. The array substrate row driving circuit according to claim 4, wherein: The second pull-down control unit includes a first control signal receiving subunit, a second control signal receiving subunit and a pull-down output subunit; The first control signal receiving subunit is electrically connected to the n-th stage first gate driving signal output terminal, the reverse scan control signal terminal and the pull-down output subunit; The second control signal receiving subunit is electrically connected to the n+pth stage first gate driving signal output terminal, the forward scanning control signal terminal and the pull-down output subunit; The pull-down output subunit is also electrically connected to the second reference signal terminal and the n-th stage pull-down signal output terminal.

6. The array substrate row driving circuit according to claim 5, wherein: The first control signal receiving sub-unit includes an eighth transistor, a gate of the eighth transistor is electrically connected to the n-th stage first gate driving signal output terminal, a source of the eighth transistor is electrically connected to the reverse scan control signal terminal, and a drain of the eighth transistor is electrically connected to the pull-down output sub-unit; The second control signal receiving sub-unit includes a ninth transistor, a gate of the ninth transistor being electrically connected to the n+p-th stage first gate driving signal output terminal, a source of the ninth transistor being electrically connected to the forward scan control signal terminal, and a drain of the ninth transistor being electrically connected to the pull-down output sub-unit; The pull-down output subunit includes a tenth transistor, the gate of the tenth transistor is electrically connected to the first control signal receiving subunit and the second control signal receiving subunit, the source of the tenth transistor is electrically connected to the second reference signal terminal, and the drain of the tenth transistor is electrically connected to the n-th level pull-down output signal terminal.

7. A display panel, characterized in that: include: The array substrate row driving circuit according to any one of claims 4 to 6, wherein the array substrate row driving circuit is located in a non-display area of the display panel; Multiple scan lines, multiple scan lines are located in the display area of the display panel, the qth scan line is electrically connected to the qth first gate drive signal output terminal of the array substrate row drive circuit, and the qth scan line is also electrically connected to the q-1th pull-down output terminal of the array substrate row drive circuit, wherein q is an integer greater than or equal to 2.

8. The display panel according to claim 7, wherein: The head end of the qth scan line is electrically connected to the qth stage first gate driving signal output terminal, and the tail end of the qth scan line is electrically connected to the q-1th stage pull-down output terminal.

9. A display panel, characterized in that: include: two array substrate row driver circuits according to any one of claims 4 to 6, wherein a first array substrate row driver circuit is located in a first non-display area of the display panel, and a second array substrate row driver circuit is located in a second non-display area of the display panel, and the first non-display area and the second non-display area are located on opposite sides of a display area of the display panel; A plurality of scan lines, wherein the plurality of scan lines are located in the display area; Among them, the 2q-1th scan line is electrically connected to the qth first gate drive signal output terminal of the first array substrate row driving circuit, and the 2q-1th scan line is also electrically connected to the q-1th pull-down output terminal of the second array substrate row driving circuit, and the 2qth scan line is electrically connected to the qth first gate drive signal output terminal of the second array substrate row driving circuit, and the 2qth scan line is also electrically connected to the qth pull-down output terminal of the first array substrate row driving circuit, wherein q is an integer greater than or equal to 1.

10. The display panel according to claim 9, wherein: Along the extending direction of the scan line, the first non-display area and the second non-display area are located on opposite sides of the display area; The head end of the 2q-1th scan line is electrically connected to the qth level gate drive signal output terminal of the first array substrate row driving circuit, the tail end of the 2q-1th scan line is electrically connected to the q-1th level pull-down output terminal of the second array substrate row driving circuit, the head end of the 2qth scan line is electrically connected to the qth level gate drive signal output terminal of the second array substrate row driving circuit, and the tail end of the 2qth scan line is electrically connected to the qth level pull-down output terminal of the first array substrate row driving circuit.

11. The display panel according to claim 9 or 10, characterized in that: The first scan line is electrically connected to the first-level gate drive signal output terminal of the first array substrate row driving circuit. The first scan line is also electrically connected to the virtual output terminal, which is the zero-level pull-down output terminal of the second array substrate row driving circuit.

12. The display panel according to claim 9 or 10, characterized in that: In the final gate driving module electrically connected to the last scan line, the n+pth stage first gate driving signal output terminal electrically connected to the second pull-down control unit is the first reference signal terminal; The final gate driving module is the final gate driving unit of the first array substrate row driving circuit or the final gate driving unit of the second array substrate row driving circuit.

13. The array substrate row driving circuit according to any one of claims 1 to 3, characterized in that: The n-th stage gate driving module further includes a second pull-up unit and a second pull-down unit; The second pull-up unit is electrically connected to the third clock signal terminal, the first node, and the n-stage second gate driving signal output terminal of the n-stage gate driving module, and the second pull-up unit is configured to output the n-stage second gate driving signal to the n-stage second gate driving signal output terminal under the control of the third clock signal of the third clock signal terminal and the potential of the first node; The second pull-down unit is electrically connected to the second node, the second reference signal terminal and the n-th level second gate drive signal output terminal, and the second pull-down unit is used to output the reference low-level signal to the n-th level second gate drive signal output terminal based on the potential of the second node.

14. The array substrate row driving circuit according to claim 13, wherein: The second pull-up unit includes a fourteenth transistor, a gate of the fourteenth transistor is electrically connected to the first node, a source of the fourteenth transistor is electrically connected to the third clock signal terminal, and a drain of the fourteenth transistor is electrically connected to the n-th stage second gate drive signal output terminal; The second pull-down unit includes a fifteenth transistor, a gate of the fifteenth transistor is electrically connected to the second node, a source of the fifteenth transistor is electrically connected to the second reference signal terminal, and a drain of the fifteenth transistor is electrically connected to the n-th level second gate drive signal output terminal.

15. The array substrate row driving circuit according to claim 13, wherein: An end time point when the first pull-up unit receives the first clock signal as a high-level signal is earlier than or equal to a start time point when the second pull-up unit receives the third clock signal as a high-level signal.

16. The array substrate row driving circuit according to claim 13, wherein: A starting time point of the first clock signal received as a high-level signal by the first pull-up unit is earlier than a starting time point of the third clock signal received as a high-level signal by the second pull-up unit, and an ending time point of the first clock signal received as a high-level signal by the first pull-up unit is later than a starting time point of the third clock signal received as a high-level signal by the second pull-up unit.

17. A display panel, characterized in that: include: The array substrate row driving circuit according to any one of claims 13 to 16, wherein the array substrate row driving circuit is located in a non-display area of the display panel; a plurality of first scan lines, the plurality of first scan lines being located in a display area of the display panel, the plurality of first scan lines corresponding one-to-one to and electrically connected to the multi-stage first gate drive signal output terminals of the array substrate row drive circuit; A plurality of second scan lines are provided, the plurality of second scan lines are located in the display area, and the plurality of second scan lines correspond one-to-one to and are electrically connected to the multi-stage second gate drive signal output terminals of the array substrate row drive circuit.

18. The display panel according to claim 17, wherein: The first scan lines and the second scan lines are alternately located in the display area; The rth first scan line is electrically connected to the rth first gate drive signal output terminal of the array substrate row drive circuit, and the rth second scan line is electrically connected to the rth second gate drive signal output terminal, where r is an integer greater than or equal to 1.

19. The display panel according to claim 17, wherein: The display panel comprises two array substrate row driving circuits according to any one of claims 13 to 16, wherein the first array substrate row driving circuit is located in a first non-display area of the non-display area, and the second array substrate row driving circuit is located in a second non-display area of the non-display area, and the first non-display area and the second non-display area are located on opposite sides of the display area; The rth first scan line is electrically connected to the rth stage first gate driving signal output terminal of the first array substrate row driving circuit and the rth stage first gate driving signal output terminal of the second array substrate row driving circuit; The rth second scan line is electrically connected to the rth stage second gate driving signal output terminal of the first array substrate row driving circuit and the rth stage second gate driving signal output terminal of the second array substrate row driving circuit.

20. The display panel according to claim 19, wherein Along an extension direction of the first scan line, the first non-display area and the second non-display area are located on opposite sides of the display area; The rth first scan line has a leading end electrically connected to the rth stage first gate drive signal output terminal of the first array substrate row driver circuit, and the rth first scan line has a trailing end electrically connected to the rth stage first gate drive signal output terminal of the second array substrate row driver circuit; The head end of the rth second scan line is electrically connected to the rth second gate drive signal output terminal of the first array substrate row driving circuit, and the tail end of the rth second scan line is electrically connected to the rth second gate drive signal output terminal of the second array substrate row driving circuit.

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