Panel driving circuit, display device, and display driving method

Abstract

The application relates to a panel driving circuit, a display device and a display driving method. The circuit comprises a timing controller, which is used for transmitting at least one data pair and generating at least one control signal group, the control signal group comprising multiple control signals; at least one driving chip, the driving chip comprising a data processing unit, the data processing unit being electrically connected to the timing controller through at least three connection assemblies to receive at least one data pair transmitted by the connection assemblies; different connection assemblies are located at different positions of the driving chip, and each connection assembly comprises at least one data line used for transmitting at least one data pair and at least one control line used for transmitting at least one control signal, so as to control the transmission state of the at least three connection assemblies based on the multiple control signals. The application can reduce the driving cost and shorten the verification import time of the driving chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a panel driving circuit, a display device and a display driving method. BACKGROUND

[0002] Chip On Glass (COG) is a packaging technology of encapsulating a driving chip on a glass. In order to meet different frame requirements of a Narrow Board (NB) display product, there are two wiring modes for data pairs of a COG driving chip: one is to wire from the middle position of the driving chip opposite to a receiving circuit Rx, and at this time the number of the receiving circuit Rx is one; the other is to wire from both sides of the driving chip, and at this time one receiving circuit Rx is arranged on each side of the driving chip, that is, the number of the receiving circuit Rx is two. As a result, even if the technical specifications of the display panel are the same, in order to adapt to different narrow frame requirements or achieve other development purposes, at least two different driving chips need to be developed, thereby increasing the driving cost and prolonging the driving chip verification import time. SUMMARY

[0003] Therefore, the present application provides a panel driving circuit, a display device and a display driving method, which can reduce the number of receiving circuits and clock data recovery circuits arranged in the driving chip, and adjust the connection components in the enabled state according to different product requirements by using the control lines, thereby reducing the driving cost, shortening the driving chip verification import time, and improving the development efficiency of the panel driving.

[0004] According to an aspect of the present application, a panel driving circuit is provided, which is electrically connected to a display panel, and includes: a timing controller, configured to transmit at least one data pair and generate at least one control signal group, the control signal group including a plurality of control signals; and at least one driving chip, including a data processing unit, which is electrically connected to the timing controller through at least three connection components to receive at least one data pair transmitted by the connection components; wherein different connection components are located at different positions of the driving chip, and each connection component includes at least one data line for transmitting at least one data pair and at least one control line for transmitting at least one control signal, so as to control the transmission state of at least three connection components based on a plurality of control signals.

[0005] According to another aspect of the present application, a display device is provided, which includes a display panel and the panel driving circuit.

[0006] According to another aspect of the present application, a display driving method is provided, which is applied to the panel driving circuit, and includes: judging a working mode of the timing controller according to a target frame of the display panel, the working mode including a first working mode and a second working mode; in the first working mode, controlling at least one control line in at least three connection components to be in an enabled state; and in the second working mode, controlling at least two control lines in at least three connection components to be in an enabled state, wherein the control line in the enabled state in the first working mode is different from the control line in the enabled state in the second working mode.

[0007] By connecting the receiving circuit to the timing controller through at least three connection components, and locating different connection components at different positions of the driving chip, and then controlling the transmission state of the at least three connection components based on multiple control signals, according to aspects of the present application, the number of receiving circuits and clock data recovery circuits arranged inside the driving chip can be reduced, and the connection components in the enabled state can be adjusted according to different product requirements by using the control lines, which reduces the driving cost and shortens the driving chip verification import time, thereby improving the development efficiency of the panel driving. BRIEF DESCRIPTION OF DRAWINGS

[0008] The technical solutions and other beneficial effects of the present application will be apparent from the following detailed description of the specific embodiments of the present application, combined with the accompanying drawings.

[0009] Figure 1 A schematic diagram showing a first COG wiring mode of the related art.

[0010] Figure 2 A schematic diagram showing a second COG wiring mode of the related art.

[0011] Figure 3 A schematic diagram showing a panel driving architecture of an embodiment of the present application.

[0012] Figure 4 An internal block diagram of a driving chip of an embodiment of the present application.

[0013] Figure 5 A schematic diagram of a driving chip of an embodiment of the present application.

[0014] Figure 6 A flowchart of a display driving method of an embodiment of the present application. DETAILED DESCRIPTION

[0015] With reference to the drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0016] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0017] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection or can communicate with each other; it can be direct connection, or indirect connection through intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0018] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to the same reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not in itself indicate a relationship between the various embodiments and / or settings discussed. In addition, the present application provides various specific examples of processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials. In some examples, methods, means, elements and circuits well known to those skilled in the art are not described in detail, in order to highlight the main idea of the present application.

[0019] Figure 1 A schematic diagram of the first COG routing method in the related technology is shown.

[0020] like Figure 1 As shown, from a top-down view, the driver chip has multiple input pads and multiple output pads on both sides of its width. Along the length of the driver chip, the input pads and output pads are arranged along its length.

[0021] The driver chip includes a data processing unit comprising a receiving circuit Rx and a clock and data recovery (CDR) circuit electrically connected to the receiving circuit Rx. The signals received by the receiving circuit Rx can be transferred to the clock and data recovery circuit CDR for further processing. The signals received by the receiving circuit Rx are Rx1N, Rx1P, Rx0N, and Rx0P, totaling two data pairs: Rx1N and Rx1P form one data pair, and Rx0N and Rx0P form the other data pair.

[0022] Figure 1 The two data pairs are transmitted separately through four input pads, all of which are located in the middle of the data processing unit. Figure 1 Directly below the data processing unit.

[0023] Figure 2 A schematic diagram of a second COG routing method for related technologies is shown.

[0024] like Figure 2 As shown, from a top-down view, the driver chip has multiple input pads and multiple output pads on both sides of its width. Along the length of the driver chip, the input pads and output pads are arranged along its length.

[0025] and Figure 1 The difference is, Figure 2 The driver chip has two data processing units on both sides. Each data processing unit includes a receiving circuit Rx and a clock data recovery circuit CDR corresponding to the receiving circuit Rx. The receiving circuit Rx is electrically connected to the corresponding clock data recovery circuit CDR.

[0026] The data processing unit on the left receives signals Rx0P-L, Rx0N-L, Rx1N-L, Rx1P-L, and Rx-L-EN, and the data processing unit on the right receives signals Rx0P-R, Rx0N-R, Rx1N-R, Rx1P-R, and Rx-R-EN. The receiving circuit in the data processing unit on the left is enabled by Rx-L-EN, and the receiving circuit in the data processing unit on the right is enabled by Rx-R-EN. Both the data processing unit on the left and the data processing unit on the right receive two data pairs.

[0027] Figure 2 The two data pairs on the left and a control signal Rx-L-EN are transmitted by five input pads, and the two data pairs on the right and a control signal Rx-R-EN are transmitted by five input pads. The five input pads on the left and the five input pads on the right are located on the two sides of the driving chip, for example, the lower left corner and the lower right corner in Figure 2

[0028] In practical applications, Figure 1 and Figure 2 These two layouts will affect the demand for narrow frame of display products. Therefore, even if the technical specifications of the display panel are the same, in order to adapt to different narrow frame requirements or achieve other development purposes, at least two different driving chips need to be developed, thereby increasing the driving cost and prolonging the driving chip verification import time.

[0029] The present application provides a panel driving circuit, which is electrically connected to a display panel, and includes a timing controller, a driving chip, and a connection assembly. The timing controller is used for transmitting at least one data pair and generating at least one control signal group, and the control signal group includes a plurality of control signals. The driving chip includes a data processing unit, which is electrically connected to the timing controller through at least three connection assemblies to receive at least one data pair transmitted by the connection assembly. Different connection assemblies are located at different positions of the driving chip, and each connection assembly includes at least one data line for transmitting at least one data pair and at least one control line for transmitting at least one control signal, so as to control the transmission state of at least three connection assemblies based on a plurality of control signals.

[0030] ​By connecting the receiving circuit to the timing controller through at least three connection components, and locating different connection components at different positions of the driving chip, and then controlling the transmission state of the at least three connection components based on multiple control signals, the embodiment of the application can reduce the number of receiving circuits and clock data recovery circuits arranged inside the driving chip, and adjust the connection components in the enabled state according to different product requirements by using the control lines, which reduces the driving cost and shortens the driving chip verification import time, thereby improving the development efficiency of the panel driving.

[0031] Figure 3 A schematic diagram of a panel driving architecture of an embodiment of the application is shown. As shown in Figure 3 The panel driving circuit of the embodiment of the application is electrically connected to a display panel 1. The following takes a liquid crystal display panel as an example to illustrate the display panel 1, but those skilled in the art can understand that the type of the display panel is not limited in the application.

[0032] The display panel 1 can include a plurality of pixels arranged in rows and columns, each of the pixels is electrically connected to a data line, and each row of the pixels is electrically connected to a scan line. The data line can transmit positive polarity data or negative polarity data. Optionally, the driving mode of the display panel can be a column inversion mode.

[0033] In an embodiment, the driving chip of the application can be a first driving chip 21 or a second driving chip 22. The first driving chip 21 can be a source driver, and the second driving chip 22 can be a gate driver. The panel driving circuit can include the first driving chip 21 and the second driving chip 22.

[0034] In an embodiment, the first driving chip 21 and the second driving chip 22 are packaged on the glass substrate of the display panel by a chip on glass COG method. Optionally, the timing controller can also be packaged on the glass substrate of the display panel by a chip on glass COG method, which can further save space and process. The COG method directly packages the chip on the glass through anisotropic conductive adhesive, so as to realize the interconnection and packaging of the chip conductive bump and the transparent conductive pad on the glass. Optionally, a plurality of pixels are arranged on the glass substrate of the display panel, and the first driving chip 21, the second driving chip 22 and the timing controller can be arranged on one side of the plurality of pixels.

[0035] In an embodiment, the timing controller is configured to transmit at least one data pair and generate at least one control signal group, the control signal group comprising a plurality of control signals. Each of the data pair can comprise positive polarity data and negative polarity data. The positive polarity data and the negative polarity data can be for the same pixel, but at different time instants for driving the pixel. The number of the data pair can be determined according to the number of pixels, or in other words, the resolution of the display panel. Optionally, each control signal group comprises three control signals. It can be understood that the number of the data pair is not limited in the present application.

[0036] In an embodiment, the driving chip comprises a data processing unit 201, the data processing unit 201 comprising a receiving circuit 211 and a clock data recovery circuit 212 electrically connected to the receiving circuit 211, the receiving circuit 211 being electrically connected to the timing controller through at least three connection components, and the clock data recovery circuit 212 being configured to further process at least one data pair received by the receiving circuit 211.

[0037] In the present application, the timing controller can receive original display data from the mainboard, which does not conform to the data format required by the first driving chip 21 and the second driving chip 22. Therefore, the original display data needs to be processed by the timing controller to generate display data conforming to the data format required by the first driving chip 21 and the second driving chip 22, and then the processed display data is transmitted to the first driving chip 21 and the second driving chip 22. The first driving chip 21 outputs the positive polarity data and the negative polarity data, and the second driving chip 22 outputs the scanning signal. In some embodiments, the scanning signal can also be regarded as a kind of data form.

[0038] After the first driving chip 21 receives the display data processed by the timing controller, the display data needs to be further processed by the clock data recovery circuit 212 to generate the required positive polarity data and negative polarity data. The clock data recovery circuit 212 can recover the clock signal and data information from the serial data stream. Its working principle is to recover the normal clock and data information by sampling, clock recovery, signal demodulation and other processing of the serial data signal. In high-speed serial communication, due to the attenuation of the transmission signal and other factors, the clock signal and the data signal are severely disturbed and deformed. The clock data recovery circuit 212 extracts and recovers the clock through the internal circuit design and algorithm of the clock data recovery circuit 212, and samples and demodulates the data at the correct time, so as to recover the original clock and data information. The second driving chip 22 also has similar processing inside as the first driving chip 21.

[0039] In one embodiment, at least three connection components include a first connection component, a second connection component, and a third connection component. The receiving circuit 211 is electrically connected to the timing controller via the three connection components: the first connection component, the second connection component, and the third connection component.

[0040] The first, second, and third connecting components have the same number of data lines and the same number of control lines. Optionally, each of the first, second, and third connecting components has only one control line, meaning each connecting component has one control line.

[0041] by Figure 3 For example, for the first driver chip 21, the first connection component may include a first control line L1, the second connection component may include a second control line L2, and the third connection component may include a third control line L3; for the second driver chip 22, the first connection component may include a fourth control line L4, the second connection component may include a fifth control line L5, and the third connection component may include a sixth control line L6. The first driver chip 21 can also be electrically connected to the display panel via a trace L7, and the second driver chip 22 can also be electrically connected to the display panel via a trace L8.

[0042] Figure 4 An internal block diagram of the driver chip according to an embodiment of this application is shown. Figure 4 As shown, taking the first driver chip 21 as an example, the first driver chip 21 may include a data processing unit 210, and the data processing unit 210 may include a receiving circuit 211 and a clock data recovery circuit 212 electrically connected to the receiving circuit 211. It should be noted that... Figure 4 The data processing unit 210 in the example is exemplary. In practical applications, the driver chip may directly include a receiving circuit 211 and a clock data recovery circuit 212, without a separate data processing unit 210. In other words, the receiving circuit 211 and the clock data recovery circuit 212 may coexist in the data processing unit 210 within the driver chip, or they may be set separately within the driver chip.

[0043] In one embodiment, such as Figure 4As shown, the timing controller comprises a sending circuit 31 and a processor 32. The sending circuit 31 is configured to send at least one data pair to at least one of the drive chips and generate at least one control signal group. The processor 32 is electrically connected to the sending circuit 31, and the processor 32 is configured to adjust a plurality of control signals according to a preset working mode, so as to control the transmission state of at least three connection assemblies based on the plurality of control signals. The sending circuit 31 can be arranged correspondingly with the receiving circuit 211 of the first drive chip 21.

[0044] In an embodiment, the second connection assembly is located on the middle line of the drive chip in the length direction, and the first connection assembly and the third connection assembly are located on both sides of the second connection assembly. Figure 4 In an embodiment, the second control line L2 of the second connection assembly is located on the middle line of the drive chip in the length direction, and the first control line L1 of the first connection assembly and the third control line L3 of the third connection assembly are located on both sides of the second control line L2 of the second connection assembly.

[0045] In an embodiment, the control signal group comprises a first control signal, a second control signal and a third control signal, the control line of the first connection assembly is configured to transmit the first control signal, the control line of the second connection assembly is configured to transmit the second control signal, and the control line of the third connection assembly is configured to transmit the third control signal. Figure 4 In an embodiment, the first control line L1 transmits the first control signal, the second control line L2 transmits the second control signal, and the third control line L3 transmits the third control signal.

[0046] In an embodiment, the second control signal is opposite in voltage level to the first control signal and the third control signal, and the first control signal and the third control signal are the same in voltage level. Optionally, when the second control signal is at a high voltage level, the first control signal and the third control signal are both at a low voltage level; and when the second control signal is at a low voltage level, the first control signal and the third control signal are both at a high voltage level.

[0047] Figure 5 A schematic diagram of the drive chip according to an embodiment of the present application is shown.

[0048] In an embodiment, the drive chip further comprises a plurality of input pads, and the plurality of input pads are arranged in a first direction. The first direction can be the length direction of the drive chip, i.e. the horizontal direction in the embodiment. Figure 5 The drive chip can further comprise a plurality of output pads. The plurality of input pads are arranged in rows, and the plurality of output pads are also arranged in rows. The plurality of input pads and the plurality of output pads are oppositely arranged at both ends of the drive chip in the width direction of the drive chip.

[0049] The connection component includes at least three input pads, two of which are used to transmit a data pair and the other input pad is used to transmit a control signal.

[0050] by Figure 5 For example, the signals transmitted by the first connection component on the left are Rx0P-L, Rx0N-L, Rx1N-L, Rx1P-L, and Rx-L-EN; the signals transmitted by the second connection component in the middle are Rx1N, Rx1P, Rx0N, Rx0P, and Rx-C-EN; and the signals transmitted by the third connection component on the right are Rx0P-R, Rx0N-R, Rx1N-R, Rx1P-R, and Rx-R-EN. Among these, Rx0P-L, Rx0N-L, Rx1N-L, and Rx1P-L are two data pairs, and Rx-L-EN is the first control signal; Rx1N, Rx1P, Rx0N, and Rx0P are two data pairs, and Rx-C-EN is the second control signal; Rx0P-R, Rx0N-R, Rx1N-R, and Rx1P-R are two data pairs, and Rx-R-EN is the third control signal.

[0051] In one embodiment, in the driver chip, for the same connection component, multiple data lines are arranged adjacently, and the control line is arranged on one side of the multiple adjacent data lines. For example... Figure 5 As shown, the signals transmitted by the first connection component on the left are Rx0P-L, Rx0N-L, Rx1N-L, Rx1P-L, and Rx-L-EN. Rx0P-L is the positive polarity data of the first data pair, Rx0N-L is the negative polarity data of the first data pair, Rx1N-L is the negative polarity data of the second data pair, Rx1P-L is the positive polarity data of the second data pair, and Rx-L-EN is the first control signal transmitted by the control line. The control line can be configured according to... Figure 5 The signals shown are arranged in sequence. In the first connection component, the first control line can be placed on the far left, while the other four data lines can be placed adjacent to each other.

[0052] This application also provides a display device, which includes a display panel and the panel driving circuit.

[0053] Figure 6 A flowchart illustrating a display driving method according to an embodiment of this application is provided. Figure 6 As shown, the display driving method is applied to the panel driving circuit, and the processor can be used to execute the display driving method, which includes:

[0054] Step S1: determining a working mode of the timing controller according to a target frame of the display panel, the working mode including a first working mode and a second working mode;

[0055] The target frame of the display panel can be a whole frame preset by the display panel and the panel driving circuit. According to the target frame, it can be determined in advance that which working mode is most suitable in actual application, that is, the target frame can be matched with the working mode of the processor. In actual application, the working mode of the processor in the timing controller can also be determined according to other conditions, which is not limited in the application.

[0056] Step S2: in the first working mode, at least one control line in at least three connection assemblies is in an enabled state.

[0057] Optionally, in the first working mode, the second control line of the second connection assembly is in the enabled state. At this time, the sending circuit can transmit data to the receiving circuit through the second connection assembly, but cannot transmit data through the first connection assembly and the third connection assembly.

[0058] Step S3: in the second working mode, at least two control lines in at least three connection assemblies are in the enabled state, wherein the control line in the enabled state in the first working mode is different from the control line in the enabled state in the second working mode.

[0059] Optionally, in the second working mode, the first control line of the first connection assembly and the third control line of the third connection assembly are in the enabled state. At this time, the sending circuit can transmit data to the receiving circuit through the first connection assembly and the third connection assembly, but cannot transmit data through the second connection assembly.

[0060] In summary, by electrically connecting the receiving circuit to the timing controller through at least three connection assemblies, and locating different connection assemblies at different positions of the driving chip, and then controlling the transmission state of at least three connection assemblies based on multiple control signals, the application can be compatible with multiple working modes, and the specifications of the panel converge. It is not necessary to redesign the driving circuit for different panel specifications, which reduces the number of receiving circuits and clock data recovery circuits, and also reduces the number of driving chips required in the whole, at least saves 50% of the signal processing circuit, which reduces the driving cost and shortens the driving chip verification import time, thereby improving the development efficiency of panel driving.

[0061] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0062] The panel driving circuit, the display device and the display driving method provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above embodiment descriptions are only used to help understand the technical solutions of the present application and the core ideas thereof. It should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently, and the modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A panel driving circuit, characterized in that, The panel driving circuit is electrically connected to the display panel, and the panel driving circuit includes: A timing controller is used to transmit at least one data pair and generate at least one control signal group, the control signal group including a plurality of control signals; At least one driver chip, the driver chip including a data processing unit, the data processing unit being electrically connected to the timing controller via at least three connection components to receive at least one data pair transmitted by the connection components; The different connection components are located at different positions of the driver chip, and each connection component includes at least one data line for transmitting at least one data pair and at least one control line for transmitting at least one control signal, so as to control the transmission state of at least three connection components based on multiple control signals. The driver chip also includes: Multiple input pads, wherein the multiple input pads are arranged along a first direction; The connection component includes at least three input pads, wherein two of the input pads are used to transmit a data pair and the other input pad is used to transmit a control signal; The panel driving circuit is used to implement the display driving method, which includes: The operating mode of the timing controller is determined based on the target border of the display panel, and the operating mode includes a first operating mode and a second operating mode. In the first operating mode, at least one control line of at least three of the connection components is enabled. In the second operating mode, at least two control lines of at least three of the connection components are enabled, wherein the control lines enabled in the first operating mode are different from the control lines enabled in the second operating mode.

2. The panel driving circuit according to claim 1, characterized in that, The at least three connecting components include a first connecting component, a second connecting component, and a third connecting component, wherein the first connecting component and the third connecting component are located on opposite sides of the second connecting component.

3. The panel driving circuit according to claim 2, characterized in that, The first connection component, the second connection component, and the third connection component have the same number of data lines, and the first connection component, the second connection component, and the third connection component have the same number of control lines.

4. The panel driving circuit according to claim 2, characterized in that, The control signal group includes a first control signal, a second control signal, and a third control signal. The control line of the first connecting component is used to transmit the first control signal, the control line of the second connecting component is used to transmit the second control signal, and the control line of the third connecting component is used to transmit the third control signal.

5. The panel driving circuit according to claim 1, characterized in that, In the driver chip, for the same connection component, multiple data lines are arranged adjacently, and the control line is arranged on one side of the multiple adjacent data lines.

6. The panel driving circuit according to claim 1, characterized in that, The driving chip is a first driving chip or a second driving chip, and the panel driving circuit includes: The first driver chip is a source driver. The second driving chip is a gate driver; The first driver chip and the second driver chip are packaged on the glass substrate of the display panel.

7. The panel driving circuit according to claim 6, characterized in that, The timing controller includes: A transmitting circuit is configured to transmit at least one data pair to at least one of the driver chips and generate at least one group of control signals. A processor, electrically connected to the transmitting circuit, is configured to adjust a plurality of control signals according to a preset operating mode, so as to control the transmission status of at least three of the connection components based on the plurality of control signals.

8. A display device, characterized in that, The display device includes a display panel and a panel driving circuit as described in any one of claims 1-7.

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