Composite driving circuit, display panel and display device

Abstract

A composite drive circuit, a display panel (PNL) and a display device, the display panel (PNL) comprising a plurality of composite drive circuits (XDC) and comprising a light emitting element (DD) and a photodetector (OPD) driven by the composite drive circuit (XDC). The display panel (PNL) comprises a plurality of row partitions (HHA) arranged in sequence along a column direction (DV), and each row partition (HHA) is provided with an enable signal line group (EMLS) for loading the same enable signal (EM). The composite drive circuit (XDC) and the photodetector (OPD) driven by the composite drive circuit (XDC) are located in different row partitions (HHA), respectively.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a composite driving circuit, a display panel and a display device. BACKGROUND

[0002] In the optical fingerprint identification display panel, pixel driving circuit and fingerprint identification circuit need to be respectively arranged, which makes the driving circuit on the display panel more complex.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a composite driving circuit, a display panel and a display device, which simplify the driving circuit on the display panel.

[0005] According to one aspect of the present disclosure, a display panel is provided, comprising a plurality of composite driving circuits and light emitting elements and photodetectors driven by the composite driving circuits; the composite driving circuit comprises a first pixel driving circuit for driving the light emitting element and an optical detection driving circuit for driving the photodetector;

[0006] The first pixel driving circuit comprises a driving transistor and a first light emitting control transistor; the driving transistor can output a driving current for driving the light emitting element under the control of the voltage on the gate of the driving transistor; the driving transistor is electrically connected to the pixel electrode of the light emitting element through the first light emitting control transistor;

[0007] The optical detection driving circuit comprises an output control transistor; the device electrode of the photodetector is electrically connected to the sensing signal line through the output control transistor;

[0008] The display panel comprises a plurality of row partitions arranged in sequence along the column direction, and each row partition is provided with an enable signal line group for loading the same enable signal;

[0009] At least one of the row partitions is provided with the composite driving circuit, the gate of the output control transistor of the composite driving circuit and the gate of the first light emitting control transistor are electrically connected to the enable signal line group; one of the first light emitting control transistor and the output control transistor is turned on in response to the high level signal of the enable signal, and the other is turned on in response to the low level signal of the enable signal; the composite driving circuit and the photodetector driven by the composite driving circuit are located in different row partitions respectively.

[0010] According to an embodiment of the present disclosure, the composite drive circuit and the photodetector driven by the composite drive circuit are located in two adjacent row partitions, respectively.

[0011] According to an embodiment of the present disclosure, the drive transistor and the first light-emitting control transistor are P-type transistors, and the output control transistor is a metal-oxide-semiconductor transistor.

[0012] According to an embodiment of the present disclosure, the first pixel drive circuit further comprises a storage capacitor and a data write transistor, the gate of the drive transistor is electrically connected to the storage capacitor, and the drive transistor is configured to output a drive current for driving the light-emitting element under the control of a voltage on the gate of the drive transistor; and the data write transistor is configured to write drive data into the storage capacitor.

[0013] According to an embodiment of the present disclosure, the first pixel drive circuit further comprises a capacitor reset transistor, a threshold compensation transistor, a second light-emitting control transistor, and an electrode reset transistor, wherein,

[0014] the source of the capacitor reset transistor is configured to load a first initial voltage, the drain of the capacitor reset transistor is electrically connected to a first node, and the gate of the capacitor reset transistor is configured to load a first reset signal;

[0015] the source of the threshold compensation transistor is electrically connected to a third node, the drain of the threshold compensation transistor is electrically connected to the first node, and the gate of the threshold compensation transistor is configured to load a scan signal;

[0016] the source of the drive transistor is electrically connected to a second node, the drain of the drive transistor is electrically connected to the third node, and the gate of the drive transistor is electrically connected to the first node;

[0017] the source of the data write transistor is configured to load drive data, the drain of the data write transistor is electrically connected to the second node, and the gate of the data write transistor is configured to load a scan signal;

[0018] the source of the second light-emitting control transistor is configured to load a drive power supply, the drain of the second light-emitting control transistor is electrically connected to the second node, and the gate of the second light-emitting control transistor is configured to load the same enable signal as the gate of the first light-emitting control transistor;

[0019] the source of the first light-emitting control transistor is electrically connected to the third node, and the drain of the first light-emitting control transistor is electrically connected to a pixel electrode of the light-emitting element.

[0020] The source of the electrode reset transistor is used for loading a second initial voltage, the drain of the electrode reset transistor is electrically connected with the drain of the first light emitting control transistor, and the gate of the electrode reset transistor is used for loading a second reset signal.

[0021] According to an embodiment of the present disclosure, the display panel comprises a substrate, a driving layer and a device layer which are sequentially stacked;

[0022] The first pixel driving circuit and the optical detection driving circuit are located in the driving layer, and the light emitting element and the photodetector are located in the device layer.

[0023] According to an embodiment of the present disclosure, in the row partition provided with the composite driving circuit, the group of enable signal lines comprises at least one first enable signal line and at least one second enable signal line;

[0024] The gate of each first light emitting control transistor in the row partition is electrically connected with the first enable signal line, and the gate of the output control transistor is electrically connected with the second enable signal line.

[0025] According to an embodiment of the present disclosure, the display panel comprises a display area and a peripheral area surrounding the display area; the composite driving circuit is arranged in the display area;

[0026] The first enable signal line and the second enable signal line pass through the display area along the row direction, and the end portions of the first enable signal line and the second enable signal line of the same group of enable signal lines are electrically connected in the peripheral area.

[0027] According to an embodiment of the present disclosure, the device layer comprises a pixel electrode layer, a pixel definition layer, a composite functional material layer and a common electrode layer COML which are sequentially stacked on the side of the driving layer away from the substrate; the composite functional material layer comprises a photoelectric conversion material layer and an electroluminescent material layer.

[0028] The pixel electrode layer comprises a pixel electrode of the light emitting element, a device electrode of the photodetector and a device trace;

[0029] The device electrode of the photodetector is electrically connected with the optical detection driving circuit driving the photodetector through the device trace.

[0030] According to an embodiment of the present disclosure, in the composite driving circuit, the wiring area of the optical detection driving circuit is located within the wiring area of the first pixel driving circuit.

[0031] According to an embodiment of the present disclosure, the display panel further comprises a second pixel driving circuit and a light emitting element driven by the second pixel driving circuit.

[0032] According to an embodiment of the present disclosure, the composite driving circuit and the second pixel driving circuit are arranged into a plurality of driving circuit rows; and one or more driving circuit rows are included in any one of the row partitions.

[0033] According to an embodiment of the present disclosure, in any one of the row partitions, at most one of the driving circuit rows has the composite driving circuit.

[0034] The composite driving circuit and the second pixel driving circuit are arranged into a plurality of driving circuit columns.

[0035] Each of the optical detection driving circuits in the same driving circuit column is electrically connected to the same sensing signal line.

[0036] According to an embodiment of the present disclosure, the composite driving circuit and the second pixel driving circuit are arranged into a plurality of driving circuit columns; and a plurality of composite driving circuits in at least one of the driving circuit columns are located in the same row partition.

[0037] The plurality of composite driving circuits in the same row partition and in the same driving circuit column are respectively connected to different sensing signal lines.

[0038] According to an embodiment of the present disclosure, the composite driving circuit and the second pixel driving circuit are arranged into a plurality of driving circuit columns.

[0039] The display panel includes a driving power supply wire corresponding to each of the driving circuit columns; and each of the first pixel driving circuit and the second pixel driving circuit in the driving circuit column is electrically connected to the corresponding driving power supply wire.

[0040] The display panel is further provided with a power supply arrangement wire arranged in the same layer as the enable signal line group, the power supply arrangement wire extending in the row direction and being electrically connected to each of the driving power supply wires.

[0041] According to an embodiment of the present disclosure, the first pixel driving circuit and the second pixel driving circuit are the same.

[0042] According to a second aspect of the present disclosure, a display device is provided, including the display panel described above.

[0043] According to a third aspect of the present disclosure, a composite driving circuit is provided, including a first pixel driving circuit for driving a light emitting element and an optical detection driving circuit for driving a photodetector.

[0044] The first pixel driving circuit comprises a driving transistor and a first light-emitting control transistor; the driving transistor is capable of outputting a driving current for driving the light-emitting element under the control of a voltage on the gate of the driving transistor; the driving transistor is electrically connected to the pixel electrode of the light-emitting element through the first light-emitting control transistor.

[0045] The optical detection driving circuit comprises an output control transistor; the device electrode of the photodetector is electrically connected to the output end of the optical detection driving circuit through the output control transistor.

[0046] The gate of the first light-emitting control transistor and the gate of the output control transistor are used to load the same enable signal; one of the first light-emitting control transistor and the output control transistor is turned on in response to a high-level signal of the enable signal, and the other is turned on in response to a low-level signal of the enable signal.

[0047] According to an embodiment of the present disclosure, the driving transistor and the first light-emitting control transistor are P-type transistors, and the output control transistor is a metal oxide semiconductor transistor.

[0048] According to an embodiment of the present disclosure, the first pixel driving circuit further comprises a storage capacitor and a data writing transistor; the gate of the driving transistor is electrically connected to the storage capacitor, and is used to output a driving current for driving the light-emitting element under the control of a voltage on the gate of the driving transistor; the data writing transistor is configured to be capable of writing driving data into the storage capacitor.

[0049] According to an embodiment of the present disclosure, the first pixel driving circuit further comprises a capacitor reset transistor, a threshold compensation transistor, a second light-emitting control transistor and an electrode reset transistor, wherein,

[0050] The source of the capacitor reset transistor is used to load a first initial voltage; the drain of the capacitor reset transistor is electrically connected to a first node; and the gate of the capacitor reset transistor is used to load a first reset signal.

[0051] The source of the threshold compensation transistor is electrically connected to a third node; the drain of the threshold compensation transistor is electrically connected to the first node; and the gate of the threshold compensation transistor is used to load a scanning signal.

[0052] The source of the driving transistor is electrically connected to a second node; the drain of the driving transistor is electrically connected to the third node; and the gate of the driving transistor is electrically connected to the first node.

[0053] The source of the data writing transistor is used for loading driving data, the drain of the data writing transistor is electrically connected with the second node, and the gate of the data writing transistor is used for loading a scanning signal.

[0054] The source of the second light emitting control transistor is used for loading a driving power supply, the drain of the second light emitting control transistor is electrically connected with the second node, and the gate of the second light emitting control transistor is used for loading the same enable signal as the gate of the first light emitting control transistor.

[0055] The source of the first light emitting control transistor is electrically connected with the third node, and the drain of the first light emitting control transistor is electrically connected with the pixel electrode of the light emitting element.

[0056] The source of the electrode reset transistor is used for loading a second initial voltage, the drain of the electrode reset transistor is electrically connected with the drain of the first light emitting control transistor, and the gate of the electrode reset transistor is used for loading a second reset signal.

[0057] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0058] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. It is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those of ordinary skill in the art without creative labor based on these drawings.

[0059] Figure 1 For an embodiment of the present disclosure, a schematic diagram of the distribution of light emitting elements and photodetectors on a display panel.

[0060] Figure 2 For an embodiment of the present disclosure, a schematic diagram of the distribution of light emitting elements and photodetectors on a display panel.

[0061] Figure 3 For an embodiment of the present disclosure, a schematic diagram of the structure of a composite driving circuit.

[0062] Figure 4 For an embodiment of the present disclosure, a schematic diagram of the structure of a composite driving circuit.

[0063] Figure 5 For an embodiment of the present disclosure, a schematic diagram of the distribution of driving circuits of a driving layer.

[0064] Figure 6For an embodiment of the present disclosure, a schematic diagram of distribution of the driving circuit of the driving layer.

[0065] Figure 7 For an embodiment of the present disclosure, a schematic diagram of distribution of the driving circuit of the driving layer.

[0066] Figure 8 For an embodiment of the present disclosure, a schematic diagram of distribution of the driving circuit of the driving layer.

[0067] Figure 9 For an embodiment of the present disclosure, a schematic diagram of distribution of the driving circuit, the light emitting element, and the photodetector.

[0068] Figure 10 For an embodiment of the present disclosure, a schematic diagram of distribution of the driving circuit, the light emitting element, and the photodetector.

[0069] Figure 11 For an embodiment of the present disclosure, a timing diagram of the enable signal.

[0070] Figure 12 For an embodiment of the present disclosure, a schematic diagram of structure of the display panel.

[0071] Figure 13 For an embodiment of the present disclosure, a schematic diagram of structure of the low-temperature polysilicon semiconductor layer.

[0072] Figure 14 For an embodiment of the present disclosure, a schematic diagram of structure of the first gate layer.

[0073] Figure 15 For an embodiment of the present disclosure, a schematic diagram of structure of the second gate layer.

[0074] Figure 16 For a first example of the present disclosure, a schematic diagram of structure of the third gate layer.

[0075] Figure 17 For a second example of the present disclosure, a schematic diagram of structure of the third gate layer.

[0076] Figure 18 For a third example of the present disclosure, a schematic diagram of structure of the third gate layer.

[0077] Figure 19 For a first example of the present disclosure, a schematic diagram of structure of the first source-drain metal layer.

[0078] Figure 20 For a second example of the present disclosure, a schematic diagram of structure of the first source-drain metal layer.

[0079] Figure 21 For a third example of the present disclosure, a schematic diagram of structure of the first source-drain metal layer.

[0080] Figure 22 Structure diagram of the second source-drain metal layer in the first and second examples of the present disclosure.

[0081] Figure 23 Structure diagram of the second source-drain metal layer in the third example of the present disclosure.

[0082] Figure 24 Structure diagram of the pixel electrode layer in the first and second examples of the present disclosure.

[0083] Figure 25 Structure diagram of the pixel electrode layer in the third example of the present disclosure. DETAILED DESCRIPTION

[0084] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations may, however, be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example implementations to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and description of the same elements will be omitted from description of subsequent figures. In addition, the drawings are only schematic and are non-limiting.

[0085] Although relative terms such as "upper", "lower", etc. are used herein to describe one component's relationship to another component of the icon, these terms are used herein for convenience only and are not necessarily limiting. It will be further understood that, when an icon is turned over, such that the upper portion is now a lower portion, and vice versa, a component described as being "on" another component of the icon can be repositioned to be "on" the other component of the icon. When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure or that the structure is "directly" on the other structure or that the structure is "indirectly" on the other structure via another structure.

[0086] The terms "one", "a", "an", "the", and "at least one" are used to mean that "one or more" of something is present; the terms "comprising", "having", and "including" are used to mean "including, but not limited to"; and the term "or" is used to mean "and / or" both. The term "another" is used to mean "at least a second" or "at least a third". The term "another" is used to mean "at least a second" or "at least a third". The term "first", "second", and "third" are used to mean "first", "second", and "third" and are not used in any other context, such as "the first X and the second X", which would mean at least two Xs.

[0087] A transistor refers to an element including at least a gate, a drain, and a source. A transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. The channel region refers to a region through which current mainly flows. In the case of using a transistor with opposite polarity, or in the case of a change in the direction of current in circuit operation, the functions of the "source" and the "drain" are sometimes interchanged. Therefore, in this specification, the "source" and the "drain" can be interchanged with each other, and refer to opposite two terminals (terminals other than the gate) of a transistor, respectively, to distinguish the two terminals in terms of nomenclature, and not to limit the input terminal or the output terminal of the transistor or the like having a specific current flow direction.

[0088] In the embodiment of the present disclosure, the structure layer A is formed on the side of the structure layer B away from the substrate, which can be understood as that the structure layer A is formed on the side of the structure layer B away from the substrate. When the structure layer B is a patterned structure, part of the structure of the structure layer A can also be at the same physical height as the structure layer B or lower than the physical height of the structure layer B, wherein the substrate is the height reference.

[0089] The present disclosure provides a display panel PNL and a display device using the display panel PNL. Referring to Figure 1 , Figure 2 and Figure 3 , the display panel PNL includes a display area AA and a peripheral area BB surrounding the display area AA. In the display area AA, the display panel PNL is provided with light emitting elements DD and a pixel driving circuit PDC (not shown in Figure 1 and Figure 2 ) for driving the light emitting elements DD. In at least part of the display area AA, the display panel PNL is further provided with a photodetector OPD and an optical detection driving circuit MDC (not shown in Figure 1 and Figure 2 ) for driving the photodetector OPD.

[0090] Thus, the display device (such as a mobile phone, a watch, a notebook screen, etc.) of the embodiment of the present disclosure can realize picture display by driving the light emitting elements DD through the pixel driving circuit PDC, realize optical detection by driving the photodetector OPD through the optical detection driving circuit MDC, and further realize fingerprint recognition, touch control, ambient light detection, heart rate monitoring, or realize other functions by using the optical detection result. In an embodiment of the present disclosure, the photodetector OPD can be arrayed, for example, arrayed locally (as shown in Figure 2 or arrayed throughout the display area AA (as shown in Figure 1The photoelectric detector OPD can be distributed in a local area of the display area AA. For example, the photoelectric detector OPD can be distributed in a local area of the display area AA as shown in FIG. 1. When the photoelectric detector OPD is distributed in a local area, optical detection can be performed in the local area where the photoelectric detector OPD is distributed. For example, optical detection can be performed in the local area to realize fingerprint recognition. When the photoelectric detector OPD is distributed in the entire display area AA, optical detection can be performed in the entire display area AA. For example, optical detection can be performed in the entire display area AA to realize full-screen fingerprint recognition or realize touch control.

[0091] In the display panel PNL of an embodiment of the present disclosure, the wiring area of at least part of the pixel driving circuit PDC overlaps with the wiring area of the optical detection driving circuit MDC. For example, the wiring area of the optical detection driving circuit MDC is located within the wiring area of the pixel driving circuit PDC. In an embodiment of the present disclosure, the pixel driving circuit PDC and the optical detection driving circuit MDC arranged to overlap with each other can constitute a composite driving circuit XDC. The pixel driving circuit PDC can be defined as a first pixel driving circuit PDC1. The pixel driving circuit PDC that does not belong to the composite driving circuit XDC can be defined as a second pixel driving circuit PDC2 (as shown in FIG. 1). Figure 5 In an embodiment of the present disclosure, all the pixel driving circuits PDC can be the first pixel driving circuit PDC1, or part of the pixel driving circuits PDC can be the first pixel driving circuit PDC1 and the rest of the pixel driving circuits PDC can be the second pixel driving circuit PDC2. In other words, in the display panel PNL of the present disclosure, the display area AA can include at least the composite driving circuit XDC. The composite driving circuit XDC includes the first pixel driving circuit PDC1 for driving the light emitting element DD and the optical detection driving circuit MDC for driving the photoelectric detector OPD. In some embodiments, the display panel PNL can not include the second pixel driving circuit PDC2. In other embodiments, the display panel PNL can further include the second pixel driving circuit PDC2 and the light emitting element DD driven by the second pixel driving circuit PDC2. Optionally, the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 can be the same or different. In the present disclosure, the first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 are exemplarily described as the same pixel driving circuit PDC.

[0092] In an embodiment of the present disclosure, the display panel PNL can be provided with two driving circuits, i.e., the composite driving circuit XDC and the second pixel driving circuit PDC2. The composite driving circuit XDC includes the first pixel driving circuit PDC1 and the optical detection driving circuit MDC. The first pixel driving circuit PDC1 and the optical detection driving circuit MDC are arranged to overlap with each other. The first pixel driving circuit PDC1 and the second pixel driving circuit PDC2 can be the same.

[0093] In the embodiments of the present disclosure, the first pixel driving circuit PDC1 driving the light emitting element DD and the optical detection driving circuit MDC driving the photodetector OPD are arranged to overlap with each other, so that the wiring space of the pixel driving circuit PDC can be avoided from being occupied by the optical detection driving circuit MDC, and the size of the pixel driving circuit PDC can be avoided from being too small due to the avoidance of the optical detection driving circuit MDC, and the distribution density of the pixel driving circuit PDC can be avoided from being restricted. In this way, in some cases, the stability of the light emitting element DD driving process can be ensured by avoiding the size reduction of the pixel driving circuit PDC, and the influence of crosstalk, insufficient charging, insufficient voltage holding capability and the like on the display effect can be reduced. In some cases, the display panel PNL can be provided with more pixel driving circuits PDC and have a higher resolution.

[0094] In some embodiments of the present disclosure, referring to Figure 3 The optical detection driving circuit MDC can include an output control transistor TN, and the photodetector OPD and the output end of the optical detection driving circuit MDC are electrically connected through the output control transistor TN, for example, the photodetector OPD and the sensing signal line SSL are electrically connected through the output control transistor TN. In an example, the output control transistor TN can be turned on in response to a second level signal loaded on the gate TNG of the output control transistor, and can be turned off in response to a first level signal loaded on the gate TNG of the output control transistor.

[0095] Referring to Figures 5 to 10 In the display area AA, there are also wires for loading signals to the pixel driving circuit PDC and the optical detection driving circuit MDC, and transmitting signals of the optical detection driving circuit MDC. Among them, the wires can include row wires extending along the row direction DH and column wires extending along the column direction DV. According to the difference between the pixel driving circuit PDC and the optical detection driving circuit MDC, the display panel PNL has different wires.

[0096] In an example, the column wires include a driving power supply wire VDDL, a data wire DataL and a sensing signal line SSL; the driving power supply wire VDDL is used to provide a driving power supply VDD to the pixel driving circuit PDC; the data wire DataL is used to provide driving data Data to the pixel driving circuit PDC; under the driving of the driving power supply VDD, the pixel driving circuit PDC can output a driving current driving the light emitting element DD according to the driving data Data. The signal generated by the photodetector OPD is transmitted to the sensing signal line SSL through the optical detection driving circuit MDC, so as to be transmitted to the corresponding control component (such as a fingerprint identification chip) by the sensing signal line SSL.

[0097] In one example, the composite driving circuits XDC and the second pixel driving circuit PDC2 are arranged into multiple driving circuit columns VPDC. Each driving circuit column VPDC is arranged along the row direction DH, and each driving circuit column VPDC includes multiple driving circuits arranged sequentially along the column direction DV. Within the same driving circuit column VPDC, the pixel driving circuit PDC may include only the composite driving circuit XDC, only the second pixel driving circuit PDC2, or a combination of both.

[0098] Optionally, in the display panel PNL, each drive circuit column (VPDC) corresponds to a column trace group. Each column trace group includes data traces (DataL) and power supply traces (VDDL) for driving each drive circuit in the VPDC column. If the VPDC column has a composite drive circuit (XDC), the column trace group corresponding to the VPDC column may further include sensing signal lines (SSL) for receiving the output signals of optical detection drive circuits (MDCs) of these composite drive circuits (XDCs). In other words, if each pixel drive circuit (PDC) in a VPDC column is a second pixel drive circuit (PDC2), the column trace group corresponding to the VPDC column may include data traces (DataL) and power supply traces (VDDL) for driving each second pixel drive circuit (PDC2). If a VPDC column includes both composite drive circuits (XDC) and second pixel drive circuits (PDC2), or only composite drive circuits (XDC), the column trace group corresponding to the VPDC column may include data traces (DataL), power supply traces (VDDL), and sensing signal lines (SSL).

[0099] In one example, the driving power supply trace VDDL for each pixel driving circuit PDC driving the same column of driving circuits VPDC can be a single trace; that is, a column trace group can include one driving power supply trace VDDL. Optionally, the display panel PNL can also be configured with a driving power auxiliary trace VDDLA (VDDL connected in parallel with the driving power supply trace VDDL). Figures 5 to 10 (Not shown in the image) to reduce the impedance of the drive power trace VDDL. The drive power trace VDDL and the drive power auxiliary trace VDDLA can be disposed on two different conductive film layers (e.g., disposed on the first source / drain metal layer SD1 and the second source / drain metal layer SD2, respectively), and in particular, they can overlap each other. Of course, in other embodiments of this disclosure, two adjacent drive power traces VDDL can be electrically connected to each other and merged into a wider drive power trace VDDL, for example, two adjacent pixel drive circuits PDC can be arranged in a mirror symmetrical manner.

[0100] In an example, the data line DataL driving each pixel driving circuit PDC in the same driving circuit column VPDC can be one, i.e., one column line group can include one data line DataL. Of course, the display panel PNL can also set multiple data lines DataL (for example, two) for each driving circuit column VPDC as needed, i.e., one column line group can include multiple data lines DataL, and two pixel driving circuits PDC adjacent in the column direction can be driven by different data lines DataL. For example, in order to improve the refresh rate of the display panel PNL, each column line group can include two data lines DataL; two pixel driving circuits PDC adjacent in the column direction can be driven by different data lines DataL, respectively. Of course, in other embodiments of the present disclosure, some pixel driving circuits PDC of two adjacent driving circuit columns VPDC can also share the same data line DataL, for example, the pixel driving circuits PDC in the even rows of each driving circuit column VPDC are connected to the right data line DataL, and the pixel driving circuits PDC in the odd rows are connected to the left data line DataL, or vice versa.

[0101] In the present disclosure, the setting mode, the setting number, the shape, the position, etc. of the data line DataL and the driving power supply line VDDL can be set according to the needs of the pixel driving circuit PDC, which will not be described one by one in the present disclosure.

[0102] In an embodiment of the present disclosure, each driving circuit column VPDC has a composite driving circuit XDC, which makes the photodetector OPD driven by the composite driving circuit XDC have a larger resolution in the row direction DH. In another embodiment of the present disclosure, referring to Figures 5 to 8 , the driving circuit column VPDC can include a first driving circuit column VPDCA and a second driving circuit column VPDCB, the first driving circuit column VPDCA only includes the second pixel driving circuit PDC2; the second driving circuit column VPDCB includes the composite driving circuit XDC. Of course, the second driving circuit column VPDCB can include the second pixel driving circuit PDC2 or not, which can be determined according to the resolution requirement of the photodetector OPD in the row direction DH. Optionally, at least one first driving circuit column VPDCA is arranged between two adjacent second driving circuit columns VPDCB, which can reduce the resolution of the photodetector OPD in the row direction DH, reduce the cost of the display panel PNL and reduce the power consumption of the display panel PNL under the premise of meeting the optical detection requirement.

[0103] In an example, referring to Figure 5 and Figure 6The first driving circuit column VPDCA and the second driving circuit column VPDCB are arranged sequentially at intervals; thus, in the row direction DH, the resolution of the photodetector OPD is half the resolution of the light-emitting element DD.

[0104] In another example, see Figure 7 A second drive circuit column VPDCB is set every three first drive circuit columns VPDCA; thus, in the row direction DH, the resolution of the photodetector OPD is 1 / 4 of the resolution of the light-emitting element DD.

[0105] In embodiments of this disclosure, see Figures 5 to 8 The composite drive circuit XDC and the second pixel drive circuit PDC2 can be arranged into multiple rows of drive circuits HPDC arranged along the column direction DV. Each row of drive circuits HPDC includes multiple drive circuits arranged in the same row. The display panel PNL can be divided into multiple row partitions HHA arranged sequentially along the column direction DV. Each row partition HHA includes one row of drive circuits HPDC or multiple adjacent rows of drive circuits HPDC. An enable signal line group EMLS for loading the same enable signal EM is provided in the same row partition HHA. A composite drive circuit XDC is provided in at least one row partition HHA. See also... Figure 3 The first pixel driving circuit PDC1 is equipped with a first light-emitting control transistor T6, which controls whether the driving current of the first pixel driving circuit PDC1 can flow to the light-emitting element DD. In the row partition HHA equipped with the composite driving circuit XDC, the gate T6G of the first light-emitting control transistor of the first pixel driving circuit PDC1 and the gate TNG of the output control transistor are both connected to the enable signal line group EMLS. When the enable signal EM on the enable signal line group EMLS is a first level signal, the first light-emitting control transistor T6 is turned on, allowing the driving current of the first pixel driving circuit PDC1 to flow through the light-emitting element DD; when the enable signal EM on the enable signal line group EMLS is a second level signal, the first light-emitting control transistor T6 is turned off, preventing the driving current of the first pixel driving circuit PDC1 from flowing through the light-emitting element DD. Thus, at least one of the row partitions HHA is provided with the composite drive circuit XDC, and the gate TNG of the output control transistor and the gate T6G of the first light-emitting control transistor of the composite drive circuit XDC are electrically connected to the enable signal line group EMLS; one of the first light-emitting control transistor T6G and the output control transistor TN is turned on in response to the high-level signal of the enable signal EM, and the other is turned on in response to the low-level signal of the enable signal EM.

[0106] Further, each second pixel driving circuit PDC2 in the same row partition HHA also includes a first light emitting control transistor T6, and the gate electrode T6G of the first light emitting control transistor T6 of the second pixel driving circuit PDC2 is also connected to the enable signal line group EMLS. In this way, in the same row partition HHA, the gate electrode T6G of each first light emitting control transistor and the gate electrode TNG of each output control transistor are both connected to the same enable signal line group EMLS.

[0107] Optionally, the enable signal line group EMLS can include one enable signal line or multiple enable signal lines. In an example, in one row partition HHA, the enable signal line group EMLS includes a first enable signal line EMLA corresponding to each driving circuit row HPDC, and each first enable signal line EMLA is used to drive the corresponding driving circuit row HPDC. When the row partition HHA also includes a composite driving circuit XDC, the enable signal line group EMLS also includes a second enable signal line EMLB corresponding to each row composite driving circuit XDC, and each second enable signal line EMLB is used to drive the optical detection driving circuit MDC in the same row.

[0108] In an embodiment of the present disclosure, referring to Figures 4 to 8 , the display panel PNL includes a first enable signal line EMLA and a scan wire GL extending in the row direction DH. The first enable signal line EMLA is used to control whether the driving current of the pixel driving circuit PDC can be loaded to the driven light emitting element DD. For example, the pixel driving circuit PDC can include a driving transistor T3 and a first light emitting control transistor T6; the driving transistor T3 can output a driving current for driving the light emitting element DD under the control of the voltage on the gate electrode T3G of the driving transistor; and the driving transistor T3 is electrically connected to the pixel electrode of the light emitting element DD through the first light emitting control transistor T6. The gate electrode T6G of the first light emitting control transistor can be electrically connected to the first enable signal line EMLA; when the signal on the first enable signal line EMLA causes the first light emitting control transistor T6 to be cut off, the driving transistor T3 cannot generate a driving current according to the voltage on the gate electrode T3G of the driving transistor, and the light emitting element DD cannot emit light. When the signal on the first enable signal line EMLA causes the first light emitting control transistor T6 to be turned on, and the required conditions such as providing a driving power source VDD are met, the driving transistor T3 can output a driving current under the control of the voltage on the gate electrode T3G of the driving transistor, and the driving current can flow through the light emitting element DD to drive the light emitting element DD to emit light.

[0109] The scan wire GL is used to control whether the driving data Data on the data wire DataL can be written to the pixel driving circuit PDC electrically connected with the data wire DataL. For example, the pixel driving circuit PDC can be provided with a data writing transistor T4, a storage capacitor Cst, etc., the gate T3G of the driving transistor is electrically connected with the storage capacitor Cst, used to output a driving current for driving the light emitting element DD under the control of the voltage on the gate T3G of the driving transistor; the data writing transistor T4 is configured to be able to write the driving data Data into the storage capacitor Cst. Specifically, the storage capacitor Cst can be electrically connected with the gate T3G of the driving transistor (as the first node N1), the gate T4G of the data writing transistor is electrically connected with the scan wire GL, and the source T4S of the data writing transistor is electrically connected with the data wire DataL. When the signal on the gate T4G of the data writing transistor makes the data writing transistor T4 conduct, the driving data Data on the data wire DataL can be loaded on the pixel driving circuit PDC, specifically can be written into the storage capacitor Cst for controlling the voltage of the first node N1. In this way, when the pixel driving circuit PDC can output a driving current, the driving current is related to the driving data Data written into the pixel driving circuit PDC. In this way, in some embodiments, the row wire corresponding to the driving circuit row HPDC can include the first enable signal line EMLA and the scan wire GL.

[0110] In some embodiments of the present disclosure, the display panel PNL can be further provided with a reset control line RL and an initial voltage line VinitL extending along the row direction DH, the reset control line RL controls the reset of the pixel driving circuit PDC, for example, controls the pixel driving circuit PDC to reset the first node N1 before writing the driving data Data (write the signal loaded on the initial voltage line VinitL to the first node N1), or controls the pixel driving circuit PDC to reset the pixel electrode of the light emitting element DD before or after the light emitting element DD emits light (write the signal loaded on the initial voltage line VinitL to the pixel electrode of the light emitting element DD). In an example, the reset control line RL can include a first reset control line RL1 and a second reset control line RL2, and the initial voltage line VinitL includes a first initial voltage line VInit1L and a second initial voltage line Vinit2L; wherein the first reset control line RL1 is used to control the pixel driving circuit PDC to reset the first node N1 before writing the driving data Data, specifically, by responding to the first reset signal Re1 to write the first initial voltage Vinit1 loaded on the first initial voltage line VInit1L to the first node N1; the second reset control line RL2 is used to control the pixel driving circuit PDC to reset the pixel electrode of the light emitting element DD before or after the light emitting element DD emits light, specifically, by responding to the second reset signal Re2 to write the second initial voltage Vinit2 loaded on the second initial voltage line Vinit2L to the pixel electrode of the light emitting element DD. The first reset control line RL1 and the second reset control line RL2 can be two different lines, or can be the same line. When the first reset control line RL1 and the second reset control line RL2 are two different lines, the signals on the first reset control line RL1 and the second reset control line RL2 can be the same or different. The first initial voltage line VInit1L and the second initial voltage line Vinit2L can be two different lines, or can be the same line (i.e., the initial voltage line VinitL). When the first initial voltage line VInit1L and the second initial voltage line Vinit2L are two different lines, the first initial voltage Vinit1 and the second initial voltage Vinit2 can be the same or different.

[0111] For example, in one example, the pixel driving circuit PDC includes a capacitor reset transistor T1, a source T1S of the capacitor reset transistor is electrically connected with the initial voltage line VinitL1, a gate T1G of the capacitor reset transistor is electrically connected with the first reset control line RL1, and a drain T1D of the capacitor reset transistor is electrically connected with the first node N1. When the signal on the first reset control line RL1 makes the capacitor reset transistor T1 conduct, the first initial voltage can be loaded to the first node N1 so that the voltage of the first node N1 is reset to the first initial voltage.

[0112] For example, in one example, the pixel driving circuit PDC includes an electrode reset transistor T7, a source T7S of the electrode reset transistor is electrically connected with the initial voltage line VinitL2, a gate T7G of the electrode reset transistor is electrically connected with the second reset control line RL2, and a drain T7D of the electrode reset transistor is electrically connected with the pixel electrode of the light emitting element DD. When the signal on the second reset control line RL2 makes the electrode reset transistor T7 conduct, the second initial voltage can be loaded to the pixel electrode of the light emitting element DD so that the voltage of the pixel electrode of the light emitting element DD is reset to the second initial voltage.

[0113] Thus, in some embodiments, the row wire corresponding to the driving circuit row HPDC can further include the reset control line RL and the initial voltage line VinitL, for example, the first reset control line RL1, the second reset control line RL2, the first initial voltage line VInit1L and the second initial voltage line Vinit2L.

[0114] Further, in the two adjacent rows of pixel driving circuits PDC, the second reset control line RL2 connected by the pixel driving circuit PDC in the previous row is the same wire as the first reset control line RL1 connected by the pixel driving circuit PDC in the next row; the second initial voltage line Vinit2L connected by the pixel driving circuit PDC in the previous row is the same wire as the first initial voltage line VInit1L connected by the pixel driving circuit PDC in the next row. In other words, in the row wires corresponding to the two adjacent driving circuit rows HPDC respectively, the second reset control line RL2 corresponding to the previous driving circuit row HPDC is the same reset control line RL as the first reset control line RL1 corresponding to the next driving circuit row HPDC, and the second initial voltage line Vinit2L corresponding to the previous driving circuit row HPDC is the same initial voltage line VinitL as the first initial voltage line VInit1L corresponding to the next driving circuit row HPDC.

[0115] In one embodiment of the present disclosure, the pixel driving circuit PDC can further include a threshold compensation transistor T2, which compensates the threshold voltage of the driving transistor T3, so that the driving current output by the driving transistor T3 is irrelevant to the threshold voltage of the driving transistor T3. This can eliminate the non-uniformity of the display panel PNL caused by the non-uniformity of the performance of the driving transistor T3 in space. In one example, the source T2S of the threshold compensation transistor is electrically connected with the drain T3D of the driving transistor (as the third node N3), the drain T2D of the threshold compensation transistor is electrically connected with the first node N1, and the gate T2G of the threshold compensation transistor is electrically connected with the scan wire GL. The drain T4D of the data writing transistor is electrically connected with the source T3S of the driving transistor (as the second node N2). The pixel driving circuit PDC can further be provided with a second light-emitting control transistor T5, the source T5S of which is used to load the driving power VDD, the drain T5D of which is electrically connected with the second node N2, and the gate T5G of which is electrically connected with the first enable signal line EMLA. In this way, after the threshold compensation transistor T2 and the data writing transistor T4 are turned on by the signal on the scan wire GL, the voltage written on the first node N1 is related to the driving data Data and the threshold voltage of the driving transistor T3, realizing the writing of data and the threshold compensation of the driving transistor T3. This finally makes the driving current output by the driving transistor T3 related to the written driving data Data, and irrelevant to the threshold voltage of the driving transistor T3.

[0116] Of course, in other embodiments of the present disclosure, the threshold compensation transistor T2 and the data writing transistor T4 can also not respond to the same signal, for example, one responds to a high-level signal and the other responds to a low-level signal, so that the threshold compensation transistor T2 and the data writing transistor T4 can be opened at the same time in some time periods and can be closed at the same time in other time periods; accordingly, the wires to which the gates T2G of the threshold compensation transistor and the gates T4G of the data writing transistor are connected are different.

[0117] It can be understood that the above introduction of the partial row wires is only an exemplary introduction. In order to realize the driving of the light-emitting element DD and the loading of signals to the pixel driving circuit PDC, the display panel PNL can be provided with only part of the above row wires as needed, or new row wires can be added as needed.

[0118] As follows, the pixel driving circuit PDC of the display panel PNL of the present disclosure, the partial row wires and the partial DL are further explained and described by taking a pixel driving circuit PDC with a 7-capacitance reset transistor T1C as an example.

[0119] The pixel driving circuit PDC of the example includes a storage capacitor Cst, a capacitor reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a second light-emitting control transistor T5, a first light-emitting control transistor T6, and an electrode reset transistor T7; wherein the drain of the threshold compensation transistor T2D, the gate of the driving transistor T3G, and the first electrode plate of the storage capacitor CP1 are electrically connected to the first node N1, the source of the driving transistor T3S, the drain of the second light-emitting control transistor T5D, and the drain of the data writing transistor T4D are electrically connected to the second node N2, the drain of the driving transistor T3D, the source of the threshold compensation transistor T2S, and the source of the first light-emitting control transistor T6S are electrically connected to the third node N3; the drain of the data writing transistor T4D is electrically connected to the second electrode plate of the storage capacitor CP2. The source of the capacitor reset transistor T1S is used to load a first initial voltage, the gate of the capacitor reset transistor T1G is used to load a first reset signal, the gate of the threshold compensation transistor T2G is used to load a scan signal Gate, the source of the data writing transistor T4S is used to load a driving data Data, the gate of the data writing transistor T4G is used to load a scan signal Gate, the source of the second light-emitting control transistor T5S is used to load a driving power VDD, the gate of the second light-emitting control transistor T5G and the gate of the first light-emitting control transistor T6G are used to load a first level signal, the gate of the electrode reset transistor T7G is used to load a second reset signal, and the source of the electrode reset transistor T7S is used to load a second initial voltage. The drain of the first light-emitting control transistor T6D and the drain of the electrode reset transistor T7D are electrically connected to the pixel electrode of the light-emitting element DD.

[0120] In this example, the row wires corresponding to the driving circuit row HPDC include a first enable signal line EMLA for loading an enable signal EM, a scan wire GL for loading a scan signal Gate, a first reset control line RL1 for loading a first reset signal, a second reset control line RL2 for loading a second reset signal, a first initial voltage line VInit1L for loading a first initial voltage, and a second initial voltage line Vinit2L for loading a second initial voltage. Among the row wires corresponding to the adjacent two driving circuit rows HPDC, the second reset control line RL2 corresponding to the previous driving circuit row HPDC and the first reset control line RL1 corresponding to the next driving circuit row HPDC are the same reset control line RL, and the second initial voltage line Vinit2L corresponding to the previous driving circuit row HPDC and the first initial voltage line VInit1L corresponding to the next driving circuit row HPDC are the same initial voltage line VinitL.

[0121] In the example, the enable signal EM is a low-level signal when the pixel driving circuit PDC is enabled, and the enable signal EM is a high-level signal when the optical detection driving circuit MDC is enabled. Each row partition HHA includes a plurality of driving circuit rows HPDC, and each driving circuit row HPDC in each row partition HHA is controlled by the same enable signal EM. See Figure 11 In the plurality of row partitions HHA that are sequentially adjacent, the enable signal EM of each row partition HHA can be a low-level signal in sequence, so that the pixel driving circuit PDC in each row partition HHA is enabled in sequence. In the example, Figure 11 In the example, the enable signal EM(N) represents the enable signal EM in the Nth row partition HHA, the enable signal EM(N+1) represents the enable signal EM in the N+1th row partition HHA, and so on, and the enable signal EM(N+5) represents the enable signal EM in the N+5th row partition HHA.

[0122] In some embodiments of the present disclosure, see Figure 3 and Figure 4 The optical detection driving circuit MDC can include an output control transistor TN, and the photodetector OPD is electrically connected to the output end of the optical detection driving circuit MDC through the output control transistor TN, for example, the photodetector OPD is electrically connected to the sensing signal line SSL through the output control transistor TN. Further, in the composite driving circuit XDC, the gate TNG of the output control transistor and the gate T6G of the first light-emitting control transistor are used to load the same signal. The gate T6G of the first light-emitting control transistor and the gate TNG of the output control transistor are used to load the same enable signal EM; one of the first light-emitting control transistor T6 and the output control transistor TN is used to be turned on in response to the high-level signal of the enable signal EM, and the other is used to be turned on in response to the low-level signal of the enable signal EM. Specifically, the output control transistor TN can be turned on in response to the second-level signal loaded on the gate TNG of the output control transistor, and can be turned off in response to the first-level signal loaded on the gate TNG of the output control transistor; the first light-emitting control transistor T6 can be turned on in response to the first-level signal loaded on the gate T6G of the first light-emitting control transistor, and can be turned off in response to the second-level signal loaded on the gate T6G of the first light-emitting control transistor. Wherein, one of the first-level signal and the second-level signal is the high-level signal of the enable signal EM, and the other is the low-level signal of the enable signal EM. Because the gate TNG of the output control transistor and the gate T6G of the first light-emitting control transistor load the same enable signal EM, the output control transistor TN and the first light-emitting control transistor T6 in the composite driving circuit XDC are alternatively turned on.

[0123] In an example, seeFigures 4 to 8 The row wire of the display panel PNL can further include a second enable signal line EMLB extending along the row direction DH; the gate of the output control transistor TNG is electrically connected with the second enable signal line EMLB. The first enable signal line EMLA of the first pixel driving circuit PDC1 for driving the composite driving circuit XDC and the second enable signal line EMLB of the optical detection driving circuit MDC for driving the composite driving circuit XDC can be electrically connected with each other, so that both of them load the same enable signal EM.

[0124] In an example, the first enable signal lines EMLA and the second enable signal lines EMLB in the same row partition HHA can be electrically connected with each other, so as to ensure that the enable signal EML in the same row partition HHA loads the same enable signal EM.

[0125] In an example, the driving transistor T3 and the first light emitting control transistor T6 are P-type transistors, and the output control transistor TN is a metal oxide semiconductor transistor. In this way, the first level signal is a low level signal, and the second level signal is a high level signal. Further, the driving transistor T3 and the first light emitting control transistor T6 are low temperature poly-silicon transistors.

[0126] In some embodiments of the present disclosure, referring to Figures 5 to 8 The display panel PNL can be divided into a plurality of row partitions HHA arranged in sequence along the column direction DV, and each row partition HHA includes one driving circuit row HPDC or a plurality of adjacent driving circuit rows HPDC. In some embodiments of the present disclosure, the enable signals EML in the same row partition HHA can be electrically connected with each other, so that the enable signals EML in the same row partition HHA load the same enable signal EM. Correspondingly, in the adjacent two row partitions HHA, the timing of the loaded enable signals EM is different.

[0127] In an example, in the plurality of row partitions HHA arranged in sequence along the column direction DV, the enable signal EM in each row partition HHA is modulated into a first level signal (for example, modulated into a low level signal) one by one, that is, the enable signal EML of each row partition HHA can be loaded with the first level signal step by step. When the enable signal EM in the row partition HHA is the first level signal, the pixel driving circuit PDC in the row partition HHA drives the light emitting element DD to emit light and the optical detection driving circuit MDC in the row partition HHA is electrically disconnected. When the enable signal EM in the row partition HHA is not the first level signal, the enable signal EM can be a second level signal, the pixel driving circuit PDC in the row partition HHA does not drive the light emitting element DD to emit light and the optical detection driving circuit MDC in the row partition HHA is electrically connected.

[0128] Optionally, the light emitting element DD driven by the pixel driving circuit PDC in the row partitioned HHA can be located in the row partitioned HHA; the photodetector OPD driven by the optical detection driving circuit MDC in the row partitioned HHA can be located in a different row partitioned HHA from the optical detection driving circuit MDC, for example, the optical detection driving circuit MDC and the photodetector OPD are located in two adjacent row partitioned HHAs. In this way, when the enable signal EM in a selected row partitioned HHA is at the first level signal, the pixel driving circuit PDC in the selected row partitioned HHA can drive the light emitting element DD to emit light; the photodetector OPD in the selected row partitioned HHA can generate a detection signal with the light emitting element DD as a light source. In other row partitioned HHAs other than the selected row partitioned HHA, the enable signal EM in the row partitioned HHA adjacent to the selected row partitioned HHA is at the second level signal to make the optical detection driving circuit MDC therein electrically conductive. At this time, the photodetector OPD in the selected row partitioned HHA generates a signal under the irradiation of a light source, and the photodetector OPD in the selected row partitioned HHA is located in the other row partitioned HHA and can output the signal, so that the signal generated by the photodetector OPD can be loaded onto the sensing signal line SSL.

[0129] Further, the photodetector OPD can be located in the gap between the light emitting elements DD to avoid occupying the space of the light emitting element DD and affecting the aperture ratio of the display panel PNL.

[0130] In an embodiment of the present disclosure, the display panel PNL can further be provided with a power distribution line EMLC extending in the row direction DH. If a driving circuit row HPDC does not have a first pixel driving circuit PDC1 and does not need to be provided with a second enable signal line EMLB for driving the optical detection driving circuit MDC, the driving circuit row HPDC can be provided with the power distribution line EMLC. The power distribution line EMLC can be electrically connected with at least part of the driving power supply wires VDDL that intersect and overlap, for example, each driving power supply wire VDDL that intersects and overlaps. In this way, on the one hand, the power distribution line EMLC and the second enable signal line EMLB do not occupy the space of the same driving circuit row HPDC, so that the display panel PNL will not cause yield reduction due to too many lines; on the other hand, the power distribution line EMLC can electrically connect the driving power supply wires VDDL, thereby making the distribution grid of the driving power supply VDD, improving the uniformity of the driving power supply VDD, and further improving the uniformity of the display panel PNL.

[0131] In an example, the power distribution line EMLC is arranged in the driving circuit row HPDC in a position and shape consistent with the position and shape of the second enable signal line EMLB in the driving circuit row HPDC, and the power distribution line EMLC and the second enable signal line EMLB are arranged on the same layer. In this way, on the one hand, the design and preparation of the power distribution line EMLC and the second enable signal line EMLB are facilitated, and on the other hand, the uniformity of the patterning process in the preparation of the power distribution line EMLC and the second enable signal line EMLB can be improved.

[0132] In an embodiment of the present disclosure, the output control transistor TN can include one transistor or a plurality of sub-transistors connected in series. For example, the output control transistor TN includes two sub-transistors connected in series, each of which has a source, a drain and a gate, and the source of one sub-transistor is electrically connected to the drain of the other sub-transistor. In this way, the leakage of the output control transistor TN can be reduced, the crosstalk between the signals of different photodetectors OPD can be avoided, and the accuracy of the photodetector OPD can be improved.

[0133] In an example, each photodetector OPD driven by the optical detection driving circuit MDC in the same row partition HHA can be located in the same row partition HHA. In this way, the optical detection driving circuit MDC and the photodetector OPD driven thereby in the same row partition HHA can work synchronously, which can reduce the difficulty of processing the light detection signal.

[0134] Referring to Figures 5 to 8 In an embodiment of the present disclosure, the driving circuit row HPDC provided with the composite driving circuit XDC can be defined as a second driving circuit row HPDCB, and the driving circuit row HPDC not provided with the composite driving circuit XDC can be defined as a first driving circuit row HPDCA. In the plurality of driving circuit rows HPDC of one row partition HHA, only one second driving circuit row HPDCB can be provided, a plurality of second driving circuit rows HPDCB can be provided, or no second driving circuit row HPDCB can be provided. For example, in the example of Figure 5 each row partition HHA includes two driving circuit rows HPDC, one of which is a first driving circuit row HPDCA and the other of which is a second driving circuit row HPDCB. For example, in the example of Figure 8 one row partition HHA includes two driving circuit rows HPDC, and both of the two driving circuit rows HPDC are second driving circuit rows HPDCB. For example, in the example of Figure 10In the example, each row partition HHA has two drive circuit rows HPDC; wherein, in some row partitions HHA, the drive circuit rows HPDC are all the first drive circuit row HPDCCA, that is, they do not contain composite drive circuit XDC; wherein, in some row partitions HHA, the drive circuit rows HPDC include the second drive circuit row HPDCB, that is, they contain composite drive circuit XDC. More specifically, in Figure 10 In the example, in two adjacent row partitions HHA, one row partition HHA does not include the composite drive circuit XDC; the other row partition HHA does not include the second pixel drive circuit PDC2, meaning it consists entirely of composite drive circuits XDC. Thus, the resolution of the photodetector OPD in the column direction DV can be adjusted by changing the number and density of the second drive circuit rows HPDCB.

[0135] In one embodiment of this disclosure, multiple composite drive circuits XDCs are arranged in the same column in at least one row partition HHA, and each composite drive circuit XDC is electrically connected to a different sensing signal line SSL. In other words, if a second drive circuit column VPDCB has multiple composite drive circuits XDCs within at least one row partition HHA, then the column routing group corresponding to the second drive circuit column VPDCB needs to be provided with multiple sensing signal lines SSL corresponding one-to-one with the multiple composite drive circuits XDCs, so that the multiple composite drive circuits XDCs arranged in the same column within the same row partition HHA are electrically connected to different sensing signal lines SSL. For example, in... Figure 10 In the example, the second driving circuit column VPDCB has two composite driving circuits XDC within at least one row partition HHA. The column trace group corresponding to this second driving circuit column VPDCB is provided with two sensing signal lines SSL. The two composite driving circuits XDC in the same column within the row partition HHA are electrically connected to the two sensing signal lines SSL respectively. Thus, when all the composite driving circuits XDC in the row partition HHA are turned on in response to the second level signal, the signals of the photodetectors OPD driven by each composite driving circuit XDC can be output to different sensing signal lines SSL, avoiding resolution loss caused by the merging of photodetector OPD signals.

[0136] See Figure 12In this embodiment of the disclosure, the display panel PNL may include a substrate BP, a driving layer F100, and a device layer F200 stacked sequentially. The driving layer F100 is provided with a pixel driving circuit PDC for driving the light-emitting elements DD and an optical detection driving circuit MDC for driving the photodetector OPD. The light-emitting elements DD and the photodetector OPD are disposed on its device layer. In one example, the photodetector OPD is disposed in the gap between two adjacent light-emitting elements DD, and uses the light emitted by the adjacent light-emitting elements DD as a light source.

[0137] In some embodiments of this disclosure, the substrate BP can be an inorganic material or an organic material. For example, in one embodiment, the substrate BP can be made of glass materials such as soda-lime glass, quartz glass, or sapphire glass, or metal materials such as stainless steel, aluminum, or nickel. In another embodiment, the substrate BP can be made of polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or combinations thereof. In yet another embodiment, the substrate BP can also be a flexible substrate BP, for example, the substrate BP can be made of polyimide (PI). The substrate BP can also be a composite of multiple materials. For example, in one embodiment of this disclosure, the substrate BP may include a bottom film, a pressure-sensitive adhesive layer, a first polyimide layer and a second polyimide layer stacked sequentially.

[0138] In the driving layer F100, any one of the pixel driving circuit PDC and the optical detection driving circuit MDC can include a transistor, and the pixel driving circuit PDC can further include a storage capacitor. Further, the transistor can be a thin film transistor, which can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, or other types of semiconductor material; and the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0139] It can be understood that the types of any two transistors among the transistors in the pixel driving circuit can be the same or different. For example, in one embodiment, in a pixel driving circuit, some transistors can be N-type transistors and some transistors can be P-type transistors. For another example, in another embodiment of the present disclosure, in a pixel driving circuit, the material of the active layer of some transistors can be low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors can be metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low-temperature polysilicon transistor. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polysilicon transistors, and some thin film transistors are metal oxide transistors.

[0140] Optionally, the driving layer F100 can include at least two semiconductor layers and a plurality of conductive metal layers stacked between the substrate BP and the device layer, and an insulating layer can be arranged between the semiconductor layers, the conductive metal layers, and other film layers. The semiconductor layers can form the channel region of the transistor and the source and drain connected to the channel region, the conductive metal layers can form the gate of the transistor and the electrode plate of the storage capacitor, and the conductive metal layers can also electrically connect the transistor, the storage capacitor, and the like to form the pixel driving circuit PDC and the optical detection driving circuit MDC. Further, the semiconductor layers can include a low-temperature polysilicon semiconductor layer SEMI1 and a metal oxide semiconductor layer SEMI2. The conductive metal layers can include a plurality of gate layers (for example, two or three gate layers) and at least one source-drain metal layer (for example, 1-3 source-drain metal layers). The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor.

[0141] In one embodiment of the present disclosure, referring to Figure 12The driving layer F100 can include, in sequence, a low-temperature polysilicon semiconductor layer SEMI1, a first gate layer GT1, a second gate layer GT2, a metal oxide semiconductor layer SEMI2, a third gate layer GT3, a first source-drain metal layer SD1, and a second source-drain metal layer SD2, and insulating layers can be arranged between the layers, which can be inorganic or organic insulating layers.

[0142] As an example, referring to Figure 12 The insulating layers in the driving layer F100 can include, for example, a first buffer layer Buff1 on the side of the low-temperature polysilicon semiconductor layer SEMI1 close to the substrate BP, a first gate insulating layer GI1 between the low-temperature polysilicon semiconductor layer SEMI1 and the first gate layer GT1, a first interlayer dielectric layer ILD1 between the first gate layer GT1 and the second gate layer GT2, a second interlayer dielectric layer ILD2 and a second buffer layer Buff2 between the second gate layer GT2 and the metal oxide semiconductor layer SEMI2, a second gate insulating layer GI2 between the metal oxide semiconductor layer SEMI2 and the third gate layer GT3, a third interlayer dielectric layer ILD3 between the first source-drain metal layer SD1 and the third gate layer GT3, a first planarization layer PLN1 between the first source-drain metal layer SD1 and the second source-drain metal layer SD2, a second planarization layer PLN2 on the side of the second source-drain metal layer SD2 away from the substrate BP, and the like. The metal oxide semiconductor layer SEMI2 is arranged on the surface of the second buffer layer Buff2. Of course, a passivation layer can be arranged on the surface of the first source-drain metal layer SD1 or the second source-drain metal layer SD2 as needed.

[0143] Optionally, the first buffer layer Buff1, the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer dielectric layer ILD1, the second interlayer dielectric layer ILD2, the third interlayer dielectric layer ILD3, and the second buffer layer Buff2 can be made of inorganic insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride, and the like. The second buffer layer Buff2 and the second gate insulating layer GI2, in particular, can be made of silicon oxide to reduce defects on the surface of the metal oxide semiconductor layer SEMI2. The first planarization layer PLN1 and the second planarization layer PNL2 can be made of organic insulating materials, such as photosensitive resin.

[0144] In one embodiment of the present disclosure, the channel region of each transistor of the pixel driving circuit PDC is located in the low-temperature polysilicon semiconductor layer SEMI1, i.e., each transistor of the pixel driving circuit PDC is a low-temperature polysilicon transistor. Of course, in other embodiments of the present disclosure, some transistors of the pixel driving circuit PDC can be low-temperature polysilicon transistors and some transistors can be metal-oxide transistors.

[0145] In one embodiment of the present disclosure, the device layer F200 includes, in sequence from the side of the driving layer away from the substrate BP, a pixel electrode layer ANDL, a pixel definition layer PDL, a composite functional material layer MXL, and a common electrode layer COML; the composite functional material layer MXL includes an electroluminescent material layer EL and a photoelectric conversion material layer LE. The pixel electrode layer includes the pixel electrode of the light emitting element DD, the device electrode of the photodetector OPD, and a device lead; the device electrode of the photodetector OPD is electrically connected to the optical detection driving circuit MDC that drives the photodetector OPD through the device lead. In other words, the device electrode of the photodetector OPD, the device lead, and the pixel electrode of the light emitting element DD can be arranged in the same layer, and the photodetector OPD and the composite driving circuit XDC are electrically connected through the device lead.

[0146] For example, referring to Figure 9 and Figure 10 , there is a device trace ANDBL between the photodetector OPD and the composite driving circuit XDC, and the device trace ANDBL is arranged across the row partition HHA so that the photodetector OPD and the composite driving circuit XDC are located in different row partitions HHA.

[0147] In one embodiment of the present disclosure, referring to Figure 10 , at least one row partition HHA has a plurality of composite driving circuits XDC arranged in the same column, and the plurality of composite driving circuits XDC are respectively electrically connected to the photodetectors OPD driven by them through the device traces ANDBL, and these device traces ANDBL are all located on the same side of the composite driving circuit XDC in the row direction DH, for example, all located on the left side or the right side of the composite driving circuit XDC. In other words, the device traces ANDBL connected by the plurality of composite driving circuits XDC arranged in the same column in the row partition HHA are all located on the same side of the composite driving circuit XDC in the row direction DH. This can facilitate the layout of the device traces ANDBL and reduce the crosstalk that may be caused by the device traces ANDBL crossing lines.

[0148] In one example, the device layer F200 can further have a support post layer PS including a plurality of support posts in the display area, and the support posts are located on the surface of the pixel definition layer PDL away from the substrate BP to support a fine metal mask (FMM) in an evaporation process.

[0149] In one embodiment of the present disclosure, the electroluminescent material layer covers at least the pixel electrode exposed by the pixel definition layer PDL. The electroluminescent material layer can include an organic electroluminescent material layer, and can include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Each film layer of the organic electroluminescent material layer EL can be prepared by an evaporation process, and a fine metal mask or an open mask can be used to define the pattern of each film layer during evaporation. The common electrode layer COML can cover the organic electroluminescent material layer EL in the display area. In this way, the pixel electrode, the common electrode layer COML, and the electroluminescent material layer between the pixel electrode and the common electrode layer COML form an organic electroluminescent diode, and any one of the organic electroluminescent diodes can serve as a sub-pixel of the display panel.

[0150] Optionally, the device layer can further include a light extraction layer located on the side of the common electrode layer COML away from the substrate BP to enhance the light extraction efficiency of the organic electroluminescent diode.

[0151] Optionally, the display panel can further include a thin film encapsulation layer TFE. The thin film encapsulation layer TFE is arranged on the surface of the device layer F200 away from the substrate BP, and can include inorganic encapsulation layers and organic encapsulation layers arranged alternately. The touch layer is arranged on the side of the thin film encapsulation layer TFE away from the substrate BP. The inorganic encapsulation layer can effectively block moisture and oxygen from the outside, preventing water and oxygen from invading the organic electroluminescent material layer EL and causing material degradation. Optionally, the edge of the inorganic encapsulation layer can be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer can be located between the edge of the display area and the edge of the inorganic encapsulation layer. In one example, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence on the side of the device layer away from the substrate BP.

[0152] As follows, the pixel driving circuit PDC is taken as an example to describe the display panel. Figure 4The structure, wiring mode and function of the display panel PNL in the embodiments of the present disclosure are further exemplarily described by taking the first pixel driving circuit PDC1 and the optical detection driving circuit MDC in the example as examples of the output control transistor TN. In this example, the pixel driving circuit PDC has 7 low-temperature polysilicon transistors and 1 storage capacitor. It can be understood that in other embodiments of the present disclosure, the number, type, storage capacitor, connection mode and distribution position of the transistors in the pixel driving circuit PDC, etc. can be different from the present example. In this example, the display panel PNL is provided with a circuit layout area PDCA for laying out the pixel driving circuit PDC, the circuit layout area PDCA is rectangular and arrayed, which makes most of the transistors of each pixel driving circuit PDC located in the circuit layout area PDCA; however, part of the transistors of the pixel driving circuit PDC can be located in the circuit layout area PDCA of other pixel driving circuits PDC. Specifically, in this example, the electrode reset transistor T7 of the pixel driving circuit PDC can be located in the circuit layout area PDCA of the pixel driving circuit PDC adjacent in the same column; correspondingly, the electrode reset transistor T7 in the circuit layout area PDCA of the pixel driving circuit PDC is the electrode reset transistor T7 of the pixel driving circuit PDC adjacent in the same column. According to the type and distribution of the output control transistor TN, three different examples such as the first example to the third example are provided.

[0153] Referring to Figure 12 In the display panel PNL in this example, the driving layer of the display panel PNL includes a first buffer layer Buff1, a low-temperature polysilicon semiconductor layer SEMI1, a first gate insulating layer GI1, a first gate layer GT1, a first interlayer dielectric layer ILD1, a second gate layer GT2, a second interlayer dielectric layer ILD2, a second buffer layer Buff2, a metal oxide semiconductor layer SEMI2, a second gate insulating layer GI2, a third gate layer GT3, a third interlayer dielectric layer ILD3, a first source-drain metal layer SD1, a first planarization layer PLN1, a second source-drain metal layer SD2, a second planarization layer PLN2, which are sequentially stacked. The low-temperature polysilicon semiconductor layer SEMI1, the first gate layer GT1 and the second gate layer GT2 in the first example to the third example can be the same.

[0154] Figure 13 For the display panel PNL in the three examples, a structure diagram of the low-temperature polysilicon semiconductor layer SEMI1 of the display panel PNL is shown. Referring to Figure 13The low-temperature polysilicon semiconductor layer SEMI1 can be provided with a channel region T1Act of a capacitor reset transistor, a channel region T2Act of a threshold compensation transistor, a channel region T3Act of a driving transistor, a channel region T4Act of a data write transistor, a channel region T5Act of a second light-emitting control transistor, a channel region T6Act of a first light-emitting control transistor, a channel region T7Act of an electrode reset transistor, and conductorized connection regions. The conductorized connection regions can include the source and drain of each transistor, which are respectively connected to both ends of the channel region of the transistor. The source T1S of the capacitor reset transistor is electrically connected to the initial voltage line VinitL provided on the second gate layer GT2 through the second metal transfer structure ML2 provided on the first source-drain metal layer SD1, so as to load Vinit to the source T1S of the capacitor reset transistor. Referring to Figure 13 The source T1S of the capacitor reset transistor of the present pixel driving circuit PDC can be connected to the source T7S of the electrode reset transistor of the column-adjacent pixel driving circuit PDC. The drain T1D of the capacitor reset transistor and the drain T2D of the threshold compensation transistor are connected to each other, and can be electrically connected to the first electrode plate CP1 of the storage capacitor provided on the first gate layer GT1 through the third metal transfer structure ML3 provided on the first source-drain metal layer SD1, which can cover the channel region T3Act of the driving transistor to multiplex as the gate T3G of the driving transistor, so that the drain T1D of the capacitor reset transistor, the drain T2D of the threshold compensation transistor, the first electrode plate CP1 of the storage capacitor, and the third metal transfer structure ML3 serve as part of the first node N1. The source T2S of the threshold compensation transistor is connected to the drain T3D of the driving transistor and the source T6S of the first light-emitting control transistor to serve as part of the second node N2. The drain T6D of the first light-emitting control transistor is connected to the drain T7D of the electrode reset transistor, and can be electrically connected to the pixel electrode ANDA through the fifth metal transfer structure ML5 provided on the second source-drain metal layer SD2 through a via and the fourth metal transfer structure ML4 provided on the first source-drain metal layer SD1. The source T5S of the second light-emitting control transistor is electrically connected to the driving power supply line VDDL provided on the first source-drain metal layer SD1 through a via, and the drain T5D of the second light-emitting control transistor, the source T3S of the driving transistor, and the drain T4D of the data write transistor serve as part of the third node N3. The source T4S of the data write transistor is located on one side of the circuit layout area PDCA in the row direction DH and is connected to the channel region T4Act of the data write transistor, and is electrically connected to the data line DataL provided on the first source-drain metal layer SD1 through a via, so as to load the driving data Data to the source T4S of the data write transistor.

[0155] The channel region T1Act of the capacitor reset transistor can include two sub-channel regions, and the two sub-channel regions are electrically connected through the conductorized low-temperature polysilicon, which makes the capacitor reset transistor T1 equivalent to two sub-transistors in series, thereby reducing the leakage of the capacitor reset transistor T1 to improve the voltage holding capability of the storage capacitor Cst. The channel region T2Act of the threshold compensation transistor can include two sub-channel regions, and the two sub-channel regions are electrically connected through the conductorized low-temperature polysilicon, which makes the threshold compensation transistor T2 equivalent to two sub-transistors in series, thereby reducing the leakage of the threshold compensation transistor T2 to improve the voltage holding capability of the storage capacitor Cst.

[0156] The two sub-channel regions of the capacitor reset transistor T1 and the channel region T7Act of the electrode reset transistor can be arranged in the same row, so they can be arranged to overlap the reset control line RL located in the first gate layer GT1, so that part of the reset control line RL simultaneously serves as the gate T1G of the capacitor reset transistor and the gate T7G of the electrode reset transistor.

[0157] The two sub-channel regions of the threshold compensation transistor T2 can be arranged perpendicular to each other, and one sub-channel region is arranged in the same row as the channel region T4Act of the data writing transistor. The scan wire GL located in the first gate layer GT1 overlaps the channel region T4Act of the data writing transistor to make the overlapping part serve as the gate T4G of the data writing transistor, and the scan wire GL overlaps one channel region of the threshold compensation transistor T2 to make the overlapping part serve as the gate of one sub-transistor of the threshold compensation transistor T2; the scan wire GL can have a side branch part, which overlaps the other channel region of the threshold compensation transistor T2 to make the overlapping part serve as the gate of the other sub-transistor of the threshold compensation transistor T2.

[0158] The channel region T5Act of the second light-emitting control transistor and the channel region T6Act of the first light-emitting control transistor are arranged in the same row, so the first enable signal line EMLA located in the first gate layer GT1 can overlap the channel region T5Act of the second light-emitting control transistor and the channel region T6Act of the first light-emitting control transistor at the same time; the part of the first enable signal line EMLA overlapping the channel region T5Act of the second light-emitting control transistor can serve as the gate T5G of the second light-emitting control transistor, and the part of the first enable signal line EMLA overlapping the channel region T6Act of the first light-emitting control transistor can serve as the gate T6G of the first light-emitting control transistor.

[0159] Figure 14 The structure of the first gate layer GT1 in the three example display panels PNL is shown in the following figures. Referring to Figure 14The first gate layer GT1 is provided with a reset control line RL and a scan wire GL extending along the row direction DH, and a first enable signal line EMLA, and a first electrode plate CP1 of a storage capacitor. Further, referring to Figure 14 In the same circuit layout area PDCA, the reset control line RL, the scan wire GL, the first electrode plate CP1 of the storage capacitor, and the first enable signal line EMLA are arranged in sequence along the column direction DV.

[0160] Figure 15 The second gate layer GT2 of the three example display panels PNL is shown in the structural diagram. Referring to Figure 15 The second gate layer GT2 is provided with an initial voltage line VinitL extending along the row direction DH, and a first metal transfer structure ML1 and a second electrode plate CP2 of a storage capacitor. The first metal transfer structure ML1 is electrically connected with the driving power supply wire VDDL in the first source-drain metal layer SD1, and can partially overlap with the source T4S of the data writing transistor. In this way, the first metal transfer structure ML1 can stabilize the source T4S of the data writing transistor, reduce the signal fluctuation on the data wire DataL to the crosstalk of the pixel driving circuit PDC, and further improve the stability of the pixel driving circuit PDC. The second electrode plate CP2 of the storage capacitor is arranged in overlap with the first electrode plate CP1 of the storage capacitor, and is electrically connected with the driving power supply wire VDDL in the first source-drain metal layer SD1 through a via. The second electrode plate CP2 of the storage capacitor has an HA exposing the first electrode plate CP1 of the storage capacitor, and the third metal transfer structure ML3 can be electrically connected with the first electrode plate CP1 of the storage capacitor through the HA. Further, in the same circuit layout area PDCA, the initial voltage line VinitL, the first metal transfer structure ML1, and the second electrode plate CP2 of the storage capacitor can be arranged in sequence along the column direction DV.

[0161] In an example, the second electrode plates CP2 of the storage capacitors in the same row adjacent circuit layout areas PDCA can be connected with each other, so that the adjacent driving power supply wires VDDL are electrically connected through the second electrode plates CP2 of the storage capacitors. In this way, the distribution grid of the driving power supply VDD can be made, and the uniformity of the driving power supply VDD can be improved.

[0162] In one example, if the circuit arrangement area PDCA is used to arrange the composite drive circuit XDC, the second electrode plate CP2 of the storage capacitor can also be arranged to overlap the channel region TNAct of the output control transistor in the metal oxide semiconductor layer SEMI2 to shield light for the channel region TNAct of the output control transistor. For example, the second electrode plate CP2 of the storage capacitor can have a light shielding area SA, and the channel region TNAct of the output control transistor can be located in the light shielding area SA in the orthographic projection of the second gate layer GT2. Of course, in other examples, the second gate layer GT2 can also be provided with a light shielding component alone, or the second gate layer GT2 can be provided with the second enable signal line EMLB to drive the output control transistor TN together with the second enable signal line EMLB in the third gate layer GT3.

[0163] Figure 16 For the display panel PNL of the first example, a structural schematic diagram of the third gate layer GT3 and the metal oxide semiconductor layer SEMI2. In the first example, only one drive circuit row HPDC in one row partition HHA is provided with the composite drive circuit XDC, and the output control transistor TN in the composite drive circuit XDC has two sub-channel regions. Referring to Figure 16 In the first example, the third gate layer GT3 is provided with the second enable signal line EMLB and the power distribution line EMLC; wherein the second enable signal line EMLB overlaps one sub-channel region of the output control transistor TN so that the overlapping part serves as the gate of one sub-transistor of the output control transistor TN; the second enable signal line EMLB has a side branch part, which overlaps another sub-channel region of the output control transistor TN so that the overlapping part serves as the gate of another sub-transistor of the output control transistor TN. At the drive circuit row HPDC without the composite drive circuit XDC, the third gate layer GT3 is provided with the power distribution line EMLC, which is used to be electrically connected with the drive power supply line VDDL in the first source-drain metal layer SD1, so as to further grid the distribution of the drive power supply VDD.

[0164] Figure 17 For the display panel PNL of the second example, a structural schematic diagram of the third gate layer GT3 and the metal oxide semiconductor layer SEMI2. In the second example, only one drive circuit row HPDC in one row partition HHA is provided with the composite drive circuit XDC, and the output control transistor TN in the composite drive circuit XDC has only one channel region. Referring to Figure 17In the second example, the third gate layer GT3 is provided with the second enable signal line EMLB and the power distribution line EMLC; wherein the second enable signal line EMLB overlaps with the channel region of the output control transistor TN so that the overlapping part serves as the gate of the output control transistor TN. At the driving circuit row HPDC where the composite driving circuit XDC is not provided, the third gate layer GT3 is provided with the power distribution line EMLC, which is used to be electrically connected with the driving power line VDDL located in the first source-drain metal layer SD1, so that the distribution of the driving power VDD is further meshed.

[0165] Figure 18 For the display panel PNL of the third example, a structural schematic diagram of the third gate layer GT3 and the metal-oxide semiconductor layer SEMI2. In the second example, wherein the two driving circuit rows HPDC in at least one row partition HHA are provided with the composite driving circuit XDC, and the output control transistor TN in the composite driving circuit XDC has only one channel region. Referring to Figure 18 In the third example, the circuit layout area PDCA corresponding to the two driving circuit rows HPDC are both provided with the second enable signal line EMLB, and the second enable signal line EMLB overlaps with the channel region TNAct of the output control transistor so that the overlapping part serves as the gate TNG of the output control transistor.

[0166] Figure 19 For the display panel PNL of the first example, a structural schematic diagram of the first source-drain metal layer SD1. Wherein the black-filled circle represents the position of the via when the first source-drain metal layer SD1 is connected with the underlying film layers (low-temperature polysilicon semiconductor layer SEMI1, first gate layer GT1, second gate layer GT2, metal-oxide semiconductor layer SEMI2, third gate layer GT3, etc.) through a via. Referring to Figure 19In the first example, the first source-drain metal layer SD1 is provided with a data wire DataL, a driving power supply wire VDDL, and the second metal transfer structure ML2, the third metal transfer structure ML3, and the fourth metal transfer structure ML4 are arranged in each circuit layout area PDCA. In the circuit layout area PDCA corresponding to the composite driving circuit XDC, the sixth metal transfer structure MN1 and the seventh metal transfer structure MN2 are further arranged. The data wire DataL is electrically connected to the source T4S of the data writing transistor through a via; the driving power supply wire VDDL is electrically connected to the first metal transfer structure ML1, the source T5S of the second light-emitting control transistor, and the second electrode plate CP2 of the storage capacitor through a via; the second metal transfer structure ML2 is electrically connected to the initial voltage line VinitL and the source T1S of the capacitor reset transistor through a via, and is further electrically connected to the source T7S of the electrode reset transistor of the pixel driving circuit PDC in the previous row through a via; the third metal transfer structure ML3 is electrically connected to the drain T1D of the capacitor reset transistor and the drain T2D of the threshold compensation transistor through a via. The fourth metal transfer structure ML4 is electrically connected to the drain T7D of the electrode reset transistor and the drain T6D of the first light-emitting control transistor through a via. The fourth metal transfer structure ML4 is further electrically connected to the fifth metal transfer structure ML5 in the second source-drain metal layer SD2 through a via, and the fifth metal transfer structure ML5 is electrically connected to the pixel electrode ANDA in the pixel electrode layer ANDL through a via, so that the pixel driving circuit PDC in the circuit layout area PDCA drives the light-emitting element DD. In the first example, the sixth metal transfer structure MN1 has two transfer parts and a transfer line connecting the two transfer parts; the first transfer part of the sixth metal transfer structure MN1 is electrically connected to the drain TND of the output control transistor through a via, the second transfer part of the sixth metal transfer structure MN1 is electrically connected to the ninth metal transfer structure MN4 in the second source-drain metal layer SD2 through a via, and the ninth metal transfer structure MN4 is used to be electrically connected to the device electrode ANDB in the pixel electrode layer ANDL through the device wire ANDBL. The seventh metal transfer structure MN2 has two transfer parts and a transfer line connecting the two transfer parts; the first transfer part of the seventh metal transfer structure MN2 is electrically connected to the source TNS of the output control transistor through a via, the second transfer part of the seventh metal transfer structure MN2 is electrically connected to the eighth metal transfer structure MN3 in the second source-drain metal layer SD2 through a via, and the eighth metal transfer structure MN3 is electrically connected to the sensing signal line SSL. In this way, the signal generated by the photodetector OPD can be forwarded to the corresponding sensing signal line SSL through the channel region TNAct of the output control transistor. In the circuit layout area PDCA corresponding to the driving circuit row HPDC without the composite driving circuit XDC, the driving power supply wire VDDL is further electrically connected to the power distribution line EMLC in the third gate layer GT3 through a via.

[0167] Figure 20 For the second example, a schematic diagram of the structure of the first source-drain metal layer SD1 in the display panel PNL. In the diagram, the black-filled circles represent the positions of the vias when the first source-drain metal layer SD1 is connected to the underlying layers (low-temperature polysilicon semiconductor layer SEMI1, first gate layer GT1, second gate layer GT2, metal-oxide semiconductor layer SEMI2, third gate layer GT3, etc.) via the vias. See Figure 20In the second example, the first source-drain metal layer SD1 is provided with a data wire DataL and a driving power supply wire VDDL, and is provided with a second metal transfer structure ML2, a third metal transfer structure ML3 and a fourth metal transfer structure ML4 in each circuit layout area PDCA. In the circuit layout area PDCA corresponding to the composite driving circuit XDC, a sixth metal transfer structure MN1 and a seventh metal transfer structure MN2 are further provided. The data wire DataL is electrically connected to the source T4S of the data writing transistor through a via; the driving power supply wire VDDL is electrically connected to the first metal transfer structure ML1, the source T5S of the second light-emitting control transistor and the second electrode plate CP2 of the storage capacitor through a via; the second metal transfer structure ML2 is electrically connected to the initial voltage line VinitL and the source T1S of the capacitor reset transistor through a via, and is further electrically connected to the source T7S of the electrode reset transistor of the pixel driving circuit PDC in the previous row through a via; the third metal transfer structure ML3 is electrically connected to the drain T1D of the capacitor reset transistor and the drain T2D of the threshold compensation transistor through a via. The fourth metal transfer structure ML4 is electrically connected to the drain T7D of the electrode reset transistor and the drain T6D of the first light-emitting control transistor through a via. The fourth metal transfer structure ML4 is further electrically connected to the fifth metal transfer structure ML5 in the second source-drain metal layer SD2 through a via, and the fifth metal transfer structure ML5 is electrically connected to the pixel electrode ANDA in the pixel electrode layer ANDL through a via, so as to drive the light-emitting element DD in the circuit layout area PDCA. In the second example, the sixth metal transfer structure MN1 has two transfer parts, the first transfer part of the sixth metal transfer structure MN1 is electrically connected to the drain TND of the output control transistor through a via, and the second transfer part of the sixth metal transfer structure MN1 is electrically connected to the ninth metal transfer structure MN4 in the second source-drain metal layer SD2 through a via, and the ninth metal transfer structure MN4 is used to be electrically connected to the device electrode ANDB in the pixel electrode layer ANDL through the device wire ANDBL. The seventh metal transfer structure MN2 has two transfer parts, the first transfer part of the seventh metal transfer structure MN2 is electrically connected to the source TNS of the output control transistor through a via, and the second transfer part of the seventh metal transfer structure MN2 is electrically connected to the eighth metal transfer structure MN3 in the second source-drain metal layer SD2 through a via, and the eighth metal transfer structure MN3 is electrically connected to the sensing signal line SSL. In this way, the signal generated by the photodetector OPD can be forwarded to the corresponding sensing signal line SSL through the channel region TNAct of the output control transistor. In the circuit layout area PDCA corresponding to the driving circuit row HPDC without the composite driving circuit XDC, the driving power supply wire VDDL is further electrically connected to the power supply arrangement wire EMLC in the third gate layer GT3 through a via.

[0168] Figure 21Fig. 3 shows a schematic diagram of the structure of the first source-drain metal layer SD1 in the display panel PNL of the third example. The black-filled circles represent the positions of the vias when the first source-drain metal layer SD1 is connected to the underlying layers (the low-temperature polysilicon semiconductor layer SEMI1, the first gate layer GT1, the second gate layer GT2, the metal-oxide semiconductor layer SEMI2, the third gate layer GT3, etc.) via the vias. The first source-drain metal layer SD1 of the display panel PNL of the third example is basically the same as the first source-drain metal layer SD1 of the display panel PNL of the second example, except that the sixth metal transfer structure MN1 and the seventh metal transfer structure MN2 are arranged in each of the two adjacent partial circuit layout areas PDCA.

[0169] Figure 22 Fig. 4 shows a schematic diagram of the structure of the second source-drain metal layer SD2 in the display panel PNL of the first example and the second example. The second source-drain metal layer SD2 is provided with a driving power supply auxiliary line VDDLA corresponding to the driving power supply line VDDL, a sensing signal line SSL corresponding to the second driving circuit column VPDCB, an eighth metal transfer structure MN3 and a ninth metal transfer structure MN4 in the circuit layout area PDCA corresponding to the composite driving circuit XDC, and a fifth metal transfer structure ML5 in each circuit layout area PDCA. The driving power supply auxiliary line VDDLA is electrically connected to the driving power supply line VDDL, for example, via a via in each circuit layout area PDCA, which can reduce the impedance of the driving power supply line VDDL and improve the uniformity of the driving power supply VDD. The eighth metal transfer structure MN3 is electrically connected to the sensing signal line SSL, and the ninth metal transfer structure MN4 is electrically connected to the seventh metal transfer structure MN2 in the first source-drain metal layer SD1, which enables the photodetector OPD connected to the ninth metal transfer structure MN4 to be connected to the sensing signal line SSL via the output control transistor TN. The fifth metal transfer structure ML5 is electrically connected to the fourth metal transfer structure ML4 in the first source-drain metal layer SD1 and to the light-emitting element DD, so that the pixel driving circuit PDC can drive the light-emitting element DD.

[0170] Figure 23A structure diagram of the display panel PNL in the third example at the second source-drain metal layer SD2. In the third example, the structure of the second source-drain metal layer SD2 is similar to that in the first example and the second example, and the only difference is that the area corresponding to the second driving circuit column VPDCB is provided with two sensing signal lines SSL for connecting two adjacent composite driving circuits XDC respectively. Correspondingly, the eighth metal transfer structure MN3 and the ninth metal transfer structure MN4 are respectively arranged in the circuit layout area PDCA corresponding to each of the two adjacent composite driving circuits XDC, and the eighth metal transfer structure MN3 is electrically connected with the corresponding sensing signal line SSL.

[0171] Figure 24 A structure diagram of the display panel PNL in the first example and the second example at the pixel electrode layer ANDL.

[0172] The pixel electrode layer ANDL is provided with a pixel electrode ANDA, a device electrode ANDB, and a device trace ANDBL. The pixel electrode ANDA is electrically connected with the fifth metal transfer structure ML5 of the second source-drain metal layer SD2 through a via at the end HC, so that the pixel driving circuit PDC drives the light emitting element DD. The device electrode ANDB is electrically connected with the ninth metal transfer structure MN4 of the second source-drain metal layer SD2 through the device trace ANDBL, so that the optical detection driving circuit MDC drives the photodetector OPD. Referring to Figure 24 , the end HB of the device trace ANDBL away from the device electrode ANDB is located in a different row partition HHA from the device electrode ANDB; this makes the photodetector OPD driven by the optical detection driving circuit MDC and the composite driving circuit XDC respectively located in different row partitions HHA.

[0173] Figure 25 A structure diagram of the display panel PNL in the third example at the pixel electrode layer ANDL. The pixel electrode layer ANDL is provided with a pixel electrode ANDA, a device electrode ANDB, and a device trace ANDBL. The pixel electrode ANDA is electrically connected with the fifth metal transfer structure ML5 of the second source-drain metal layer SD2 through a via, so that the pixel driving circuit PDC drives the light emitting element DD. The device electrode ANDB is electrically connected with the ninth metal transfer structure MN4 of the second source-drain metal layer SD2 through the device trace ANDBL, so that the optical detection driving circuit MDC drives the photodetector OPD. Referring to Figure 25The two optical detection driving circuits MDC driven by the two optical detectors OPD in the same column in the same row partition HHA are located in another adjacent row partition HHA; and the two device wires ANDBL are located on the same side of the pixel electrode ANDA. This makes the lengths of the two device wires ANDBL different. Of course, the lengths of the two device wires ANDBL can also be made the same by means of bridging or the like to improve the uniformity of the optical detectors OPD.

[0174] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the concepts disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A display panel, comprising a plurality of composite driving circuits, and a light-emitting element and a photodetector driven by the composite driving circuits; the composite driving circuits comprising a first pixel driving circuit for driving the light-emitting element and an optical detection driving circuit for driving the photodetector; in, The first pixel driving circuit includes a driving transistor and a first light-emitting control transistor; The driving transistor can output a driving current to drive the light-emitting element under the control of the voltage on the gate of the driving transistor; the driving transistor is electrically connected to the pixel electrode of the light-emitting element through the first light-emitting control transistor; The optical detection driving circuit includes an output control transistor; the device electrodes of the photodetector are electrically connected to the sensing signal line through the output control transistor. The display panel includes multiple row partitions arranged sequentially along the column direction, and each row partition is provided with an enable signal line group for loading the same enable signal; At least one of the row partitions is provided with the composite driving circuit, and the gate of the output control transistor and the gate of the first light-emitting control transistor of the composite driving circuit are electrically connected to the enable signal line group; one of the first light-emitting control transistor and the output control transistor is turned on in response to a high-level signal of the enable signal, and the other is turned on in response to a low-level signal of the enable signal; the composite driving circuit and the photodetector driven by the composite driving circuit are located in different row partitions; The display panel includes a substrate, a driving layer, and a device layer stacked sequentially. The first pixel driving circuit and the optical detection driving circuit are located in the driving layer, and the light-emitting element and the photodetector are located in the device layer; The device layer includes a pixel electrode layer, a pixel definition layer, a composite functional material layer, and a common electrode layer, which are sequentially stacked on the side of the driving layer away from the substrate; the composite functional material layer includes a photoelectric conversion material layer and an electroluminescent material layer. The pixel electrode layer includes the pixel electrode of the light-emitting element, the device electrode of the photodetector, and device traces; The device electrodes of the photodetector are electrically connected to the optical detection driving circuit that drives the photodetector through the device traces.

2. The display panel according to claim 1, wherein, The composite driving circuit and the photodetector driven by the composite driving circuit are located in two adjacent row partitions, respectively.

3. The display panel according to claim 1, wherein, The driving transistor and the first light-emitting control transistor are P-type transistors, and the output control transistor is a metal-oxide-semiconductor transistor.

4. The display panel according to claim 1, wherein, The first pixel driving circuit further includes a storage capacitor and a data writing transistor. The gate of the driving transistor is electrically connected to the storage capacitor and is used to output a driving current for driving the light-emitting element under the control of the voltage on the gate of the driving transistor. The data writing transistor is configured to write driving data into the storage capacitor.

5. The display panel according to claim 4, wherein, The first pixel driving circuit further includes a capacitor reset transistor, a threshold compensation transistor, a second light-emitting control transistor, and an electrode reset transistor, wherein, The source of the capacitor reset transistor is used to apply a first initial voltage, the drain of the capacitor reset transistor is electrically connected to the first node, and the gate of the capacitor reset transistor is used to apply a first reset signal. The source of the threshold compensation transistor is electrically connected to the third node, the drain of the threshold compensation transistor is electrically connected to the first node, and the gate of the threshold compensation transistor is used to load a scan signal. The source of the driving transistor is electrically connected to the second node, the drain of the driving transistor is electrically connected to the third node, and the gate of the driving transistor is electrically connected to the first node. The source of the data writing transistor is used to load driving data, the drain of the data writing transistor is electrically connected to the second node, and the gate of the data writing transistor is used to load a scan signal. The source of the second light-emitting control transistor is used to load the driving power supply, the drain of the second light-emitting control transistor is electrically connected to the second node, and the gate of the second light-emitting control transistor is used to load the same enable signal as the gate of the first light-emitting control transistor. The source of the first light-emitting control transistor is electrically connected to the third node, and the drain of the first light-emitting control transistor is electrically connected to the pixel electrode of the light-emitting element. The source of the electrode reset transistor is used to apply a second initial voltage, the drain of the electrode reset transistor is electrically connected to the drain of the first light-emitting control transistor, and the gate of the electrode reset transistor is used to apply a second reset signal.

6. The display panel according to claim 1, wherein, In the row partition where the composite drive circuit is provided, the enable signal line group includes at least one first enable signal line and at least one second enable signal line; The gate of each first light-emitting control transistor in the row partition is electrically connected to the first enable signal line, and the gate of the output control transistor in the row partition is electrically connected to the second enable signal line.

7. The display panel according to claim 6, wherein, The display panel includes a display area and a peripheral area surrounding the display area; the composite driving circuit is disposed in the display area; The first enable signal line and the second enable signal line pass through the display area along the row direction, and the ends of the first enable signal line and the second enable signal line of the same enable signal line group are electrically connected in the peripheral area.

8. The display panel according to claim 1, wherein, In the composite driving circuit, the wiring area of ​​the optical detection driving circuit is located within the wiring area of ​​the first pixel driving circuit.

9. The display panel according to any one of claims 1 to 7, wherein, The display panel also includes a second pixel driving circuit and a light-emitting element driven by the second pixel driving circuit.

10. The display panel according to claim 9, wherein, The composite driving circuit and the second pixel driving circuit are arranged in multiple driving circuit rows; any row partition includes one or more driving circuit rows.

11. The display panel according to claim 10, wherein, In any given row partition, at most one of the drive circuit rows has the composite drive circuit; The composite driving circuit and the second pixel driving circuit are arranged in multiple driving circuit columns; Each optical detection drive circuit located in the same drive circuit column is electrically connected to the same sensing signal line.

12. The display panel according to claim 10, wherein, The composite driving circuit and the second pixel driving circuit are arranged in multiple driving circuit columns; at least one of the multiple composite driving circuits in the driving circuit column is located in the same row partition; Multiple composite drive circuits located within the same row partition and in the same drive circuit column are respectively connected to different sensing signal lines.

13. The display panel according to claim 9, wherein, The composite driving circuit and the second pixel driving circuit are arranged in multiple driving circuit columns; The display panel includes drive power lines that correspond one-to-one with each of the drive circuit columns; Each first pixel driving circuit and second pixel driving circuit in the driving circuit array is electrically connected to the corresponding driving power supply trace. The display panel is also provided with a power busbar wiring arranged on the same layer as the enable signal line group. The power busbar wiring extends along the row direction and is electrically connected to each of the drive power lines.

14. The display panel according to claim 9, wherein, The first pixel driving circuit and the second pixel driving circuit are the same.

15. A display device comprising the display panel as described in any one of claims 1 to 14.

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