Display panel and display device

Abstract

A display panel and display device are disclosed. The display panel includes a substrate, a circuit structure layer, a light-emitting structure layer, and a plurality of transparent conductive layers. The transparent conductive layers are located between the circuit structure layer and the light-emitting structure layer, and include a plurality of first-type conductive lines and a plurality of second-type conductive lines. The portion of the first-type conductive lines extending along a first direction overlaps with the orthographic projection of the shielding electrode (60) on the substrate, while the portion of the second-type conductive lines extending along the first direction does not overlap with the orthographic projection of the shielding electrode (60) on the substrate. At least one first-type light-emitting device is connected to at least one first-pixel driving circuit (QD1) through at least one first-type conductive line, and at least one second-type first-light-emitting device is connected to at least one first-pixel driving circuit (QD1) through at least one second-type conductive line. The first-type first-light-emitting device is configured to emit first-color light, and the second-type first-light-emitting device is configured to emit second-color light, wherein the second-color light is different from the first-color light.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display panel and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Under-display camera technology is a novel technology proposed to increase the screen-to-body ratio of display devices. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, embodiments of this disclosure provide a display panel, including: a substrate, a circuit structure layer and a light-emitting structure layer stacked on the substrate, and a plurality of conductive layers disposed between the circuit structure layer and the light-emitting structure layer; wherein,

[0005] The substrate includes: a first display area and a second display area, wherein the second display area is located on at least one side of the first display area, and the light transmittance of the first display area is greater than that of the second display area;

[0006] The circuit structure layer includes: a first gate signal line, a constant voltage line, a plurality of shielding electrodes, and a plurality of pixel circuits located in the second display area. Each pixel circuit includes a driving transistor with a gate. The plurality of pixel circuits include a plurality of first pixel driving circuits. The first gate signal line is connected to the gate of the driving transistor. The constant voltage line is configured to provide a first constant voltage to the plurality of pixel circuits. The shielding electrodes are connected to the constant voltage line, and the orthographic projection of the first gate signal line onto the substrate falls within the orthographic projection of the shielding electrode onto the substrate.

[0007] The plurality of conductive layers include: a plurality of conductive lines, the plurality of conductive lines including: a plurality of first-type conductive lines and a plurality of second-type conductive lines, wherein the orthographic projection of the portion of the first-type conductive line extending along a first direction on the substrate overlaps with the orthographic projection of at least one of the plurality of shielding electrodes on the substrate, and the orthographic projection of the portion of the second-type conductive line extending along the first direction on the substrate does not overlap with the orthographic projection of the plurality of shielding electrodes on the substrate.

[0008] The light-emitting structure layer includes: a plurality of first light-emitting devices located in the first display area; the plurality of first light-emitting devices includes: a plurality of first-type first light-emitting devices and a plurality of second-type first light-emitting devices; at least one of the first-type first light-emitting devices is connected to at least one of the plurality of first-type conductive lines through at least one of the plurality of first-type conductive lines; at least one of the plurality of second-type first light-emitting devices is connected to at least one of the plurality of first-type conductive lines through at least one of the plurality of second-type conductive lines; the first pixel driving circuit is configured to drive the first light-emitting devices to emit light; the first-type first light-emitting devices are configured to emit first-color light; and the second-type first light-emitting devices are configured to emit second-color light, wherein the second-color light is different from the first-color light.

[0009] On the other hand, this disclosure also provides a display device, including a display panel as described in the above embodiments.

[0010] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings.

[0011] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects will become clear. Attached Figure Description

[0012] The accompanying drawings are provided to illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure, but do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0013] Figure 1 This is a schematic diagram of the structure of the display panel in an embodiment of this disclosure;

[0014] Figure 2 This is a plan view of the display panel in an embodiment of this disclosure;

[0015] Figure 3 This is an equivalent circuit diagram of the pixel driving circuit in the embodiments of this disclosure;

[0016] Figure 4 This is a first partial schematic diagram of the display panel in an embodiment of the present disclosure;

[0017] Figure 5This is a schematic diagram showing the conductive lines passing through shielding electrodes in the first display area of ​​some technologies;

[0018] Figure 6A This is a second partial schematic diagram of the display panel in an embodiment of this disclosure;

[0019] Figure 6B This is a third partial schematic diagram of the display panel in an embodiment of this disclosure;

[0020] Figure 6C This is a fourth partial schematic diagram of the display panel in an embodiment of this disclosure;

[0021] Figure 7 This is a schematic diagram of a first connection between the first light-emitting device and the first pixel driving circuit in an exemplary embodiment of the present disclosure.

[0022] Figure 8 for Figure 7 A schematic diagram of the connection of the first transparent conductive line in the first transparent conductive layer;

[0023] Figure 9 for Figure 7 A schematic diagram showing the connection of the second transparent conductive line in the second transparent conductive layer;

[0024] Figure 10 for Figure 7 A schematic diagram of the connection of the third transparent conductive line in the third transparent conductive layer;

[0025] Figure 11 for Figure 7 A schematic diagram of the connection of the metal conductive lines in the middle metal conductive layer;

[0026] Figure 12 This is a schematic diagram illustrating a second connection between the first light-emitting device and the first pixel driving circuit in an exemplary embodiment of the present disclosure.

[0027] Figure 13 This is a schematic diagram of a third connection between the first light-emitting device and the first pixel driving circuit in an exemplary embodiment of the present disclosure;

[0028] Figure 14 This is a schematic diagram showing the semiconductor layer formed according to an embodiment of the present disclosure;

[0029] Figure 15A This is a schematic diagram showing the formation of the first conductive layer according to an embodiment of this disclosure;

[0030] Figure 15B for Figure 15A A planar schematic diagram of the first conductive layer in the middle;

[0031] Figure 16A This is a schematic diagram showing the formation of the second conductive layer according to an embodiment of this disclosure;

[0032] Figure 16B for Figure 16A A schematic diagram of the second conductive layer in the middle;

[0033] Figure 17 This is a schematic diagram showing the formation of the fourth insulating layer according to an embodiment of this disclosure;

[0034] Figure 18A This is a schematic diagram showing the formation of the third conductive layer according to an embodiment of this disclosure;

[0035] Figure 18B for Figure 18A A schematic diagram of the third conductive layer in the middle;

[0036] Figure 19 This is a schematic diagram showing the formation of the fifth insulating layer according to an embodiment of this disclosure;

[0037] Figure 20A This is a schematic diagram showing the formation of the fourth conductive layer according to an embodiment of this disclosure;

[0038] Figure 20B for Figure 20A A schematic diagram of the fourth conductive layer in the middle;

[0039] Figure 21A This is a schematic diagram showing the formation of the first transparent conductive layer according to an embodiment of the present disclosure;

[0040] Figure 21B for Figure 21A A planar schematic diagram of the first transparent conductive layer;

[0041] Figure 22A This is a schematic diagram showing the formation of the second transparent conductive layer according to an embodiment of this disclosure;

[0042] Figure 22B for Figure 22A A planar schematic diagram of the second transparent conductive layer;

[0043] Figure 23A This is a schematic diagram showing the formation of the third transparent conductive layer according to an embodiment of the present disclosure;

[0044] Figure 23B for Figure 23A A planar schematic diagram of the third transparent conductive layer;

[0045] Figure 24A This is a first schematic diagram of an embodiment of the present disclosure after the anode layer has been formed;

[0046] Figure 24B for Figure 23A A schematic diagram of the intermediate anode layer;

[0047] Figure 24C This is a second schematic diagram after the anode layer has been formed according to an embodiment of this disclosure;

[0048] Figure 25 This is a schematic diagram showing the pixel definition layer after it has been formed according to an embodiment of this disclosure. Detailed Implementation

[0049] This document describes several embodiments, but these descriptions are exemplary and not limiting. Many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the accompanying drawings and discussed in exemplary embodiments, many other combinations of the disclosed features are possible. Unless specifically limited, any feature or element of any embodiment may be used in conjunction with, or substitute for, any other feature or element of any other embodiment.

[0050] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0051] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0052] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0053] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0054] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0055] In this specification, a transistor is a device that includes at least three terminals: a gate electrode (or control electrode), a drain electrode (drain terminal, drain region, or drain electrode), and a source electrode (source terminal, source region, or source electrode). A transistor has a channel region between the drain and source electrodes, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the area through which current primarily flows.

[0056] In this specification, to distinguish the two terminals of a transistor other than the gate electrode (gate or control electrode), one terminal is directly described as the first terminal and the other as the second terminal. The first terminal can be the drain electrode and the second terminal can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0057] The transistors used in the embodiments of this disclosure can all be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. For example, the thin-film transistors used in the embodiments of this disclosure may include, but are not limited to, oxide TFTs or low-temperature poly-silicon TFTs (LTPS TFTs). Here, the embodiments of this disclosure do not limit the scope of the application.

[0058] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0059] In this disclosure, "approximately," "roughly," and "approximately" refer to situations where there are no strict limits and the process and measurement errors are allowed. For example, in this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0060] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0061] In this embodiment, the first direction X can refer to the extension direction of the grid lines in the display area or the horizontal direction; the second direction Y can refer to the extension direction of the data lines in the display area or the vertical direction; and the third direction Z can refer to the direction perpendicular to the plane of the display panel or the thickness direction of the display panel, etc. The first direction X and the second direction Y can be perpendicular to each other, and the first direction X and the third direction Z can be perpendicular to each other.

[0062] With the development of display technology, full-screen or narrow-bezel products, with their large screen-to-body ratio and ultra-narrow bezels, have gradually become the development trend of display products. For products such as smart terminals, sensors such as camera sensors or fingerprint sensors are usually installed. To improve the screen-to-body ratio, full-screen or narrow-bezel products typically adopt under-display camera (FDC) or under-display fingerprint technology, placing the camera and other sensors in the under-display camera area of ​​the display panel. This under-display camera area not only has a certain transmittance but also has display functionality, achieving full display in the camera area (Full Display in Camera, FDC).

[0063] Figure 1 This is a schematic diagram of the structure of a display panel. (Example) Figure 1As shown, on a plane parallel to the display panel, the display area AA of the display panel may include: a first display area AA1 and a second display area AA2, where the second display area AA2 may be located on at least one side of the first display area AA1. For example, the second display area AA2 may at least partially surround the first display area AA1. For example, the second display area AA2 may include: a transition display area AAG, which is adjacent to the first display area AA1. For example, the position of the first display area AA1 may correspond to the position of the sensor, configured to display an image and transmit light, with the transmitted light being received by the sensor. The first display area AA1 may also be referred to as the sensor corresponding area, the under-display camera display area, or the light-transmitting display area, etc. For example, the second display area AA2 is configured to display an image, and the second display area AA2 may also be referred to as the normal resolution display area, the normal subpixel area, or the low transmittance display area, etc. For example, the transition display area AAG is configured to display an image and configure signal traces, which are connected to signal lines in the light-transmitting display area to lead out these signal lines. The transition display area AAG may also be referred to as a dummy subpixel area.

[0064] In one exemplary embodiment, the light transmittance of the first display area AA1 is higher than that of the second display area AA2. The light transmittance of the first display area AA1 is also higher than that of the transition display area AAG. Here, light transmittance refers to the ability of light to pass through a medium, and is the percentage of luminous flux passing through a transparent or translucent body relative to its incident luminous flux. Thus, since the position of the first display area AA1 can correspond to the position of the sensor, there is an overlap between the sensor's orthographic projection on the display panel and the first display area AA1, allowing more light to pass through the display panel and be received by the sensor. For example, "the sensor's orthographic projection on the display panel overlaps with the first display area AA1" could mean that a portion of the sensor's orthographic projection on the display panel is located within the first display area AA1, or that the entire orthographic projection of the sensor on the display panel is located within the first display area AA1, or that the sensor's photosensitive window's orthographic projection on the display panel is located within the first display area AA1, etc. This embodiment of the present disclosure does not limit this.

[0065] In one exemplary embodiment, the resolutions of the first display area AA1 and the second display area AA2 may be the same, or the resolution of the first display area AA1 may be lower than that of the second display area AA2. Resolution (Pixels Per Inch, PPI) refers to the number of pixels per unit area, also known as pixel density. A higher PPI value indicates that the display panel can display images at a higher density, resulting in richer image details.

[0066] In one exemplary embodiment, the first display area AA1 may be located at the upper part, lower part, or edge of the display area of ​​the display panel. For example, the first display area AA1 may be located at the top center of the display area of ​​the display panel, and the second display area AA2 may surround the first display area AA1. Alternatively, the first display area AA1 may be located at other positions such as the upper left or upper right corner of the display area of ​​the display panel, and the second display area AA2 may surround at least one side of the first display area AA1 (e.g., one side, the top and bottom sides, or the left and right sides). Here, the embodiments of this disclosure do not limit this.

[0067] In one exemplary embodiment, the shape of the first display area AA1 in a plane parallel to the display panel can be any one or more of the following: square, rectangle, polygon, circle, elliptical semicircle, or pentagon, etc. For example, the shape of the display area of ​​the display panel can be rectangular, such as a rounded rectangle, and the first display area AA1 can be circular. Here, the embodiments of this disclosure do not limit this.

[0068] In one exemplary embodiment, the shape of the outer contour of the transition display area AAG in a plane parallel to the display panel can be any one or more of the following: rectangle, polygon, circle, and ellipse, etc. This disclosure does not limit this aspect.

[0069] In one exemplary embodiment, the sensor may include, but is not limited to, a camera sensor, a fingerprint sensor, a light sensor, an infrared sensor, an ultrasonic sensor, a LiDAR (Light Detection and Ranging) sensor, or a radar sensor. This disclosure does not limit the scope of the sensor.

[0070] In one exemplary embodiment, on a plane perpendicular to the display panel, the first display area AA1 may include: a first circuit structure layer disposed on a substrate and a first light-emitting structure layer disposed on the side of the first circuit structure layer away from the substrate. The second display area AA2 may include a second circuit structure layer disposed on a substrate and a second light-emitting structure layer disposed on the side of the second circuit structure layer away from the substrate.

[0071] In one exemplary embodiment, the first circuit structure layer of the first display area AA1 includes multiple stacked insulating layers, which may be referred to as a composite insulating layer. The first light-emitting structure layer of the first display area AA1 may include multiple functional sub-pixels, each of which may include a first light-emitting device sp1. The first light-emitting device sp1 may include at least a first anode. The first anode of at least one functional sub-pixel is connected via a conductive line (e.g., a transparent conductive line) to at least one first pixel driving circuit QD1 in the transition display area AAG of the second display area AA2. The first pixel driving circuit QD1 is configured to output a corresponding current to the connected first light-emitting device sp1 via the conductive line. The first light-emitting device sp1 is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0072] In one exemplary embodiment, the second circuit structure layer of the second display area AA2 may include a plurality of first pixel driving circuits QD1 and a plurality of second pixel driving circuits QD2. This second circuit structure layer may be referred to as a driving structure layer. The area in the second display area AA2 where the first pixel driving circuits QD1 are disposed may be referred to as a transition display area AAG. The second light-emitting structure layer of the second display area AA2 may include a plurality of normal sub-pixels. Each normal sub-pixel may include a second light-emitting device sp2. The second light-emitting device sp2 may include at least a second anode. The second anode of at least one normal sub-pixel is connected to at least one second pixel driving circuit QD2. The second pixel driving circuit QD2 is configured to directly output a corresponding current to the connected second light-emitting device sp2. The second light-emitting device sp2 is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0073] For example, if the first light-emitting device sp1 and the first pixel driving circuit QD1 that drives it are located in different display areas, then the first light-emitting device sp1 can be called a non-in-situ driven light-emitting device, and the first pixel driving circuit QD1 can be called a non-in-situ pixel driving circuit. Similarly, if the second light-emitting device sp2 and the second pixel driving circuit QD2 that drives it are both located in the second display area AA2, then the second light-emitting device sp2 can be called an in-situ driven light-emitting device, and the second pixel driving circuit QD2 can be called an in-situ pixel driving circuit.

[0074] In one exemplary embodiment, the display area of ​​the display panel may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P may include a plurality of sub-pixels. A sub-pixel may be the smallest portion with controllable brightness. At least one sub-pixel may include a light-emitting device and a pixel driving circuit connected to the light-emitting device, the pixel driving circuit being configured to drive the connected light-emitting device to emit light.

[0075] In one exemplary embodiment, the light-emitting device can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting device can be an OLED, which emits red, green, blue, or white light under the drive of its corresponding pixel driving circuit.

[0076] In one exemplary embodiment, taking an OLED as an example, the light-emitting device may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting device may be electrically connected to a corresponding pixel driving circuit.

[0077] In one exemplary embodiment, the color of the light emitted by the light-emitting device can be determined by those skilled in the art based on the actual application scenario. For example, at least one of the plurality of pixel units P may include three sub-pixels, which may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. As another example, at least one of the plurality of pixel units P may include four sub-pixels, which may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively. This disclosure does not limit the scope of the embodiments.

[0078] In one exemplary embodiment, the shape of the light-emitting device may be rectangular, rhomboid, pentagonal, or hexagonal, etc.

[0079] In one exemplary embodiment, multiple sub-pixels in a pixel unit can be arranged in various ways, such as horizontally side-by-side, vertically side-by-side, X-shaped, cross-shaped, or triangular. For example, if a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or triangularly. Similarly, if a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, square, or diamond-shaped. Figure 2 As shown, taking four sub-pixels—one red sub-pixel, one blue sub-pixel, and two green sub-pixels—as an example, the four sub-pixels can be arranged in a diamond shape to form an RGGB pixel arrangement. However, this embodiment of the present disclosure does not limit this arrangement.

[0080] In one exemplary embodiment, the arrangement of pixel units in the first display area AA1 may be the same as or different from the arrangement of pixel units in the second display area AA2. The number of sub-pixels included in a pixel unit in the first display area AA1 may be the same as or different from the number of sub-pixels included in a pixel unit in the second display area AA2. The arrangement of the sub-pixels included in a pixel unit in the first display area AA1 may be the same as or different from the arrangement of the sub-pixels included in a pixel unit in the second display area AA2. This embodiment of the present disclosure does not limit this aspect.

[0081] In one exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.

[0082] In one exemplary embodiment, the pixel driving circuit of this exemplary embodiment adopts a 7T1C structure as an example for description. Figure 3 The equivalent circuit diagram of the pixel driving circuit in the embodiments of this disclosure is shown below. Figure 3 As shown, the pixel driving circuit may include seven transistors (transistor T1 to transistor T7) and a storage capacitor Cst. The pixel driving circuit can be connected to eight signal lines (scan signal line GL, data signal line DL, first power supply line PL1, second power supply line PL2, light emission control line EML, first initial signal line INIT1, second initial signal line INIT2, first reset control line RST1, and second reset control line RST2). Specifically, transistor T3 can also be called the driving transistor, transistor T4 can also be called the data writing transistor, transistor T2 can also be called the threshold compensation transistor, transistor T5 can also be called the first light emission control transistor, transistor T6 can also be called the second light emission control transistor, transistor T1 can also be called the first reset transistor, and transistor T7 can also be called the second reset transistor.

[0083] In one exemplary embodiment, transistors can be categorized into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0084] In one exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the manufacturing process, reduces the manufacturing difficulty of the display panel, and improves product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0085] In one exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display panel to form a low-temperature polycrystalline oxide (LTPO) display panel leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0086] In one exemplary embodiment, such as Figure 3As shown, the display panel may include: a scan signal line GL, a data signal line DL, a first power line PL1, a second power line PL2, an emissive control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. In an exemplary embodiment, the first power line PL1 may be configured to provide a constant first voltage signal VDD to the pixel driving circuit, and the second power line PL2 may be configured to provide a constant second voltage signal VSS to the pixel driving circuit, wherein the first voltage signal VDD is greater than the second voltage signal VSS. The scan signal line GL may be configured to provide a scan signal SCAN to the pixel driving circuit, the data signal line DL may be configured to provide a data signal DATA to the pixel driving circuit, the emissive control line EML may be configured to provide an emissive control signal EM to the pixel driving circuit, the first reset control line RST1 may be configured to provide a first reset control signal RESET1 to the pixel driving circuit, and the second reset control line RST2 may be configured to provide a second reset control signal RESET2 to the pixel driving circuit. In one exemplary embodiment, in the nth row pixel driving circuit, the first reset control line RST1 can be electrically connected to the scan signal line GL of the (n-1)th row pixel driving circuit to be input with the scan signal SCAN(n-1), i.e., the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). The second reset control line RST2 can be electrically connected to the scan signal line GL of the nth row pixel driving circuit to be input with the scan signal SCAN(n), i.e., the second reset control signal RESET2(n) is the same as the scan signal SCAN(n). In one exemplary embodiment, the second reset control line RST2 electrically connected to the nth row pixel driving circuit and the first reset control line RST1 electrically connected to the (n+1)th row pixel driving circuit can be a single integrated structure. Here, n is an integer greater than 0. This reduces the number of signal lines on the display panel, enabling a narrow bezel design for the display panel. However, this embodiment is not limited to this.

[0087] In one exemplary embodiment, a first initial signal line INIT1 can be configured to provide a first initial signal to a pixel driving circuit, and a second initial signal line INIT2 can be configured to provide a second initial signal to the pixel driving circuit. For example, the first initial signal may be different from the second initial signal. Both the first and second initial signals can be constant voltage signals, the magnitude of which may be, for example, between a first voltage signal VDD and a second voltage signal VSS, but are not limited thereto. In other examples, the first and second initial signals may be the same, and only the first initial signal line may be configured to provide the first initial signal.

[0088] In one exemplary embodiment, to save wiring, the first power line PL1 can be used as a constant voltage line. For example, in other examples, the first initial signal line INIT1 can also be used as a constant voltage line to save wiring. Examples of constant voltage lines are not limited to the first power line PL1 and the first initial signal line INIT1; any signal line that provides a constant voltage in the pixel circuit can be used as a constant voltage line.

[0089] In one exemplary embodiment, the scan signal line GL, the light emission control line EML, the first initial signal line INIT1, the second initial signal line INIT2, the first reset control line RST1, and the second reset control line RST2 can extend in the horizontal direction, and the first power line PL1, the second power line PL2, and the data signal line DL can extend in the vertical direction.

[0090] In one exemplary embodiment, such as Figure 3As shown, the third transistor T3 is electrically connected to the light-emitting device EL, and outputs a drive current to drive the light-emitting device EL to emit light under the control of signals such as the scan signal SCAN, data signal DATA, first voltage signal VDD, and second voltage signal VSS. The gate of the fourth transistor T4 is electrically connected to the scan signal line GL, the first terminal of the fourth transistor T4 is electrically connected to the data signal line DL, and the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the third transistor T3. The gate of the second transistor T2 is electrically connected to the scan signal line GL, the first terminal of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the second terminal of the second transistor T2 is electrically connected to the second terminal of the third transistor T3. The gate of the fifth transistor T5 is electrically connected to the light-emitting control line EML, the first terminal of the fifth transistor T5 is electrically connected to the first power supply line PL1, and the second terminal of the fifth transistor T5 is electrically connected to the first terminal of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the light-emitting control line EML, the first terminal of the sixth transistor T6 is electrically connected to the second terminal of the third transistor T3, and the second terminal of the sixth transistor T6 is electrically connected to the anode of the light-emitting device EL. The gates of the first transistor T1 and the third transistor T3 are electrically connected and configured to reset the gate of the third transistor T3. The seventh transistor T7 is electrically connected to the anode of the light-emitting device EL and configured to reset the anode of the light-emitting device EL. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first terminal of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second terminal of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first terminal of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second terminal of the seventh transistor T7 is electrically connected to the anode of the light-emitting device EL. The first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second capacitor plate of the storage capacitor Cst is electrically connected to the first power supply line PL1.

[0091] In one exemplary embodiment, such as Figure 3 As shown, the pixel driving circuit may include: a first node N1, a second node N2, a third node N3, and a fourth node N4. Specifically, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3, and the second transistor T2; the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, and the third transistor T3; the third node N3 is the connection point of the third transistor T3, the second transistor T2, and the sixth transistor T6; and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting device EL. The fourth node N4 is the anode connection node.

[0092] In one exemplary embodiment, the light-emitting device EL can be an organic light-emitting diode (OLED), including an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0093] The following is based on Figure 3 Taking the pixel driving circuit shown as an example where all transistors are P-type transistors, for instance... Figure 3 The operation of the pixel driving circuit shown will be explained.

[0094] In one exemplary embodiment, the operation of the pixel driving circuit during a frame display time period may include: a first stage S1, a second stage S2, and a third stage S3.

[0095] The first stage, S1, is called the reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first transistor T1. The first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize N1 and clear the original data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan signal line GL is a high-level signal, and the light emission control signal EM provided by the light emission control line EML is a high-level signal, turning off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this stage, the light-emitting device EL does not emit light.

[0096] The second stage, S2, is called the data writing stage or threshold compensation stage. The scan signal SCAN provided by the scan signal line GL is a low-level signal, while the first reset control signal RESET1 provided by the first reset control line RST1 and the light emission control signal EM provided by the light emission control line EML are both high-level signals. The data signal line DL outputs the data signal DATA. During this stage, because the first capacitor plate of the storage capacitor Cst is low, the third transistor T3 is turned on. The low-level scan signal SCAN turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on, allowing the data voltage Vdata output from the data signal line DL to be supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output from the data signal line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage at the first capacitor plate of the storage capacitor Cst (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output from the data signal line DL, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the anode of the light-emitting device EL, initializing (resetting) the anode of the light-emitting device EL, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the light-emitting device EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, causing the first transistor T1 to turn off. The light emission control signal EM provided by the light emission control signal line EML is a high-level signal, which disconnects the fifth transistor T5 and the sixth transistor T6.

[0097] The third stage, S3, is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, while the scan signal SCAN provided by the scan signal line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. When the light-emitting control signal EM provided by the light-emitting control signal line EML is low, the fifth transistor T5 and the sixth transistor T6 are turned on. The first voltage signal VDD output from the first power supply line PL1 provides a driving voltage to the anode of the light-emitting device EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting device EL to emit light.

[0098] During the pixel circuit driving process, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and its first terminal. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0099] I = K × (Vgs - Vth)2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 .

[0100] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data signal line DL, and VDD is the first voltage signal output by the first power supply line PL1.

[0101] As can be seen from the above formula, the current flowing through the light-emitting device EL is independent of the threshold voltage of the third transistor T3. Therefore, the pixel driving circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3.

[0102] Figure 4 This is a first partial schematic diagram of the display panel in an embodiment of this disclosure. Figure 1 The enlarged view of the Q region illustrates the planar structure of the area near the transitional display area AAG in the first display area AA1, and also illustrates the planar structure of the transitional display area AAG and its surrounding area in the second display area AA2.

[0103] In one exemplary embodiment, such as Figure 4 As shown, the first display area AA1 can only have a first light-emitting device sp1, without the first pixel driving circuit QD1 driving the first light-emitting device sp1, so that the first display area AA1 can both display and transmit light. For example, the first light-emitting device sp1 can include at least a first anode, and at least one first pixel driving circuit QD1 in the transition display area AAG of the second display area AA2 is connected to the first anode of at least one first light-emitting device sp1 through a conductive line L (e.g., a transparent conductive line). The conductive line L can extend from the first display area AA1 to the transition display area AAG of the second display area AA2. In this way, by placing the first pixel driving circuit QD1 driving the first light-emitting device sp1 in the transition display area AAG of the second display area AA2, the occlusion of light by the pixel driving circuit can be reduced, thereby increasing the transmittance of the first display area AA1. For example, taking the first pixel driving circuit QD1 as... Figure 3 Taking the pixel driving circuit of 7T1C as an example, one end of the conductive line L (e.g., a transparent conductive line) can be electrically connected to the fourth node N4 (i.e., the anode connection node) of the first pixel driving circuit QD1, and the other end of the conductive line L can be electrically connected to the first anode of the first light-emitting device sp1.

[0104] In one exemplary embodiment, such as Figure 4 As shown, the second display area AA2 may include: a plurality of first pixel driving circuits QD1, a plurality of second pixel driving circuits QD2, and a plurality of second light-emitting devices sp2. At least one of the plurality of second pixel driving circuits QD2 is configured to be connected to at least one second light-emitting device sp2 in the second display area AA2. The second pixel driving circuit QD2 is configured to directly output a corresponding current to the connected second light-emitting device sp2, causing the second light-emitting device sp2 to emit light of a corresponding brightness. That is, the second light-emitting device sp2 electrically connected to the second pixel driving circuit QD2 may be located within the second display area AA2, and all or part of the second light-emitting device sp2 may be located within the second display area AA2. For example, the orthographic projection of at least one second pixel driving circuit QD2 onto the substrate and the orthographic projection of at least one second light-emitting device sp2 onto the substrate may at least partially overlap.

[0105] In one exemplary embodiment, such as Figure 4 As shown, the transition display area AAG in the second display area AA2 may include: a plurality of first pixel driving circuits QD1. At least one of the plurality of first pixel driving circuits QD1 can be connected to at least one first light-emitting device sp1 in the first display area AA1 via a conductive line L. The at least one first pixel driving circuit QD1 is configured to output a corresponding current to the connected first light-emitting device sp1 via the conductive line L, causing the first light-emitting device sp1 to emit light of a corresponding brightness. That is, the first light-emitting device sp1 electrically connected to the first pixel driving circuit QD1 can be located in a different display area from the first pixel driving circuit QD1. For example, the orthographic projection of at least one first pixel driving circuit QD1 on the substrate and the orthographic projection of at least one first light-emitting device sp1 on the substrate may not overlap. In an exemplary embodiment, as shown... Figure 4 As shown, the transition display area AAG may further include: a plurality of second pixel driving circuits QD2 and a plurality of second light-emitting devices sp2. At least one of the plurality of second pixel driving circuits QD2 can be connected to at least one second light-emitting device sp2 in the transition display area AAG. The second pixel driving circuit QD2 is configured to directly output a corresponding current to the connected second light-emitting device sp2, causing the second light-emitting device sp2 to emit light of a corresponding brightness. In an exemplary embodiment, one or more second pixel driving circuits QD2 may be provided between adjacent first pixel driving circuits QD1. For example, two second pixel driving circuits QD2 may be provided between adjacent first pixel driving circuits QD1, or, as... Figure 4 As shown, four second pixel driving circuits QD2, etc., can be arranged between adjacent first pixel driving circuits QD1. However, this embodiment does not limit this.

[0106] In one exemplary embodiment, such as Figure 4 As shown, the transition display area AAG may also include an invalid pixel driving circuit QD0. Setting up an invalid pixel driving circuit can help improve the uniformity of components in multiple film layers during the etching process, ensuring the uniformity of the display panel. For example, the invalid pixel driving circuit can have a structure roughly the same as the first pixel driving circuit QD1 and the second pixel driving circuit QD2 in the same row or column, except that it is not electrically connected to any light-emitting device.

[0107] In one exemplary embodiment, the conductive line L may be made of a transparent conductive material. For example, the transparent conductive material may be a conductive oxide material, such as indium tin oxide (ITO). This disclosure does not limit the scope of the embodiment.

[0108] In this exemplary embodiment, the pixel driving circuit refers to a region divided according to the substrate structure layer, and the light-emitting device refers to a region divided according to the light-emitting structure layer. For example, the positions of the light-emitting device and the pixel driving circuit driving the light-emitting device may correspond, or they may not correspond. For example, multiple second light-emitting devices sp2 in the transition display area AAG can be arranged normally with conventional spacing, while some second pixel driving circuits QD2 in the transition display area AAG can be arranged compactly with small spacing to leave space for the first pixel driving circuit QD1 driving the first light-emitting device sp1. In this case, the positions of the second light-emitting devices sp2 and the second pixel driving circuit QD2 in the transition display area AAG do not correspond. As another example, multiple first light-emitting devices sp1 are disposed in the first display area AA1, while the first pixel driving circuit QD1 is disposed in the transition display area AAG. In this case, the positions of the first light-emitting devices sp1 in the first display area AA1 and the first pixel driving circuit QD1 driving the first light-emitting device sp1 do not correspond.

[0109] In one exemplary embodiment, in the transition display area AAG, the area where the first pixel driving circuit QD1 is disposed can be obtained by reducing the size of the second pixel driving circuit QD2. For example, the area where the first pixel driving circuit QD1 is disposed can be obtained by reducing the size of the second pixel driving circuit QD2 in the first direction X; or, the area where the first pixel driving circuit QD1 is disposed can be obtained by reducing the size of the second pixel driving circuit QD2 in the second direction Y; or, the area where the first pixel driving circuit QD1 is disposed can be obtained by reducing the size of the second pixel driving circuit QD2 in the first direction X and the second direction Y. Here, the embodiments of this disclosure do not limit this.

[0110] For example, taking the area where the first pixel driving circuit QD1 is disposed as an example, by reducing the size of the second pixel driving circuit QD2 in the first direction X, for example, as... Figure 4 As shown, the original 'a' column pixel driving circuits can be compressed along the first direction X, thereby adding space for one more column of pixel driving circuits. The space occupied by the 'a' column pixel driving circuits before compression and the 'a+1' column pixel driving circuits after compression can be the same. Here, 'a' can be an integer greater than 1, for example, 'a' can be equal to 2, 3, or 4. For example, the second pixel driving circuit QD2 and the first pixel driving circuit QD1 can typically be arranged in a 2-over-1, 3-over-1, or 4-over-1 manner along the first direction X, compressing 2, 3, or 4 second pixel driving circuits QD2 along the first direction X to leave one position for the first pixel driving circuit QD1. This embodiment of the present disclosure does not limit this. In this case, the size of the second pixel driving circuit QD2 along the first direction X can be smaller than the size of the second light-emitting device sp2 along the first direction X.

[0111] For example, taking the reduction of the size of the second pixel driving circuit QD2 in the second direction Y to obtain the area for setting the first pixel driving circuit QD1 as an example, the original b rows of pixel driving circuits can be compressed along the second direction Y, thereby adding a row of pixel driving circuits. The space occupied by the b rows of pixel driving circuits before compression and the b+1 rows of pixel driving circuits after compression is the same. Here, b can be an integer greater than 1. For example, b can be equal to 2, 3, or 4. In this case, the size of the second pixel driving circuit QD2 in the second direction Y can be smaller than the size of the second light-emitting device sp2 in the second direction Y.

[0112] In one exemplary embodiment, since the transition display area AAG is provided with not only a first pixel driving circuit QD1 electrically connected to the first light-emitting device sp1, but also a second pixel driving circuit QD2 electrically connected to the second light-emitting device sp2, the number of pixel driving circuits in the transition display area AAG can be greater than the number of first light-emitting devices sp1 in the first display area AA1.

[0113] In one exemplary embodiment, a shielding electrode 60 is provided in the display panel to reduce crosstalk between the capacitances of conductive lines (such as ITO traces) to the first node N1. Figure 5 This is a schematic diagram showing the conductive lines passing through the shielding electrode in the first display area AA1 of some technologies, such as... Figure 5As shown, the shielding electrode 60 below the conductive lines is irregularly shaped and reflective, causing uneven line widths of the multiple conductive lines L (1 to 7) passing through the shielding electrode 60. Specifically, the conductive lines passing through wider sections of the shielding electrode 60 are thinner, while those passing through narrower sections are wider. This results in significant capacitance differences between conductive lines in the same row and between adjacent pixels, leading to a display inhomogeneity (mura) problem.

[0114] like Figure 5 As shown, taking the conductive line passing through the wider part of the shielding electrode 60 as conductive line 7 and the conductive line passing through the narrower part of the shielding electrode 60 as conductive line 3 as an example, the inventors of this disclosure have measured the line widths of the conductive lines passing through the wider and narrower parts of the shielding electrode 60 as shown in Table 1. In Table 1, CD(7) refers to the line width of the conductive line 7 passing through the shielding electrode 60 for different display panels, representing the line width of the conductive line passing through the widest part of the shielding electrode 60; CD(3) refers to the line width of the conductive line 3 passing through the shielding electrode 60 for different display panels, representing the line width of the conductive line passing through the narrowest part of the shielding electrode 60.

[0115] Table 1. Measured linewidth of conductive wire L passing through the shielding electrode.

[0116] Display panel CD(7) CD(3) Panel1 1.85 1.90 Panel2 1.76 2.03 Panel3 1.67 1.89 Panel4 1.71 1.94 Panel5 1.82 1.98 Panel6 1.85 1.98 Panel7 1.80 1.98 Average line width 1.78 1.96

[0117] Analysis of the data shown in Table 1 reveals that due to the irregular shape of the shielding electrode 60, i.e., the inconsistent width of the shielding electrode 60, the linewidth (critical dimension, CD) of the conductive lines differs by approximately 0.2 μm. This results in a capacitance difference of approximately 0.1 fF between conductive lines (such as ITO traces) within a single pixel unit. Furthermore, considering the pixel driving circuit... Figure 3 Taking the pixel driving circuit of the 7T1C shown as an example, one end of the conductive line L can be electrically connected to the fourth node N4 (i.e., the anode connection node) of the first pixel driving circuit QD1, and the other end of the conductive line L can be electrically connected to the anode of the first light-emitting device sp1. Since the conductive line L extends from the first display area AA1 to the transition display area AAG to realize the electrical connection between the first pixel driving circuit QD1 and the first light-emitting device sp1, the length of the conductive line L is relatively long. As a result, the capacitance between the conductive lines (such as ITO traces) in a pixel unit may differ by several hundred fF. Thus, at low grayscale, due to the long turn-on time and the large node capacitance of the fourth node N4 (i.e., the anode connection node), the capacitance difference between the conductive lines (such as ITO traces) of adjacent pixels in the same row is large, which will greatly affect the turn-on time and cause the mura problem.

[0118] In some examples, the capacitance differences of the conductive lines in the display panel are significant. The varying lengths of the conductive lines of multiple light-emitting devices located in the first display area AA1 result in different capacitance variations among light-emitting devices emitting different colors of light. The capacitance difference of the conductive lines connected to red-emitting devices is greater than that of the conductive lines connected to blue-emitting devices, while the capacitance difference of the conductive lines connected to green-emitting devices is larger. This significant capacitance difference in the conductive lines connected to green-emitting devices reduces the emission time of the green-emitting devices, leading to brightness differences in the display panel and causing display defects. At low grayscale levels, the defect severity of green-emitting devices is greater than that of red-emitting devices, and the defect severity of red-emitting devices is greater than that of blue-emitting devices. For example, at the same grayscale level, the driving current for blue-emitting devices can be greater than that for red-emitting devices, and the driving current for red-emitting devices can be greater than that for green-emitting devices. The driving current for green-emitting light-emitting devices is the smallest among the three primary color light-emitting devices. Therefore, when the capacitance of the fourth node N4 (i.e., the anode connection node) of light-emitting devices emitting different colors is the same, the green-emitting light-emitting device will turn on later than the red-emitting and blue-emitting light-emitting devices. At low grayscale levels, using a connection method from near to far will result in some green-emitting light-emitting devices not turning on, affecting the display effect.

[0119] This disclosure provides a display panel, which may include: a substrate, a circuit structure layer and a light-emitting structure layer stacked on the substrate, and a plurality of conductive layers disposed between the circuit structure layer and the light-emitting structure layer; wherein, the substrate includes: a first display area and a second display area, the second display area being located on at least one side of the first display area, and the light transmittance of the first display area being greater than that of the second display area; the circuit structure layer includes: a first gate signal line, a constant voltage line, a plurality of shielding electrodes, and a plurality of pixel circuits located in the second display area, the pixel circuits including driving transistors, the driving transistors including gates, and the plurality of pixel circuits including a plurality of first pixel driving circuits; the first gate signal line is connected to the gate of the driving transistor; the constant voltage line is configured to provide a first constant voltage to the plurality of pixel circuits; the shielding electrodes are connected to the constant voltage line, and the orthographic projection of the first gate signal line on the substrate falls within the orthographic projection of the shielding electrode on the substrate; the plurality of conductive layers include: a plurality of conductive lines, the plurality of conductive lines including: a plurality of first-type conductive lines and a plurality of second-type conductive lines, the orthographic projection of the portion of the first-type conductive lines extending along a first direction on the substrate being connected to the plurality of first-pixel driving circuits; the first gate signal line is connected to the gate of the driving transistor; the constant voltage line is configured to provide a first constant voltage to the plurality of pixel circuits; the shielding electrodes are connected to the constant voltage line, and the orthographic projection of the first-type conductive lines extending along a first direction on the substrate is connected to the first-pixel driving circuits; the first gate signal line is connected to the gate of the driving transistor; the constant voltage line is configured to provide a first constant voltage to the plurality of pixel circuits; the shielding electrodes are connected to the constant voltage line, and the shielding electrodes are connected to the shielding electrodes; the shielding electrodes are connected to the shielding electrodes; the shielding electrodes are connected to the shielding electrodes; the shielding electrodes are connected to the shielding electrodes; the shielding At least one of the shielding electrodes overlaps in its orthographic projection onto the substrate, while the orthographic projection of the portion of the second type of conductive line extending along the first direction does not overlap with the orthographic projection of the plurality of shielding electrodes onto the substrate; the light-emitting structure layer includes: a plurality of first light-emitting devices located in the first display area, the plurality of first light-emitting devices including: a plurality of first-type first light-emitting devices and a plurality of second-type first light-emitting devices, at least one of the first-type first light-emitting devices being connected to at least one of the plurality of first-type conductive lines through at least one of the plurality of first-type conductive lines, at least one of the plurality of second-type first light-emitting devices being connected to at least one of the plurality of first-type first-pixel driving circuits through at least one of the plurality of second-type conductive lines, the first pixel driving circuit being configured to drive the first light-emitting devices to emit light, the first-type first light-emitting devices being configured to emit first-color light, the second-type first light-emitting devices being configured to emit second-color light, the second-color light being different from the first-color light.

[0120] Thus, in the display panel provided by the exemplary embodiments of this disclosure, on the one hand, by ensuring that the orthographic projections of the first type of conductive lines connected to the first type of first light-emitting devices overlap with those of the shielding electrodes on the substrate, the uniformity of the linewidth of the first type of conductive lines can be maintained, resulting in a smaller capacitance difference among the first type of conductive lines. On the other hand, by ensuring that the orthographic projections of the second type of conductive lines connected to the second type of first light-emitting devices do not overlap with those of the shielding electrodes on the substrate, the uniformity of the linewidth of the second type of conductive lines can be maintained, resulting in a smaller capacitance difference among the second type of conductive lines. Therefore, by optimizing the wiring arrangement, brightness differences can be improved, and the display effect can be enhanced.

[0121] In one exemplary embodiment, the shielding electrode can be a regular shape, for example, a rectangle. Thus, by setting the shielding electrode to a rectangular shape, the routing environment of the first type of conductive lines can be kept consistent, the linewidth uniformity of the first type of conductive lines can be improved, and the capacitance difference of the first type of conductive lines can be minimized.

[0122] In one exemplary embodiment, the plurality of first light-emitting devices in the first display area may include: a plurality of groups of first light-emitting devices. The first light-emitting devices in each group of the plurality of groups of first light-emitting devices may be arranged along a first direction X, and the plurality of groups of first light-emitting devices may be arranged along a second direction Y. The second direction Y intersects the first direction X; for example, the second direction is perpendicular to the first direction. In at least one group of first light-emitting devices sp1, the plurality of first pixel driving circuits QD1 electrically connected to the plurality of first-type first light-emitting devices are closer to the first display area than each of the plurality of first pixel driving circuits QD1 electrically connected to the plurality of second-type first light-emitting devices. This reduces the difference in the length of the conductive lines connecting the first-type first light-emitting devices, thereby mitigating or avoiding display defects.

[0123] In one exemplary embodiment, taking a transparent conductive layer as an example, the display panel may include three transparent conductive layers, which may include a first transparent conductive layer, a second transparent conductive layer, and a third transparent conductive layer sequentially disposed along a side away from the substrate. The first transparent conductive layer may include multiple first transparent conductive lines, the second transparent conductive layer may include multiple second transparent conductive lines, and the third transparent conductive layer may include multiple third transparent conductive lines. For example, the orthographic projections of the portions of the first transparent conductive lines extending along the first direction, the portions of the second transparent conductive lines extending along the first direction, and the portions of the third transparent conductive lines extending along the first direction onto the substrate may not overlap, i.e., there are no overlapping traces. For example, the orthographic projections of the portions of the third transparent conductive lines extending along the first direction and the portions of the second transparent conductive lines extending along the first direction onto the substrate may not overlap, i.e., there are no overlapping traces. For example, the dimensions of the portions of the first transparent conductive lines extending along the first direction X in the second direction Y, the portions of the second transparent conductive lines extending along the first direction X in the second direction Y, and the portions of the third transparent conductive lines extending along the first direction X in the second direction Y may be approximately the same.

[0124] In one exemplary embodiment, among at least one group of first light-emitting devices in the first display area, a plurality of first-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via a first transparent conductive line, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via a third transparent conductive line.

[0125] In one exemplary embodiment, among at least one group of first light-emitting devices in the first display area, a plurality of first-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via a first transparent conductive line, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via a second transparent conductive line.

[0126] In one exemplary embodiment, among at least one group of first light-emitting devices in the first display area, a plurality of first-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via a second transparent conductive line, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits in the second display area via a first transparent conductive line.

[0127] In one exemplary embodiment, among at least one group of first light-emitting devices in the first display area, a plurality of first-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via a third transparent conductive line, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits in the second display area via a first transparent conductive line.

[0128] In one exemplary embodiment, among at least one group of first light-emitting devices in the first display area, a plurality of second-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via a first transparent conductive line, and a plurality of second-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via a third transparent conductive line.

[0129] In one exemplary embodiment, among at least one group of first light-emitting devices in the first display area, the transparent conductive lines electrically connected to a plurality of second-type first light-emitting devices near the center of the first display area are of the same type as the transparent conductive lines electrically connected to a plurality of first-type first light-emitting devices near the center of the first display area; or, the transparent conductive lines electrically connected to a plurality of second-type first light-emitting devices near the edge of the first display area are of the same type as the transparent conductive lines electrically connected to a plurality of first-type first light-emitting devices near the edge of the first display area.

[0130] In one exemplary embodiment, among at least one group of first light-emitting devices in the first display area, the transparent conductive lines electrically connected to a plurality of second-type first light-emitting devices near the center of the first display area are of a different type than the types of electrical connections of the plurality of first-type first light-emitting devices near the center of the first display area; or, the transparent conductive lines electrically connected to a plurality of second-type first light-emitting devices near the edge of the first display area are of a different type than the types of transparent conductive lines electrically connected to the plurality of first-type first light-emitting devices near the edge of the first display area.

[0131] In one exemplary embodiment, among at least one group of first light-emitting devices in the first display area, a plurality of second-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via a first transparent conductive line, and a plurality of second-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via a third transparent conductive line.

[0132] In one exemplary embodiment, among at least one group of first light-emitting devices in the first display area, a plurality of first-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via a first transparent conductive line; a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via a third transparent conductive line; and a plurality of first-type first light-emitting devices located between the plurality of first-type first light-emitting devices near the center of the first display area and the plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via a second transparent conductive line. In the at least one group of first light-emitting devices in the first display area, a plurality of second-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via a first transparent conductive line; a plurality of second-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via a third transparent conductive line; and a plurality of second-type first light-emitting devices located between the plurality of second-type first light-emitting devices near the center of the first display area and the plurality of second-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via a second transparent conductive line.

[0133] In one exemplary embodiment, in at least one group of first light-emitting devices in the first display area, a transparent conductive line electrically connected to a plurality of first-type first light-emitting devices is located on one side of the transfer electrode of the group of first light-emitting devices in a second direction.

[0134] In one exemplary embodiment, in at least one group of first light-emitting devices in the first display area, a transparent conductive line electrically connected to a plurality of second-type first light-emitting devices is located on the other side of the transfer electrode of the group of first light-emitting devices in a second direction.

[0135] In one exemplary embodiment, the first display area includes: a first sub-region and a second sub-region, the second sub-region being located on at least one side of the first sub-region and adjacent to the second display area; at least one first light-emitting device located in the first sub-region among a plurality of first light-emitting devices is connected to at least one first pixel driving circuit among a plurality of first pixel driving circuits through conductive lines of a plurality of conductive layers; at least one first light-emitting device located in the second sub-region among a plurality of first light-emitting devices is connected to at least one first pixel driving circuit among a plurality of first pixel driving circuits through conductive lines of a metal conductive layer in the circuit structure layer.

[0136] In one exemplary embodiment, the metal conductive layer and the shielding electrode are located in the same film layer.

[0137] In one exemplary embodiment, the shielding electrode may be rectangular in shape.

[0138] In one exemplary embodiment, the light-emitting structure layer may further include: a plurality of second light-emitting devices located in the second display area; the plurality of pixel circuits further include: a plurality of second pixel driving circuits, at least one of the plurality of second pixel driving circuits being electrically connected to at least one of the plurality of second light-emitting devices, and the at least one second pixel driving circuit being configured to drive at least one second light-emitting device to emit light.

[0139] In one exemplary embodiment, the second display area may include a transition display area and a normal display area, wherein the transition display area is located on at least one side of the normal display area and is adjacent to the first display area; the transition display area may include a plurality of first pixel driving circuits; the normal display area includes at least a portion of a plurality of second light-emitting devices and at least a portion of a plurality of second pixel driving circuits, wherein at least a portion of the plurality of second light-emitting devices is connected to at least a portion of the plurality of second pixel driving circuits.

[0140] In one exemplary embodiment, the transition display area may include: a plurality of sub-transition areas; the light-emitting structure layer may further include: a plurality of second light-emitting devices located in at least one sub-transition area near the first display area among the plurality of sub-transition areas; the circuit structure layer may further include: a plurality of second pixel driving circuits located in at least one sub-transition area near the first display area among the plurality of sub-transition areas; at least one of the plurality of second pixel driving circuits is electrically connected to at least one of the plurality of second light-emitting devices, and the at least one second pixel driving circuit is configured to drive at least one second light-emitting device to emit light.

[0141] In one exemplary embodiment, the light-emitting structure layer may further include: a plurality of second light-emitting devices located in the second display area; the circuit structure layer may further include: a plurality of second pixel driving circuits located in the second display area, wherein at least one of the plurality of second pixel driving circuits is electrically connected to at least one of the plurality of second light-emitting devices, and the at least one second pixel driving circuit is configured to drive at least one second light-emitting device to emit light.

[0142] In one exemplary embodiment, the first color light can be green light, and the second color light can include at least one of red light and blue light. For example, the first type of first light-emitting device can include a green first light-emitting device sp1_g, which is configured to emit green light; the second type of first light-emitting device can include a blue first light-emitting device sp1_b and a red first light-emitting device sp1_r, where the blue first light-emitting device sp1_b is configured to emit blue light and the red first light-emitting device sp1_r is configured to emit red light.

[0143] The following description, using the example of a display panel comprising three transparent conductive layers, a first type of first light-emitting device including a green first light-emitting device sp1_g, and a second type of first light-emitting device including a blue first light-emitting device sp1_b and a red first light-emitting device sp1_r, is illustrated in conjunction with the accompanying drawings.

[0144] In one exemplary embodiment, the capacitance of the anode connection node can be reduced by decreasing the length of the conductive line connected to the anode connection node of the green first light-emitting device sp1_g, thereby ensuring that the green first light-emitting device sp1_g can be turned on normally. In the following example, taking the first pixel driving circuit QD1 electrically connected to the green first light-emitting device sp1_g as being closest to the first display area AA1 as an example, that is, the first pixel driving circuit QD1 electrically connected to the green first light-emitting device sp1_g is preferentially arranged close to the first display area AA1. Wherein, in the exemplary embodiment of this disclosure, "element A is close to element B" can mean that there are no other elements A and other elements B between element A and element B, but there can be other elements besides elements A and element B. For example, the "first pixel driving circuit QD1 electrically connected to the green first light-emitting device sp1_g near the first display area AA1" described in the exemplary embodiments of this disclosure may refer to a situation where the first pixel driving circuit QD1 electrically connected to the green first light-emitting device sp1_g and the first display area AA1 do not have a first pixel driving circuit QD1 electrically connected to the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b, but may have other pixel driving circuits such as a second pixel driving circuit QD2 or an invalid pixel driving circuit QD0.

[0145] In one exemplary embodiment, the plurality of first light-emitting devices sp1 in the first display area AA1 may include: a plurality of green first light-emitting devices sp1_g, a plurality of blue first light-emitting devices sp1_b, and a plurality of red first light-emitting devices sp1_r. The green first light-emitting devices sp1_g are configured to emit green light, the blue first light-emitting devices sp1_b are configured to emit blue light, and the red first light-emitting devices sp1_r are configured to emit red light. In at least one group of first light-emitting devices sp1, the plurality of second pixel driving circuits QD2 electrically connected to the green first light-emitting device sp1_g are closer to the first display area AA1 than each of the plurality of second pixel driving circuits QD2 electrically connected to the blue first light-emitting device sp1_b and the red first light-emitting device sp1_r. This reduces the difference in the length of the conductive lines electrically connected to the green first light-emitting device sp1_g, thereby mitigating or avoiding display defects.

[0146] Figure 6A This is a second partial schematic diagram of the display panel in an embodiment of this disclosure. Figure 6B This is a third partial schematic diagram of the display panel in an embodiment of this disclosure. Figure 6C This is a fourth partial schematic diagram of the display panel in an embodiment of this disclosure, illustrating a portion of the display area. For example... Figures 6A to 6C As shown, the first display area AA1 may have a center line CL extending along the second direction Y. The first display area AA1 may be divided into a left half and a right half along the center line CL. The conductive lines connecting the first light-emitting devices in the left half and the right half may be approximately symmetrical about the center line CL. Wherein, Figures 6A to 6C In addition to illustrating some of the light-emitting devices in the first display area AA1, the diagram also illustrates some of the light-emitting devices in the sub-transition area of ​​the transition display area AAG, which is close to the first display area AA1.

[0147] In one exemplary embodiment, such as Figure 6A and Figure 6B As shown, the first display area AA1 may include a first sub-region AA1a and a second sub-region AA1b. The second sub-region AA1b may surround the first sub-region AA1a and be adjacent to the transition display area AAG. That is, the second sub-region AA1b may be located between the first sub-region AA1a and the transition display area AAG. The second sub-region AA1b may be an edge region of the first display area AA1, and the first sub-region AA1a may be the center region of the first display area AA1.

[0148] In one exemplary embodiment, such as Figure 6AAs shown, the shape of the first display area AA1 can be approximately circular, and the shape of the first sub-area AA1a can be a circle with a diameter smaller than that of the first display area AA1. The first sub-area AA1a can be an annulus surrounding the first sub-area AA1a. Figure 6B As shown, the shape of the first display area AA1 can be approximately circular, the first sub-region AA1a can be an approximately circular shape with a diameter smaller than that of the first display area AA1, and the first sub-region AA1a can be an approximately circular ring surrounding the first sub-region AA1a. Here, the embodiments of this disclosure do not limit this.

[0149] In one exemplary embodiment, such as Figure 6A and Figure 6B As shown, the film layer containing the conductive lines connecting at least one of the first light-emitting devices located in the first sub-region AA1a is different from the film layer containing the conductive lines connecting at least one of the first light-emitting devices located in the first sub-region AA1a. For example, at least one of the first light-emitting devices located in the first sub-region AA1a is electrically connected to at least one of the first light-emitting devices through conductive lines in a transparent conductive layer; at least one of the first light-emitting devices located in the first sub-region AA1a is connected to at least one of the first pixel driving circuits through conductive lines in a metal conductive layer in the circuit structure layer. For example, the conductive lines in the metal conductive layer can be conductive lines in a first source / drain metal layer (SD1) or conductive lines in a second source / drain metal layer (SD2). This embodiment of the present disclosure does not limit this aspect.

[0150] In one exemplary embodiment, the conductive lines of the metal conductive layer and the shielding electrode are located in the same film layer. For example, the shielding electrode and the conductive lines of the metal conductive layer may both be located in the second source / drain metal layer.

[0151] In one exemplary embodiment, such as Figure 6A and Figure 6B As shown, in a group of first light-emitting devices, the number of green first light-emitting devices sp1_g in the first sub-region AA1a can be greater than or equal to the number of green first light-emitting devices sp1_g in the second sub-region AA1b.

[0152] In one exemplary embodiment, the transition display area AAG in the second display area AA2 may include: a plurality of sub-transition areas; the light-emitting structure layer may further include: a plurality of second light-emitting devices located in at least one sub-transition area of ​​the plurality of sub-transition areas near the first display area; the circuit structure layer may further include: a plurality of second pixel driving circuits located in at least one sub-transition area of ​​the plurality of sub-transition areas near the first display area; at least one of the plurality of second pixel driving circuits is electrically connected to at least one of the plurality of second light-emitting devices, and the at least one second pixel driving circuit is configured to drive at least one second light-emitting device to emit light.

[0153] For example, Figure 6A and Figure 6B The diagram illustrates 48 columns of light-emitting devices on both sides of the center line CL. Specifically, on the left side of the center line CL, columns 1 to 39 can be located in the first sub-region AA1a, and columns 40 to 44 can be located in the second sub-region AA1b. Columns 1 to 39 and columns 40 to 44 are designated as first light-emitting devices sp1, and can be horizontally arranged via conductive lines L extending from the first display area AA1 to the transition display area AAG in the second display area AA2, connecting to the first pixel driving circuit QD1 in the transition display area AAG. For example, the film layer on which the conductive lines of columns 1 to 39 are located can be different from the film layer on which the conductive lines of columns 40 to 44 are located. For example, regarding the light-emitting devices in the first display area AA1, such as... Figures 6A to 13 As shown, the first to 39th columns of light-emitting devices in the first sub-region AA1a can be driven by the horizontal arrangement of conductive lines in the transparent conductive layer. After the arrangement space of the transparent conductive layer is fully utilized, the 40th to 44th columns of light-emitting devices in the second sub-region AA1b can be driven by the horizontal arrangement of conductive lines in the metal conductive layer (such as the second source / drain metal layer SD2). For example, for the light-emitting devices in the transition display area AAG that are close to the first display area AA1, the 45th to 48th columns of light-emitting devices can be located in the sub-transition area AAGn closest to the first display area AA1 in the transition display area AAG. The 45th to 48th columns of light-emitting devices can be the second light-emitting devices sp2, using an in-situ driving method, that is, the 45th to 48th columns of light-emitting devices are directly connected to the second pixel driving circuit QD2 located in the transition display area AAG. In this way, the transmittance will not be affected, and a good transition from the transition display area AAG to the first display area AA1 is guaranteed.

[0154] In one exemplary embodiment, such as Figure 6CAs shown, the first display area AA1 may include: a first pull line area AA1-1, a second pull line area AA1-2, a third pull line area AA1-3, and a fourth pull line area AA1-4 arranged sequentially away from the center of the first display area AA1. The first pull line area AA1-1 may be a region of the first display area AA1 that is relatively close to the geometric center of the first display area AA1, and the fourth pull line area AA1-4 may be a region of the first display area AA1 that is relatively close to the edge of the first display area AA1. For example, taking the shape of the first display area AA1 as approximately circular, the shapes of the first pull line area AA1-1, the second pull line area AA1-2, the third pull line area AA1-3, and the fourth pull line area AA1-4 may be parts of an approximately semi-circle. The dimension of the first pull wire area AA1-1 in the second direction Y can be larger than the dimension of the second pull wire area AA1-2 in the second direction Y, the dimension of the second pull wire area AA1-2 in the second direction Y can be larger than the dimension of the third pull wire area AA1-3 in the second direction Y, and the dimension of the second pull wire area AA1-2 in the second direction Y can be larger than the dimension of the fourth pull wire area AA1-4 in the second direction Y. Here, this embodiment does not limit the scope of the invention.

[0155] In one exemplary embodiment, such as Figure 6C As shown, the first light-emitting device sp1 in the first pull-wire area AA1-1 can be electrically connected by the first conductive line L1 of the first transparent conductive layer, the second pull-wire area AA1-2 can be electrically connected by the second conductive line L2 of the second transparent conductive layer, the third pull-wire area AA1-3 can be electrically connected by the third conductive line L3 of the third transparent conductive layer, and the fourth pull-wire area AA1-4 can be electrically connected by the conductive line of the metal conductive layer (such as the second source / drain metal layer).

[0156] For example, Figure 6C The diagram illustrates 48 columns of light-emitting devices on both sides of the center line CL. Specifically, on the left side of the center line CL, columns 1 to 13 can be located in the first pull line area AA1-1, columns 14 to 26 in the second pull line area AA1-2, columns 27 to 39 in the third pull line area AA1-3, and columns 40 to 44 in the fourth pull line area AA1-4. Columns 1 to 39 and columns 40 to 44 are designated as first light-emitting devices sp1, which can be horizontally arranged via conductive lines L extending from the first display area AA1 to the transition display area AAG in the second display area AA2, and connected to the first pixel driving circuit QD1 in the transition display area AAG. For example, regarding the light-emitting devices in the first display area AA1, such as... Figure 6CAs shown, the light-emitting devices in columns 1 to 13 of the first pull-wire area AA1-1 can be driven by the horizontal arrangement of the first transparent conductive lines in the first transparent conductive layer. After the arrangement space of the first transparent conductive layer is fully utilized, the light-emitting devices in columns 14 to 26 of the second pull-wire area AA1-2 can be driven by the horizontal arrangement of the second transparent conductive lines in the second transparent conductive layer. After the arrangement space of the second transparent conductive layer is fully utilized, the light-emitting devices in columns 27 to 39 of the third pull-wire area AA1-3 can be driven by the horizontal arrangement of the third transparent conductive lines in the third transparent conductive layer. After the arrangement space of the transparent conductive layer is fully utilized, the light-emitting devices in columns 40 to 44 of the fourth pull-wire area AA1-4 can be driven by the horizontal arrangement of conductive lines in the metal conductive layer (such as the second source / drain metal layer SD2). For example, for the light-emitting devices in the transition display area AAG that are close to the first display area AA1, the light-emitting devices in columns 45 to 48 can be located in the sub-transition area AAGn that is closest to the first display area AA1 in the transition display area AAG. The light-emitting devices in columns 45 to 48 can be the second light-emitting devices sp2. The in-situ driving method is adopted, that is, the light-emitting devices in columns 45 to 48 are directly connected to the second pixel driving circuit QD2 located in the transition display area AAG. In this way, the transmittance will not be affected, and a good transition from the transition display area AAG to the first display area AA1 is guaranteed.

[0157] In this example, the first light-emitting device sp1 near the center of the first display area AA1 can be electrically connected using conductive lines from a transparent conductive layer. After utilizing the routing space of the transparent conductive layer, the first light-emitting device sp1 near the edge of the first display area AA1 can be electrically connected using conductive lines from a metal conductive layer (such as a second source / drain metal layer). This ensures that the aperture remains constant, the routing environment is uniform, and the mask is not increased. Furthermore, since the load of the metal conductive layer (such as the second source / drain metal layer) is relatively small, its impact on the surrounding routing environment is minimal. In addition, using conductive lines from a metal conductive layer (such as the second source / drain metal layer) to electrically connect the light-emitting devices at the boundary positions has a minimal impact on the transmittance of the first display area AA1.

[0158] The following is for reference. Figures 6A to 6C The layout shown, in conjunction with the accompanying drawings, illustrates the connection method of the light-emitting devices in the first display area AA1. In the following example, the connection relationship between a group of first light-emitting devices in the left half of the first display area AA1 and a row of first pixel driving circuits QD1 in the transition display area AAG of the second display area AA2 is illustrated; other structures are omitted. Different line types are used to represent the transparent conductive lines of different layers: the first transparent conductive line L1 is represented by a solid line, the second transparent conductive line L2 by a dashed line, and the third transparent conductive line L3 by a dotted-dash line.

[0159] Figure 7 This is a schematic diagram of a first connection between the first light-emitting device and the first pixel driving circuit QD1 in an exemplary embodiment of this disclosure. Figure 8 for Figure 7 A schematic diagram of the connection of the first transparent conductive line L1 in the first transparent conductive layer. Figure 9 for Figure 7 A schematic diagram of the connection of the second transparent conductive line L2 in the second transparent conductive layer. Figure 10 for Figure 7 A schematic diagram of the connection of the third transparent conductive line L3 in the third transparent conductive layer. Figure 11 for Figure 7 A schematic diagram of the connection of the metal conductive line L4 in the middle metal conductive layer. Figure 12 This is a schematic diagram of a second connection between the first light-emitting device and the first pixel driving circuit QD1 in an exemplary embodiment of this disclosure. Figure 13 This is a schematic diagram illustrating a third connection between the first light-emitting device and the first pixel driving circuit QD1 in an exemplary embodiment of this disclosure. The following is in conjunction with... Figures 6A to 13 The connection method of the light-emitting device is explained.

[0160] In one exemplary embodiment, such as Figure 7 and Figure 8 As shown, the green first light-emitting device sp1_g in the first sub-region AA1a of the first display area AA1 can be electrically connected to the first pixel driving circuit QD1 in the transition display area AAG of the second display area AA2 via the first transparent conductive line L1 located in the first transparent conductive layer. Figure 7 and Figure 9 As shown, the green first light-emitting device sp1_g in the first sub-region AA1a can be electrically connected to the first pixel driving circuit QD1 in the transition display area AAG via the second transparent conductive line L2 located in the second transparent conductive layer. Figure 7 and Figure 10 As shown, the green first light-emitting device sp1_g in the first sub-region AA1a can be electrically connected to the first pixel driving circuit QD1 of the transition display area AAG via the third transparent conductive line L3 located in the third transparent conductive layer. Figure 7As shown, multiple green first light-emitting devices sp1_g near the center of the first display area AA1 are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG via the first transparent conductive line L1. Multiple green first light-emitting devices sp1_g near the edge of the second display area AA1 are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG via the third transparent conductive line L3. That is, multiple green first light-emitting devices sp1_g moving away from the transition display area AAG along the first direction X are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG via the first transparent conductive line L1, and multiple green first light-emitting devices sp1_g near the transition display area AAG are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG via the third transparent conductive line L3. Figure 7 As shown, the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L3, which are electrically connected to the green first light-emitting device sp1_g, are located on the same side, for example, the upper side, of the anode connection electrode of this group of first light-emitting devices in the second direction Y. Figure 7 As shown, the orthographic projections of the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L3 electrically connected to the green first light-emitting device sp1_g onto the display panel plane may overlap with the orthographic projection of the shielding electrode 60 onto the display panel plane. The shielding electrode 60 is configured to shield the crosstalk between the conductive lines' capacitance to the first node N1.

[0161] In one exemplary embodiment, such as Figure 7 and Figure 8 As shown, the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b in the first sub-region AA1a can be electrically connected to the first pixel driving circuit QD1 of the transition display area AAG through the first transparent conductive line L1 located in the first transparent conductive layer. Figure 7 and Figure 9 As shown, the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b in the first sub-region AA1a can be electrically connected to the first pixel driving circuit QD1 of the transition display area AAG through the second transparent conductive line L2 located in the second transparent conductive layer. Figure 7 and Figure 10 As shown, the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b in the first sub-region AA1a can be electrically connected to the first pixel driving circuit QD1 of the transition display area AAG through the third transparent conductive line L3 located in the third transparent conductive layer. Figures 7 to 10As shown, multiple red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b in the first sub-region AA1a, close to the transition display area AAG, can be electrically connected to the first pixel driving circuit QD1 of the transition display area AAG via the third transparent conductive line L3 located in the third transparent conductive layer. Conversely, multiple red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b in the first sub-region AA1a, far from the transition display area AAG, can be electrically connected to the first pixel driving circuit QD1 of the transition display area AAG via the first transparent conductive line L1 located in the first transparent conductive layer. Figure 7 As shown, the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L3, which are electrically connected to the red first light-emitting device sp1_r, are located on the same side of the transfer electrode of this group of first light-emitting devices in the second direction Y, for example, on the lower side. Figure 7 As shown, the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L3, which are electrically connected to the blue first light-emitting device sp1_b, are located on the same side of the group of first light-emitting devices in the second direction Y, for example, on the lower side. Figure 7 As shown, the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L32 electrically connected to the red first light-emitting device sp1_r, and the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L32 electrically connected to the blue first light-emitting device sp1_b, are located on the same side of the transition electrode of this group of first light-emitting devices in the second direction Y, for example, on the lower side. Figure 7 As shown, the orthographic projections of the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L3, which are electrically connected to the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b, onto the display panel plane may not overlap with the orthographic projection of the shielding electrode 60 onto the display panel plane.

[0162] In one exemplary embodiment, such as Figure 7 As shown, the second transparent conductive line L2 electrically connected to the green first light-emitting device sp1_g and the second transparent conductive line L2 electrically connected to the blue first light-emitting device sp1_b are located on both sides of the transition electrode of the group of first light-emitting devices in the second direction Y. The second transparent conductive line L2 electrically connected to the green first light-emitting device sp1_g and the second transparent conductive line L2 electrically connected to the red first light-emitting device sp1_r are located on both sides of the transition electrode of the group of first light-emitting devices in the second direction Y.

[0163] In one exemplary embodiment, such as Figure 7 and Figure 11 As shown, the green first light-emitting device sp1_g in the second sub-region AA1b can be electrically connected to the first pixel driving circuit QD1 of the transition display area AAG via the metal conductive line L4 located in the metal conductive layer. Figure 7 and Figure 11 As shown, the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b in the second sub-region AA1b can be electrically connected to the first pixel driving circuit QD1 of the transition display area AAG through the metal conductive line L4 located in the metal conductive layer. Figure 7 and Figure 11 As shown, the metal conductive line L4 connecting the green first light-emitting device sp1_g, the red first light-emitting device sp1_r, and the blue first light-emitting device sp1_b is located on the same side, for example, the lower side, of the transfer electrode of this group of first light-emitting devices in the second direction Y. Figure 7 and Figure 11 As shown, the orthographic projection of the metal conductive line L4, which is electrically connected to the first light-emitting device sp1, onto the display panel plane may not overlap with the orthographic projection of the shielding electrode 60 onto the display panel plane. For example... Figure 7 and Figure 11 As shown, the orthographic projection of the metal conductive line L4 electrically connected to the first light-emitting device sp1 on the display panel plane may overlap with the orthographic projections of the first transparent conductive lines L1, the second transparent conductive line L2, and the third transparent conductive line L3 electrically connected to the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b on the display panel plane. For example... Figure 7 and Figure 11 As shown, the orthographic projection of the metal conductive line L4 electrically connected to the first light-emitting device sp1 on the display panel plane may not overlap with the orthographic projection of the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L3 electrically connected to the green first light-emitting device sp1_g on the display panel plane.

[0164] In one exemplary embodiment, the wiring space of the first transparent conductive layer can be arranged with approximately 10 to 15 first transparent conductive lines L1, for example, such as Figure 7 and Figure 8 As shown, the routing space of the first transparent conductive layer can accommodate 13 first transparent conductive lines L1. The routing space of the second transparent conductive layer can accommodate approximately 10 to 15 second transparent conductive lines L2, for example, as... Figure 7 and Figure 9 As shown, the routing space of the second transparent conductive layer can accommodate 13 second transparent conductive lines L2. The routing space of the third transparent conductive layer can accommodate approximately 10 to 15 third transparent conductive lines L3, for example, as... Figure 7 and Figure 10 As shown, the routing space of the third transparent conductive layer can accommodate 13 third transparent conductive lines L3. For example, as Figure 7 and Figure 11 As shown, the trace arrangement space of the metal conductive layer can accommodate approximately 5 metal conductive lines L4. However, this embodiment of the present disclosure does not limit this arrangement.

[0165] For example, the conductive metal layer can be a first source-drain metal layer (SD1) or a second source-drain metal layer (SD2). For example, the first source-drain metal layer (SD1) can include: the first and second electrodes of multiple transistors in the pixel driving circuit, data signal lines, and first power supply lines, etc. For example, the second source-drain metal layer (SD2) can include: a shielding electrode 60.

[0166] In one exemplary embodiment, such as Figure 7 , Figure 12 and Figure 13 As shown, the second light-emitting device sp2, which is relatively close to the first display area AA1 in the second display area AA2, adopts an in-situ driving method. That is, both the second light-emitting device sp2, which is relatively close to the first display area AA1 in the transition display area, and the second pixel driving circuit QD2 that drives the second light-emitting device sp2 are located in the transition display area AAG. For example, as Figure 7 As shown, the light-emitting devices in columns 45 to 48 are driven in situ.

[0167] In one exemplary embodiment, such as Figure 12 As shown, multiple green first light-emitting devices sp1_g near the center of the first display area AA1 are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG via the first transparent conductive line L1. Multiple green first light-emitting devices sp1_g near the edge of the first display area AA1 (i.e., relatively closer to the second display area AA2) are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG via the second transparent conductive line L2 of the second transparent conductive layer. Multiple red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b near the center of the first display area AA1 are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG via the first transparent conductive line L1. Multiple red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b near the edge of the first display area AA1 (i.e., relatively closer to the second display area AA2) are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG via the second transparent conductive line L2 of the second transparent conductive layer.

[0168] In one exemplary embodiment, such as Figure 13As shown, multiple green first light-emitting devices sp1_g near the center of the first display area AA1 are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG through the second transparent conductive line L2 of the second transparent conductive layer. Multiple green first light-emitting devices sp1_g near the edge of the first display area AA1 (i.e., relatively close to the second display area AA2) are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG through the first transparent conductive line L1 of the first transparent conductive layer. Multiple red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b near the center of the first display area AA1 are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG through the first transparent conductive line L1. Multiple red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b near the edge of the first display area AA1 (i.e., relatively close to the second display area AA2) are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG through the third transparent conductive line L3 located in the third transparent conductive layer.

[0169] In this example, for the first light-emitting device sp1 in the first display area AA1, the first light-emitting device sp1 near the center in the first sub-region AA1a can be electrically connected using the first transparent conductive line L1 of the first transparent conductive layer. After utilizing the wiring space of the first transparent conductive layer, it can be electrically connected using the second transparent conductive line L2 of the second transparent conductive layer. After utilizing the wiring space of the second transparent conductive layer, the first light-emitting device sp1 relatively close to the transition display area AAG in the first sub-region AA1a can be electrically connected using the third transparent conductive line L3 of the third transparent conductive layer. After utilizing the wiring space of the third transparent conductive layer, it can be electrically connected using the metal conductive line L4 of the metal conductive layer in the second sub-region AA1b. Of course, other arrangements can also be used. For example, the first light-emitting device sp1 close to the transition display area AAG can be electrically connected using the second transparent conductive line L2 of the second transparent conductive layer. Here, this embodiment of the disclosure does not limit this.

[0170] The structure of a display panel is illustrated below using an example of the fabrication process. The "patterning process" described in this disclosure, for metallic, inorganic, or transparent conductive materials, includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0171] In one exemplary embodiment, the display panels of the second display area AA2 and the first display area AA1, in a direction perpendicular to the display panel, may include: a substrate, a circuit structure layer disposed on the substrate, a first transparent conductive layer, a second transparent conductive layer, a third transparent conductive layer, and a light-emitting structure layer. The circuit structure layer of the first display area AA1 may include: multiple insulating layers. The circuit structure layer of the second display area AA2 may include: multiple first pixel driving circuits and multiple second pixel driving circuits. A first planarization layer may be disposed between the first and second transparent conductive layers, and a second planarization layer may be disposed between the second and third transparent conductive layers. A third planarization layer may be disposed between the third transparent conductive layer and the light-emitting structure layer. For example, the first to third planarization layers may be organic material layers. The light-emitting structure layer may include: an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer. The anode layer may include: the anode of a first light-emitting device located in the first display area AA1 and the anode of a second light-emitting device located in the second display area AA2. For example, the anode area of ​​the first light-emitting device may be smaller than the anode area of ​​the second light-emitting device emitting light of the same color, so as to improve the light transmittance of the first display area AA1. In other examples, the display panel may include two or more transparent conductive layers. This disclosure does not limit the scope of the present invention.

[0172] In an exemplary embodiment, the fabrication process of the display panel may include the following operations. The following description uses a first pixel driving circuit QD1 and a second pixel driving circuit QD2 in the second display area AA2 as an example. The first pixel driving circuit QD1 in the transition display area AAG can be as follows: Figure 3The pixel driving circuit shown is illustrated. Furthermore, the structure of the second pixel driving circuit QD2 can be substantially the same as that of the first pixel driving circuit QD1. The structure of the invalid pixel driving circuit can also be substantially similar to that of the first pixel driving circuit QD1, but the invalid pixel driving circuit has no via connections and does not receive signals. Those skilled in the art can understand this by referring to the relevant descriptions; the embodiments disclosed herein will not be elaborated upon further.

[0173] (1) Provide a substrate.

[0174] In one exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. For example, a rigid substrate may include, but is not limited to, one or more of glass and quartz. For example, a flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. For example, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., configured to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0175] (2) Form a semiconductor layer pattern on the substrate.

[0176] In one exemplary embodiment, forming a semiconductor layer pattern on a substrate may include: sequentially depositing a first insulating thin film and a semiconductor thin film on the substrate, patterning the semiconductor thin film using a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, such as... Figure 14 As shown.

[0177] In one exemplary embodiment, the first insulating layer may be referred to as a buffer layer and is configured to improve the substrate's resistance to water and oxygen. The semiconductor layer may be referred to as an active (ACT) layer.

[0178] In one exemplary embodiment, such as Figure 14As shown, the semiconductor layer of the second display area AA2 may include at least the active layers of multiple transistors of the pixel driving circuit, such as the first active layer 11 of the first transistor T1, the second active layer 12 of the second transistor T2, the third active layer 13 of the third transistor T3, the fourth active layer 14 of the fourth transistor T4, the fifth active layer 15 of the fifth transistor T5, the sixth active layer 16 of the sixth transistor T6, and the seventh active layer 17 of the seventh transistor T7.

[0179] In one exemplary embodiment, such as Figure 14 As shown, the active layers of multiple transistors in a pixel driving circuit (e.g., the first active layer 11 to the seventh active layer 17) can be an interconnected monolithic structure.

[0180] In one exemplary embodiment, such as Figure 14 As shown, the second active layer 12 and the sixth active layer 16 can be located on one side of the first direction X of the third active layer 13, and the fourth active layer 14 and the fifth active layer 15 can be located on the opposite side of the first direction X of the third active layer 13. The fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 are located on one side of the second direction Y of the third active layer 13, and the first active layer 11, the second active layer 12 and the fourth active layer 14 can be located on the opposite side of the second direction Y of the third active layer 13.

[0181] In one exemplary embodiment, such as Figure 14 As shown, the first active layer 11 can be shaped like an "n". The second active layer 12 can be shaped like an inverted "L". The third active layer 13 can be shaped like an "Ω". The fourth active layer 14, the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 can all be shaped like an "I".

[0182] In one exemplary embodiment, the active layer of each transistor may include: at least one channel region, and a first region and a second region located on either side of the channel region. For example, the channel region may be undoped and have semiconductor characteristics. The first and second regions may be located on either side of the channel region and are doped with impurities, thus becoming conductive. The impurities may vary depending on the type of transistor. In some examples, the doped regions of the active layer may be interpreted as source or drain electrodes of the transistor. Portions of the active layer between transistors may be interpreted as doped wiring that can be configured to electrically connect the transistors.

[0183] In one exemplary embodiment, such as Figure 14As shown, the first region 11-1 of the first active layer 11, the first region 14-1 of the fourth active layer 14, the first region 15-1 of the fifth active layer 15, and the first region 17-1 of the seventh active layer 17 can be configured independently. The second region 11-2 of the first active layer 11 can simultaneously serve as the first region 12-1 of the second active layer 12 and the second gate signal unit SL2. The first region 13-1 of the third active layer 13 can simultaneously serve as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15. The second region 13-2 of the third active layer 13 can simultaneously serve as the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16. The second region 16-2 of the sixth active layer 16 can simultaneously serve as the second region 17-2 of the seventh active layer 17.

[0184] In one exemplary embodiment, the semiconductor layer may be made of a metal oxide material. For example, the metal oxide material may include, but is not limited to: oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten, indium, and zinc, oxides containing titanium and indium, oxides containing titanium, indium, and tin, oxides containing indium and zinc, oxides containing silicon, indium, and tin, oxides containing indium, gallium, and zinc, etc. For example, the semiconductor layer may be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc., meaning this disclosure applies to transistors manufactured based on oxide technology, silicon technology, or organic technology. For example, the semiconductor layer may be a single layer, a double layer, or multiple layers, etc. Here, the embodiments of this disclosure do not limit this.

[0185] In one exemplary embodiment, the first insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer.

[0186] (3) Form the pattern of the first conductive layer.

[0187] In one exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, such as... Figure 15A and Figure 15B As shown, Figure 15B for Figure 15A A planar schematic diagram of the first conductive layer.

[0188] In one exemplary embodiment, the second insulating layer may be referred to as a gate insulating (GI) layer, and the first conductive layer may be referred to as a first gate metal (Gate1) layer.

[0189] In one exemplary embodiment, such as Figure 15A and Figure 15B As shown, the first conductive layer of the second display area AA2 may include at least: a scan signal line 21, a first reset control line 22, a light emission control line 23, a first electrode 24 of the storage capacitor Cst, and a second reset control line 25.

[0190] In one exemplary embodiment, the first electrode 24 of the storage capacitor may be rectangular in shape, with chamfered corners. The orthographic projection of the first electrode 24 onto the substrate at least partially overlaps with the orthographic projection of the third active layer 13 onto the substrate. In one exemplary embodiment, the first electrode 24 may simultaneously serve as a first electrode of the storage capacitor and the gate electrode of the third transistor T3. For example, the transistors used in embodiments of this disclosure may include various structures, such as top-gate, bottom-gate, or dual-gate structures. In one exemplary embodiment, the second transistor T2 and the first transistor T1 connected to the gate electrode of the third transistor T3 may be dual-gate thin-film transistors, which can help reduce the leakage current of the gate electrode of the third transistor T3.

[0191] In one exemplary embodiment, the scan signal line 21, the first reset control line 22, the second reset control line 25, and the light emission control line 23 may be linearly shaped, with the main body extending along a first direction X. The scan signal line 21 and the light emission control line 23 may be located on opposite sides of the first electrode plate 24 in a second direction Y. The first reset control line 22 may be located on the side of the scan signal line 21 away from the first electrode plate 24. The second reset control line 25 may be located on the side of the scan signal line 21 away from the first electrode plate 24.

[0192] In one exemplary embodiment, the region where the scan signal line 21 overlaps with the second active layer 12 can serve as a gate electrode of the second transistor T2, and the orthographic projection of the scan signal line 21 onto the substrate and the orthographic projection of the second active layer 12 onto the substrate have a first overlapping region. For example, the scan signal line 21 is provided with a gate block 21-1 protruding towards the first reset control line 22, and the region where the gate block 21-1 overlaps with the second active layer 12 can serve as another gate electrode of the second transistor T2, and the orthographic projection of the gate block 21-1 onto the substrate and the orthographic projection of the second active layer 12 onto the substrate have a second overlapping region, thus forming a dual-gate structure for the second transistor T2. For example, the gate electrodes of the scan signal line 21 and the second transistor T2 of the pixel driving circuit in the same row can be an integrally connected structure.

[0193] In one exemplary embodiment, the region where the scan signal line 21 overlaps with the fourth active layer 14 can serve as the gate electrode of the fourth transistor T4, and there is an overlap between the orthographic projection of the scan signal line 21 on the substrate and the orthographic projection of the fourth active layer 14 on the substrate. For example, the scan signal line 21 and the gate electrode of the fourth transistor T4 of the pixel driving circuit in the same row can be an integral structure that is interconnected.

[0194] In one exemplary embodiment, the region where the first reset control line 22 overlaps with the first active layer 11 can serve as the gate electrode of the first transistor T1 in a dual-gate structure, and the orthographic projection of the first reset control line 22 on the substrate overlaps with the orthographic projection of the first active layer 11 on the substrate. For example, the first reset control line 22 and the gate electrode of the first transistor T1 in the same row of the pixel driving circuit can be an integral structure that is interconnected.

[0195] In one exemplary embodiment, the region where the second reset control line 25 overlaps with the seventh active layer 17 serves as the gate electrode of the seventh transistor T7, and the orthographic projection of the second reset control line 25 on the substrate overlaps with the orthographic projection of the second active layer 12 on the substrate. For example, the second reset control line 25 and the gate electrode of the seventh transistor T7 in the same row of the pixel driving circuit can be an integral structure that is interconnected.

[0196] In one exemplary embodiment, the region where the light-emitting control line 23 overlaps with the fifth active layer 15 serves as the gate electrode of the fifth transistor T5, and the region where the light-emitting control line 23 overlaps with the sixth active layer 16 serves as the gate electrode of the sixth transistor T6. The orthographic projections of the light-emitting control line 23 onto the substrate and the fifth active layer 15 onto the substrate overlap, as do the orthographic projections of the light-emitting control line 23 onto the substrate and the sixth active layer 16 onto the substrate. For example, the light-emitting control line 23, along with the gate electrodes of the fifth transistor T5 and the sixth transistor T6 of the pixel driving circuit in the same row, can be an integrally connected structure.

[0197] In one exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7. The semiconductor layer in the region not shielded by the first conductive layer is conducted, that is, the first region and the second region of the first active layer to the seventh active layer are both conducted.

[0198] In one exemplary embodiment, the second conductive layer may be formed of a metallic material. For example, the metallic material may include, but is not limited to, any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the metals listed above, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). For example, the second conductive layer may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0199] In one exemplary embodiment, the second insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer.

[0200] (4) Form the pattern of the second conductive layer.

[0201] In one exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer, such as... Figure 16A and Figure 16B As shown, Figure 16B for Figure 16A A planar schematic diagram of the second conductive layer.

[0202] In one exemplary embodiment, the third insulating layer may be referred to as the gate insulating (GI) layer, and the second conductive layer may be referred to as the second gate metal (Gate2) layer.

[0203] In one exemplary embodiment, such as Figure 16A and Figure 16B As shown, the second conductive layer of the second display area AA2 may include at least: a first initial signal line 31, a second initial signal line 32, a second electrode 33 of the storage capacitor Cst, a stop block 34, and an electrode connection line 35.

[0204] In one exemplary embodiment, the second electrode 33 of the storage capacitor may be located between the scan signal line 21 and the light emission control line 23 of the pixel driving circuit. The second electrodes 33 of adjacent pixel driving circuits in the first direction X or the opposite direction of the first direction X may be connected by electrode connecting lines 35. The first end of the electrode connecting line 35 is connected to the second electrode 33 of the pixel driving circuit, and the second end of the electrode connecting line 35 extends along the first direction X or the opposite direction of the first direction X and is connected to the second electrode 33 of the adjacent pixel driving circuit. That is, the electrode connecting line 35 is configured to connect the second electrodes 33 of adjacent pixel driving circuits in a unit row to each other.

[0205] In one exemplary embodiment, the second plates of multiple pixel driving circuits in a unit row can be interconnected into an integrated structure through the plate connection line. The second plates of the integrated structure can be reused as power connection lines, ensuring that the multiple second plates in a unit row have the same potential. This helps to improve the uniformity of the panel, avoid display defects in the display panel, and ensure the display effect of the display panel.

[0206] In one exemplary embodiment, the outline of the second electrode plate 33 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 33 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 24 on the substrate. The first electrode plate 24 and the second electrode plate 33 constitute the storage capacitor of the pixel driving circuit.

[0207] In one exemplary embodiment, the second electrode plate 33 is provided with an opening 36, which may be located in the middle of the second electrode plate 33. For example, the opening 36 may be rectangular, allowing the second electrode plate 33 to form an annular structure. For example, the opening 36 exposes a third insulating layer covering the first electrode plate 24, and the orthographic projection of the first electrode plate 24 onto the substrate includes the orthographic projection of the opening 36 onto the substrate. For example, the opening 36 may be configured to accommodate a subsequently formed first via, which is located within the opening 36 and exposes the first electrode plate 24, allowing the second electrode of the subsequently formed first transistor T1 to be connected to the first electrode plate 24 through the first via.

[0208] In one exemplary embodiment, the shapes of the first initial signal line 31 and the second initial signal line 32 may be line shapes that extend along the first direction X of the main body portion.

[0209] In one exemplary embodiment, the block 34 may be located between the scan signal line 21 and the first initial signal line 31. For example, the shape of the block 34 may be a broken line. For example, the block 34 may include a first electrode segment extending along a first direction X and a second electrode segment extending along a second direction Y. For example, the orthographic projection of the block 34 on the substrate at least partially overlaps with the orthographic projection of the subsequently formed data signal line 45 on the substrate, thereby the block 34 can shield the impact of data voltage jumps on critical nodes, preventing data voltage jumps from affecting the potential of critical nodes in the pixel driving circuit and improving the display effect. For example, the orthographic projection of the block 34 on the substrate at least partially overlaps with the orthographic projection of the second region 11-2 of the first active layer 11 (which is also the first region 12-1 and the second gate signal section SL2 of the second active layer 12) on the substrate, thereby the block 34 can block the second gate signal section SL2, thus shielding the impact of voltage jumps on critical nodes, preventing voltage jumps from affecting the potential of critical nodes in the pixel driving circuit and improving the display effect. For example, the second electrode segment of the left-side block 34 can extend to the left-side pixel driving circuit (not shown in the figure) to block the conductive connection portion of its second transistor T2, and the first electrode segment of the right-side block 34 can extend to the left-side pixel driving circuit to block the conductive connection portion of its second transistor T2. Of course, in some other embodiments, the block 34 may not be provided, or the orthographic projection of the block 34 on the substrate may not overlap with the orthographic projection of the second gate signal line SL2 on the substrate.

[0210] (5) Form the fourth insulating layer pattern.

[0211] In one exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed; patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer; and having a plurality of vias on the fourth insulating layer, such as... Figure 17 As shown.

[0212] In one exemplary embodiment, the fourth insulating layer may be referred to as an interlayer dielectric (ILD) layer.

[0213] In one exemplary embodiment, such as Figure 17 As shown, the multiple vias may include: first via V1, second via V2, third via V3, fourth via V4, fifth via V5, sixth via V6, seventh via V7, eighth via V8, ninth via V9, tenth via V10 and eleventh via V11.

[0214] In one exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the opening 36 of the second electrode plate 33 onto the substrate. The fourth and third insulating layers within the first via V1 are etched away, exposing the surface of the first electrode plate 24. The first via V1 is configured to connect the second electrode of the subsequently formed first transistor T1 to the first electrode plate 24 through the via.

[0215] In one exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the range of the orthographic projection of the second electrode plate 33 onto the substrate. The fourth insulating layer within the second via V2 is etched away, exposing the surface of the second electrode plate 33. The second via V2 is configured to allow the first electrode of the subsequently formed fifth transistor T5 to be connected to the second electrode plate 33 through the via.

[0216] In one exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the fifth active layer 55 onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched away, exposing the surface of the first region of the fifth active layer 55. The third via V3 is configured to allow the first electrode of the subsequently formed fifth transistor T5 to be connected to the first region of the fifth active layer 55 through the via.

[0217] In one exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is within the range of the orthographic projection of the second region of the sixth active layer 66 onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing the surface of the second region of the sixth active layer 16 (which is also the second region of the seventh active layer). The fourth via V4 is configured to allow the second electrode of the subsequently formed sixth transistor T6 (which is also the second electrode of the seventh transistor T7) to be connected to the second region of the sixth active layer 16 through the via.

[0218] In one exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer 14 onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched away, exposing the surface of the first region of the fourth active layer 14. The fifth via V5 is configured to allow the first electrode of the subsequently formed fourth transistor T4 to be connected to the first region of the fourth active layer 14 through the via.

[0219] In one exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the range of the orthographic projection of the second region of the first active layer 11 onto the substrate. The fourth, third, and second insulating layers within the sixth via V6 are etched away, exposing the surface of the second region of the first active layer 11 (which is also the first region of the second active layer 12). The sixth via V6 is configured to allow the second electrode of the subsequently formed first transistor T1 (the first electrode of the second transistor T2) to be connected to the second region of the first active layer 11 through the via.

[0220] In one exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate lies within the orthographic projection of the first region of the seventh active layer 17 onto the substrate. The fourth, third, and second insulating layers within the seventh via V7 are etched away, exposing the surface of the first region of the seventh active layer 17. The seventh via V7 is configured to allow the first electrode of the subsequently formed seventh transistor T7 to be connected to the first region of the seventh active layer through the via.

[0221] In one exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the range of the orthographic projection of the first region of the first active layer 11 onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the eighth via V8 are etched away, exposing the surface of the first region of the first active layer 11. The eighth via V8 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the first region of the first active layer 11 through the via.

[0222] In one exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is within the range of the orthographic projection of the first initial signal line 31 on the substrate. The fourth insulating layer inside the ninth via V9 is etched away, exposing the surface of the first initial signal line 31. The ninth via V9 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the first initial signal line 31 through the via.

[0223] In one exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate is within the range of the orthographic projection of the second initial signal line 32 onto the substrate. The fourth insulating layer within the tenth via V10 is etched away, exposing the surface of the second initial signal line 32. The tenth via V10 is configured to allow the first electrode of the subsequently formed seventh transistor T7 to be connected to the second initial signal line 32 through the via.

[0224] In one exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the block 34 onto the substrate. The fourth insulating layer within the eleventh via V11 is etched away, exposing the surface of the block 34. The eleventh via V11 is configured to allow a subsequently formed first power line to be connected to the block 34 through the via.

[0225] In one exemplary embodiment, the via pattern of the second pixel driving circuit QD2 or the invalid pixel driving circuit may be substantially the same as the via pattern of the first pixel driving circuit QD1.

[0226] (6) Form the pattern of the third conductive layer.

[0227] In one exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on a fourth insulating layer, such as... Figure 18A and Figure 18B As shown, Figure 18B for Figure 18A A planar schematic diagram of the third conductive layer.

[0228] In one exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0229] In one exemplary embodiment, the third conductive layer of the second display area AA2 may include: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a data signal line 45, and a first power line 46.

[0230] In one exemplary embodiment, the first connecting electrode 41 may be a strip shape in which the main body extends along the second direction Y. In one exemplary embodiment, the first connecting electrode 41 may serve as a first gate signal line SL1, which is connected to the gate electrode of the third transistor T3. In one exemplary embodiment, the first connecting electrode 41 may simultaneously serve as the first gate signal line SL1, the second electrode of the first transistor T1, and the first electrode of the second transistor T2. The first end of the first connecting electrode 41 is connected to the first electrode plate 24 (which is also the gate electrode of the third transistor T3) through a first via V1 and an opening 36, thereby connecting the first gate signal line SL1 and the gate electrode of the third transistor T3. The second end of the first connecting electrode 41 is connected to the second region of the first active layer (which is also the first region of the second active layer) through the sixth via V6, so that the second electrode of the first transistor T1 and the first electrode of the second transistor T2 of the first electrode plate 24 (which is also the gate electrode of the third transistor T3) have the same potential. In this way, the second electrode of the first transistor T1, the first electrode of the second transistor T2 and the gate electrode of the third transistor T3 are connected, and the second gate signal line SL2 is connected to the first gate signal line SL1.

[0231] For example, the first gate signal line SL1 and the second gate signal line SL2 are made of different materials. For example, the material of the first gate signal line SL1 may include a metal, and the material of the second gate signal line SL2 may include a conductive material formed by conductorlizing a semiconductor material.

[0232] For example, the first gate signal line SL1, the second gate signal line SL2, and the gate electrode of the third transistor T3 are connected to form a first node N1 (also called the gate signal section). The potentials on the first node N1 are the same. Of course, in other embodiments, the second gate signal line SL2 may not be provided; in this case, the gate electrode of the third transistor T3 and the first gate signal line SL1 constitute the first node N1. For example, the second gate signal line SL2 can be the second electrode of the first transistor T1, or it can be the first electrode of the second transistor T2.

[0233] In one exemplary embodiment, the second connection electrode 42 can be a strip shape in which the main body extends along the second direction Y. The first end of the second connection electrode 42 is connected to the first region of the first active layer 11 through an eighth via V8, and the second end of the second connection electrode 42 is connected to the first initial signal line 31 through a ninth via V9. In one exemplary embodiment, the second connection electrode 42 can serve as the first electrode of the first transistor T1, enabling the first initial signal line 31 to write the first initial signal into the first transistor T1.

[0234] In one exemplary embodiment, the third connection electrode 43 can be a strip shape in which the main body extends along the second direction Y. The first end of the third connection electrode 43 is connected to the first region of the seventh active layer 17 through the seventh via V7, and the second end of the third connection electrode 43 is connected to the second initial signal line 32 through the tenth via V10. In one exemplary embodiment, the third connection electrode 43 can serve as the first electrode of the seventh transistor T7, enabling the second initial signal line 32 to write the second initial signal into the seventh transistor T7.

[0235] In one exemplary embodiment, the fourth connection electrode 44 may be rectangular in shape. The fourth connection electrode 44 is connected to the second region of the sixth active layer 16 (which is also the second region of the seventh active layer 17) through a fourth via V4, such that the second regions of the sixth active layer 16 and the seventh active layer 17 have the same potential. For example, the fourth connection electrode 44 may serve as the second electrode of the sixth transistor T6 (or the second electrode of the seventh transistor T7), and the fourth connection electrode 44 is configured to connect to the subsequently formed anode electrode.

[0236] In one exemplary embodiment, the data signal line 45 may be a line shape in which the main body extends along the second direction Y. The data signal line 45 is connected to the first region of the fourth active layer 14 through a fifth via V5. Therefore, the data signal line 45 can serve as the first electrode of the fourth transistor T4, enabling the data signal line 45 to write data signals to the first electrode of the fourth transistor T4. For example, the orthographic projection of the data signal line 45 on the substrate overlaps with the orthographic projection of the stop 34 on the substrate.

[0237] In one exemplary embodiment, the first power line 46 can be a line shape in which the main body extends along the second direction Y. The first power line 46 is connected to the first region of the fifth active layer 15 through the third via V3, and to the second electrode plate 33 through the second via V2. Thus, since the first power line 46 is connected to both the second electrode plate 33 and the first region of the fifth active layer 15, the first power line 46 writes the first power signal to the first electrode of the fifth transistor T5, and makes the second electrode plate 33 and the first region of the fifth active layer have the same potential. For example, the first power line 46 can serve as the first electrode of the fifth transistor T5. The orthographic projection of the first power line 46 on the substrate overlaps with the orthographic projection of the block 34 on the substrate. The first power line 46 is connected to the block 34 through the eleventh via V11. Thus, since the first power line 46 is configured to provide a constant voltage to the pixel driving circuit, the voltage on the block 34 can be stabilized, which can serve as a shielding function.

[0238] In one exemplary embodiment, the first power line 46 can be a non-uniform width design. The non-uniform width design of the first power line 46 can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance generated by the first power line.

[0239] In one exemplary embodiment, the third conductive layer may be formed of a metallic material. For example, the metallic material may include, but is not limited to, any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the metals listed above, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The third conductive layer may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0240] (7) Form the fourth conductive layer pattern.

[0241] In one exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fifth insulating film and a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fifth insulating layer covering the third conductive layer, such as... Figure 19 As shown, a fourth conductive layer is formed on the fifth insulating layer, such as... Figure 20A and Figure 20B As shown, Figure 20B for Figure 20A A planar schematic diagram of the fourth conductive layer.

[0242] In one exemplary embodiment, the fifth insulating layer may include a plurality of vias, which may include a second first via V21 and a second second via V22. For example, the orthographic projection of the second first via V21 on the substrate overlaps with the orthographic projection of the first power line 46 on the substrate, and is configured to expose the surface of the first power line 46. For example, the orthographic projection of the second second via V22 on the substrate overlaps with the orthographic projection of the fourth connecting electrode 44 on the substrate, and is configured to expose the surface of the fourth connecting electrode 44.

[0243] In one exemplary embodiment, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0244] In one exemplary embodiment, the fourth conductive layer of the second display area AA2 may include at least a shielding electrode 60 and a fifth connecting electrode 50.

[0245] In one exemplary embodiment, the orthographic projection of the shielding electrode 60 on the substrate overlaps with the orthographic projection of the first gate signal line SL1 on the substrate. A shielding block 60-1 is provided on one side of the shielding electrode 60 in the first direction X. The orthographic projection of the shielding block 60-1 on the substrate at least partially overlaps with the orthographic projection of the first power line 46 on the substrate. The shielding block 60-1 is connected to the first power line 46 through a second via V21. The shielding block 60-1 is configured to connect the shielding electrode 60 to the first power line 46 through the second via V21. The first power line 46 is configured to provide a constant voltage to the pixel driving circuit. Thus, the voltage on the shielding electrode 60 is stable, which can achieve a shielding effect. Since the light emission signal of the anode is led out in the first display area AA1 through the conductive line L, the shielding electrode 60 can avoid the influence of the conductive line L on key nodes (such as the first node N1), thereby improving the display effect. For example, the orthographic projection of the first gate signal line SL1 on the substrate falls completely within the boundary range of the orthographic projection of the shielding electrode 60 on the substrate, thus enabling the shielding electrode 60 to achieve a better shielding effect. For example, to mitigate mura and improve display quality, the distance between the orthographic projection of the first gate signal line SL1 onto the substrate and the boundary between the orthographic projection of the shielding electrode 60 onto the substrate is greater than or equal to 1.75 μm. Because the area occupied by a pixel unit is limited, the distance of the shielding electrode 60 extending beyond the first gate signal line SL1 can be limited. For example, in some embodiments, to achieve better shielding, the distance between the orthographic projection of the first gate signal line SL1 onto the substrate and the boundary between the orthographic projection of the shielding electrode SE onto the substrate is greater than or equal to 2.33 μm.

[0246] In one exemplary embodiment, when the display panel includes a second gate signal line SL2, the second gate signal line SL2 is connected to the first gate signal line SL1 to form a first node N1. Therefore, the orthographic projection of the shielding electrode 60 on the substrate overlaps with the orthographic projection of the second gate signal line SL2 on the substrate.

[0247] In one exemplary embodiment, the orthographic projection of the shielding electrode 60 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 24 (which is also the gate electrode of the third transistor T3) on the substrate, the orthographic projection of the first gate signal line SL1 (which is also the second electrode of the first transistor T1 and the first electrode of the second transistor T2) on the substrate, and the orthographic projection of the second gate signal line SL2 (which is also the second region of the first active layer 11 and the first region of the second active layer 12) on the substrate.

[0248] In one exemplary embodiment, the orthographic projection of the shielding electrode 60 on the substrate overlaps with a portion of the orthographic projection of the second gate signal line SL2 on the substrate, and the orthographic projection of the block 34 on the substrate overlaps with a portion of the orthographic projection of the second gate signal line SL2 on the substrate. Thus, in Figure 20A In the display panel shown, the shielding electrode 60 and the stop block 34 form a double-layer shield for the second gate signal line SL2.

[0249] In one exemplary embodiment, the orthographic projection of the shielding electrode 60 on the substrate overlaps with the orthographic projection of the block 34 on the substrate.

[0250] In one exemplary embodiment, the orthographic projection of the shielding electrode 60 on the substrate overlaps with the orthographic projection of the first gate signal line SL1 on the substrate, and the orthographic projection of the block 34 on the substrate overlaps with the orthographic projection of the second gate signal line SL2 on the substrate. Thus, the shielding electrode 60, the shielding electrode SE, and the block 34 together provide shielding for the first node N1.

[0251] Of course, in other embodiments, the block 34 may not be provided, or the orthographic projection of the block 34 on the substrate and the orthographic projection of the second gate signal line SL2 on the substrate may not overlap.

[0252] In one exemplary embodiment, the shielding electrode 60 can be a regular shape, for example, a rectangle. By making the shielding electrode 60 a regular shape, the width of the shielding electrode 60 at different locations can be made uniform, thereby ensuring a consistent linewidth for the transparent conductor passing over the shielding electrode 60 and reducing its impact on the linewidth of the transparent conductor. This, in turn, helps to improve the problem of uneven brightness.

[0253] In one exemplary embodiment, the fifth connecting electrode 50 may be rectangular in shape. The orthographic projection of the fifth connecting electrode onto the substrate at least partially overlaps with the orthographic projection of the fourth connecting electrode 44 onto the substrate. The fifth connecting electrode 50 may serve as an anode connecting electrode. The fifth connecting electrode 50 is connected to the fourth connecting electrode 44 through a second via V22 and is configured to connect to a subsequently formed anode electrode.

[0254] In one exemplary embodiment, in a plane perpendicular to the display panel, the circuit structure layer of the second display area AA2 may include: a substrate and a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, and a fourth conductive layer sequentially stacked on the substrate. The semiconductor layer may include: the active layer of multiple transistors in the first pixel driving circuit QD1 and the second pixel driving circuit QD2; the first conductive layer may include: the gate electrode of multiple transistors, the first electrode of a storage capacitor, a scan signal line, a first reset control line, a light emission control line, and a second reset control line; the second conductive layer may include: the second electrode of the storage capacitor, electrode connection lines, a stop block, a first initial signal line, and a second initial signal line; the third conductive layer may include: the first and second electrodes of multiple transistors, a data signal line, and a first power supply line; and the fourth conductive layer may include: an anode connection electrode and a shielding electrode. That is, the circuit structure layer of the second display area AA2 may include: the first pixel driving circuit QD1 and the second pixel driving circuit QD2.

[0255] In one exemplary embodiment, in a plane perpendicular to the display panel, the light-transmitting area of ​​the first display area AA1 may include: a substrate and a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer sequentially stacked on the substrate. The non-light-transmitting area of ​​the first display area AA1 may include: a substrate and a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer sequentially stacked on the substrate. That is, the circuit structure layer of the first display area AA1 does not have a pixel driving circuit.

[0256] In one exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo.

[0257] In one exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0258] At this point, the circuit structure layer has been fabricated on the substrate.

[0259] (8) Form the first transparent conductive layer.

[0260] In one exemplary embodiment, a sixth insulating film and a first transparent conductive film are deposited on the substrate on which the aforementioned pattern is formed. The first transparent conductive film is patterned using a patterning process to form a sixth insulating layer covering the fourth conductive layer, and a first transparent conductive layer disposed on the sixth insulating layer, such as... Figure 21A and Figure 21B As shown.

[0261] In one exemplary embodiment, the first transparent conductive layer may include a sixth connecting electrode 61.

[0262] In one exemplary embodiment, the sixth connecting electrode 61 may be rectangular in shape. The orthographic projection of the sixth connecting electrode 61 onto the substrate at least partially overlaps with the orthographic projection of the fifth connecting electrode 50 onto the substrate. When the first light-emitting device is electrically connected to the first pixel driving circuit QD1 of the transition display area AAG via the first transparent conductive line L1 located in the first transparent conductive layer, the sixth connecting electrode 61 can serve as a transfer electrode for the first light-emitting device. The sixth connecting electrode 61 is connected to the fifth connecting electrode 50 through a via in the sixth insulating layer and is configured to connect to the subsequently formed anode electrode.

[0263] In one exemplary embodiment, the first transparent conductive layer may further include a first transparent conductive line L1. For example, one end of the first transparent conductive line L1 may be connected to a sixth connecting electrode 61 located in the first display area AA1, and the other end of the first transparent conductive line L1 may be connected to a sixth connecting electrode 61 located in the first pixel driving circuit QD1 of the transition display area AAG in the second display area AA2. In this way, the subsequently formed anode electrode can be connected to the first pixel driving circuit QD1 in the transition display area AAG.

[0264] (9) Form a second transparent conductive layer.

[0265] In one exemplary embodiment, a first planarization film is coated on a substrate on which the aforementioned pattern is formed, and a first planarization layer is formed by a patterning process. Subsequently, a second transparent conductive film is deposited, and the second transparent conductive film is patterned by a patterning process to form a second transparent conductive layer disposed on the first planarization layer, such as... Figure 22Aand Figure 22B As shown.

[0266] In one exemplary embodiment, the second transparent conductive layer may include a seventh connecting electrode 71.

[0267] In one exemplary embodiment, the seventh connecting electrode 71 may be rectangular in shape. The orthographic projection of the seventh connecting electrode 71 onto the substrate at least partially overlaps with the orthographic projection of the sixth connecting electrode 61 onto the substrate. When the first light-emitting device is electrically connected to the first pixel driving circuit QD1 of the transition display area AAG via the second transparent conductive line L2 located in the second transparent conductive layer, the seventh connecting electrode 71 can serve as a transfer electrode for the first light-emitting device. The seventh connecting electrode 71 is connected to the sixth connecting electrode 61 through a via in the first planarization layer and is configured to connect to the subsequently formed anode electrode.

[0268] In one exemplary embodiment, the second transparent conductive layer may further include a second transparent conductive line L2. For example, one end of the second transparent conductive line L2 may be connected to a seventh connection electrode 71 located in the first display area AA1, and the other end of the second transparent conductive line L2 may be connected to a seventh connection electrode 71 located in the first pixel driving circuit QD1 of the transition display area AAG in the second display area AA2. In this way, the subsequently formed anode electrode can be connected to the first pixel driving circuit QD1 in the transition display area AAG.

[0269] (10) Form a third transparent conductive layer.

[0270] In one exemplary embodiment, a second planarization film is coated on the substrate on which the aforementioned pattern is formed, and a second planarization layer is formed by a patterning process. Subsequently, a third transparent conductive film is deposited, and the third transparent conductive film is patterned by a patterning process to form a third transparent conductive layer disposed on the second planarization layer, such as... Figure 23A and Figure 23B As shown.

[0271] In one exemplary embodiment, the third transparent conductive layer may include an eighth connecting electrode 81.

[0272] In one exemplary embodiment, the eighth connecting electrode 81 may be rectangular in shape. The orthographic projection of the eighth connecting electrode 81 onto the substrate at least partially overlaps with the orthographic projection of the seventh connecting electrode 71 onto the substrate. When the first light-emitting device is electrically connected to the first pixel driving circuit QD1 located in the transition display area AAG in the second display area AA2 via the third transparent conductive line L3 located in the third transparent conductive layer, the eighth connecting electrode 81 can serve as a transfer electrode for the first light-emitting device. The eighth connecting electrode 81 is connected to the seventh connecting electrode 71 through a via in the second planarization layer and is configured to connect to the subsequently formed anode electrode.

[0273] In one exemplary embodiment, the third transparent conductive layer may further include a third transparent conductive line L3. For example, one end of the third transparent conductive line L3 may be connected to an eighth connection electrode 81 located in the first display area AA1, and the other end of the second transparent conductive line L2 may be connected to an eighth connection electrode 81 located in the first pixel driving circuit QD1 of the transition display area AAG in the second display area AA2. In this way, the subsequently formed anode electrode can be connected to the first pixel driving circuit QD1 in the transition display area AAG.

[0274] In one exemplary embodiment, the conductive line L may include one or more of a first transparent conductive line L1, a second transparent conductive line L2, and a third transparent conductive line L3. For example, the orthographic projection of the conductive line L1 onto the substrate overlaps with the orthographic projection of the first pixel driving circuit QD1 onto the substrate. For example, the orthographic projection of the conductive line L1 onto the substrate overlaps with the orthographic projection of the first gate signal line SL1 in the first pixel driving circuit QD1 onto the substrate. The shielding electrode 60 is located between the conductive line L1 and the first gate signal line SL1. In embodiments of this disclosure, after forming the pixel driving circuit, the shielding electrode 60 is formed, then the conductive lines L1 (such as the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L3) are formed, and then the light-emitting device is formed. Thus, the film layer containing the shielding electrode 60 is located between the film layer containing the conductive line L1 and the film layer containing the first gate signal line SL1, and the film layer containing the shielding electrode 60 is located between the film layer containing the conductive line L1 and the film layer containing the gate electrode of the third transistor T3.

[0275] (11) Forming a light-emitting structural layer.

[0276] In one exemplary embodiment, a third planarization film is coated on the substrate on which the aforementioned pattern is formed, and a third planarization layer is formed by a patterning process. Subsequently, an anolyte conductive film is deposited, and the anolyte conductive film is patterned by a patterning process to form an anolyte layer disposed on the third planarization layer, such as... Figure 24A and Figure 24B As shown. Subsequently, a pixel definition film is coated on the substrate forming the aforementioned pattern, and a pixel definition layer (PDL) is formed through masking, exposure, and development processes. The pixel definition layer has multiple pixel openings that expose the anode layer, and the pixel openings are configured to define the light-emitting area of ​​the pixel unit, such as... Figure 25 As shown. An organic light-emitting layer is formed within the aforementioned pixel opening, and the organic light-emitting layer is connected to the anode. Subsequently, a cathode thin film is deposited, and the cathode thin film is patterned using a patterning process to form a cathode pattern. The cathode is electrically connected to both the organic light-emitting layer and the second power line. Subsequently, an encapsulation layer is formed on the cathode, and the encapsulation layer may include a stacked structure of inorganic / organic / inorganic materials. Figure 24A , Figure 24B and Figure 25 The diagram below uses the eight light-emitting devices in the second display area AA2 as an example, omitting the structure of the second pixel driving circuit QD2. Figure 24C The illustration takes the connection between the second anode of one of the second light-emitting devices in the second display area AA2 and the second pixel driving circuit QD2 as an example. The structure of the light-emitting device in the first display area AA1 can be basically similar, and those skilled in the art can understand it by referring to the relevant descriptions. The embodiments disclosed herein will not be described in detail here.

[0277] In one exemplary embodiment, the anode layer may include a first anode electrode 91, a second anode electrode 92, and a third anode electrode 93.

[0278] In one exemplary embodiment, the first anode electrode 91 can serve as the anode of a green light-emitting device. The orthographic projection of the first anode electrode 91 onto the substrate may overlap with the orthographic projections of the eighth connecting electrode 81, the seventh connecting electrode 71, the sixth connecting electrode 61, and the fifth connecting electrode 50 onto the substrate.

[0279] In one exemplary embodiment, the second anode electrode 92 can serve as the anode of a red light-emitting device. The orthographic projection of the second anode electrode 92 onto the substrate may overlap with the orthographic projections of the eighth connecting electrode 81, the seventh connecting electrode 71, the sixth connecting electrode 61, and the fifth connecting electrode 50 onto the substrate.

[0280] In one exemplary embodiment, the third anode electrode 93 can serve as the anode of a blue light-emitting device. The orthographic projection of the third anode electrode 93 onto the substrate may overlap with the orthographic projections of the eighth connecting electrode 81, the seventh connecting electrode 71, the sixth connecting electrode 61, and the fifth connecting electrode 50 onto the substrate.

[0281] In one exemplary embodiment, the plurality of pixel openings may include: a first pixel opening 94, a second pixel opening 95, and a third pixel opening 96.

[0282] In one exemplary embodiment, the shape of the first pixel opening 94 can be pentagonal. The orthographic projection of the first pixel opening 94 onto the substrate falls within the boundary of the orthographic projection of the first anode electrode 91 onto the substrate.

[0283] In one exemplary embodiment, the shape of the second pixel opening 95 can be hexagonal. The orthographic projection of the second pixel opening 95 onto the substrate falls within the boundary of the orthographic projection of the second anode electrode 92 onto the substrate.

[0284] In one exemplary embodiment, the shape of the third pixel opening 96 may be hexagonal. The orthographic projection of the third pixel opening 96 onto the substrate falls within the boundary of the orthographic projection of the third anode electrode 93 onto the substrate.

[0285] In one exemplary embodiment, the first to third transparent conductive layers may be made of transparent conductive materials, such as indium tin oxide (ITO). The sixth insulating layer and the first to third planarization layers may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode layer may be made of a reflective material such as metal, and the cathode may be made of a transparent conductive material. This disclosure does not limit the scope of the embodiments described herein.

[0286] The structure and fabrication process of the display panel in this embodiment are merely illustrative. In one exemplary embodiment, the structure and patterning process can be modified and increased or decreased according to the actual application scenario. The fabrication process of this exemplary embodiment can be implemented using currently mature fabrication equipment, is well compatible with fabrication processes in some technologies, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0287] In one exemplary embodiment, the display panel may include four or more transparent conductive layers. The transparent conductive lines electrically connected to the first type of first light-emitting device and the second type of first light-emitting device in the first sub-region of the first display area may be located in two different transparent conductive layers, and at least one transparent conductive layer may be spaced between the two different transparent conductive layers.

[0288] In the display panel provided in this embodiment, by adjusting the wiring method of the transparent conductive lines electrically connected to the first type of first light-emitting device and the second type of first light-emitting device in the first display area, the uniformity of the conductive lines can be ensured, thereby improving the display uniformity of the first display area and enhancing the display effect of the first display area.

[0289] This disclosure also provides a display device. The display device may include the display panel described in one or more of the exemplary embodiments above.

[0290] In one exemplary embodiment, the display device may further include a sensor located on the non-display side of the display panel, and the orthographic projection of the sensor onto the display panel overlaps with the first display area of ​​the display panel.

[0291] Here, the display device can be a product with image (including static images or dynamic images, where dynamic images can be video) display capabilities.

[0292] In one exemplary embodiment, the display device may include, but is not limited to, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, billboards, laser printers with display functions, drawing screens, personal digital assistants (PDAs), digital cameras, portable camcorders, viewfinders, navigators, vehicles, large-area walls, information query devices (such as business query devices for e-government, banks, hospitals, power companies, etc.), or monitors, or any other product or component with display functions. This disclosure does not limit the scope of the application.

[0293] In one exemplary embodiment, the sensor may include, but is not limited to, a camera sensor, a fingerprint sensor, a light sensor, an infrared sensor, or an ultrasonic sensor. This disclosure does not limit the specific type of sensor used.

[0294] The description of the above display device embodiments is similar to that of the above display panel embodiments, and has similar beneficial effects. For technical details not disclosed in the display device embodiments of this disclosure, those skilled in the art should refer to the description in the display panel embodiments of this disclosure for understanding, and will not repeat them here.

[0295] While the embodiments disclosed herein are as described above, the above content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein, but the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display panel, comprising: The system comprises a substrate, a circuit structure layer and a light-emitting structure layer stacked on the substrate, and a plurality of conductive layers disposed between the circuit structure layer and the light-emitting structure layer; wherein... The substrate includes: a first display area and a second display area, wherein the second display area is located on at least one side of the first display area, and the light transmittance of the first display area is greater than that of the second display area; The circuit structure layer includes: a first gate signal line, a constant voltage line, multiple shielding electrodes, and multiple pixel circuits located in the second display area. Each pixel circuit includes a driving transistor with a gate, and each pixel circuit includes multiple first pixel driving circuits. The first gate signal line is connected to the gate of the driving transistor. The constant voltage line is configured to provide a first constant voltage to the multiple pixel circuits. The shielding electrode is connected to the constant voltage line, and the orthographic projection of the first gate signal line onto the substrate falls within the orthographic projection of the shielding electrode onto the substrate. The shielding electrode has a regular shape. The plurality of conductive layers include: a plurality of conductive lines, the plurality of conductive lines including: a plurality of first-type conductive lines and a plurality of second-type conductive lines, wherein the orthographic projection of the portion of the first-type conductive line extending along a first direction on the substrate overlaps with the orthographic projection of at least one of the plurality of shielding electrodes on the substrate, and the orthographic projection of the portion of the second-type conductive line extending along the first direction on the substrate does not overlap with the orthographic projection of the plurality of shielding electrodes on the substrate. The light-emitting structure layer includes: a plurality of first light-emitting devices located in the first display area; the plurality of first light-emitting devices includes: a plurality of first-type first light-emitting devices and a plurality of second-type first light-emitting devices; at least one of the first-type first light-emitting devices is connected to at least one of the plurality of first-type conductive lines through at least one of the plurality of first-type conductive lines; at least one of the plurality of second-type first light-emitting devices is connected to at least one of the plurality of first-type conductive lines through at least one of the plurality of second-type conductive lines; the first pixel driving circuit is configured to drive the first light-emitting devices to emit light; the first-type first light-emitting devices are configured to emit first-color light; and the second-type first light-emitting devices are configured to emit second-color light, wherein the second-color light is different from the first-color light.

2. The display panel according to claim 1, wherein, The first display area includes multiple first light-emitting devices: multiple groups of first light-emitting devices, wherein the first light-emitting devices in each group of the multiple groups of first light-emitting devices are arranged along the first direction, and the multiple groups of first light-emitting devices are arranged along a second direction, wherein the second direction intersects the first direction; In the at least one group of first light-emitting devices, the plurality of first pixel driving circuits electrically connected to the plurality of first type first light-emitting devices are closer to the first display area than each of the plurality of first pixel driving circuits electrically connected to the plurality of second type first light-emitting devices.

3. The display panel according to claim 2, wherein, The plurality of conductive layers include: a first transparent conductive layer, a second transparent conductive layer, and a third transparent conductive layer disposed sequentially along a side away from the substrate; the first transparent conductive layer includes a plurality of first transparent conductive lines, the second transparent conductive layer includes a plurality of second transparent conductive lines, and the third transparent conductive layer includes a plurality of third transparent conductive lines.

4. The display panel according to claim 3, wherein, In at least one group of first light-emitting devices in the first display area, a plurality of first-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first-pixel driving circuits through the first transparent conductive line, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first-pixel driving circuits through the third transparent conductive line.

5. The display panel according to claim 3, wherein, In at least one group of first light-emitting devices in the first display area, a plurality of first-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first-pixel driving circuits through the first transparent conductive line, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first-pixel driving circuits through the second transparent conductive line.

6. The display panel according to claim 3, wherein, In at least one group of first light-emitting devices in the first display area, a plurality of first-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first-pixel driving circuits through the second transparent conductive line, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first-pixel driving circuits in the second display area through the first transparent conductive line.

7. The display panel according to claim 3, wherein, In at least one group of first light-emitting devices in the first display area, a plurality of first-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through the third transparent conductive line, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits in the second display area through the first transparent conductive line.

8. The display panel according to any one of claims 4 to 7, wherein, In at least one group of first light-emitting devices in the first display area, a plurality of second-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through the first transparent conductive line, and a plurality of second-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through the third transparent conductive line.

9. The display panel according to any one of claims 4 to 7, wherein, In at least one group of first light-emitting devices in the first display area, the transparent conductive lines electrically connected to a plurality of second-type first light-emitting devices near the center of the first display area are of the same type as the transparent conductive lines electrically connected to a plurality of first-type first light-emitting devices near the center of the first display area, or the transparent conductive lines electrically connected to a plurality of second-type first light-emitting devices near the edge of the first display area are of the same type as the transparent conductive lines electrically connected to a plurality of first-type first light-emitting devices near the edge of the first display area.

10. The display panel according to any one of claims 4 to 7, wherein, In at least one group of first light-emitting devices in the first display area, the transparent conductive lines electrically connected to a plurality of second-type first light-emitting devices near the center of the first display area are of a different type than the types of electrical connections of a plurality of first-type first light-emitting devices near the center of the first display area; or, the transparent conductive lines electrically connected to a plurality of second-type first light-emitting devices near the edge of the first display area are of a different type than the types of transparent conductive lines electrically connected to a plurality of first-type first light-emitting devices near the edge of the first display area.

11. The display panel according to any one of claims 4 to 7, wherein, In at least one group of first light-emitting devices in the first display area, a plurality of second-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through the first transparent conductive line, and a plurality of second-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through the third transparent conductive line.

12. The display panel according to any one of claims 4 to 7, wherein, In at least one group of first light-emitting devices in the first display area, the conductive lines connecting the plurality of first-type first light-emitting devices are located on one side of the transfer electrode of the group of first light-emitting devices in the second direction.

13. The display panel of claim 12, wherein, In at least one group of first light-emitting devices in the first display area, the conductive lines connecting the plurality of second-type first light-emitting devices are located on the other side of the transition electrode of the group of first light-emitting devices in a second direction.

14. The display panel according to claim 3, wherein, In at least one group of first light-emitting devices in the first display area, a plurality of first-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first-pixel driving circuits through the first transparent conductive line; a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first-pixel driving circuits through the third transparent conductive line; and a plurality of first-type first light-emitting devices located between the plurality of first-type first light-emitting devices near the center of the first display area and the plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first-pixel driving circuits through the second transparent conductive line. In at least one group of first light-emitting devices in the first display area, a plurality of second-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first-pixel driving circuits through the first transparent conductive line, a plurality of second-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first-pixel driving circuits through the third transparent conductive line, and a plurality of second-type first light-emitting devices located between the plurality of second-type first light-emitting devices near the center of the first display area and the plurality of second-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first-pixel driving circuits through the second transparent conductive line.

15. The display panel according to any one of claims 1 to 7, wherein, The first display area includes: a first sub-area and a second sub-area, wherein the second sub-area is located between the first sub-area and the second display area; At least one of the plurality of first light-emitting devices located in the first sub-region is connected to at least one of the plurality of first pixel driving circuits through the conductive lines of the plurality of conductive layers. At least one of the plurality of first light-emitting devices located in the second sub-region is connected to at least one of the plurality of first pixel driving circuits through a conductive line in the metal conductive layer of the circuit structure layer.

16. The display panel of claim 15, wherein, The conductive metal layer and the shielding electrode are located in the same film layer.

17. The display panel according to any one of claims 1 to 7, wherein, The light-emitting structure layer further includes: a plurality of second light-emitting devices located in the second display area; The plurality of pixel circuits further includes: a plurality of second pixel driving circuits, at least one of the plurality of second pixel driving circuits being electrically connected to at least one of the plurality of second light-emitting devices, and the at least one second pixel driving circuit being configured to drive the at least one second light-emitting device to emit light.

18. The display panel according to claim 17, wherein, The second display area includes a transition display area and a normal display area, wherein the transition display area is located between the first display area and the normal display area; The transition display area includes: the plurality of first pixel driving circuits; The normal display area includes at least a portion of the plurality of second light-emitting devices and at least a portion of the plurality of second pixel driving circuits, wherein at least a portion of the plurality of second light-emitting devices is connected to at least a portion of the plurality of second pixel driving circuits.

19. The display panel of any one of claims 1 to 7, wherein, The first color light is green light, and the second color light includes at least one of blue light and red light.

20. A display device comprising: The display panel as described in any one of claims 1 to 19.

21. The display device of claim 20, further comprising: The sensor is located on the non-display side of the display panel, and the orthographic projection of the sensor on the display panel overlaps with the first display area of ​​the display panel.

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