A gallium oxide MISFET device structure and preparation method thereof

Abstract

The present invention provides a gallium oxide MISFET device structure and a preparation method thereof, belonging to the technical field of semiconductor devices. The device structure includes a drain electrode, a gallium oxide substrate, an epitaxial layer and a source electrode from bottom to top. A current blocking layer is arranged in the surface layer of the epitaxial layer, and the middle part of the current blocking layer is a current channel. At least one adjustment layer connected to the current blocking layer is arranged in the epitaxial layer at the current channel. The bottom of the adjustment layer extends toward the inside of the epitaxial layer close to the gallium oxide substrate, and the extension direction forms an obtuse angle with the current blocking layer. A gate dielectric layer is deposited on the upper surface of the epitaxial layer; along the direction from the source electrode to the drain electrode, ohmic contact metal layers forming ohmic contact with the epitaxial layer are arranged on both sides of the gate dielectric layer. A gate is arranged on the upper surface of the gate dielectric layer, and a passivation dielectric layer is arranged between the gate electrode and the source electrode. The device structure can better protect the gate dielectric without affecting the threshold voltage of the device, and improve the reverse withstand voltage value and short circuit tolerance.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a gallium oxide MISFET device structure and a preparation method thereof. Background Art

[0002] Among wide bandgap semiconductor materials, gallium oxide (Ga2O3) has a bandgap width of 4.8eV, an ideal breakdown electric field strength of 8MV / cm, and a Baliga's figure-of-merit (BFOM) of up to 3400. The BFOM of Ga2O3 is about 4 times that of GaN and 10 times that of SiC. Therefore, under the same withstand voltage, Ga2O3 power devices have lower on-resistance and lower power consumption than GaN devices or SiC devices, which can greatly reduce the power loss of the device during operation.

[0003] However, it is difficult to achieve p-type doping of gallium oxide, which limits the application of gallium oxide in bipolar power devices compared to materials that can be bipolar doped. There are three main reasons why it is difficult to obtain p-type gallium oxide with hole conduction: first, it is difficult to find acceptor impurities with small activation energy; second, according to theoretical calculations, the maximum dispersion of the valence band of Ga2O3 is small and the effective mass is very large, resulting in free holes almost becoming a local distribution with low mobility; finally, theoretical predictions have been made specifically for Ga2O3, and due to local lattice distortion, the local self-capture energy of free holes in the volume is very large, which leads to the formation of small poles, which undoubtedly prohibits the conduction of effective holes. Based on the above reasons, gallium oxide can currently only be made into Metal-Insulator Semiconductor Field Effect Transistor (MISFET) or Junction Field-Effect Transistor (JFET) devices with n-type conductivity in the drain, source and drift region.

[0004] In order to realize enhanced devices and reduce the electric field at the metal-semiconductor interface, the existing technology (DOI: 10.1109 / IEDM19573.2019.8993526) etches the gallium oxide epitaxial layer to form grooves on the surface, and then deposits insulating dielectrics such as SiO2 and Al2O3 into the grooves to form the gate dielectric of the MISFET device, thereby manufacturing an enhanced MISFET device. Compared with planar MISFET devices, enhanced MISFETs have a normally-off characteristic because the metal gate or polysilicon gate can completely deplete the conductive channel, and the gate electrode has a certain depth, which can effectively shield part of the electric field during reverse bias, so that the surface electric field is reduced to a certain extent, which can reduce leakage current.

[0005] However, the gallium oxide material cannot be thermally oxidized to achieve the larger depth of gate dielectric deposition in the above-mentioned prior art, but it is necessary to form deep trenches in the gallium oxide material and then form gate dielectric deposition on the surface of the deep trenches. However, due to the large depth of the deep trenches, the thickness of the gate dielectric layer in the deep trenches is uneven, which affects the uniformity of the device threshold voltage. Due to the lack of effective PN junction protection, the electric field strength at the bottom of the gate trench is large, and avalanche breakdown is prone to occur, resulting in low device reliability. In addition, in order for trench-type gallium oxide devices to achieve enhanced functions, the spacing between the two trenches needs to be less than 0.35μm. Electron beam lithography machines are currently often used to define this distance, but electron beam lithography machines are expensive and have slow lithography efficiency, and do not have the ability to be mass-produced. Therefore, this structure cannot meet industrial production and commercial applications. Summary of the invention

[0006] In order to solve at least one of the above problems, the present invention provides a gallium oxide MISFET device structure, which can better protect the gate dielectric and improve the reverse withstand voltage and short circuit tolerance without affecting the device threshold voltage.

[0007] Specifically, the present invention adopts the following technical solutions to achieve the above objectives:

[0008] A gallium oxide MISFET device structure comprises, from bottom to top, a drain, a gallium oxide substrate, an epitaxial layer and a source; in the epitaxial layer, a current blocking layer is arranged in the surface layer of the epitaxial layer, and the middle part of the current blocking layer is a current channel; at least one adjustment layer connected to the current blocking layer is arranged in the epitaxial layer at the current channel, the bottom of the adjustment layer extends toward the inside of the epitaxial layer close to the gallium oxide substrate, and the extension direction of the adjustment layer forms an obtuse angle with the current blocking layer; a gate dielectric layer is deposited on the upper surface of the epitaxial layer; ohmic contact metal layers forming ohmic contact with the epitaxial layer are arranged on both sides of the gate dielectric layer along the direction from the source to the drain; a gate is arranged on the upper surface of the gate dielectric layer, and a passivation dielectric layer is arranged between the gate and the source.

[0009] In a preferred embodiment, the gallium oxide substrate is an n-type gallium oxide substrate.

[0010] In a preferred embodiment, a low resistance layer is provided in the epitaxial layer, the upper surface of the low resistance layer is flush with the upper surface of the epitaxial layer, the lower surface of the low resistance layer contacts the upper surface of the current blocking layer, and the middle part of the low resistance layer is a current channel.

[0011] In a further preferred embodiment, the thickness of the low resistance layer is greater than 0 and does not exceed 0.4 μm.

[0012] In a further preferred embodiment, the doping concentration of the low resistance layer is 1×10 18 -1×10 20 cm -3 .

[0013] In a preferred embodiment, the epitaxial layer is an n-type gallium oxide layer.

[0014] In a preferred embodiment, the epitaxial layer has a thickness of 5 to 15 μm.

[0015] In a preferred embodiment, the doping concentration of the epitaxial layer is 5×10 15 ~5×10 16 cm -3 .

[0016] In a preferred embodiment, the thickness of the current blocking layer is 0.5-1 μm.

[0017] In a preferred embodiment, the distance between the top of the current blocking layer and the upper surface of the epitaxial layer is 0.2-1 μm.

[0018] In a preferred embodiment, the doping concentration of the current blocking layer is 1×10 18 ~1×10 20 cm -3 .

[0019] In a preferred embodiment, the length of the adjustment layer extending toward the inside of the epitaxial layer close to the gallium oxide substrate is 0.5-1 μm.

[0020] In a further preferred embodiment, the angle between the extending direction of the regulating layer and the current blocking layer is 135° to 165°.

[0021] In a preferred embodiment, the doping concentration of the regulating layer is 1×10 18 ~1×10 20 cm -3 .

[0022] In a preferred embodiment, the thickness of the gate dielectric layer is 30-100 nm.

[0023] In a preferred embodiment, the gate dielectric layer is made of any one of aluminum oxide, hafnium oxide, and barium titanate.

[0024] In a preferred embodiment, the gate electrode is made of any one of Cr, Pt and Au.

[0025] In a preferred embodiment, the thickness of the passivation dielectric layer is 0.5-2 μm.

[0026] In a preferred embodiment, the material of the passivation dielectric layer is any one of silicon dioxide, silicon nitride, and borophosphosilicate glass.

[0027] In a preferred embodiment, the thickness of the ohmic contact metal layer is 20-200 nm.

[0028] In a preferred embodiment, the metal of the ohmic contact metal layer is titanium.

[0029] In a preferred embodiment, the metal of the drain electrode is a titanium-gold alloy, wherein the thickness of the titanium layer is 20-200 nm, and the thickness of the gold layer is 50-200 nm.

[0030] In a preferred embodiment, the metal of the source electrode is Ti, Al, Cu, Au alloy layer, wherein the thickness of the Ti layer is 10-100 nm, the thickness of the Al layer is 50-100 nm, the thickness of the Cu layer is 10-50 nm, and the thickness of the Au layer is 50-200 nm.

[0031] The present invention also provides a method for preparing the gallium oxide MISFET device structure, comprising the following steps:

[0032] growing an epitaxial layer on a gallium oxide substrate;

[0033] Forming current blocking layers at both ends of the epitaxial layer away from the gallium oxide substrate by ion implantation, and a current channel is formed between the two current blocking layers;

[0034] Forming at least one adjustment layer connected to the current blocking layer in the epitaxial layer at the current channel by ion implantation using an off-angle implantation method;

[0035] Depositing a gate dielectric layer on a surface of the epitaxial layer away from the gallium oxide substrate, and manufacturing a gate on the surface of the gate dielectric layer;

[0036] Depositing a passivation dielectric layer on the surface of the epitaxial layer away from the gallium oxide substrate; making a drain on the surface of the gallium oxide substrate away from the epitaxial layer;

[0037] Etching away both sides of the gate dielectric layer and the passivation dielectric layer, and evaporating an ohmic contact metal layer, and annealing;

[0038] A metal layer is deposited on the surface of the obtained device structure as a source electrode.

[0039] In a preferred embodiment, after the adjustment layer is formed, a low-resistance layer is formed in the epitaxial layer by ion implantation.

[0040] In a further preferred embodiment, the element implanted into the low resistance layer is silicon or tin.

[0041] In a further preferred embodiment, the ion implantation conditions for forming the low resistance layer are: implantation energy of 20 to 100 keV, implantation dose of 1.5×10 13 ~2.5×10 13 cm -2 .

[0042] In a preferred embodiment, the ion implantation conditions for forming the current blocking layer are: implantation energy of 300-400 keV, implantation dose of 3.0×10 13 ~4.0×10 13 cm -2 .

[0043] In a preferred embodiment, the implantation element of the current blocking layer is nitrogen or magnesium.

[0044] In a preferred embodiment, the ion implantation conditions for forming the adjustment layer are: implantation energy of 450-550 keV, implantation dose of 3.8×10 13 ~4.8×10 13 cm -2 .

[0045] In a preferred embodiment, the implanted element of the adjustment layer is nitrogen or magnesium.

[0046] In a preferred embodiment, the annealing condition is: in an inert gas atmosphere, maintaining at 450-500° C. for 60-120 seconds.

[0047] In a preferred embodiment, the angle of the off-angle implantation is 15° to 45° relative to the surface of the epitaxial layer.

[0048] The present invention has the following beneficial effects: (1) The preparation of gallium oxide MISFET is achieved by controlling the injection depth of the current blocking layer (the distance between the top surface of the current blocking layer and the upper surface of the epitaxial layer). When the injection depth of the current blocking layer is small enough, the work function difference between the gate metal and the epitaxial layer will cause the electrons in this injection depth to be depleted. When the gate voltage is 0V and the drain-source is forward biased, the device is normally off due to the lack of a conductive channel. When the gate-source voltage is forward biased, the electrons are attracted to the bottom of the gate dielectric layer under the attraction of the gate electric field to form an inversion layer. Under the forward biased drain-source voltage, the device is turned on. (2) In the gallium oxide MISFET device structure of the present invention, a high resistance layer is formed under the current channel as a regulating layer of the device. On the one hand, the regulating layer can shield the reverse electric field inside the device, reduce the electric field strength at the interface, and increase the life of the gate dielectric layer; on the other hand, the regulating layer occupies part of the current channel, thereby reducing the forward saturation current, which can improve the short-circuit tolerance of the device, so that when a short circuit occurs in the device, there is enough time to shut down. (3) The method for preparing gallium oxide MISFET devices in the present invention is completed by converting a more difficult photolithography process into an easily controlled ion implantation process. It no longer relies on expensive and inefficient electron beam lithography machines to form lines below 0.3 μm, but controls the energy of ion implantation to achieve a conductive layer with a thickness of less than 1 μm. Therefore, the method has higher production stability, making it possible to mass produce gallium oxide enhancement devices, and the photolithography of other steps can be completed by i-line and g-line lithography machines. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 is a schematic diagram of the gallium oxide MISFET device structure provided in Example 1, and is also a schematic diagram of the gallium oxide MISFET device structure prepared in Example 6;

[0050] Figures 2 to 9 Schematic diagram of the structure obtained in each step of the process of preparing the gallium oxide MISFET device structure in Examples 3, 4, and 5; Fig. 9 It is also a schematic diagram of the gallium oxide MISFET device structure provided in Example 2;

[0051] Fig.10 A schematic diagram of another gallium oxide MISFET device structure provided by the present invention;

[0052] Fig.11 Combination Fig. 9 A schematic diagram of another gallium oxide MISFET device structure provided by the present invention, wherein the regulating layer is arranged in three-dimensional space;

[0053] Fig.12 A schematic diagram of another gallium oxide MISFET device structure provided by the present invention.

[0054] In the figure: 1. Gallium oxide substrate; 2. Epitaxial layer; 3. Current blocking layer; 4. Second photoresist layer; 5. Second window; 6. Adjustment layer; 7. Low resistance layer; 8. Gate dielectric layer; 9. Gate; 10. Passivation dielectric layer; 11. Drain; 12. Ohmic contact metal layer; 13. Source; 14. Current channel. DETAILED DESCRIPTION

[0055] The following content is combined with the embodiments to clearly and completely describe the technical solution of the present invention so that those skilled in the art can fully understand the present invention. Obviously, the described embodiments are only some preferred embodiments of the present invention, rather than all embodiments. Any equivalent transformation or substitution made by ordinary technicians in this field to the following implementation methods without creative work belongs to the protection scope of the present invention.

[0056] Directional terms mentioned in the present invention, such as words such as "from bottom to top", "up", "lower", "top" and the like, refer to directions in the accompanying drawings. Therefore, directional terms are only used for illustration and not for limiting the present invention. Ordinal numbers used in the present invention, such as "first", "second", etc., are only used for descriptive purposes to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The "thickness" described in the following embodiments refers to the dimension of the element along the direction from the drain to the source (or along the gallium oxide substrate to the epitaxial layer). The methods not described in detail in the following embodiments are all conventional methods well known to those skilled in the art.

[0057] The present invention provides a gallium oxide MISFET device structure, which comprises a drain electrode, a gallium oxide substrate, an epitaxial layer and a source electrode in order from bottom to top; in the epitaxial layer, a current blocking layer is arranged in the surface layer of the epitaxial layer, and the middle part of the current blocking layer is a current channel; at least one adjustment layer connected to the current blocking layer is arranged in the epitaxial layer at the current channel, and the bottom of the adjustment layer extends toward the inside of the epitaxial layer close to the gallium oxide substrate, and the extension direction of the adjustment layer forms an obtuse angle with the current blocking layer; a gate dielectric layer is deposited on the upper surface of the epitaxial layer; ohmic contact metal layers forming ohmic contact with the epitaxial layer are arranged on both sides of the gate dielectric layer along the direction from the source electrode to the drain electrode; a gate electrode is arranged on the upper surface of the gate dielectric layer, and a passivation dielectric layer is arranged between the gate electrode and the source electrode.

[0058] In some embodiments, a low resistance layer is provided in the epitaxial layer, the upper surface of the low resistance layer is flush with the upper surface of the epitaxial layer, the lower surface of the low resistance layer contacts the upper surface of the current blocking layer, and the middle part of the low resistance layer is a current channel.

[0059] The method for preparing the gallium oxide MISFET device structure of the present invention comprises the following steps:

[0060] growing an epitaxial layer on a gallium oxide substrate;

[0061] Forming current blocking layers at both ends of the epitaxial layer away from the gallium oxide substrate by ion implantation, and a current channel is formed between the two current blocking layers;

[0062] Forming at least one adjustment layer connected to the current blocking layer in the epitaxial layer at the current channel by ion implantation using an off-angle implantation method;

[0063] Depositing a gate dielectric layer on a surface of the epitaxial layer away from the gallium oxide substrate, and manufacturing a gate on the surface of the gate dielectric layer;

[0064] Depositing a passivation dielectric layer on the surface of the epitaxial layer away from the gallium oxide substrate; making a drain on the surface of the gallium oxide substrate away from the epitaxial layer;

[0065] Etching away both sides of the gate dielectric layer and the passivation dielectric layer, and evaporating an ohmic contact metal layer, and annealing;

[0066] A metal layer is deposited on the surface of the obtained device structure as a source electrode.

[0067] In some embodiments, after the adjustment layer is fabricated, a low-resistance layer is formed in the epitaxial layer by ion implantation.

[0068] Furthermore, the doping type of the gallium oxide substrate is n-type.

[0069] Furthermore, the thickness of the low-resistance layer is greater than 0 and does not exceed 0.4 μm, preferably 0.3 μm.

[0070] Furthermore, the doping concentration of the low resistance layer is 1×10 18 -1×10 20 cm -3 ; preferably 5×10 19 cm -3 .

[0071] Furthermore, the implanted element of the low resistance layer is silicon or tin, preferably silicon.

[0072] In some embodiments, the epitaxial layer is an n-type gallium oxide layer.

[0073] In some embodiments, the thickness of the epitaxial layer is 5 to 15 μm, preferably 10 μm.

[0074] In some embodiments, the doping concentration of the epitaxial layer is 5×10 15~5×10 16 cm -3 ; preferably 2×10 16 cm -3 .

[0075] In some embodiments, the current blocking layer has a thickness of 0.5-1 μm.

[0076] In some embodiments, the distance between the top of the current blocking layer and the upper surface of the epitaxial layer is 0.2-1 μm.

[0077] In some embodiments, the doping concentration of the current blocking layer is 1×10 18 ~1×10 20 cm -3 ; preferably 5×10 19 cm -3 .

[0078] In some embodiments, the implantation element of the current blocking layer is nitrogen or magnesium.

[0079] In some embodiments, the length of the adjustment layer extending into the inner portion of the epitaxial layer close to the gallium oxide substrate is 0.5-1 μm.

[0080] In some embodiments, an angle between an extending direction of the regulating layer and the current blocking layer is 135° to 165°.

[0081] In some embodiments, the doping concentration of the regulating layer is 1×10 18 ~1×10 20 cm -3 ; preferably 5×10 19 cm -3 .

[0082] In some embodiments, the implanted element of the regulating layer is nitrogen or magnesium.

[0083] In some embodiments, the gate dielectric layer has a thickness of 30-100 nm.

[0084] In some embodiments, the gate dielectric layer is made of any one of aluminum oxide, hafnium oxide, and barium titanate.

[0085] In some embodiments, the gate is made of any one of Cr, Pt, and Au.

[0086] In some embodiments, the thickness of the passivation dielectric layer is 0.5-2 μm.

[0087] In some embodiments, the material of the passivation dielectric layer is any one of silicon dioxide, silicon nitride, and borophosphosilicate glass (BPSG).

[0088] In some embodiments, the thickness of the ohmic contact metal layer is 20-200 nm.

[0089] In some embodiments, the metal of the ohmic contact metal layer is titanium.

[0090] In some embodiments, the ion implantation conditions for forming the low resistance layer are: implantation energy of 20 to 100 keV, implantation dose of 1.5×10 13 ~2.5×10 13 cm -2 .

[0091] In some embodiments, the ion implantation conditions for forming the current blocking layer are: implantation energy of 300-400 keV, implantation dose of 3.0×10 13 ~4.0×10 13 cm -2 .

[0092] In some embodiments, the ion implantation conditions for forming the adjustment layer are: implantation energy of 450-550 keV, implantation dose of 3.8×10 13 ~4.8×10 13 cm -2 .

[0093] In some embodiments, the annealing condition is: in an inert gas atmosphere, maintaining at 450-500° C. for 60-120 seconds.

[0094] In some embodiments, the angle of the off-angle implantation is 15° to 45° relative to the surface of the epitaxial layer.

[0095] In some embodiments, the metal of the drain electrode is a titanium-gold alloy, wherein the thickness of the titanium layer is 20 to 200 nm, and the thickness of the gold layer is 50 to 200 nm.

[0096] In some embodiments, the metal of the source electrode is a Ti, Al, Cu, Au alloy layer, wherein the thickness of the Ti layer is 10-100 nm, the thickness of the Al layer is 50-100 nm, the thickness of the Cu layer is 10-50 nm, and the thickness of the Au layer is 50-200 nm.

[0097] Example 1

[0098] like Figure 1As shown, this embodiment provides a gallium oxide MISFET device structure, which includes a drain 11, a gallium oxide substrate 1, an epitaxial layer 2 and a source 13 from bottom to top. A current blocking layer 3 is formed by ion implantation at both ends of the epitaxial layer 2 near the upper surface. The middle of the current blocking layer 3 is a current channel 14. The epitaxial layer 2 between the top of the current blocking layer 3 and the upper surface of the epitaxial layer 2 is a conductive layer. An adjustment layer 6 is formed in the epitaxial layer 2 at the location of the current channel 14 by ion implantation. The adjustment layer 6 is connected to the current blocking layer 3, and the bottom of the adjustment layer 6 extends toward the inside of the epitaxial layer 2 close to the gallium oxide substrate 1, and the angle between the extension direction and the current blocking layer 3 is an obtuse angle (for example, 135°). A gate dielectric layer 8 is deposited on the upper surface of the epitaxial layer 2. Along the direction from the source 13 to the drain 11, ohmic contact metal layers 12 that form ohmic contact with the epitaxial layer 2 are deposited on both sides of the gate dielectric layer 8. A gate 9 is deposited on the upper surface of the gate dielectric layer 8. A passivation dielectric layer 10 is deposited on the upper surface of the gate 9, and a source 13 is deposited on the upper surface of the device. The passivation dielectric layer 10 is used to isolate the gate 9 and the source 13. The doping type of the gallium oxide substrate 1 is n-type. The epitaxial layer 2 is 10 μm thick and has a doping concentration of 2×10 16 cm -3 The injection element of the current blocking layer 3 is nitrogen, the thickness is 0.5 μm, and the doping concentration is 5×10 19 cm -3 The distance between the top of the current blocking layer 3 and the upper surface of the epitaxial layer 2 is 0.2 μm. The implanted element of the adjustment layer 6 is nitrogen, and the doping concentration is 5×10 19 cm -3 , the length of the adjustment layer 6 extending into the epitaxial layer 2 close to the gallium oxide substrate 1 is 0.5μm. The gate dielectric layer 8 is an aluminum oxide layer with a thickness of 30nm. The material of the gate 9 is Cr metal. The passivation dielectric layer 10 is a silicon dioxide layer with a thickness of 1μm. The drain 11 is a titanium-gold alloy layer, wherein the titanium layer is 20nm thick and the gold layer is 80nm thick. The ohmic contact metal layer 12 is a titanium layer with a thickness of 20nm. The source 13 is a Ti, Al, Cu, and Au alloy layer, wherein the thickness of the Ti layer is 10nm, the thickness of the Al layer is 70nm, the thickness of the Cu layer is 10nm, and the thickness of the Au layer is 60nm.

[0099] Example 2

[0100] like Fig. 9As shown, this embodiment provides a gallium oxide MISFET device structure, which includes a drain 11, a gallium oxide substrate 1, an epitaxial layer 2 and a source 13 from bottom to top. A current blocking layer 3 is formed by ion implantation at both ends of the epitaxial layer 2 near the upper surface. The middle of the current blocking layer 3 is a current channel 14. The epitaxial layer 2 between the top of the current blocking layer 3 and the upper surface of the epitaxial layer 2 is a conductive layer. An adjustment layer 6 is formed in the epitaxial layer 2 at the location of the current channel 14 by ion implantation. The adjustment layer 6 is connected to the current blocking layer 3, and its bottom extends to the inside of the epitaxial layer 2 close to the gallium oxide substrate 1, and the angle between the extension direction and the current blocking layer 3 is an obtuse angle (for example, 150°). A low resistance layer 7 is formed by ion implantation in the epitaxial layer 2 above the current blocking layer 3, the upper surface of the low resistance layer 7 is flush with the upper surface of the epitaxial layer 2, and the lower surface is in contact with the upper surface of the current blocking layer 3, and the epitaxial layer 2 in the middle of the low resistance layer 7 is the current channel 14. A gate dielectric layer 8 is deposited on the upper surface of the epitaxial layer 2. In the direction from the source 13 to the drain 11, ohmic contact metal layers 12 are deposited on both sides of the gate dielectric layer 8 to form an ohmic contact with the epitaxial layer 2. A gate 9 is deposited on the upper surface of the gate dielectric layer 8. A passivation dielectric layer 10 is deposited on the upper surface of the gate 9. The source 13 is deposited on the upper surface of the device. The passivation dielectric layer 10 is used to isolate the gate 9 and the source 13. The implanted element of the low-resistance layer 7 is silicon, the thickness is 0.3 μm, and the doping concentration is 5×10 19 cm -3 The materials, sizes, doping types and concentrations of other components are the same as those in Example 1.

[0101] Example 3

[0102] Referring to 2 to 9, this embodiment provides a method for preparing a gallium oxide MISFET device structure, comprising the following steps:

[0103] S1. On the gallium oxide substrate 1, HVPE (Hydride Vapor Phase Epitaxy) method is used to epitaxially grow a doping concentration of 2×10 16 cm -3 , an n-type gallium oxide epitaxial layer with a thickness of 10μm.

[0104] S2, apply a first photoresist on the upper surface of the epitaxial layer 2, and form a first window by photolithography for injecting a current blocking layer; inject nitrogen into both ends of the epitaxial layer 2 near the upper surface by ion implantation at room temperature to form a current blocking layer 3, and then remove the first photoresist. The middle of the two current blocking layers 3 is a current channel 14. The energy for injecting nitrogen is 350keV, and the injection dose is 3.6×10 13 cm -2 The doping concentration of the current blocking layer 3 is 5×10 19 cm-3 The thickness in the direction from the gallium oxide substrate 1 to the epitaxial layer 2 is 0.5 μm, and the distance between the top and the upper surface of the epitaxial layer 2 is 0.2 μm.

[0105] S3, apply a second photoresist on the upper surface of the epitaxial layer 2 to form a second photoresist layer 4, and form a second window 5 by photolithography for injecting the adjustment layer; inject nitrogen into the epitaxial layer 2 through the second window 5 by ion implantation at room temperature using a deflection implantation method to form an adjustment layer 6, and then remove the second photoresist layer 4. The energy for injecting nitrogen is 500 keV, and the implantation dose is 4.0×10 13 cm -2 The doping concentration of the adjustment layer 6 is 5×10 19 cm -3 The length extending in the epitaxial layer 2 toward the gallium oxide substrate 1 is 0.5 μm, the distance between its top and the upper surface of the epitaxial layer 2 is 0.2 μm, and the bias injection angle is 30° relative to the upper surface of the epitaxial layer 2, that is, the angle between the extension direction of the adjustment layer 6 and the current blocking layer 3 is 150°.

[0106] S4, apply a third photoresist on the upper surface of the epitaxial layer 2, and form a third window by photolithography for injecting the low-resistance layer; in the direction from the epitaxial layer 2 to the gallium oxide substrate 1, silicon is injected into both sides of the epitaxial layer 2 by ion implantation at room temperature to form a low-resistance layer 7, and the epitaxial layer 2 located between the two parts of the low-resistance layer 7 is the current channel 14. The upper surface of the low-resistance layer 7 is flush with the upper surface of the epitaxial layer 2, and the lower surface is in contact with the upper surface of the current blocking layer 3. The energy for injecting silicon is 20keV, and the injection dose is 2.3×10 13 cm -2 The doping concentration of the low resistance layer 7 is 5×10 19 cm -3 , thickness is 0.3μm.

[0107] S5, depositing a 30nm thick aluminum oxide layer on the upper surface of the epitaxial layer 2 as the gate dielectric layer 8. Depositing metal Cr on the upper surface of the gate dielectric layer 8, and then patterning and etching the Cr metal layer using an i-line photolithography machine to obtain a gate 9.

[0108] S6. Deposit 1 μm thick silicon dioxide on the upper surface of the device structure obtained in step S4 as a passivation dielectric layer 10 for isolating the gate and the source.

[0109] S7, evaporating a titanium-gold alloy layer on the lower surface of the substrate 1 as the drain electrode 11. The thickness of the titanium layer is 20 nm, and the thickness of the gold layer is 80 nm.

[0110] S8, etching away both sides of the gate dielectric layer 8 and the passivation dielectric layer 10, and then evaporating a 20nm thick titanium metal layer as the ohmic contact metal layer 12, and annealing the obtained device at 470°C for 90s in a nitrogen atmosphere so that the ohmic contact metal layer 12 forms an ohmic contact with the epitaxial layer 2.

[0111] S9, depositing Ti, Al, Cu, and Au alloy layers on the surface of the device structure obtained in step S7 as the source electrode 13. The thickness of the Ti layer is 10 nm, the thickness of the Al layer is 70 nm, the thickness of the Cu layer is 10 nm, and the thickness of the Au layer is 60 nm.

[0112] Example 4

[0113] Reference Figures 2 to 9 This embodiment provides a method for preparing a gallium oxide MISFET device structure, comprising the following steps:

[0114] S1. On the gallium oxide substrate 1, HVPE (Hydride Vapor Phase Epitaxy) method is used to epitaxially grow a doping concentration of 5×10 15 cm -3 , an n-type gallium oxide epitaxial layer with a thickness of 5μm.

[0115] S2, apply a first photoresist on the upper surface of the epitaxial layer 2, and form a first window for injecting a current blocking layer by photolithography; inject Mg into the epitaxial layer at room temperature to form a current blocking layer 3, and then remove the first photoresist. The middle of the two current blocking layers 3 is a current channel 14. The energy for injecting magnesium is 300 keV, and the injection dose is 3.0×10 13 cm -2 The doping concentration of the current blocking layer 3 is 1×10 18 cm -3 , with a thickness of 0.7 μm and a distance of 1 μm between its top and the upper surface of the epitaxial layer 2.

[0116] S3, apply the second photoresist 4 on the upper surface of the epitaxial layer 2, and form the second window 5 by photolithography for injecting the adjustment layer; inject Mg element into the epitaxial layer 2 through the second window 5 at room temperature by using the angle injection method to form the adjustment layer 6, and then remove the second photoresist 4. The energy for injecting the magnesium element is 450keV, and the injection dose is 3.8×10 13 cm -2 The doping concentration of the adjustment layer 6 is 1×10 18 cm -3The length extending in the epitaxial layer 2 toward the gallium oxide substrate 1 is 0.8 μm, the distance between its top and the upper surface of the epitaxial layer 2 is 1 μm, and the bias injection angle is 15° relative to the upper surface of the epitaxial layer 2, that is, the angle between the extension direction of the adjustment layer 6 and the current blocking layer 3 is 165°.

[0117] S4, a third photoresist is applied on the upper surface of the epitaxial layer 2, and a third window is formed by photolithography for injecting the low-resistance layer; in the direction from the epitaxial layer 2 to the gallium oxide substrate 1, tin is injected into both sides of the epitaxial layer 2 at room temperature to form a low-resistance layer 7, and the epitaxial layer 2 located between the two parts of the low-resistance layer 7 is the current channel 14. The upper surface of the low-resistance layer 7 is flush with the upper surface of the epitaxial layer 2, and the lower surface is in contact with the upper surface of the current blocking layer 3. The energy for injecting the tin element is 50 keV, and the injection dose is 1.5×10 13 cm -2 The doping concentration of the low resistance layer 7 is 1×10 18 cm -3 , thickness is 0.4μm.

[0118] S5, depositing a 50 nm thick barium titanate layer on the upper surface of the epitaxial layer 2 as the gate dielectric layer 8. Depositing metal Pt on the upper surface of the gate dielectric layer 8, and then patterning and etching the Pt metal layer using a g-line photolithography machine to obtain a gate 9.

[0119] S6. Deposit a 0.5 μm thick silicon nitride layer on the upper surface of the device structure obtained in step S4 as a passivation dielectric layer 10 for isolating the gate and the source.

[0120] S7, evaporating a titanium-gold alloy layer on the lower surface of the substrate 1 as the drain electrode 11. The thickness of the titanium layer is 200 nm, and the thickness of the gold layer is 50 nm.

[0121] S8, etching away both sides of the gate dielectric layer 8 and the passivation dielectric layer 10, and then evaporating a 200nm thick titanium metal layer as the ohmic contact metal layer 12, and annealing the obtained device at 450°C for 120s in a nitrogen atmosphere so that the ohmic contact metal layer 12 forms an ohmic contact with the epitaxial layer 2.

[0122] S9, depositing Ti, Al, Cu, and Au alloy layers on the surface of the device structure obtained in step S7 as the source electrode 13. The thickness of the Ti layer is 30 nm, the thickness of the Al layer is 50 nm, the thickness of the Cu layer is 20 nm, and the thickness of the Au layer is 200 nm.

[0123] Example 5

[0124] Reference Figures 2 to 9 This embodiment provides a method for preparing a gallium oxide MISFET device structure, comprising the following steps:

[0125] S1. On the gallium oxide substrate 1, HVPE (Hydride Vapor Phase Epitaxy) method is used to epitaxially grow a doping concentration of 5×10 16 cm -3 , an n-type gallium oxide epitaxial layer with a thickness of 15μm.

[0126] S2, apply a first photoresist on the upper surface of the epitaxial layer 2, and form a first window for injecting a current blocking layer by photolithography; inject nitrogen into the epitaxial layer at room temperature to form a current blocking layer 3, and then remove the first photoresist. The middle of the two current blocking layers 3 is a current channel 14. The energy for injecting nitrogen is 400keV, and the injection dose is 4.0×10 13 cm -2 The doping concentration of the current blocking layer 3 is 1×10 20 cm -3 , with a thickness of 1 μm and a distance of 0.5 μm between its top and the upper surface of the epitaxial layer 2.

[0127] S3, apply the second photoresist 4 on the upper surface of the epitaxial layer 2, and form the second window 5 by photolithography for injecting the adjustment layer; inject Mg element into the epitaxial layer 2 through the second window 5 by the deflection injection method at room temperature to form the adjustment layer 6, and then remove the second photoresist 4. The energy for injecting the magnesium element is 550keV, and the injection dose is 4.8×10 13 cm -2 The doping concentration of the adjustment layer 6 is 1×10 20 cm -3 The length extending in the epitaxial layer 2 toward the gallium oxide substrate 1 is 1 μm, the distance between its top and the upper surface of the epitaxial layer 2 is 0.5 μm, and the bias injection angle is 45° relative to the upper surface of the epitaxial layer 2, that is, the angle between the extension direction of the adjustment layer 6 and the current blocking layer 3 is 135°.

[0128] S4, apply a third photoresist on the upper surface of the epitaxial layer 2, and form a third window by photolithography for injecting the low-resistance layer; in the direction from the epitaxial layer 2 to the gallium oxide substrate 1, inject silicon elements into both sides of the epitaxial layer 2 at room temperature to form a low-resistance layer 7, and the epitaxial layer 2 located between the two parts of the low-resistance layer 7 is the current channel 14. The upper surface of the low-resistance layer 7 is flush with the upper surface of the epitaxial layer 2, and the lower surface is in contact with the upper surface of the current blocking layer 3. The energy for injecting silicon elements is 100 keV, and the injection dose is 2.5×10 13 cm -2 The doping concentration of the low resistance layer 7 is 1×10 20 cm -3 , thickness is 0.1μm.

[0129] S5, depositing a 100 nm thick hafnium oxide layer on the upper surface of the epitaxial layer 2 as the gate dielectric layer 8. Depositing metal Au on the upper surface of the gate dielectric layer 8, and then patterning and etching the Au metal layer using an i-line lithography machine to obtain a gate 9.

[0130] S6. Deposit a BPSG layer with a thickness of 2 μm on the upper surface of the device structure obtained in step S4 as a passivation dielectric layer 10 for isolating the gate and the source.

[0131] S7, vapor-depositing a titanium-gold alloy layer on the lower surface of the gallium oxide substrate 1 as the drain electrode 11. The thickness of the titanium layer is 50 nm, and the thickness of the gold layer is 200 nm.

[0132] S8, etching away both sides of the gate dielectric layer 8 and the passivation dielectric layer 10, and then evaporating a 100nm thick titanium metal layer as the ohmic contact metal layer 12, and annealing the obtained device at 450°C for 120s in a nitrogen atmosphere so that the ohmic contact metal layer 12 forms an ohmic contact with the epitaxial layer 2.

[0133] S9, depositing Ti, Al, Cu, and Au alloy layers on the surface of the device structure obtained in step S7 as the source electrode 13. The thickness of the Ti layer is 30 nm, the thickness of the Al layer is 50 nm, the thickness of the Cu layer is 20 nm, and the thickness of the Au layer is 200 nm.

[0134] Example 6

[0135] The method for preparing the gallium oxide MISFET device structure in this embodiment is different from that in embodiment 3 in that only one adjustment layer 6 is formed in step S3, and there is no step S4. The obtained device structure is as follows: Figure 1 shown.

[0136] It should be noted that the cell structure of the gallium oxide MISFET device in the present invention is not limited in any way, and can generally be a bar, square, circle or hexagon. In order to balance the forward conduction and reverse withstand voltage performance of the device, in addition to the structure in the embodiment, when the adjustment layer 6 is formed by ion implantation in step S3, it can be as follows Fig.10 The single-sided injection shown can also be Fig. 9 and Fig.11 The shown arrangement is formed periodically in three-dimensional space. Fig. 9 and Fig.11 The upper section AA' is perpendicular to the section BB'. Fig.12 As shown, in order to achieve better electric field shielding effect and short-circuit tolerance, the adjustment layer 6 can be injected on both sides in some directions in the three-dimensional space (such as on the section AA') and the adjustment layers on both sides are connected, while in other directions (such as on the section BB'), the adjustment layer can be any one of a single-sided structure, a double-sided structure or no adjustment layer.

[0137] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. For any person skilled in the art, the present invention may have various changes and modifications. Any simple equivalent changes and modifications made according to the scope of protection of the present invention and the contents of the specification should be included in the scope of protection of the present invention.

Claims

1. A gallium oxide MISFET device structure, characterized in that: It includes a drain electrode, a gallium oxide substrate, an epitaxial layer and a source electrode from bottom to top; in the epitaxial layer, a current blocking layer is arranged in the surface layer of the epitaxial layer, and the distance between the top of the current blocking layer and the upper surface of the epitaxial layer is 0.2-1 μm; The middle part of the current blocking layer is a current channel; at least one adjustment layer connected to the current blocking layer is arranged in the epitaxial layer at the current channel; the bottom of the adjustment layer extends toward the inside of the epitaxial layer close to the gallium oxide substrate, and the extension direction forms an obtuse angle with the current blocking layer; a gate dielectric layer is deposited on the upper surface of the epitaxial layer; ohmic contact metal layers forming ohmic contact with the epitaxial layer are arranged on both sides of the gate dielectric layer in a direction from the source electrode to the drain electrode; a gate is arranged on the upper surface of the gate dielectric layer, and a passivation dielectric layer is arranged between the gate electrode and the source electrode.

2. The gallium oxide MISFET device structure according to claim 1, characterized in that: The thickness of the current blocking layer is 0.5-1 μm; or / and the length of the regulating layer extending toward the inside of the epitaxial layer close to the gallium oxide substrate is 0.5-1 μm.

3. The gallium oxide MISFET device structure according to claim 1, characterized in that: The thickness of the gate dielectric layer is 30-100 nm; or / and the thickness of the passivation dielectric layer is 0.5-2 μm; or / and the thickness of the ohmic contact metal layer is 20-200 nm.

4. The gallium oxide MISFET device structure according to claim 1, characterized in that: The doping concentration of the epitaxial layer is 5×10 15 ~5×10 16 cm -3 ; or / and the doping concentration of the current blocking layer is 1×10 18 ~1×10 20 cm -3 ; or / and the doping concentration of the adjustment layer is 1×10 18 ~1×10 20 cm -3 .

5. The gallium oxide MISFET device structure according to claim 1, characterized in that: A low resistance layer is arranged in the epitaxial layer, the upper surface of the low resistance layer is flush with the upper surface of the epitaxial layer, the lower surface of the low resistance layer contacts the upper surface of the current blocking layer, and the middle part of the low resistance layer is a current channel.

6. The gallium oxide MISFET device structure according to claim 5, characterized in that: The thickness of the low resistance layer is greater than 0 and does not exceed 0.4 μm.

7. The gallium oxide MISFET device structure according to claim 5, characterized in that: The doping concentration of the low resistance layer is 1×10 18 ~1×10 20 cm -3 .

8. The method for preparing a gallium oxide MISFET device structure according to any one of claims 1 to 7, characterized in that: The following steps are involved: growing an epitaxial layer on a gallium oxide substrate; Forming current blocking layers at both ends of the epitaxial layer away from the gallium oxide substrate by ion implantation, and a current channel is formed between the two current blocking layers; Forming at least one adjustment layer connected to the current blocking layer in the epitaxial layer at the current channel by ion implantation using an off-angle implantation method; Depositing a gate dielectric layer on a surface of the epitaxial layer away from the gallium oxide substrate, and manufacturing a gate on the surface of the gate dielectric layer; Depositing a passivation dielectric layer on the surface of the epitaxial layer away from the gallium oxide substrate; making a drain on the surface of the gallium oxide substrate away from the epitaxial layer; Etching away both sides of the gate dielectric layer and the passivation dielectric layer, and evaporating an ohmic contact metal layer, and annealing; A metal layer is deposited on the surface of the obtained device structure as a source electrode.

9. The preparation method according to claim 8, characterized in that: After the adjustment layer is manufactured, a low-resistance layer is formed in the epitaxial layer by ion implantation.

10. The preparation method according to claim 8, characterized in that: The annealing condition is to maintain the temperature at 450-500° C. for 60-120 seconds in an inert gas atmosphere; or / and the angle of the off-angle implantation is 15°-45° relative to the surface of the epitaxial layer.

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