Memory, electronic device

Abstract

Embodiments of the present application provide a memory and an electronic device, and relate to the technical field of memories, and are used to improve the area utilization of the memory while implementing unipolar memory. The memory comprises a first circuit structure layer, a second circuit structure layer and a plurality of interconnection structures. The first circuit structure layer comprises a first inverter. The second circuit structure layer comprises a second inverter. The plurality of transistors of the first inverter and the plurality of transistors of the second inverter have the same polarity. The plurality of transistors of the first inverter and the plurality of transistors of the second inverter are sequentially arranged along a first direction parallel to a reference surface. The orthographic projection of the plurality of transistors of the first inverter on the reference surface and the orthographic projection of the plurality of transistors of the second inverter on the reference surface overlap, and the first inverter and the second inverter are electrically connected through the plurality of interconnection structures. The above-mentioned memory is applied to an electronic device to improve the storage capacity of the electronic device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, in particular to a memory and an electronic device. BACKGROUND

[0002] Static random access memory (SRAM) is a kind of semiconductor memory based on flip-flop logic circuit. As long as it is in the power-on state, the information written in SRAM will not disappear, and no refresh circuit is needed. As shown in Figure 1 The traditional silicon (Si) based SRAM includes 6 metal oxide semiconductor field effect transistors (MOSFETs). Among them, Q1, Q2, Q5 and Q6 are n-type metal oxide semiconductor field effect transistors (NMOSFETs), and Q3 and Q4 are p-type metal oxide semiconductor field effect transistors (PMOSFETs).

[0003] In the computer storage architecture, the storage speed of SRAM is fast, and it is mainly used for cache, generally integrated in the central processing unit (CPU). With the continuous improvement of computer performance, SRAM as an important medium for data exchange occupies more and more area in CPU, resulting in serious degradation of power performance area cost (PPAC).

[0004] Therefore, the academic and industrial circles have proposed to use 3D stacking method to improve the area utilization of chips while continuously improving the chip process. SRAM is a relatively independent module compared with other logic computing units, and it is easier to integrate SRAM and logic devices in 3D by using back-end-of-line (BEOL) or stacking process.

[0005] However, for the traditional silicon-based SRAM, it is very difficult to realize 3D integration by using BEOL process or stack process, and the process temperature requirement is also very high. Although the oxide semiconductor has the advantages of stackability and low-temperature process, the oxide semiconductor is a unipolar channel material, which makes the circuit design of the SRAM more complex when applied to the SRAM, and causes the area occupied by the devices (such as transistors) in the SRAM and the interconnection lines between the devices to increase. SUMMARY

[0006] Embodiments of the present application provide a memory and an electronic device, which are used to realize unipolar memory while improving the area utilization of the memory.

[0007] To achieve the above object, embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a memory is provided, which includes a first circuit structure layer, a second circuit structure layer and a plurality of interconnection structures. The first circuit structure layer includes a first inverter. The second circuit structure layer is arranged in a stack with the first circuit structure layer and includes a second inverter. The plurality of interconnection structures are located between the first circuit structure layer and the second circuit structure layer.

[0009] The first inverter and the second inverter each include a plurality of transistors, and the plurality of transistors of the first inverter and the plurality of transistors of the second inverter have the same polarity. The plurality of transistors of the first inverter and the plurality of transistors of the second inverter are arranged in sequence along a first direction parallel to a reference plane. The reference plane is a plane on which a lower surface of the first circuit structure layer is located. The orthogonal projection of the plurality of transistors of the first inverter on the reference plane and the orthogonal projection of the plurality of transistors of the second inverter on the reference plane overlap, and the first inverter and the second inverter are electrically connected through the plurality of interconnection structures.

[0010] In the memory provided by the embodiments of the present application, the plurality of transistors in the first inverter and the second inverter have the same polarity, so that the plurality of transistors can be prepared by using a unipolar channel material (such as an oxide semiconductor material, an organic semiconductor material, etc.) in the process of preparing the memory, thereby enabling the memory to be prepared by using a back-end-of-line process or a stack process, simplifying the process, realizing 3D integration of the memory and a logic device for controlling the memory, reducing the occupied area of the memory, and improving the area utilization of the memory.

[0011] The same polarity of the plurality of transistors also enables the plurality of transistors to be arranged compactly, and the storage unit does not need to use additional space to separate transistors of different polarities, thereby further reducing the occupied area of the storage unit and improving the area utilization of the memory.

[0012] Compared with the case that the whole memory cell is arranged in the same circuit structure layer, the first inverter of the memory cell is arranged in the first circuit structure layer and the second inverter is arranged in the second circuit structure layer in the embodiment of the present application, so that 3D stacking of the memory cell is realized, and the area utilization of the memory can be further improved.

[0013] Meanwhile, in the memory provided by the embodiment of the present application, the plurality of transistors in the first inverter are arranged in the first direction in sequence, and the plurality of transistors are arranged regularly, so that the area occupied by the first inverter in the first circuit structure layer can be smaller. The plurality of transistors in the second inverter are arranged in the first direction in sequence, and the plurality of transistors are arranged regularly, so that the area occupied by the second inverter in the second circuit structure layer can be smaller. The smaller area occupied by the first inverter and the second inverter makes the area of the orthographic projection of the memory cell on the reference surface smaller.

[0014] The orthographic projection of the plurality of transistors of the first inverter on the reference surface overlaps with the orthographic projection of the plurality of transistors of the second inverter on the reference surface. In this way, on the one hand, it is conducive to realizing the electrical connection between the first inverter and the second inverter through the plurality of interconnection structures, and simplifying the connection form between the first inverter and the second inverter. On the other hand, it can further reduce the area occupied by each memory cell and improve the area utilization of the memory.

[0015] In some embodiments, the transistor includes a first electrode, a gate electrode and a second electrode arranged in a second direction in sequence, the second direction being parallel to the reference surface and perpendicular to the first direction. In the orthographic projection onto the reference surface, the gate electrode of the transistor of the first inverter overlaps with the first electrode of the transistor of the second inverter, and the second electrode of the transistor of the first inverter overlaps with the gate electrode of the transistor of the second inverter.

[0016] In this way, the overlapping area of the transistor of the first inverter and the transistor of the second inverter is larger, and the area occupied by the memory cell is smaller. Meanwhile, the gate electrode of the transistor of the first inverter overlaps with the first electrode of the transistor of the second inverter, and the second electrode of the transistor of the first inverter overlaps with the gate electrode of the transistor of the second inverter, which is also conducive to making the interconnection structure perpendicular to the first circuit structure layer and the second circuit structure layer, simplifying the plurality of interconnection structures, so that the orthographic projection of the interconnection structure on the reference surface is smaller, and the area occupied by the interconnection structure is smaller.

[0017] In some embodiments, in the orthographic projection onto the reference surface, the first electrode of the transistor of the first inverter and the second electrode of the transistor of the second inverter are staggered with each other. In this way, the plurality of transistors in the first inverter and the second inverter can be conveniently electrically connected with other wirings (such as power voltage lines, connection lines, etc.).

[0018] In some embodiments, the first inverter includes a first transistor, a second transistor, a third transistor and a fourth transistor; the third transistor, the first transistor, the fourth transistor and the second transistor are sequentially arranged along the first direction; the first transistor and the fourth transistor share a gate; the first circuit structure layer further includes a first connection line and a second connection line, a second electrode of the third transistor and a second electrode of the first transistor are electrically connected through the first connection line, and a second electrode of the fourth transistor and a second electrode of the second transistor are electrically connected through the second connection line.

[0019] In some embodiments, the second inverter includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; the fifth transistor, the seventh transistor, the sixth transistor and the eighth transistor are sequentially arranged along the first direction; the sixth transistor and the seventh transistor share a gate; the second circuit structure layer further includes a third connection line and a fourth connection line, a first electrode of the fifth transistor and a first electrode of the seventh transistor are electrically connected through the third connection line, and a first electrode of the sixth transistor and a first electrode of the eighth transistor are electrically connected through the fourth connection line.

[0020] In some embodiments, the plurality of interconnection structures includes a first interconnection structure, a second interconnection structure, a third interconnection structure and a fourth interconnection structure; a gate of the third transistor and a first electrode of the seventh transistor are electrically connected through the first interconnection structure; a gate of the seventh transistor and the first connection line are electrically connected through the second interconnection structure; a gate of the first transistor and the fourth connection line are electrically connected through the third interconnection structure; a gate of the eighth transistor and the second connection line are electrically connected through the fourth interconnection structure.

[0021] In some embodiments, the first circuit structure layer further includes a first gate-on transistor, and the first gate-on transistor is located on a side of the third transistor away from the first transistor along the first direction; the second circuit structure layer further includes a second gate-on transistor, and the second gate-on transistor is located on a side of the eighth transistor away from the sixth transistor along the first direction; the first gate-on transistor and the second gate-on transistor include a first electrode, a gate and a second electrode sequentially arranged along the second direction; the second electrode of the first gate-on transistor is electrically connected with the first connection line.

[0022] In some embodiments, the plurality of interconnection structures includes a fifth interconnection structure, and a first electrode of the second gate-on transistor and a gate of the second transistor are electrically connected through the fifth interconnection structure.

[0023] In some embodiments, the memory further comprises a fifth connection line and a sixth connection line, the fifth connection line and the sixth connection line are located on a side of the second circuit structure layer away from the first circuit structure layer; the fifth connection line is electrically connected with the gate of the fifth transistor and the gate of the eighth transistor; the sixth connection line is electrically connected with the first electrode of the seventh transistor and the first electrode of the second gating transistor; in the orthogonal projection to the reference plane, the fifth connection line overlaps with the gate of the fifth transistor and the gate of the eighth transistor, and the sixth connection line overlaps with the first electrode of the seventh transistor and the first electrode of the second gating transistor.

[0024] In some embodiments, the gate of the first gating transistor comprises a first part and a second part, the second part is away from the third transistor relative to the first part; in the orthogonal projection to the reference plane, the first part overlaps with the first electrode of the fifth transistor, and the second part does not overlap with the first electrode of the fifth transistor; the memory further comprises a word line located on a side of the second circuit structure layer away from the first circuit structure layer, the word line extends along the first direction; the word line is electrically connected with the gate of the first gating transistor and the gate of the second gating transistor, in the orthogonal projection to the reference plane, the word line overlaps with the second part and the gate of the second gating transistor.

[0025] In some embodiments, the memory further comprises a first bit line and a second bit line located on a side of the second circuit structure layer away from the first circuit structure layer and extending along the second direction; wherein the first bit line is electrically connected with the first electrode of the first gating transistor, and the second bit line is electrically connected with the second electrode of the second gating transistor; in the orthogonal projection to the reference plane, the first bit line overlaps with the first electrode of the first gating transistor, and the second bit line overlaps with the second electrode of the second gating transistor.

[0026] In some embodiments, the memory further comprises a first bit line, a plurality of first power voltage lines, a plurality of first ground lines, a second bit line, a plurality of second power voltage lines and a plurality of second ground lines. The first bit line, the plurality of first power voltage lines and the plurality of first ground lines are located on a side of the first circuit structure layer away from the second circuit structure layer and all extend along the second direction; the second bit line, the plurality of second power voltage lines and the plurality of second ground lines are located on a side of the second circuit structure layer away from the first circuit structure layer and all extend along the second direction.

[0027] The first bit line is electrically connected with the first electrode of the first gate transistor, the plurality of first power voltage lines are electrically connected with the first electrodes of the first transistor and the second transistor, and the plurality of first ground lines are electrically connected with the first electrodes of the third transistor and the fourth transistor; in the orthographic projection onto the reference plane, the first bit line overlaps with the first electrode of the first gate transistor, the plurality of first power voltage lines overlap with the first electrodes of the first transistor and the second transistor, and the plurality of first ground lines overlap with the first electrodes of the third transistor and the fourth transistor.

[0028] The second bit line is electrically connected with the second electrode of the second gate transistor, the plurality of second power voltage lines are electrically connected with the second electrodes of the fifth transistor and the sixth transistor, and the plurality of second ground lines are electrically connected with the second electrodes of the seventh transistor and the eighth transistor; in the orthographic projection onto the reference plane, the second bit line overlaps with the second electrode of the second gate transistor, the plurality of second power voltage lines overlap with the second electrodes of the fifth transistor and the sixth transistor, and the plurality of second ground lines overlap with the second electrodes of the seventh transistor and the eighth transistor.

[0029] In some embodiments, the second inverter includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, and the seventh transistor, the sixth transistor, the eighth transistor and the fifth transistor are arranged in sequence along the first direction; the fifth transistor shares a gate electrode with the eighth transistor, and the sixth transistor shares a gate electrode with the seventh transistor; the second circuit structure layer further includes a seventh connection line, and the first electrode of the sixth transistor is electrically connected with the first electrode of the eighth transistor through the seventh connection line.

[0030] In some embodiments, the plurality of interconnection structures include a first interconnection structure, a second interconnection structure, a third interconnection structure, a fourth interconnection structure and a fifth interconnection structure; the gate electrode of the third transistor is electrically connected with the first electrode of the seventh transistor through the first interconnection structure; the gate electrode of the seventh transistor is electrically connected with the first connection line through the second interconnection structure; the gate electrode of the first transistor is electrically connected with the seventh connection line through the third interconnection structure; the second connection line is electrically connected with the gate electrode of the eighth transistor through the fourth interconnection structure; and the gate electrode of the second transistor is electrically connected with the first electrode of the fifth transistor through the fifth interconnection structure.

[0031] In some embodiments, the first circuit structure layer further comprises a first gating transistor and a second gating transistor, along the first direction, the first gating transistor is located on a side of the third transistor away from the first transistor, and the second gating transistor is located on a side of the second transistor away from the fourth transistor. The second circuit structure layer further comprises a third gating transistor and a fourth gating transistor, along the first direction, the third gating transistor is located on a side of the seventh transistor away from the sixth transistor, and the fourth gating transistor is located on a side of the fifth transistor away from the eighth transistor.

[0032] The first gating transistor, the second gating transistor, the third gating transistor and the fourth gating transistor comprise a first electrode, a gate electrode and a second electrode arranged in sequence along the second direction; the second electrode of the first gating transistor is electrically connected to the first connection line, and the second electrode of the second gating transistor is electrically connected to the second connection line; the second circuit structure layer further comprises an eighth connection line, and the first electrode of the fifth transistor is electrically connected to the first electrode of the fourth gating transistor through the eighth connection line.

[0033] In some embodiments, the memory further comprises a ninth connection line and a tenth connection line, and the ninth connection line and the tenth connection line are located on a side of the second circuit structure layer away from the first circuit structure layer; the ninth connection line is electrically connected to the first electrode of the third gating transistor and the seventh connection line, and the tenth connection line is electrically connected to the first electrode of the seventh transistor and the eighth connection line.

[0034] In some embodiments, the memory further comprises two first connection parts and two second connection parts. One end of the ninth connection line is electrically connected to the first electrode of the third gating transistor through one of the first connection parts, and the other end is electrically connected to the seventh connection line through the other of the first connection parts. One end of the tenth connection line is electrically connected to the first electrode of the seventh transistor through one of the second connection parts, and the other end is electrically connected to the eighth connection line through the other of the second connection parts.

[0035] In some embodiments, the two first connection parts and the two second connection parts are arranged alternately along the first direction; the ninth connection line and the tenth connection line are in the same layer, the ninth connection line avoids the second connection part, and the tenth connection line avoids the first connection part; or, the ninth connection line is located on a side of the tenth connection line away from the second circuit structure layer, and the tenth connection line is in the shape of a broken line; in the orthogonal projection to the reference surface, the tenth connection line avoids the first connection part.

[0036] In some embodiments, the gate of the first pass transistor includes a first portion and a second portion, the second portion is farther away from the third transistor relative to the first portion; in the orthographic projection onto the reference plane, the first portion overlaps the first pole of the third pass transistor, and the second portion does not overlap the first pole of the third pass transistor. The gate of the second pass transistor includes a third portion and a fourth portion, the fourth portion is farther away from the second transistor relative to the third portion; in the orthographic projection onto the reference plane, the third portion overlaps the first pole of the fourth pass transistor, and the fourth portion does not overlap the first pole of the fourth pass transistor.

[0037] The memory further includes a word line located on a side of the second circuit structure layer away from the first circuit structure layer and extending along the first direction; the word line is electrically connected with the gates of the first pass transistor, the second pass transistor, the third pass transistor and the fourth pass transistor, and in the orthographic projection onto the reference plane, the word line overlaps the second portion, the fourth portion, the gate of the third pass transistor and the gate of the fourth pass transistor.

[0038] In some embodiments, the memory further includes a first bit line and a second bit line located on a side of the second circuit structure layer away from the first circuit structure layer and extending along the second direction. The first bit line is electrically connected with the first pole of the first pass transistor and the second pole of the third pass transistor, and the second bit line is electrically connected with the first pole of the second pass transistor and the second pole of the fourth pass transistor; in the orthographic projection onto the reference plane, the first bit line overlaps the first pole of the first pass transistor and the second pole of the third pass transistor, and the second bit line overlaps the first pole of the second pass transistor and the second pole of the fourth pass transistor.

[0039] In some embodiments, the memory further includes a first bit line, a second bit line, a plurality of first power supply voltage lines, a plurality of first ground lines, a third bit line, a fourth bit line, a plurality of second power supply voltage lines and a plurality of second ground lines.

[0040] The first bit line, the second bit line, the plurality of first power supply voltage lines and the plurality of first ground lines are located on a side of the first circuit structure layer away from the second circuit structure layer and all extend along the second direction. The third bit line, the fourth bit line, the plurality of second power supply voltage lines and the plurality of second ground lines are located on a side of the second circuit structure layer away from the first circuit structure layer and all extend along the second direction.

[0041] The first bit line is electrically connected with the first electrode of the first gating transistor, the second bit line is electrically connected with the first electrode of the second gating transistor, the plurality of first power supply voltage lines are electrically connected with the first electrode of the first transistor and the first electrode of the second transistor, and the plurality of first ground lines are electrically connected with the first electrode of the third transistor and the first electrode of the fourth transistor; in the orthographic projection onto the reference plane, the first bit line overlaps the first electrode of the first gating transistor, the second bit line overlaps the first electrode of the second gating transistor, the plurality of first power supply voltage lines overlap the first electrode of the first transistor and the first electrode of the second transistor, and the plurality of first ground lines overlap the first electrode of the third transistor and the first electrode of the fourth transistor.

[0042] The third bit line is electrically connected with the second electrode of the third gating transistor, the fourth bit line is electrically connected with the second electrode of the fourth gating transistor, the plurality of second power supply voltage lines are electrically connected with the second electrode of the fifth transistor and the second electrode of the sixth transistor, and the plurality of second ground lines are electrically connected with the second electrode of the seventh transistor and the second electrode of the eighth transistor; and in the orthographic projection onto the reference plane, the third bit line overlaps the second electrode of the third gating transistor, the fourth bit line overlaps the second electrode of the fourth gating transistor, the plurality of second power supply voltage lines overlap the second electrode of the fifth transistor and the second electrode of the sixth transistor, and the plurality of second ground lines overlap the second electrode of the seventh transistor and the second electrode of the eighth transistor.

[0043] In a second aspect, an electronic device is provided, which includes a circuit board and a memory as in any of the embodiments of the first aspect, and the memory is electrically connected with the circuit board.

[0044] The technical effects brought by any of the designs in the second aspect can refer to the technical effects brought by the different designs in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the present application, the following will briefly introduce the drawings needed to be used in some embodiments of the present application. Obviously, the drawings described in the following description are only some drawings of the embodiments of the present application, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual time sequence, etc. of the products involved in the embodiments of the present application.

[0046] Figure 1 A circuit diagram of a memory provided by the embodiments of the present application;

[0047] Figure 2 A structural diagram of a memory provided for an embodiment of the present application;

[0048] Figure 3 Another structural diagram of a memory provided for an embodiment of the present application;

[0049] Figure 4 Another circuit diagram of a memory provided for an embodiment of the present application;

[0050] Figure 5 Still another structural diagram of a memory provided for an embodiment of the present application;

[0051] Figure 6 A top view of a first circuit structural layer provided for an embodiment of the present application;

[0052] Figure 7 A top view of a second circuit structural layer provided for an embodiment of the present application;

[0053] Figure 8 A perspective structural diagram of a memory cell provided for an embodiment of the present application;

[0054] Figure 9 A top view of a memory cell provided for an embodiment of the present application;

[0055] Figure 10 Still another structural diagram of a memory provided for an embodiment of the present application;

[0056] Figure 11 Still another structural diagram of a memory provided for an embodiment of the present application;

[0057] Figure 12 A perspective structural diagram of a memory provided for an embodiment of the present application;

[0058] Figure 13 Still another structural diagram of a memory provided for an embodiment of the present application;

[0059] Figure 14 Another circuit diagram of a memory provided for an embodiment of the present application;

[0060] Figure 15 Still another structural diagram of a memory provided for an embodiment of the present application;

[0061] Figure 16 Another top view of a first circuit structural layer provided for an embodiment of the present application;

[0062] Figure 17 Another top view of a second circuit structural layer provided for an embodiment of the present application;

[0063] Figure 18Another top view of a storage unit provided by an embodiment of the present application;

[0064] Figure 19 Another top view of a storage unit provided by an embodiment of the present application;

[0065] Figure 20 Another top view of a storage unit provided by an embodiment of the present application;

[0066] Figure 21 Another top view of a storage unit provided by an embodiment of the present application;

[0067] Figure 22 Another top view of a storage unit provided by an embodiment of the present application; DETAILED DESCRIPTION

[0068] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the description of the present application, unless otherwise specified, " / " represents an "or" relationship between the objects before and after the " / ". For example, A / B can represent A or B. In the present application, "and / or" is only used to describe the relationship between the objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone, where A and B can be singular or plural.

[0069] In the description of the present application, unless otherwise specified, "multiple" means two or more. "At least one of the following" or similar expressions means any combination of the items, including any combination of single item or multiple items. For example, at least one of a, b, or c can mean a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

[0070] In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, "first", "second", etc. are used to distinguish the same items or similar items with basically the same function and effect. Those skilled in the art can understand that "first", "second", etc. do not limit the quantity and execution order, and "first", "second", etc. do not necessarily mean different.

[0071] In the embodiments of the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design presented as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of "exemplary" or "for example" is intended to present concepts in a concrete manner, which is easy to understand.

[0072] Figure 1 This is a circuit diagram of an SRAM. An SRAM may include multiple memory cells, a first bit line BL, a second bit line BL', a word line WL, and a power supply voltage line V. DD And ground line GND. The first bit line BL and the second bit line BL' are used to write data to or read data stored in multiple memory cells.

[0073] like Figure 1 As shown, the memory cell includes six transistors Q1 to Q6. Transistors Q1 to Q6 are all metal-oxide-semiconductor field-effect transistors. However, transistors Q1 to Q6 have different polarities; that is, transistors Q1, Q2, Q5, and Q6 are N-type transistors, while transistors Q3 and Q4 are P-type transistors.

[0074] Transistors Q1 to Q4 form an SR latch (set-reset-latch) to store a 1-bit binary code. Transistors Q5 and Q6 are selectors used to control the connection between the SR latch and the first bit line BL and the second bit line BL'. Transistors Q5 and Q6 are simultaneously turned on or off under the control of the same word line WL.

[0075] Transistors Q1 through Q6 each include a first terminal, a second terminal, and a gate. The first terminal is one of the source and the drain, and the second terminal is the other of the source and the drain. That is, when the first terminal is the source, the second terminal is the drain, or vice versa.

[0076] The first terminal of transistor Q1 is electrically connected to ground (GND), the second terminal of transistor Q1 is electrically connected to the first terminal of transistor Q3, the gate of transistor Q1 is electrically connected to the gate of transistor Q3, and the second terminal of transistor Q3 is electrically connected to the power supply voltage line V. DD Electrically connected, transistors Q1 and Q3 form a first inverter 110. The first inverter 110 has an input port IN and an output port OUT, the input port IN corresponding to the gate of transistor Q1 (or, the gate of transistor Q3), and the output port OUT corresponding to the second terminal of transistor Q1 (or, the first terminal of transistor Q3).

[0077] The first terminal of transistor Q2 is electrically connected to ground (GND), the second terminal of transistor Q2 is electrically connected to the first terminal of transistor Q4, the gate of transistor Q2 is electrically connected to the gate of transistor Q4, and the second terminal of transistor Q4 is electrically connected to the power supply voltage line V. DDThe transistor Q2 and the transistor Q4 form a second inverter 120. The second inverter 120 has an input port IN' corresponding to the gate of the transistor Q2 (or the gate of the transistor Q4) and an output port OUT' corresponding to the second electrode of the transistor Q2 (or the first electrode of the transistor Q4).

[0078] The first electrode of the transistor Q5 is connected to the first bit line BL, the second electrode of the transistor Q5 is connected to the output port OUT of the first inverter 110 and the input port IN' of the second inverter 120, and the gate of the transistor Q5 is connected to the word line WL.

[0079] The first electrode of the transistor Q6 is connected to the second bit line BL', the second electrode of the transistor Q6 is connected to the output port OUT' of the second inverter 120 and the input port IN of the first inverter 110, and the gate of the transistor Q6 is connected to the word line WL.

[0080] The working process of the storage unit will be described below. Figure 1 The working process of the storage unit will be described below.

[0081] In the write phase, the word line WL receives a high-level signal, and the transistors Q5 and Q6 are turned on. If a high-level signal is written, the first bit line BL receives a high-level signal, and the second bit line BL' receives a low-level signal. If the output port OUT is high and the output port OUT' is low, the original signals of the output port OUT and the output port OUT' are the same as those of the first bit line BL and the second bit line BL', and the signals of the output port OUT and the output port OUT' remain unchanged at this time. If the output port OUT is low and the output port OUT' is high, the signal of the output port OUT is flipped to high, and the signal of the output port OUT' is flipped to low. Then, the word line WL receives a low-level signal, and the transistors Q5 and Q6 are turned off. The levels of the output port OUT and the output port OUT' that have been written with signals are kept by the forward feedback of the latch, and the write operation is completed. When a low-level signal is written, the write process is the same as the high-level write process described above, and will not be described here.

[0082] After the write phase, the storage unit is in a static holding state. At this time, only one transistor in each of the first inverter and the second inverter is in the on state, and the other transistor is in the off state. For example, when the storage unit writes a high-level signal (i.e., the output port OUT is high and the output port OUT' is low), the transistor Q3 in the first inverter 110 is turned on, the transistor Q1 is turned off, the transistor Q2 in the second inverter 120 is turned on, and the transistor Q4 is turned off.

[0083] In the reading stage, the word line WL receives a low level signal, and the transistor Q5 and the transistor Q6 are turned off. The first bit line BL and the second bit line BL' are pre-charged to the same voltage (for example, high level), and then the word line WL receives a high level signal, and the transistor Q5 and the transistor Q6 are both turned on. When the SR latch stores a high level (the output port OUT is high level, and the output port OUT' is low level), the first bit line BL is connected with the output port OUT, and the output port OUT level remains unchanged, and the second bit line BL' is connected with the output port OUT' with low level through the turned-on transistor Q6. Since the second bit line is charged to high level, the second bit line BL' is discharged and the voltage is reduced, and within a certain time, the voltage of the second bit line BL' is reduced, and since the potential of the first bit line BL almost does not change, a voltage difference is generated between the first bit line BL and the second bit line BL'. The voltage difference increases with time, and the reading operation is completed by reading the voltage difference.

[0084] Based on Figure 1 The circuit diagram shown in the related art provides a memory 100, as shown in the figure, which includes a substrate 101, a first conductive layer 102, a second conductive layer 103 and a third conductive layer 104 which are sequentially away from the substrate 101. Figure 2

[0085] It can be understood that in addition to the above-mentioned multiple conductive layers, the memory 100 also includes multiple dielectric layers (not shown) between adjacent two conductive layers to insulate the adjacent two conductive layers.

[0086] Referring to Figure 2 , the memory 100 includes multiple transistors, a power supply voltage line V DD , a ground line GND, a word line WL, a first bit line BL and a second bit line BL'. The transistors Q1-Q6 constitute a memory cell, wherein the channel, the first electrode and the second electrode of the transistors Q1-Q6 are located in the substrate 101. The gate of the transistors Q1-Q4 is located in the first conductive layer 102. The transistors Q1 and Q3 share a gate, the transistors Q2 and Q4 share a gate, and the part of the word line WL overlapping with the channel of the transistors Q5 and Q6 respectively serves as the gate of the transistors Q5 and Q6.

[0087] The power supply voltage line V DD and the ground line GND are located in the second conductive layer 103, and the ground line GND passes through the via hole H1 to connect the first electrode of the transistor Q1 and the first electrode of the transistor Q2. The power supply voltage line V DD passes through the via hole H1 to connect the second electrode of the transistor Q3 and the second electrode of the transistor Q4. The via hole H1 can be located in the dielectric layer (not shown) between the substrate 101 and the second conductive layer 103. ​

[0088] The second conductive layer 103 also includes a first conductive pattern N1 and a second conductive pattern N2. The first conductive pattern N1 passes through a plurality of vias H1 and is electrically connected to the second terminal of transistor Q1, the first terminal of transistor Q3, and the gates of transistor Q2 and transistor Q4, respectively. The second conductive pattern N2 passes through a plurality of vias H1 and is electrically connected to the second terminal of transistor Q2, the first terminal of transistor Q4, and the gates of transistor Q1 and transistor Q3, respectively.

[0089] The first bit line BL and the second bit line BL' are located in the third conductive layer 104, and pass through vias H2 and H1 respectively to connect the first terminals of transistor Q5 and transistor Q6. Via H2 may be located in the dielectric layer (not shown) between the second conductive layer 103 and the third conductive layer 104.

[0090] The memory 100 includes an N-well region 105 and a P-well region 106, wherein transistors Q1, Q2, Q5 and Q6 are located in the N-well region 105, and transistors Q3 and Q4 are located in the P-well region 106.

[0091] like Figure 2 As shown, the multiple transistors in memory 100 occupy a large area, and the traces in memory 100 (e.g., power supply voltage lines V) DD The area occupied by the ground wire GND, gate wire WL, and conductive patterns (such as the first conductive pattern N1 and the second conductive pattern N2) is also relatively large. Moreover, since multiple conductive patterns with corners (i.e., the first conductive pattern N1 and the second conductive pattern N2) are formed in the second conductive layer 103, it is not easy to further miniaturize the second conductive layer 203 during fabrication, resulting in poor repeatability of the second conductive layer 103.

[0092] based on Figure 1 The circuit diagram shown also includes another type of memory 200, such as... Figure 3 As shown, the memory 200 includes a substrate 201, and a first conductive layer 202 and a second conductive layer 203 that are sequentially located away from the substrate 201.

[0093] It is understood that, in addition to the multiple conductive layers mentioned above, the memory 200 also includes multiple dielectric layers (not shown), which are located between two adjacent conductive layers to insulate the two adjacent conductive layers.

[0094] The memory 200 includes multiple memory cells, a power supply voltage line VDD, a ground line GND, a word line WL, a first bit line BL, and a second bit line BL'. Figure 3 The example uses only one storage unit.

[0095] Each memory cell includes transistors Q1-Q6, wherein the channels, the first electrodes and the second electrodes of the transistors Q1-Q6 are located in the substrate 201. The gates of the transistors Q1-Q6 are all located in the first conductive layer 202. Moreover, the transistor Q1 and the transistor Q3 share a gate, and the transistor Q2 and the transistor Q4 share a gate. The power voltage line V DD , the ground line GND, the word line WL, the first bit line BL and the second bit line BL' are all located in the second conductive layer 203. The word line WL is electrically connected with the gates of the transistor Q5 and the transistor Q6 through the via H3 respectively, the first bit line BL is electrically connected with the first electrode of the transistor Q5 through the via H3, and the second bit line BL' is electrically connected with the first electrode of the transistor Q6 through the via H3.

[0096] For example, the via H3 can refer to the via in the dielectric layer between the substrate 201 and the first conductive layer 202, or the via in the dielectric layer between the first conductive layer 202 and the second conductive layer 203, or the via in the dielectric layer between the substrate 201 and the first conductive layer 202, and the dielectric layer between the first conductive layer 202 and the second conductive layer 203.

[0097] The memory 200 includes N-well regions 204 and P-well regions 205, the transistors Q1, Q2, Q5 and Q6 are located in the N-well regions 204, and the transistors Q3 and Q4 are located in the P-well regions 205.

[0098] Referring to Figure 3 , although there is no conductive pattern with a corner in the above-mentioned memory 200, due to the different polarities of the plurality of transistors, it is still necessary to form a plurality of N-well regions 204 and P-well regions 205 in the memory 200. Thus, it is necessary to isolate the N-well regions 204 and the P-well regions 205 in the memory 200 by a certain space, so that the memory 200 occupies a larger area.

[0099] In addition to the larger area, due to the different polarities of the transistors in the above-mentioned two memories, it is necessary to form the above-mentioned plurality of transistors on a bipolar channel material such as silicon-based material, and the bipolar channel material is not easy to be integrated by 3D through the back-end-of-line process or the stack process, thus resulting in that the memory as a whole occupies a larger area.

[0100] Therefore, based on this, the embodiments of the present application provide a memory 300, which includes a plurality of memory cells 310, a first bit line BL, a second bit line BL', a power voltage line V DD and a ground line GND. Figure 4 The circuit diagram of the memory 300 provided by the embodiments of the present application is shown in FIG. 3. In the figure, Figure 4 one of the plurality of memory cells 310 of the memory 300 is shown in FIG. 4.

[0101] The storage unit 310 includes a first inverter 301 and a second inverter 302. The first inverter 301 includes a first input port IN1 and a second input port IN2, and a first output port OUT1 and a second output port OUT2. The second inverter 302 includes a third input port IN3 and a fourth input port IN4, and a third output port OUT3 and a fourth output port OUT4.

[0102] Referring to Figure 4 , the first input port IN1 of the first inverter 301 is electrically connected to the fourth output port OUT4 of the second inverter 302, and the second input port IN2 of the first inverter 301 is electrically connected to the third output port OUT3 of the second inverter 302. The third input port IN3 of the second inverter 302 is electrically connected to the second output port OUT2 of the first inverter 301, and the fourth input port IN4 of the second inverter 302 is electrically connected to the first output port OUT1 of the first inverter 301. In this way, the first inverter 301 and the second inverter 302 are cascaded to form a latch.

[0103] In Figure 4 the circuit diagram provided, the black dashed line represents the signal line conjugate to the black solid line. That is, the signals at the first input port IN1 and the second input port IN2 are conjugate inverses, and the signals at the first output port OUT1 and the second output port OUT2 are conjugate inverses. The signals at the third input port IN3 and the fourth input port IN4 are conjugate inverses, and the signals at the third output port OUT3 and the fourth output port OUT4 are also conjugate inverses.

[0104] It can be understood that at the intersection of the black dashed line and the black solid line, the signals between the two are not connected.

[0105] In some examples, the first inverter 301 can include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 each include a first pole, a gate, and a second pole. Among them, the first pole is one of the source and the drain, and the second pole is the other of the source and the drain. The first poles of different transistors can be the same source or the same drain, or one source and the other drain.

[0106] For example, the gate of the first transistor T1 is electrically connected to the gate of the fourth transistor T4, the first pole of the first transistor T1 is electrically connected to the power supply voltage line V DDThe second electrode of the first transistor T1 is electrically connected with the second electrode of the third transistor T3, and the first electrode of the third transistor T3 is electrically connected with the ground line GND. The first transistor T1 and the third transistor T3 form a passageway.

[0107] The gate electrode of the second transistor T2 is electrically connected with the gate electrode of the third transistor T3, and the first electrode of the second transistor T2 is electrically connected with the power voltage line V DD The second electrode of the second transistor T2 is electrically connected with the second electrode of the fourth transistor T4, and the first electrode of the fourth transistor T4 is electrically connected with the ground line GND. The second transistor T2 and the fourth transistor T4 form another passageway.

[0108] In some examples, the second inverter 302 can include a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8. The fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 each include a first electrode, a gate electrode and a second electrode, wherein the first electrode is one of a source electrode and a drain electrode, and the second electrode is the other of the source electrode and the drain electrode. The first electrodes of different transistors can be both source electrodes or both drain electrodes, or one source electrode and the other drain electrode.

[0109] For example, the gate electrode of the fifth transistor T5 is electrically connected with the gate electrode of the eighth transistor T8, the first electrode of the fifth transistor T5 is electrically connected with the first electrode of the seventh transistor T7, and the second electrode of the fifth transistor T5 is electrically connected with the power voltage line V DD The second electrode of the fifth transistor T5 is electrically connected with the second electrode of the seventh transistor T7. The fifth transistor T5 and the seventh transistor T7 form another passageway.

[0110] The gate electrode of the sixth transistor T6 is electrically connected with the gate electrode of the seventh transistor T7, the first electrode of the sixth transistor T6 is electrically connected with the first electrode of the eighth transistor T8, and the second electrode of the sixth transistor T6 is electrically connected with the power voltage line V DD The second electrode of the eighth transistor T8 is electrically connected with the ground line GND. The sixth transistor T6 and the eighth transistor T8 form another passageway.

[0111] Continuing to refer to Figure 4 The storage unit 310 further includes a first gate transistor T9 and a second gate transistor T10. The first gate transistor T9 and the second gate transistor T10 are used to control the connection between the above-mentioned latch and the first bit line BL and the second bit line BL'. The first gate transistor T9 and the second gate transistor T10 are controlled by the same word line WL and are turned on or turned off at the same time. The first gate transistor T9 and the second gate transistor T10 each include a first electrode, a gate electrode and a second electrode, wherein the first electrode is one of a source electrode and a drain electrode, and the second electrode is the other of the source electrode and the drain electrode.

[0112] For example, the first electrode of the first gating transistor T9 is electrically connected with the first bit line BL. The second electrode of the first gating transistor T9 is electrically connected with the first output port OUT1 of the first inverter 301 and the fourth input port IN4 of the second inverter 302. That is, the second electrode of the first gating transistor T9 is electrically connected with the gate of the sixth transistor T6, the gate of the seventh transistor T7, the second electrode of the first transistor T1, and the second electrode of the third transistor T3.

[0113] For example, the second electrode of the second gating transistor T10 is electrically connected with the second bit line BL'. The first electrode of the second gating transistor T10 is electrically connected with the second input port IN2 of the first inverter 301 and the third output port OUT3 of the second inverter 302. That is, the first electrode of the second gating transistor T10 is electrically connected with the gate of the third transistor T3, the gate of the second transistor T2, the first electrode of the fifth transistor T5, and the first electrode of the seventh transistor T7.

[0114] The polarities of the plurality of transistors of the plurality of storage units 310 are the same, Figure 4 In some examples, the plurality of transistors in the storage unit 310 are all N-type transistors. In other examples, the plurality of transistors in the storage unit 310 can all be P-type transistors.

[0115] The working process of the storage unit 310 will be described below with reference to the circuit diagram. Figure 4 The working process of the storage unit 310 will be described below with reference to the circuit diagram.

[0116] The working process of the storage unit 310 includes a writing process and a reading process. In the writing process, the word line WL receives a high-level signal, and the first gating transistor T9 and the second gating transistor T10 are turned on. When writing a high-level signal, the first bit line BL receives a high-level signal, and the second bit line BL' receives a low-level signal. If the voltage of the second electrode of the first gating transistor T9 (or the first output port OUT1 of the first inverter) is high, and the voltage of the first electrode of the second gating transistor T10 (or the third output port OUT3 of the second inverter) is low, then the voltage of the second electrode of the first gating transistor T9 and the voltage of the first electrode of the second gating transistor T10 remain unchanged. If the voltage of the second electrode of the first gating transistor T9 is low, and the voltage of the first electrode of the second gating transistor T10 is high, then the voltage of the second electrode of the first gating transistor T9 and the voltage of the first electrode of the second gating transistor T10 are flipped. Then, the word line WL receives a low-level signal, and the first gating transistor T9 and the second gating transistor T10 are turned off. The writing process of a low-level signal is similar to the writing process of a high-level signal, which will not be described here.

[0117] In the reading process, the word line WL receives a low level signal, and the first pass transistor T9 and the second pass transistor T10 are turned off. After the first bit line BL and the second bit line BL' are pre-charged to the same voltage (for example, pre-charged to a high level), the word line WL receives a high level signal again, and the first pass transistor T9 and the second pass transistor T10 are turned on. When the latch stores a high level (the level of the second electrode of the first pass transistor T9 is high, and the voltage of the first electrode of the second pass transistor T10 is low), the levels on the first electrode and the second electrode of the first pass transistor T9 are the same, the voltage of the first electrode and the second electrode of the second pass transistor T10 is different, the second bit line BL' is discharged, the voltage is lowered, and a voltage difference is generated between the first bit line BL and the second bit line BL', and the reading operation is completed by reading the voltage difference.

[0118] After the writing operation is completed, the storage unit 310 enters a signal static holding stage. At this time, in any parallel path of the latch, only one transistor is in the on state, and the other is in the off state. For example, when all the transistors in the latch are N-type tubes, after writing a high level, the first transistor T1, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are in the on state, and the second transistor T2, the third transistor T3, the fifth transistor T5, and the eighth transistor T8 are in the off state.

[0119] It can be understood that when all the transistors in the storage unit 310 are P-type tubes, the first pass transistor T9 and the second pass transistor T10 are turned on when the word line WL transmits a low level signal, and turned off when transmitting a high level signal. In the same working stage, the signal of the first output port OUT1 of the first inverter composed of P-type tubes is opposite to the signal of the first output port OUT1 of the first inverter composed of N-type tubes. The signal of the second output port OUT2 of the first inverter composed of P-type tubes is opposite to the signal of the second output port OUT2 of the first inverter composed of N-type tubes. The signal of the third output port OUT3 of the second inverter composed of P-type tubes is opposite to the signal of the third output port OUT3 of the second inverter composed of N-type tubes. The signal of the fourth output port OUT4 of the second inverter composed of P-type tubes is opposite to the signal of the fourth output port OUT4 of the second inverter composed of N-type tubes.

[0120] Figure 5A structural diagram of the memory 300 provided in the embodiments of the present application is shown in FIG. 1. The memory 300 includes a first circuit structure layer 10, a second circuit structure layer 20, and a plurality of interconnection structures 30. The first circuit structure layer 10 includes a first inverter 301. The second circuit structure layer 20 is stacked with the first circuit structure layer 10, and includes a second inverter 302. The interconnection structures 30 are located between the first circuit structure layer 10 and the second circuit structure layer 20.

[0121] The first inverter 301 and the second inverter 302 each include a plurality of transistors T, and the plurality of transistors T of the first inverter 301 and the plurality of transistors T of the second inverter 302 have the same polarity. The plurality of transistors T of the first inverter 301 and the plurality of transistors T of the second inverter 302 are arranged in a first direction X parallel to a reference surface S in sequence. The reference surface S is a plane on which a lower surface of the first circuit structure layer 10 is located. The plurality of transistors T of the first inverter 301 and the plurality of transistors T of the second inverter 302 overlap in orthographic projection on the reference surface S, and the first inverter 301 and the second inverter 302 are electrically connected by the plurality of interconnection structures 30.

[0122] In some examples, the plurality of transistors T in the first inverter 301 and the second inverter 302 can each be an N-type transistor. In other examples, the plurality of transistors T in the first inverter 301 and the second inverter 302 can each be a P-type transistor.

[0123] In some examples, the plurality of transistors T in the first inverter 301 and the second inverter 302 can be single-gate transistors, double-gate transistors, fin field-effect transistors (FinFETs), or gate-all-around field-effect transistors (GAAFETs), etc. The structure of the plurality of transistors T in the first inverter 301 and the second inverter 302 is not limited in the embodiments of the present application, Figure 4 In the embodiments of the present application, the plurality of transistors T in the first inverter 301 and the second inverter 302 are taken as single-gate transistors for example.

[0124] In the memory 300 provided in the embodiments of the present application, the plurality of transistors T in the first inverter 301 and the second inverter 302 have the same polarity, so that the plurality of transistors T can be prepared by using a single-polarity channel material (for example, an oxide semiconductor material, an organic semiconductor material, etc.) in the process of preparing the memory 300. Therefore, the memory 300 can be prepared by using a back-end process or a stacking process, so as to simplify the process, realize 3D integration of the memory 300 and a logic device for controlling the memory 300, reduce the area occupied by the memory 300, and improve the area utilization of the memory.

[0125] The polarities of the plurality of transistors T are the same, and the plurality of transistors can also be arranged compactly. The storage unit does not need to use extra space to separate the transistors of different polarities, so that the occupied area of the storage unit 310 can be further reduced, and the occupied area of the memory 300 is further reduced, and the area utilization of the memory is improved.

[0126] Compared with the case where the entire storage unit is arranged in the same circuit structure layer, the first inverter 301 of the storage unit 310 is arranged in the first circuit structure layer 10, and the second inverter 302 is arranged in the second circuit structure layer 20 in the embodiment of the application. The 3D stacking of the storage unit is realized, so that the area utilization of the memory can be further improved.

[0127] Meanwhile, in the memory 300 provided in the embodiment of the application, the plurality of transistors T in the first inverter 301 are arranged in the first direction X in sequence, and the plurality of transistors T are arranged regularly, so that the occupied area of the first inverter 301 in the first circuit structure layer 10 can be smaller. The plurality of transistors T in the second inverter 302 are arranged in the first direction X in sequence, and the plurality of transistors T are arranged regularly, so that the occupied area of the second inverter 302 in the second circuit structure layer 20 can be smaller. The occupied areas of the first inverter 301 and the second inverter 302 are smaller, so that the area of the orthogonal projection of the storage unit 310 on the reference surface S is also smaller.

[0128] The orthogonal projection of the plurality of transistors T of the first inverter 301 on the reference surface S overlaps the orthogonal projection of the plurality of transistors T of the second inverter 302 on the reference surface S. In this way, on the one hand, it is beneficial to realize the electrical connection of the first inverter 301 and the second inverter 302 through the plurality of interconnection structures 30, and to simplify the connection form between the first inverter 301 and the second inverter 302. On the other hand, the occupied area of each storage unit 310 can be further reduced, and the area utilization of the memory 300 is improved.

[0129] As shown in FIG. 1, Figure 5 In some embodiments, the transistor T includes a first pole 01, a gate 02 and a second pole 03 arranged in sequence along a second direction Y, and the second direction Y is parallel to the reference surface S and perpendicular to the first direction X. In the orthogonal projection to the reference surface S, the gate 02 of the transistor T of the first inverter 301 overlaps the first pole 01 of the transistor T of the second inverter 302, and the second pole 03 of the transistor T of the first inverter 301 overlaps the gate 02 of the transistor T of the second inverter 302.

[0130] In this way, the overlapping area of ​​the transistors in the first inverter 301 and the second inverter 302 is relatively large, and the area occupied by the memory cell 310 is relatively small. At the same time, the gate 02 of the transistor T of the first inverter 301 overlaps with the first electrode 01 of the transistor T of the second inverter 302, and the second electrode 03 of the transistor T of the first inverter 301 overlaps with the gate 02 of the transistor T of the second inverter 302. This also helps to make the interconnect structure 30 perpendicular to the first circuit structure layer 10 and the second circuit structure layer 20, simplifying multiple interconnect structures. As a result, the orthographic projection of the interconnect structure 30 on the reference plane S is relatively small, and the area occupied by the interconnect structure 30 is relatively small.

[0131] like Figure 5 As shown, in some embodiments, the first circuit structure layer 10 may include a first active layer 11, a first gate layer 12, a first source / drain electrode layer 13, and a multilayer dielectric layer stacked together.

[0132] The multilayer dielectric layer may include a dielectric layer located on the side of the first active layer 11 away from the first gate layer 12, a dielectric layer that insulates the first active layer 11 from the first gate layer 12, a dielectric layer that insulates the first source / drain electrode layer 13 from the first gate layer 12, etc.

[0133] In this first inverter 301, the gates 02 of the plurality of transistors T can be located in the first gate layer 12, and the first electrodes 01 and 03 of the plurality of transistors T can be located in the first source-drain electrode layer 13. The plurality of transistors T in the first inverter 301 may also include a channel 04, which can be formed in the first active layer 11. Within the same transistor T, the orthogonal projection of the channel 04 onto the reference plane S overlaps with the orthogonal projection of the gate 02 onto the reference plane S. The first electrodes 01 and 03 of the transistor T can penetrate the dielectric layer and make electrical contact with the channel 04.

[0134] See Figure 5 In some embodiments, the second circuit structure layer 20 may include a second active layer 21, a second gate layer 22, a second source / drain electrode layer 23, and a multilayer dielectric layer, which are stacked together.

[0135] The multilayer dielectric layer is located on the side of the second active layer 21 away from the second gate layer 22, and is a dielectric layer (not shown) that insulates the second active layer 21 from the second gate layer 22, and a dielectric layer (not shown) that insulates the second source / drain electrode layer 23 from the second gate layer 22.

[0136] In this second inverter 302, the gates 02 of the plurality of transistors T can be located in the second gate layer 22, and the first electrodes 01 and 03 of the plurality of transistors T can be located in the second source-drain electrode layer 23. The plurality of transistors T in the second inverter 302 may also include a channel 04, which can be formed in the second active layer 21. Within the same transistor T, the orthogonal projection of the channel 04 onto the reference plane S overlaps with the orthogonal projection of the gate 02 onto the reference plane S. The first electrodes 01 and 03 of the transistor T can penetrate the dielectric layer and contact the channel 04.

[0137] Continue reading Figure 5 In some embodiments, a dielectric layer may also be present between the first circuit structure layer 10 and the second circuit structure layer 20, and multiple interconnect structures 30 may pass through the dielectric layer (not shown) to connect the first inverter 301 in the first circuit structure layer 10 and the second inverter 302 in the second circuit structure layer 20.

[0138] Understandable, Figure 5 This is merely one possible structure of the memory 300 in this embodiment of the application, and the structure of the plurality of transistors T in the memory 300 is not limited to this.

[0139] Continue reading Figure 5 In some embodiments, in the orthographic projection onto the reference plane S, the first terminal O1 of the transistor T of the first inverter 301 and the second terminal O3 of the transistor T of the second inverter 302 are offset from each other. This arrangement facilitates the electrical connection of the multiple transistors T in the first inverter 301 and the second inverter 302 to other traces (e.g., power supply voltage line VDD, wiring GND, etc.).

[0140] like Figure 6 As shown, the first inverter 301 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. Along the first direction X, the third transistor T3, the first transistor T1, the fourth transistor T4, and the second transistor T2 are arranged sequentially. The first transistor T1 and the fourth transistor T4 share a common gate. The first circuit structure layer 10 also includes a first connection line L1 and a second connection line L2. The second terminal O3 of the third transistor T3 and the second terminal O3 of the first transistor T1 are electrically connected through the first connection line L1, and the second terminal O3 of the fourth transistor T4 and the second terminal O3 of the second transistor T2 are electrically connected through the second connection line L2.

[0141] like Figure 6 As shown, the first connecting line L1 and the second connecting line L2 can extend along the first direction X. In this way, the shapes of the first connecting line L1 and the second connecting line L2 are simple, easy to manufacture, and the area occupied by the first connecting line L1 and the second connecting line L2 can be small.

[0142] As shown in Figure 7 , the second inverter 302 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8. In the first direction X, the fifth transistor T5, the seventh transistor T7, the sixth transistor T6 and the eighth transistor T8 are arranged in sequence. The sixth transistor T6 shares a gate with the seventh transistor T7.

[0143] The second circuit structure layer 20 further includes a third connection line L3 and a fourth connection line L4. The first pole 01 of the fifth transistor T5 is electrically connected to the first pole 01 of the seventh transistor T7 through the third connection line L3. The first pole 01 of the sixth transistor T6 is electrically connected to the first pole 01 of the eighth transistor T8 through the fourth connection line L4.

[0144] In some examples, as shown in Figure 7 , the third connection line L3 and the fourth connection line L4 can extend along the first direction X. In this way, the third connection line L3 and the fourth connection line L4 have a simple shape, are easy to manufacture, and can have a smaller occupied area.

[0145] Based on the arrangement of the transistors of the first inverter 301 and the second inverter 302 described above, in some embodiments, referring to Figure 5 , the plurality of interconnection structures 30 includes a first interconnection structure 31, a second interconnection structure 32, a third interconnection structure 33 and a fourth interconnection structure 34.

[0146] The gate 02 of the third transistor T3 is electrically connected to the first pole 01 of the seventh transistor T7 through the first interconnection structure 31. The gate 02 of the seventh transistor T7 is electrically connected to the first connection line L1 through the second interconnection structure 32. The gate 02 of the first transistor T1 is electrically connected to the fourth connection line L4 through the third interconnection structure 33. The gate 02 of the eighth transistor T8 is electrically connected to the second connection line L2 through the fourth interconnection structure 34.

[0147] Figure 8 A perspective view of the storage unit 310 provided in the embodiments of the present application is shown. Referring to Figure 5 and Figure 8 , in the memory 300 provided in the embodiments of the present application, the first interconnection structure 31, the second interconnection structure 32, the third interconnection structure 33 and the fourth interconnection structure 34 can be perpendicular to the first circuit structure layer 10 and the second circuit structure layer 20, so that the structure of the plurality of interconnection structures is simple, so that the orthographic projection of the interconnection structure 30 on the reference surface S is small, and the occupied area of the interconnection structure 30 is small.

[0148] Continuing to refer to Figure 5In some embodiments, the first circuit structure layer 10 further comprises a first gate transistor T9, which is located on the side of the third transistor T3 away from the first transistor T1 along the first direction X. The second circuit structure layer 20 further comprises a second gate transistor T10, which is located on the side of the eighth transistor T8 away from the sixth transistor T6 along the first direction X.

[0149] The first gate transistor T9 and the second gate transistor T10 comprise a first electrode 01, a gate electrode 02 and a second electrode 03 arranged in sequence along the second direction Y. The second electrode 03 of the first gate transistor T9 is electrically connected with the first connection line L1.

[0150] In the case that the second circuit structure layer 20 further comprises the second gate transistor T10, as shown in Figure 5 , the plurality of interconnection structures 30 can further comprise a fifth interconnection structure 35, and the first electrode 01 of the second gate transistor T10 is electrically connected with the gate electrode 02 of the second transistor T2 through the fifth interconnection structure 35.

[0151] In some embodiments, as shown in Figure 5 and Figure 8 , the memory 300 further comprises a fifth connection line L5 and a sixth connection line L6. The fifth connection line L5 and the sixth connection line L6 are located on the side of the second circuit structure layer 20 away from the first circuit structure layer 10.

[0152] The fifth connection line L5 is electrically connected with the gate electrode 02 of the fifth transistor T5 and the gate electrode 02 of the eighth transistor T8. The sixth connection line L6 is electrically connected with the third connection line L3 and the first electrode 01 of the second gate transistor T10. In the orthogonal projection onto the reference surface S, the fifth connection line L5 overlaps with the gate electrode 02 of the fifth transistor T5 and the gate electrode 02 of the eighth transistor T8, and the sixth connection line L6 overlaps with the first electrode 01 of the seventh transistor T7 and the first electrode 01 of the second gate transistor T10. In this way, the occupied area of the memory cell 310 can be further reduced, and the integration and area utilization of the memory 300 can be improved.

[0153] In some examples, the fifth connection line L5 and the sixth connection line L6 can both extend along the first direction X. In this way, the shape of the fifth connection line L5 and the sixth connection line L6 is simple, easy to manufacture, and the occupied area of the fifth connection line L5 and the sixth connection line L6 can be smaller.

[0154] In some examples, the fifth connection line L5 and the sixth connection line L6 can be located on the same layer. At this time, the materials of the fifth connection line L5 and the sixth connection line L6 can be the same. In this way, the fifth connection line L5 and the sixth connection line L6 can be prepared at the same time, simplifying the preparation process of the memory cell 310 and reducing the preparation cost of the memory cell 310.

[0155] It can be understood that, in order to insulate the fifth connection line L5 and the sixth connection line L6 from the second circuit structure layer 20, a dielectric layer (not shown) can be formed between the fifth connection line L5 and the sixth connection line L6 and the second circuit structure layer 20.

[0156] As shown in Figure 8 , the memory 300 can include a plurality of conductive columns 14, and the plurality of conductive columns 14 can be perpendicular to the first circuit structure layer 10 and the second circuit structure layer 20. One end of the fifth connection line L5 can be electrically connected to the gate 02 of the fifth transistor T5 through one conductive column 14, and the other end of the fifth connection line L5 can be electrically connected to the gate 02 of the eighth transistor T8 through another conductive column 14. One end of the sixth connection line L6 can be electrically connected to the first pole 01 of the seventh transistor T7 through another conductive column 14, and the other end of the sixth connection line L6 can be electrically connected to the first pole 01 of the second selection transistor T10 through another conductive column 14.

[0157] Figure 9 The top view of the storage unit 310 provided by the embodiments of the present application is shown in Figure 6 and Figure 9 In some embodiments, the gate 02 of the first selection transistor T9 includes a first part 021 and a second part 022, and the second part 022 is away from the third transistor T3 relative to the first part 021. In the orthogonal projection to the reference surface S, the first part 021 overlaps the first pole 01 of the fifth transistor T5, and the second part 022 does not overlap the first pole 01 of the fifth transistor T5. In this way, the second part 022 is not blocked by the first pole 01 of the fifth transistor T5, so that the connection of the gate of the first selection transistor T9 and the word line WL can be easily realized.

[0158] In some embodiments, as shown in Figure 10 , the memory 300 further includes a word line WL, and the word line WL is located on the side of the second circuit structure layer 20 away from the first circuit structure layer 10, and the word line WL extends along the first direction X. The word line WL is electrically connected to the gate 02 of the first selection transistor T9 and the gate 02 of the second selection transistor T10, and in the orthogonal projection to the reference surface S, the word line WL overlaps the second part 022 and the gate 02 of the second selection transistor T10.

[0159] It can be understood that, in order to insulate the word line WL from the devices in the second circuit structure 20, a dielectric layer (not shown) can be provided between the word line WL and the second circuit structure layer 20.

[0160] In the embodiment of the present application, the word line WL extends along the first direction X, so that the word line WL has a simple shape, is easy to manufacture, and reduces the area occupied by the word line WL. Meanwhile, the word line WL overlaps the second part 022 and the gate 02 of the second gating transistor T10, and the word line WL can pass through the via in the dielectric layer to be electrically connected with the second part 022 and the gate 02 of the second gating transistor T10, so as to simplify the structure of the memory 300, reduce the area occupied by the memory 300, and improve the storage density and area utilization of the memory 300.

[0161] With reference to Figure 10 , the memory 300 can further include a first bit line BL and a second bit line BL', which are located on the side of the second circuit structure layer 20 away from the first circuit structure layer 10 and extend along the second direction Y.

[0162] The first bit line BL is electrically connected with the first pole 01 of the first gating transistor T9, and the second bit line BL' is electrically connected with the second pole 03 of the second gating transistor T10. In the orthogonal projection onto the reference surface S, the first bit line BL overlaps the first pole 01 of the first gating transistor T9, and the second bit line BL' overlaps the second pole 03 of the second gating transistor T10.

[0163] It can be understood that, in order to insulate the first bit line BL and the second bit line BL' from the devices in the second circuit structure layer 20, a dielectric layer (not shown) can be arranged between the first bit line BL and the second bit line BL' and the second circuit structure layer 20.

[0164] In some examples, the first bit line BL and the second bit line BL' can be located on the same layer. In this case, the materials of the first bit line BL and the second bit line BL' can be the same. In this way, the first bit line BL and the second bit line BL' can be manufactured at the same time, so as to simplify the manufacturing process of the memory 300 and reduce the manufacturing cost of the memory 300.

[0165] In the embodiment of the present application, in the orthogonal projection onto the reference surface S, the first bit line BL overlaps the first pole 01 of the first gating transistor T9, and the second bit line BL' overlaps the second pole 03 of the second gating transistor T10. In this way, the first bit line BL can pass through the via 15 in the dielectric layer to be electrically connected with the first pole 01 of the first gating transistor T9, and the second bit line BL' can pass through the via 15 in the dielectric layer to be electrically connected with the second pole 03 of the second gating transistor T10, so as to further reduce the area occupied by the memory 300, thereby improving the storage density of the memory 300.

[0166] In some embodiments, the first bit line BL and the second bit line BL' may be located on the side of the word line WL away from the second circuit structure layer 20. In other embodiments, the word line WL may be located on the side of the first bit line BL and the second bit line BL' away from the second circuit structure layer 20.

[0167] The memory 300 also includes multiple power supply voltage lines V DD And multiple grounding wires GND, in some embodiments, such as Figure 10 As shown, multiple power supply voltage lines V DD Multiple grounding wires GND can be located on the side of the second circuit structure layer 20 away from the first circuit structure layer 10 and extend along the second direction Y.

[0168] In the orthographic projection onto the reference plane S, the power supply voltage line V DD The ground wire GND overlaps with the first terminal 01 of the first transistor T1, the second terminal 03 of the fifth transistor T5, the second terminal 03 of the sixth transistor T6, and the first terminal 01 of the second transistor T2.

[0169] Thus, the power supply voltage line V DD The via 15 can be electrically connected to the first terminal 01 of the first transistor T1, the second terminal 03 of the fifth transistor T5, the second terminal 03 of the sixth transistor T6, and the first terminal 01 of the second transistor T2. The ground wire GND can be electrically connected to the first terminal 01 of the third transistor T3, the second terminal 03 of the seventh transistor T7, the first terminal 01 of the fourth transistor T4, and the second terminal 03 of the eighth transistor T8 through the via 15. The memory 300 can occupy a smaller area, thereby increasing the storage density of the memory 300.

[0170] It is understandable that, in the orthographic projection onto the reference plane S, the first bit line BL overlaps with the first terminal 01 of the first gating transistor T9, and the power supply voltage line V... DD The second terminal 03 of the first select transistor T9 overlaps with the second terminal 03 of the fifth transistor T5, while the gate 02 of the first select transistor T9 overlaps with the first terminal 01 of the fifth transistor T5, and the second terminal 03 of the first select transistor T9 overlaps with the gate 02 of the fifth transistor T5. This is to avoid the first bit line BL from intersecting with the power supply voltage line V. DD Short-circuited, the orthographic projection of the first line BL onto the reference plane S intersects with the power supply voltage line V. DD The orthographic projections of the second voltage line BL' onto the reference plane S are offset from each other. Similarly, the orthographic projection of the second voltage line BL' onto the reference plane S is offset from the projection of the power supply voltage line V. DD The orthographic projections onto the reference plane S should also be offset from each other.

[0171] In some embodiments, such asFigure 10 As shown, in the first direction X, the power voltage lines V DD and the ground lines GND can be arranged alternately.

[0172] In some other embodiments, as shown in Figure 11 and Figure 12 the memory 300 includes a plurality of power voltage lines V DD and a plurality of ground lines GND, the plurality of power voltage lines V DD may include a plurality of first power voltage lines V DD 1 and a plurality of second power voltage lines V DD 2, and the plurality of ground lines GND may include a plurality of first ground lines GND1 and a plurality of second ground lines GND2.

[0173] It can be understood that the voltages on the plurality of first power voltage lines V DD 1 and the plurality of second power voltage lines V DD 2 are the same, and the voltages on the plurality of first ground lines GND1 and the plurality of second ground lines GND2 are the same.

[0174] At this time, the first bit line BL, the plurality of first power voltage lines V DD 1 and the plurality of first ground lines GND1 can be located on the side of the first circuit structure layer 10 away from the second circuit structure layer 20, and all extend along the second direction Y. The second bit line BL', the plurality of second power voltage lines V DD 2 and the plurality of second ground lines GND2 are located on the side of the second circuit structure layer 20 away from the first circuit structure layer 10, and all extend along the second direction Y.

[0175] Among them, the first bit line BL is electrically connected to the first pole 01 of the first gating transistor T9, the plurality of first power voltage lines V DD 1 are electrically connected to the first pole 01 of the first transistor T1 and the first pole 01 of the second transistor T2, and the plurality of first ground lines GND1 are electrically connected to the first pole 01 of the third transistor T3 and the first pole 01 of the fourth transistor T4.

[0176] The second bit line BL' is electrically connected to the second pole 03 of the second gating transistor T10, the plurality of second power voltage lines V DD 2 are electrically connected to the second pole 03 of the fifth transistor T5 and the second pole 03 of the sixth transistor T6, and the plurality of second ground lines GND2 are electrically connected to the second pole 03 of the seventh transistor T7 and the second pole 03 of the eighth transistor T8.

[0177] In the orthogonal projection to the reference surface S, the first bit line BL overlaps the first pole 01 of the first gating transistor T9, and the plurality of first power voltage lines V DD1and the first electrodes 01 of the second transistors T2 overlap, the plurality of first ground lines GND1 overlap with the first electrodes 01 of the third transistors T3 and the first electrodes 01 of the fourth transistors T4.

[0178] In the orthogonal projection to the reference plane S, the second bit lines BL' overlap with the second electrodes 03 of the second gate transistors T10, and the plurality of second power voltage lines V DD 2and the second electrodes 03 of the sixth transistors T6 overlap, the plurality of second ground lines GND2 overlap with the second electrodes 03 of the seventh transistors T7 and the second electrodes 03 of the eighth transistors T8.

[0179] In this way, the first electrodes 01 of the first gate transistors T9, the first electrodes 01 of the first transistors T1, the first electrodes 01 of the second transistors T2, the first electrodes 01 of the third transistors T3 and the first electrodes 01 of the fourth transistors T4 do not need to pass through the dielectric layer and the second circuit structure layer, and are connected to the traces located on the side of the second circuit structure layer away from the first circuit structure layer, so that a transfer layer does not need to be formed on the dielectric layer and in the second circuit structure layer, thereby effectively reducing the occupied area of the memory 300 and improving the integration density of the memory 300.

[0180] For example, the first bit lines BL, the plurality of first power voltage lines VDD1 and the plurality of first ground lines GND1 can be arranged on the side of the first circuit structure layer 10 away from the second circuit structure layer 20 by using a buried power rail (BPR) technology.

[0181] In some embodiments, in the first direction X, the plurality of first power voltage lines V DD 1and the plurality of first ground lines GND1 can be arranged alternately, and the plurality of second power voltage lines V DD 2and the plurality of second ground lines GND2 can be arranged alternately.

[0182] Figure 13 Fig. 1 shows a top view of a part of a memory 300 according to an embodiment of the present application. As shown in Fig. 1, the memory 300 includes a plurality of memory cells 310. The plurality of memory cells 310 are arranged in an array, for example, the plurality of memory cells 310 can be arranged into a plurality of rows along a first direction X and a plurality of columns along a second direction Y. Figure 13

[0183] The memory cells 310 located in the same row can be connected to the same word line WL, and the memory cells 310 located in the same column can be connected to the same pair of first bit lines BL and second bit lines BL'.

[0184] ​In some embodiments, two adjacent memory cells 310 in the first direction X can be mirror-symmetrical. That is, in the first direction X, the first gate transistor T9 of two adjacent memory cells 310 are arranged adjacently, and the fifth transistor of two adjacent memory cells 310 are arranged adjacently. Alternatively, in the first direction X, the second gate transistor T10 of two adjacent memory cells 310 are arranged adjacently, and the second transistor T2 of two adjacent memory cells 310 are arranged adjacently.

[0185] In some embodiments, two adjacent memory cells 310 in the second direction Y can be mirror-symmetrical. That is, in the same circuit structure layer (the first circuit structure layer or the second circuit structure layer), the first poles of two adjacent transistors are adjacent to each other, or the second poles of two adjacent transistors are adjacent to each other.

[0186] In the first circuit structure layer 10, the first poles of the plurality of transistors are used to connect signal lines (such as power voltage lines, ground lines or bit lines), so that when two adjacent memory cells 310 in the second direction Y are mirror-symmetrical, in the first circuit layer, when the first poles of two transistors respectively located in two adjacent memory cells 310 are adjacent to each other, the first poles of the two transistors can be shared, thereby connecting the same signal line.

[0187] Similarly, in the second circuit structure layer 20, the second poles of the plurality of transistors are also used to connect signal lines, so that when two adjacent memory cells 310 in the second direction Y are mirror-symmetrical, in the second circuit structure layer 20, when the second poles of two transistors respectively located in two adjacent memory cells 310 are adjacent to each other, the second poles of the two transistors can be shared, thereby connecting the same signal line.

[0188] By such arrangement, the occupied area of the memory 300 can be further reduced, and the integration density of the memory cells 310 in the memory 300 can be improved.

[0189] In some embodiments of the present application, another memory 400 is provided, which includes a plurality of memory cells 410, a first bit line BL, a second bit line BL', a power voltage line V DD and a ground line GND. Figure 14 A circuit diagram of the memory 400 provided by the embodiments of the present application is shown in FIG. 4, wherein Figure 14 one of the plurality of memory cells 410 of the memory 400 is shown in FIG. 4.

[0190] The storage unit 410 includes a first inverter 401 and a second inverter 402. The first inverter 401 includes a first input port IN1 and a second input port IN2, and a first output port OUT1 and a second output port OUT2. The second inverter 402 includes a third input port IN3 and a fourth input port IN4, and a third output port OUT3 and a fourth output port OUT4. The connection relationship of the first inverter 401 and the second inverter 402 is the same as that of the first inverter 301 and the second inverter 302 in the above embodiment, which will not be described here again. The first inverter 401 and the second inverter 402 are cascaded to form a latch.

[0191] In some examples, the first inverter 401 can include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The second inverter 402 can include a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The foregoing plurality of transistors each includes a first pole, a gate, and a second pole. The first pole is one of a source and a drain, and the second pole is the other of the source and the drain. The first poles of different transistors can be the same source or the same drain, or one source and the other drain.

[0192] The conductive connection relationship between the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 in the first inverter 401 is the same as that between the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 in the first inverter 301 in the above embodiment. The conductive connection relationship of the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 in the second inverter 402 is the same as that of the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 in the second inverter 302 in the above embodiment. The embodiments of the present application will not be described here again.

[0193] Compared with the storage unit 310 provided in the above embodiment, the storage unit 410 provided in the embodiment of the present application increases two gate transistors. As shown in FIG. 4B, the storage unit 410 can further include a first gate transistor T9, a second gate transistor T10, a third gate transistor T11, and a fourth gate transistor T12. The first gate transistor T9 and the third gate transistor T11 are used to control the connection between the latch and the first bit line BL, and the second gate transistor T10 and the fourth gate transistor T12 are used to control the connection between the latch and the second bit line BL'. Figure 14 ​

[0194] The first gating transistor T9, the second gating transistor T10, the third gating transistor T11 and the fourth gating transistor T12 each include a first pole, a gate and a second pole, wherein the first pole is one of a source and a drain, and the second pole is the other of the source and the drain.

[0195] For example, the first pole of the first gating transistor T9 is electrically connected with the first bit line BL, and the second pole of the first gating transistor T9 is electrically connected with the first output port OUT1 of the first inverter 401 and the fourth input port IN4 of the second inverter 302. That is, the second pole of the first gating transistor T9 is electrically connected with the gate of the sixth transistor T6, the gate of the seventh transistor T7, the second pole of the first transistor T1 and the second pole of the third transistor T3.

[0196] The first pole of the second gating transistor T10 is electrically connected with the second bit line BL’, and the second pole of the second gating transistor T10 is electrically connected with the third input port IN3 of the second inverter 402 and the second output port OUT2 of the first inverter. That is, the second pole of the second gating transistor T10 is electrically connected with the gate of the fifth transistor T5, the gate of the eighth transistor T8, the second pole of the second transistor T2 and the second pole of the fourth transistor T4.

[0197] The second pole of the third gating transistor T11 is electrically connected with the first bit line BL, and the first pole of the third gating transistor T11 is electrically connected with the first input port IN1 of the first inverter 401 and the fourth output port OUT4 of the second inverter 402. That is, the first pole of the third gating transistor T11 is electrically connected with the gate of the first transistor T1, the gate of the fourth transistor T4, the first pole of the sixth transistor T6 and the first pole of the eighth transistor T8.

[0198] The second pole of the fourth gating transistor T12 is electrically connected with the second bit line BL’, and the first pole of the fourth gating transistor T12 is electrically connected with the second input port IN2 of the first inverter 401 and the third output port OUT3 of the second inverter 402. That is, the first pole of the fourth gating transistor T12 is electrically connected with the gate of the second transistor T2, the gate of the third transistor T3, the first pole of the fifth transistor T5 and the first pole of the seventh transistor T7.

[0199] The storage unit 410 provided by the embodiment of the present application increases two gating transistors, so that the stability and the read-write speed of the storage unit 410 can be improved, and the input-output port of the storage unit 410 can be stably flipped.

[0200] The polarity of the plurality of transistors of the plurality of storage units 410 provided by the above-mentioned embodiment of the present application is the same, Figure 14In some examples, all of the transistors in the memory cell 410 are N-type transistors. In other examples, all of the transistors in the memory cell 410 can be P-type transistors.

[0201] The following detailed description is provided to enable one of ordinary skill in the art to Figure 14 The operation of the memory cell 410 is described in brief with the aid of the circuit diagram provided.

[0202] The operation of the memory cell 310 includes a write process and a read process, as in the above-described embodiments. In the write phase, the word line WL receives a high-level signal, and the first pass transistor T9, the second pass transistor T10, the third pass transistor T11, and the fourth pass transistor T12 are all turned on. In the write high phase, the first bit line BL receives a high-level signal, and the second bit line BL' receives a low-level signal. If the voltage at the second electrode of the first pass transistor T9 and the second electrode of the second pass transistor T10 is high, and the voltage at the first electrode of the third pass transistor T11 and the first electrode of the fourth pass transistor T12 is low, then the voltage at the second electrode of the first pass transistor T9, the second electrode of the second pass transistor T10, the first electrode of the third pass transistor T11, and the first electrode of the fourth pass transistor T12 remains unchanged. Conversely, if the voltage at the second electrode of the first pass transistor T9 and the second electrode of the second pass transistor T10 is low, and the voltage at the first electrode of the third pass transistor T11 and the first electrode of the fourth pass transistor T12 is high, then the voltage at the second electrode of the first pass transistor T9, the second electrode of the second pass transistor T10, the first electrode of the third pass transistor T11, and the first electrode of the fourth pass transistor T12 is inverted. Then, the word line WL receives a low-level signal, and the first pass transistor T9, the second pass transistor T10, the third pass transistor T11, and the fourth pass transistor T12 are all turned off. The write low process is similar to the write high process described above, and is not described again here.

[0203] In the reading process, the word line WL receives a low level signal, the first selection transistor T9, the second selection transistor T10, the third selection transistor T11 and the fourth selection transistor T12 are all turned off. After the first bit line BL and the second bit line BL' are pre-charged to the same voltage (for example, pre-charged to high level), the word line WL receives a high level signal again, the first selection transistor T9, the second selection transistor T10, the third selection transistor T11 and the fourth selection transistor T12 are all turned on, when the latch stores a high level, the level on the first bit line BL is the same as the level on the second electrode of the first selection transistor T9, the level on the second electrode of the second selection transistor T10, the level on the first electrode of the third selection transistor T11 and the first electrode of the fourth selection transistor T12 is different, the second bit line BL' is discharged, the voltage is lowered, a voltage difference is generated between the first bit line BL and the second bit line BL', the reading operation is completed by reading the voltage difference.

[0204] After the writing operation is completed, the storage unit enters the signal static holding stage. In the signal static holding stage, only one transistor in any parallel path of the latch is in the on state, and the other is in the off state. For example, when the transistors in the latch are NMOSFET, after writing a high level, the first transistor T1, the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7 are all in the on state, and the second transistor T2, the third transistor T3, the fifth transistor T5 and the eighth transistor T8 are all in the off state.

[0205] Figure 15 The structural diagram of the memory 400 provided by the embodiment of the present application is shown in FIG. 4. Referring to FIG. 4, the memory 400 includes a first circuit structure layer 10, a second circuit structure layer 20 and a plurality of interconnection structures 30. Figure 15 The memory 400 includes a first circuit structure layer 10, a second circuit structure layer 20 and a plurality of interconnection structures 30. The first circuit structure layer 10 includes a first inverter 401. The second circuit structure layer 20 is stacked with the first circuit structure layer 10, and the second circuit structure layer 20 includes a second inverter 402. The interconnection structure 30 is located between the first circuit structure layer 10 and the second circuit structure layer 20.

[0206] The first inverter 401 and the second inverter 402 each include a plurality of transistors T, and the plurality of transistors T of the first inverter 401 and the plurality of transistors T of the second inverter 402 are of the same polarity. The plurality of transistors T of the first inverter 401 and the plurality of transistors T of the second inverter 402 are arranged in sequence along a first direction X parallel to a reference surface S. The reference surface S is a plane on which a lower surface of the first circuit structure layer 10 is located. The plurality of transistors T of the first inverter 401 and the plurality of transistors T of the second inverter 402 overlap in orthographic projection on the reference surface S, and the first inverter 401 and the second inverter 402 are electrically connected by a plurality of interconnection structures 30.

[0207] The technical effects that the memory 400 provided by the embodiments of the present application can achieve are the same as those of the memory 300 provided by the above-described embodiments, which will not be described again here.

[0208] As shown in FIG. 1, in some embodiments, the transistor T includes a first electrode 01, a gate electrode 02, and a second electrode 03 arranged in sequence along a second direction Y, and the second direction Y is parallel to the reference surface S and perpendicular to the first direction X. In orthographic projection on the reference surface S, the gate electrode 02 of the transistor T of the first inverter 401 overlaps the first electrode 01 of the transistor T of the second inverter 402, and the second electrode 03 of the transistor T of the first inverter 401 overlaps the gate electrode 02 of the transistor T of the second inverter 402. Figure 15 In this way, the transistors of the first inverter 401 and the transistors of the second inverter 402 have a large overlapping area, and the memory cell occupies a small area. At the same time, the gate electrode 02 of the transistor T of the first inverter 401 overlaps the first electrode 01 of the transistor T of the second inverter 402, and the second electrode 03 of the transistor T of the first inverter 401 overlaps the gate electrode 02 of the transistor T of the second inverter 402, which is also conducive to making the interconnection structure 30 perpendicular to the first circuit structure layer 10 and the second circuit structure layer 20, simplifying the plurality of interconnection structures, so that the orthographic projection of the interconnection structure 30 on the reference surface S is small, and the interconnection structure 30 occupies a small area.

[0209] Similar to the above-described embodiments, the first circuit structure layer 10 can include a first active layer 11, a first gate electrode layer 12, a first source / drain electrode layer 13, and a plurality of dielectric layers (not shown) arranged in layers.

[0210] The plurality of dielectric layers can include a dielectric layer located on the side of the first active layer 11 away from the first gate electrode layer 12, a dielectric layer insulating the first active layer 11 from the first gate electrode layer 12, a dielectric layer insulating the first source / drain electrode layer 13 from the first gate electrode layer 12, and the like.

[0211]

[0212] ​The gate 02 of the plurality of transistors T of the first inverter 401 can be located in the first gate layer 12, and the first pole 01 and the second pole 03 of the plurality of transistors T of the first inverter 401 can be located in the first source-drain electrode layer 13. The plurality of transistors T of the first inverter 401 can further include a channel 04, which can be formed in the first active layer 11, and in the same transistor T, the orthogonal projection of the channel 04 on the reference surface S partially overlaps the orthogonal projection of the gate 02 on the reference surface S. The first pole 01 and the second pole 03 of the transistor T can be in electrical contact with the channel 04 through a dielectric layer.

[0213] In some embodiments, the second circuit structure layer 20 can include a second active layer 21, a second gate layer 22, a second source-drain electrode layer 23, and a plurality of dielectric layers (not shown) arranged in layers.

[0214] The plurality of dielectric layers can include a dielectric layer located on the side of the second active layer 21 away from the second gate layer 22, a dielectric layer insulating the second active layer 21 from the second gate layer 22, and a dielectric layer insulating the second source-drain electrode layer 23 from the second gate layer 22.

[0215] The gate 02 of the plurality of transistors T of the second inverter 402 can be located in the second gate layer 22, and the first pole 01 and the second pole 03 of the plurality of transistors T of the second inverter 402 can be located in the second source-drain electrode layer 23. The plurality of transistors T of the second inverter 402 can further include a channel 04, which can be formed in the second active layer 21, and in the same transistor T, the orthogonal projection of the channel 04 on the reference surface S overlaps the orthogonal projection of the gate 02 on the reference surface S. The first pole 01 and the second pole 03 of the transistor T can be in contact with the channel 04 through a dielectric layer.

[0216] Continuing to refer to Figure 15 In some embodiments, there can also be a dielectric layer between the first circuit structure layer 10 and the second circuit structure layer 20, and the plurality of interconnection structures 30 can pass through the dielectric layer (not shown) to connect the first inverter 401 in the first circuit structure layer 10 and the second inverter 402 in the second circuit structure layer 20.

[0217] It can be understood that, Figure 15 This is only one possible structure of the memory 400 in the embodiments of the present application, and the structure of the plurality of transistors T in the memory 400 is not limited to this.

[0218] Continuing to refer to Figure 15In some embodiments, in the orthographic projection to the reference surface S, the first pole 01 of the transistor T of the first inverter 401 is staggered with the second pole 03 of the transistor T of the second inverter 402. In this way, the multiple transistors T in the first inverter 401 and the second inverter 402 can be conveniently connected with other wirings (for example, power voltage lines, connection lines and bit lines, etc.).

[0219] As shown in FIG. 4, the first inverter 401 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4. In the first direction X, the third transistor T3, the first transistor T1, the fourth transistor T4 and the second transistor T2 are arranged in sequence. The first transistor T1 and the fourth transistor T4 share a gate. The first circuit structure layer 10 further includes a first connection line L1 and a second connection line L2, the second pole 03 of the third transistor T3 and the second pole 03 of the first transistor T1 are electrically connected through the first connection line L1, and the second pole 03 of the fourth transistor T4 and the second pole 03 of the second transistor T2 are electrically connected through the second connection line L2. Figure 16 In some examples, the first connection line L1 and the second connection line L2 can extend along the first direction X. In this way, the shape of the first connection line L1 and the second connection line L2 is simple, easy to manufacture, and the occupied area of the first connection line L1 and the second connection line L2 can be smaller.

[0220] As shown in FIG. 5, the second inverter 402 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8, and in the first direction X, the seventh transistor T7, the sixth transistor T6, the eighth transistor T8 and the fifth transistor T5 are arranged in sequence. The fifth transistor T5 and the eighth transistor T8 share a gate, and the sixth transistor T6 and the seventh transistor T7 share a gate. The second circuit structure layer 20 further includes a seventh connection line L7, and the first pole 01 of the sixth transistor T6 and the first pole 01 of the eighth transistor T8 are electrically connected through the seventh connection line L7.

[0221] Figure 17 In some examples, the seventh connection line L7 can extend along the first direction X, and the shape of the seventh connection line L7 is simple, easy to manufacture, and the occupied area of the seventh connection line L7 can be smaller.

[0222] Based on the distribution structure of the above-mentioned first inverter 401 and the second inverter 402, in order to realize the circuit connection relationship provided in

[0223] The multiple interconnection structures 30 include a first interconnection structure 31, a second interconnection structure 32, a third interconnection structure 33, a fourth interconnection structure 34 and a fifth interconnection structure 35. Figure 14

[0224] ​​The gate 02 of the third transistor T3 is electrically connected with the first pole 01 of the seventh transistor T7 through the first interconnection structure 31. The gate 02 of the seventh transistor T7 is electrically connected with the first connection line L1 through the second interconnection structure 32. The gate 02 of the first transistor T1 is electrically connected with the seventh connection line L7 through the third interconnection structure 33. The second connection line L2 is electrically connected with the gate 02 of the eighth transistor T8 through the fourth interconnection structure 34. The gate of the second transistor T2 is electrically connected with the first pole 01 of the fifth transistor T5 through the fifth interconnection structure 35.

[0225] As shown in Figure 15 , the first interconnection structure 31, the second interconnection structure 32, the third interconnection structure 33, the fourth interconnection structure 34 and the fifth interconnection structure 35 can be perpendicular to the first circuit structure layer 10 and the second circuit structure layer 20, so that the structure of the plurality of interconnection structures is simple, so that the orthographic projection of the interconnection structure 30 on the reference surface S is small, and the occupation area of the interconnection structure 30 is small.

[0226] In some embodiments, as shown in Figure 16 and Figure 17 , the first circuit structure layer 10 further includes a first gating transistor T9 and a second gating transistor T10, along the first direction X, the first gating transistor T9 is located on the side of the third transistor T3 away from the first transistor T1, and the second gating transistor T10 is located on the side of the second transistor T2 away from the fourth transistor T4.

[0227] The second circuit structure layer 20 further includes a third gating transistor T11 and a fourth gating transistor T12, along the first direction X, the third gating transistor T11 is located on the side of the seventh transistor T7 away from the sixth transistor T6, and the fourth gating transistor T12 is located on the side of the fifth transistor T5 away from the eighth transistor T8.

[0228] The first gating transistor T9, the second gating transistor T10, the third gating transistor T11 and the fourth gating transistor T12 include a first pole 01, a gate 02 and a second pole 03 arranged in sequence along the second direction Y. The second pole 03 of the first gating transistor T9 is electrically connected with the first connection line L1, and the second pole 03 of the second gating transistor T10 is electrically connected with the second connection line L2. The second circuit structure layer 20 further includes an eighth connection line L8, and the first pole 01 of the fifth transistor T5 is electrically connected with the first pole 01 of the fourth gating transistor T12 through the eighth connection line L8.

[0229] In the embodiment, the second electrode 03 of the first transistor T1, the second electrode 03 of the third transistor T3, and the second electrode 03 of the first selection transistor T9 are electrically connected by the first connection line L1, and the second electrode 03 of the second transistor T2, the second electrode 03 of the fourth transistor T4, and the second electrode 03 of the second selection transistor T10 are electrically connected by the second connection line L2. In this way, the area of the storage unit 410 can be small, and the area utilization rate of the memory 300 can be improved.

[0230] In some examples, the eighth connection line L8 can extend along the first direction X, the shape of the eighth connection line L8 is simple, easy to manufacture, and the area of the eighth connection line L8 can be small.

[0231] Referring to Figure 15 and Figure 18 , the memory 400 further includes a ninth connection line L9 and a tenth connection line L10 located on the side of the second circuit structure layer 20 away from the first circuit structure layer 10. The ninth connection line L9 is electrically connected with the first electrode 01 of the third selection transistor T11 and the seventh connection line L7, and the tenth connection line L10 is electrically connected with the first electrode of the seventh transistor T7 and the eighth connection line L8.

[0232] In some embodiments, the memory 400 can further include two first connection portions 40 and two second connection portions 50. One end of the ninth connection line L9 is electrically connected with the first electrode 01 of the third selection transistor T11 through one first connection portion 40, and the other end is electrically connected with the seventh connection line L7 through another first connection portion 40. One end of the tenth connection line L10 is electrically connected with the first electrode 01 of the seventh transistor T7 through one second connection portion 50, and the other end is electrically connected with the eighth connection line L8 through another second connection portion 50. Wherein, the two first connection portions 40 and the two second connection portions 50 are arranged alternately along the first direction X.

[0233] In some examples, as shown in Figure 19 , the ninth connection line L9 and the tenth connection line L10 can be on the same layer, the ninth connection line L9 avoids the second connection portion 50, and the tenth connection line L10 avoids the first connection portion 40.

[0234] At this time, the structure of the ninth connection line L9 and the tenth connection line L10 in the embodiment is not limited, as long as the ninth connection line L9 avoids the second connection portion 50 and the tenth connection line L10 avoids the first connection portion 40. Figure 19 In the embodiment, the ninth connection line L9 and the tenth connection line L10 are both polyline.

[0235] In the embodiment of the application, the ninth connection line L9 and the tenth connection line L10 are in the same layer, so that the ninth connection line L9 and the tenth connection line L10 can be prepared at the same time, the preparation process of the storage unit 410 is simplified, and the preparation cost of the storage unit 410 is reduced.

[0236] In some examples, as shown in Figure 15 and Figure 18 , the ninth connection line L9 is located on the side of the tenth connection line L10 away from the second circuit structure layer 20, and the tenth connection line L10 is in a zigzag shape. In the orthogonal projection onto the reference surface S, the tenth connection line L10 avoids the first connection part 40.

[0237] At this time, the ninth connection line L9 can be in a straight line shape and extend along the first direction X. In this way, the ninth connection line L9 has a simple structure and occupies a small area, which is conducive to reducing the occupied area of the storage unit 410 and improving the integration density of the memory 400.

[0238] In some embodiments, as shown in Figure 16 , the gate 02 of the first pass transistor T9 includes a first part 021 and a second part 022, and the second part 022 is away from the third transistor T3 relative to the first part 021. In the orthogonal projection onto the reference surface S, the first part 021 overlaps the first pole 01 of the third pass transistor T11, and the second part 022 does not overlap the first pole 01 of the third pass transistor T11.

[0239] The gate 02 of the second pass transistor T10 includes a third part 023 and a fourth part 024, and the fourth part 024 is away from the second transistor T2 relative to the third part 023. In the orthogonal projection onto the reference surface S, the third part 023 overlaps the first pole 01 of the fourth pass transistor T12, and the fourth part 024 does not overlap the first pole 01 of the fourth pass transistor T12.

[0240] In this way, the second part 022 can not be blocked by the first pole of the third pass transistor T11, and the fourth part 024 can not be blocked by the first pole 01 of the fourth pass transistor T12, so that the connection of the gate of the first pass transistor T9 and the word line WL and the connection of the gate of the second pass transistor T10 and the word line WL can be easily realized.

[0241] In some embodiments, as shown in Figure 20As shown, the memory 400 further comprises a word line WL, which is located on the side of the second circuit structure layer 20 away from the first circuit structure layer 10 and extends along the first direction X. The word line WL is electrically connected with the gate 02 of the first pass transistor T9, the gate 02 of the second pass transistor T10, the gate 02 of the third pass transistor T11 and the gate 02 of the fourth pass transistor T12, and in the orthogonal projection onto the reference plane S, the word line WL overlaps with the second portion 022, the fourth portion 024, the gate 02 of the third pass transistor T11 and the gate 02 of the fourth pass transistor T12.

[0242] It can be understood that, in order to insulate the word line WL from the devices in the second circuit structure 20, a dielectric layer (not shown) can be arranged between the word line WL and the second circuit structure layer 20.

[0243] In the embodiments of the present application, the word line WL extends along the first direction X, which can make the shape of the word line WL simple, easy to manufacture, and reduce the area occupied by the word line WL. At the same time, the word line WL overlaps with the second portion 022, the fourth portion 024, the gate 02 of the third pass transistor T11 and the gate 02 of the fourth pass transistor T12, which can also enable the word line WL to pass through the via in the dielectric layer and be electrically connected with the second portion 022 and the fourth portion 024, the gate 02 of the third pass transistor T11 and the gate 02 of the fourth pass transistor T12, thereby simplifying the structure of the memory 400, reducing the area occupied by the memory 400, and improving the storage density and area utilization of the memory 400.

[0244] Continuing to refer to Figure 20 In some embodiments, the memory 400 further comprises a first bit line BL and a second bit line BL', which are located on the side of the second circuit structure layer 20 away from the first circuit structure layer 10 and extend along the second direction Y.

[0245] The first bit line BL is electrically connected with the first pole 01 of the first pass transistor T9 and the second pole 03 of the third pass transistor T11, and the second bit line BL' is electrically connected with the first pole 01 of the second pass transistor T10 and the second pole 03 of the fourth pass transistor T12. In the orthogonal projection onto the reference plane S, the first bit line BL overlaps with the first pole 01 of the first pass transistor T9 and the second pole 03 of the third pass transistor T11, and the second bit line BL' overlaps with the first pole 01 of the second pass transistor T10 and the second pole 03 of the fourth pass transistor T12.

[0246] It can be understood that, in order to insulate the first bit line BL and the second bit line BL' from the devices in the second circuit structure layer 20, a dielectric layer (not shown) can be arranged between the first bit line BL and the second bit line BL' and the second circuit structure layer 20.

[0247] In some examples, the first bit line BL and the second bit line BL' can be located in the same layer. In this case, the materials of the first bit line BL and the second bit line BL' can be the same. In this way, the first bit line BL and the second bit line BL' can be fabricated simultaneously, thereby simplifying the fabrication process of the memory 400 and reducing the fabrication cost of the memory 400.

[0248] In this embodiment, in the orthographic projection onto the reference plane S, the first bit line BL overlaps with the first electrode 01 of the first select transistor T9 and the second electrode 03 of the third select transistor T11, and the second bit line BL' overlaps with the first electrode 01 of the second select transistor T10 and the second electrode 03 of the fourth select transistor T12. Thus, the first bit line BL can pass through the via 15 in the dielectric layer and be electrically connected to the first electrode 01 of the first select transistor T9 and the second electrode 03 of the third select transistor T11, and the second bit line BL' can pass through the via 15 in the dielectric layer and be electrically connected to the first electrode 01 of the second select transistor T10 and the second electrode 03 of the fourth select transistor T12. This allows for a smaller footprint of the memory 400, thereby improving the storage density and area utilization of the memory 400.

[0249] In other embodiments, such as Figure 21 As shown, the memory 400 may include multiple power supply voltage lines V DD And multiple grounding wires GND, multiple power supply voltage lines V DD It can include multiple first power supply voltage lines V DD 1 and multiple second power supply voltage lines V DD 2. Multiple grounding wires GND may include multiple first grounding wires GND1 and multiple second grounding wires GND2.

[0250] It is understandable that multiple first power supply voltage lines V DD 1 and multiple second power supply voltage lines V DD The voltages on 2 are the same, and the voltages on multiple first grounding wires GND1 and multiple second grounding wires GND2 are the same.

[0251] The memory 400 may include a first bit line BL, a second bit line BL', a third bit line BL1, and a fourth bit line BL1', wherein the signal on the third bit line BL1 is the same as the signal on the first bit line BL, and the signal on the fourth bit line BL1' is the same as the signal on the second bit line BL'.

[0252] It can be understood that since the signal on the third bit line BL1 is the same as the signal on the first bit line BL, the transistor connected with the third bit line BL1 can be equivalent to being electrically connected with the first bit line BL in the circuit diagram. Since the signal on the fourth bit line BL1' is the same as the signal on the second bit line BL', the transistor connected with the fourth bit line BL1' can be equivalent to being electrically connected with the second bit line BL' in the circuit diagram.

[0253] For example, the first bit line BL, the second bit line BL', the plurality of first power voltage lines V DD 1 and the plurality of first ground lines GND1 are located on the side of the first circuit structure layer 10 away from the second circuit structure layer 20, and all extend along the second direction Y. The third bit line BL1, the fourth bit line BL1', the plurality of second power voltage lines V DD 2 and the plurality of second ground lines GND2 are located on the side of the second circuit structure layer 20 away from the first circuit structure layer 10, and all extend along the second direction Y.

[0254] The first bit line BL is electrically connected with the first pole 01 of the first gating transistor T9, the second bit line BL' is electrically connected with the first pole 01 of the second gating transistor T10, the plurality of first power voltage lines V DD 1 are electrically connected with the first pole 01 of the first transistor T1 and the first pole 01 of the second transistor T2, and the plurality of first ground lines GND1 are electrically connected with the first pole 01 of the third transistor T3 and the first pole 01 of the fourth transistor T4.

[0255] In the orthogonal projection to the reference surface S, the first bit line BL overlaps the first pole 01 of the first gating transistor T9, the second bit line BL' overlaps the first pole 01 of the second gating transistor T10, the plurality of first power voltage lines V DD 1 overlap the first pole 01 of the first transistor T1 and the first pole 01 of the second transistor T2, and the plurality of first ground lines GND1 overlap the first pole 01 of the third transistor T3 and the first pole 01 of the fourth transistor T4.

[0256] The third bit line BL1 is electrically connected with the second pole 03 of the third gating transistor T11, the fourth bit line BL1' is electrically connected with the second pole 03 of the fourth gating transistor T12, the plurality of second power voltage lines V DD 2 are electrically connected with the second pole 03 of the fifth transistor T5 and the second pole 03 of the sixth transistor T6, and the plurality of second ground lines GND2 are electrically connected with the second pole 03 of the seventh transistor T7 and the second pole 03 of the eighth transistor T8.

[0257] In the orthographic projection onto the reference plane S, the third bit line BL1 overlaps with the second terminal 03 of the third gating transistor T11, and the fourth bit line BL1' overlaps with the second terminal 03 of the fourth gating transistor T12. Multiple second power supply voltage lines V... DD 2 overlaps with the second terminal 03 of the fifth transistor T5 and the second terminal 03 of the sixth transistor T6, and multiple second ground wires GND2 overlap with the second terminal 03 of the seventh transistor T7 and the second terminal 03 of the eighth transistor T8.

[0258] In this way, the first pole 01 of the first select transistor T9, the first pole 01 of the second select transistor T10, the first pole 01 of the first transistor T1, the first pole 01 of the second transistor T2, the first pole 01 of the third transistor T3, and the first pole 01 of the fourth transistor T4 do not need to pass through the dielectric layer and the second circuit structure layer to connect to the third bit line BL1, the fourth bit line BL1', multiple second power supply voltage lines VDD2, and multiple second ground lines GND2 located on the side of the second circuit structure layer away from the first circuit structure layer. Therefore, there is no need to form a transition layer on the dielectric layer or in the second circuit structure layer, which effectively reduces the occupied area of ​​the memory 400 and improves the integration density of the memory 400.

[0259] In some embodiments, the memory 400 may include a plurality of memory cells 410 arranged in an array, for example, the plurality of memory cells 410 may be arranged in multiple rows along a first direction X and in multiple columns along a second direction. Memory cells 410 located in the same row may be connected to the same word line WL, and memory cells 410 located in the same column may be connected to the same pair of first bit lines BL and second bit lines BL'.

[0260] In some embodiments, two adjacent storage cells 410 in the first direction X can be mirror-symmetric.

[0261] In some embodiments, two adjacent storage cells 410 in the second direction Y can be mirror-symmetric.

[0262] The arrangement of the multiple storage units 410 in this embodiment can be similar to the arrangement of the multiple storage units 310 provided in the above embodiment, and will not be described again in this embodiment.

[0263] like Figure 22 As shown, some embodiments of this application provide an electronic device 1000, which includes a circuit board 500 and a memory (memory 300 or memory 400) provided in any of the above embodiments. The memory 300 or memory 400 is electrically connected to the circuit board 500.

[0264] The electronic device 1000 can be a terminal device, for example, a mobile phone, a tablet computer, a smart bracelet, and can also be a personal computer (PC), a server, a workstation, etc. The specific form of the electronic device 1000 is not specially limited in the embodiments of the present application.

[0265] The electronic device 1000 provided in the embodiments of the present application can achieve the same beneficial effects as the memory 300 or the memory 400 provided in the above embodiments of the present application.

[0266] In the description of the present specification, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0267] The above is merely specific implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A memory, comprising: The application relates to a circuit structure, comprising: a first circuit structure layer comprising a first inverter; a second circuit structure layer stacked with the first circuit structure layer and comprising a second inverter; a plurality of interconnection structures between the first circuit structure layer and the second circuit structure layer; wherein the first inverter and the second inverter each comprise a plurality of transistors, the plurality of transistors of the first inverter and the plurality of transistors of the second inverter have the same polarity, the plurality of transistors of the first inverter and the plurality of transistors of the second inverter are arranged in sequence along a first direction parallel to a reference plane, and the reference plane is a plane on which a lower surface of the first circuit structure layer is located; a projection of the plurality of transistors of the first inverter on the reference plane and a projection of the plurality of transistors of the second inverter on the reference plane overlap, and the first inverter and the second inverter are electrically connected through the plurality of interconnection structures.

2. The memory of claim 1, wherein, The transistor comprises a first electrode, a gate electrode and a second electrode arranged in sequence along a second direction, the second direction is parallel to the reference plane and perpendicular to the first direction; in a projection on the reference plane, the gate electrode of the transistor of the first inverter and the first electrode of the transistor of the second inverter overlap, and the second electrode of the transistor of the first inverter and the gate electrode of the transistor of the second inverter overlap.

3. The memory of claim 2, wherein, in a projection on the reference plane, the first electrode of the transistor of the first inverter and the second electrode of the transistor of the second inverter are staggered.

4. The memory of claim 2 or 3, wherein, The first inverter comprises a first transistor, a second transistor, a third transistor and a fourth transistor; along the first direction, the third transistor, the first transistor, the fourth transistor and the second transistor are arranged in sequence; the first transistor and the fourth transistor share a gate electrode; the first circuit structure layer further comprises a first connecting line and a second connecting line, the second electrode of the third transistor and the second electrode of the first transistor are electrically connected through the first connecting line, and the second electrode of the fourth transistor and the second electrode of the second transistor are electrically connected through the second connecting line.

5. The memory of claim 4, wherein, The second inverter comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; along the first direction, the fifth transistor, the seventh transistor, the sixth transistor and the eighth transistor are arranged in sequence; the sixth transistor and the seventh transistor share a gate electrode; the second circuit structure layer further comprises a third connecting line and a fourth connecting line, the first electrode of the fifth transistor and the first electrode of the seventh transistor are electrically connected through the third connecting line, and the first electrode of the sixth transistor and the first electrode of the eighth transistor are electrically connected through the fourth connecting line.

6. The memory of claim 5, wherein, the plurality of interconnection structures comprises a first interconnection structure, a second interconnection structure, a third interconnection structure and a fourth interconnection structure; The gate of the third transistor is electrically connected with the first electrode of the seventh transistor through the first interconnection structure; the gate of the seventh transistor is electrically connected with the first connection line through the second interconnection structure; the gate of the first transistor is electrically connected with the fourth connection line through the third interconnection structure; the gate of the eighth transistor is electrically connected with the second connection line through the fourth interconnection structure.

7. The memory of claim 5 or 6, wherein, The first circuit structure layer further comprises a first selection transistor, which is located on the side of the third transistor away from the first transistor along the first direction. The second circuit structure layer further comprises a second selection transistor, which is located on the side of the eighth transistor away from the sixth transistor along the first direction. The first selection transistor and the second selection transistor comprise a first electrode, a gate and a second electrode arranged in sequence along the second direction; the second electrode of the first selection transistor is electrically connected with the first connection line.

8. The memory of claim 7, wherein, The plurality of interconnection structures comprise a fifth interconnection structure, the first electrode of the second selection transistor is electrically connected with the gate of the second transistor through the fifth interconnection structure.

9. The memory of claim 7 or 8, wherein, Further comprising: A fifth connection line and a sixth connection line are located on the side of the second circuit structure layer away from the first circuit structure layer; The fifth connection line is electrically connected with the gate of the fifth transistor and the gate of the eighth transistor; the sixth connection line is electrically connected with the third connection line and the first electrode of the second selection transistor; in the orthogonal projection onto the reference plane, the fifth connection line overlaps with the gate of the fifth transistor and the gate of the eighth transistor, and the sixth connection line overlaps with the first electrode of the seventh transistor and the first electrode of the second selection transistor.

10. The memory according to any one of claims 7-9, wherein The gate of the first selection transistor comprises a first part and a second part, the second part is away from the third transistor relative to the first part; in the orthogonal projection onto the reference plane, the first part overlaps with the first electrode of the fifth transistor, and the second part does not overlap with the first electrode of the fifth transistor; The memory further comprises a word line located on the side of the second circuit structure layer away from the first circuit structure layer, the word line extends along the first direction; the word line is electrically connected with the gate of the first selection transistor and the gate of the second selection transistor, in the orthogonal projection onto the reference plane, the word line overlaps with the second part and the gate of the second selection transistor.

11. The memory of any one of claims 7-10, wherein, Further comprising: A first bit line and a second bit line are located on the side of the second circuit structure layer away from the first circuit structure layer and extend along the second direction; The first bit line is electrically connected with the first electrode of the first selection transistor, and the second bit line is electrically connected with the second electrode of the second selection transistor; in the orthogonal projection onto the reference plane, the first bit line overlaps with the first electrode of the first selection transistor, and the second bit line overlaps with the second electrode of the second selection transistor.

12. The memory of any one of claims 7-10, wherein, Further comprising: The first bit line, the plurality of first power voltage lines and the plurality of first ground lines are located on the side of the first circuit structure layer away from the second circuit structure layer, and all extend along the second direction; The second bit line, the plurality of second power voltage lines and the plurality of second ground lines are located on the side of the second circuit structure layer away from the first circuit structure layer, and all extend along the second direction; The first bit line and the first electrode of the first selection transistor are electrically connected, the plurality of first power voltage lines and the first electrodes of the first transistor and the second transistor are electrically connected, and the plurality of first ground lines and the first electrodes of the third transistor and the fourth transistor are electrically connected; in the orthographic projection onto the reference plane, the first bit line and the first electrode of the first selection transistor overlap, the plurality of first power voltage lines and the first electrodes of the first transistor and the second transistor overlap, and the plurality of first ground lines and the first electrodes of the third transistor and the fourth transistor overlap; The second bit line and the second electrode of the second selection transistor are electrically connected, the plurality of second power voltage lines and the second electrodes of the fifth transistor and the sixth transistor are electrically connected, and the plurality of second ground lines and the second electrodes of the seventh transistor and the eighth transistor are electrically connected; in the orthographic projection onto the reference plane, the second bit line and the second electrode of the second selection transistor overlap, the plurality of second power voltage lines and the second electrodes of the fifth transistor and the sixth transistor overlap, and the plurality of second ground lines and the second electrodes of the seventh transistor and the eighth transistor overlap.

13. The memory of claim 4, wherein, The second inverter includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, which are arranged in the first direction in sequence; the fifth transistor shares a gate electrode with the eighth transistor, and the sixth transistor shares a gate electrode with the seventh transistor; The second circuit structure layer further includes a seventh connection line, and the first electrode of the sixth transistor and the first electrode of the eighth transistor are electrically connected through the seventh connection line.

14. The memory of claim 13, wherein, The plurality of interconnection structures include a first interconnection structure, a second interconnection structure, a third interconnection structure, a fourth interconnection structure and a fifth interconnection structure; The gate electrode of the third transistor and the first electrode of the seventh transistor are electrically connected through the first interconnection structure; the gate electrode of the seventh transistor and the first connection line are electrically connected through the second interconnection structure; the gate electrode of the first transistor and the seventh connection line are electrically connected through the third interconnection structure; the second connection line and the gate electrode of the eighth transistor are electrically connected through the fourth interconnection structure; and the gate electrode of the second transistor and the first electrode of the fifth transistor are electrically connected through the fifth interconnection structure.

15. The memory of claim 13 or 14, wherein, The first circuit structure layer further comprises a first gating transistor and a second gating transistor, along the first direction, the first gating transistor is located on a side of the third transistor away from the first transistor, and the second gating transistor is located on a side of the second transistor away from the fourth transistor; The second circuit structure layer further comprises a third gating transistor and a fourth gating transistor, along the first direction, the third gating transistor is located on a side of the seventh transistor away from the sixth transistor, and the fourth gating transistor is located on a side of the fifth transistor away from the eighth transistor; The first gating transistor, the second gating transistor, the third gating transistor and the fourth gating transistor comprise a first electrode, a gate electrode and a second electrode arranged in sequence along the second direction; the second electrode of the first gating transistor is electrically connected with the first connection line, and the second electrode of the second gating transistor is electrically connected with the second connection line; The second circuit structure layer further comprises an eighth connection line, and the first electrode of the fifth transistor is electrically connected with the first electrode of the fourth gating transistor through the eighth connection line.

16. The memory of claim 15, wherein, Further comprising: a ninth connection line and a tenth connection line located on a side of the second circuit structure layer away from the first circuit structure layer; the ninth connection line is electrically connected with the first electrode of the third gating transistor and the seventh connection line, and the tenth connection line is electrically connected with the first electrode of the seventh transistor and the eighth connection line.

17. The memory of claim 16, wherein, Further comprising: two first connection parts, one end of the ninth connection line is electrically connected with the first electrode of the third gating transistor through one of the first connection parts, and the other end is electrically connected with the seventh connection line through the other first connection part; two second connection parts, one end of the tenth connection line is electrically connected with the first electrode of the seventh transistor through one of the second connection parts, and the other end is electrically connected with the eighth connection line through the other second connection part; Wherein, the two first connection parts and the two second connection parts are alternately arranged along the first direction; The ninth connection line and the tenth connection line are in the same layer, the ninth connection line avoids the second connection part, and the tenth connection line avoids the first connection part; or, the ninth connection line is located on a side of the tenth connection line away from the second circuit structure layer, and the tenth connection line is in the shape of a broken line; in the orthographic projection onto the reference surface, the tenth connection line avoids the first connection part.

18. The memory according to any one of claims 15-17, characterized in that: the gate electrode of the first gating transistor comprises a first part and a second part, the second part is away from the third transistor relative to the first part; in the orthographic projection onto the reference surface, the first part overlaps with the first electrode of the third gating transistor, and the second part does not overlap with the first electrode of the third gating transistor. The gate of the second gating transistor comprises a third portion and a fourth portion, the fourth portion is away from the second transistor relative to the third portion, in the orthographic projection onto the reference plane, the third portion overlaps the first pole of the fourth gating transistor, and the fourth portion does not overlap the first pole of the fourth gating transistor; The memory further comprises a word line located on the side of the second circuit structure layer away from the first circuit structure layer and extending along the first direction; the word line is electrically connected with the gates of the first gating transistor, the second gating transistor, the third gating transistor and the fourth gating transistor, and in the orthographic projection onto the reference plane, the word line overlaps the second portion, the fourth portion, the gate of the third gating transistor and the gate of the fourth gating transistor.

19. The memory of any one of claims 15-18, wherein, Further comprising: a first bit line and a second bit line located on the side of the second circuit structure layer away from the first circuit structure layer and extending along the second direction; wherein the first bit line is electrically connected with the first pole of the first gating transistor and the second pole of the third gating transistor, and the second bit line is electrically connected with the first pole of the second gating transistor and the second pole of the fourth gating transistor; in the orthographic projection onto the reference plane, the first bit line overlaps the first pole of the first gating transistor and the second pole of the third gating transistor, and the second bit line overlaps the first pole of the second gating transistor and the second pole of the fourth gating transistor.

20. The memory of any one of claims 15-18, wherein, Further comprising: a first bit line, a second bit line, a plurality of first power voltage lines and a plurality of first ground lines located on the side of the first circuit structure layer away from the second circuit structure layer and extending along the second direction; a third bit line, a fourth bit line, a plurality of second power voltage lines and a plurality of second ground lines located on the side of the second circuit structure layer away from the first circuit structure layer and extending along the second direction; wherein the first bit line is electrically connected with the first pole of the first gating transistor, the second bit line is electrically connected with the first pole of the second gating transistor, the plurality of first power voltage lines are electrically connected with the first poles of the first transistor and the second transistor, and the plurality of first ground lines are electrically connected with the first poles of the third transistor and the fourth transistor; in the orthographic projection onto the reference plane, the first bit line overlaps the first pole of the first gating transistor, the second bit line overlaps the first pole of the second gating transistor, the plurality of first power voltage lines overlap the first poles of the first transistor and the second transistor, and the plurality of first ground lines overlap the first poles of the third transistor and the fourth transistor; The third bit line is electrically connected with the second electrode of the third gating transistor, the fourth bit line is electrically connected with the second electrode of the fourth gating transistor, the plurality of second power supply voltage lines are electrically connected with the second electrode of the fifth transistor and the second electrode of the sixth transistor, and the plurality of second ground lines are electrically connected with the second electrode of the seventh transistor and the second electrode of the eighth transistor; and in the orthographic projection onto the reference plane, the third bit line and the second electrode of the third gating transistor overlap, the fourth bit line and the second electrode of the fourth gating transistor overlap, the plurality of second power supply voltage lines and the second electrode of the fifth transistor and the second electrode of the sixth transistor overlap, and the plurality of second ground lines and the second electrode of the seventh transistor and the second electrode of the eighth transistor overlap.

21. An electronic device, comprising: Comprise: a circuit board and a memory as claimed in any one of claims 1 to 20; the memory is electrically connected with the circuit board.

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