Chip electrical performance parallel detection method and device based on improved convolutional neural network

Abstract

The application discloses a chip electrical performance parallel detection method based on an improved convolutional neural network, which comprises the following steps: step 1, collecting test signals of multiple chips to be tested; step 2, performing linear superposition synthesis on the test signals of the multiple chips to be tested to generate a first composite signal, and converting the first composite signal into a two-dimensional image to obtain a first time-frequency image; step 3, inputting the first time-frequency image into a first CNN network for parallel fault detection of the multiple chips; if there is no fault, the algorithm ends and a detection result is output; if there is a fault, step 4 is performed; step 4, converting the test signals of single chips into two-dimensional images respectively to obtain multiple second time-frequency images; and step 5, inputting the multiple second time-frequency images into a second CNN network in sequence for fault detection of the single chips and outputting a detection result. The method realizes real-time parallel detection of multiple chips and improves the accuracy and efficiency of chip defect detection.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor testing technology, specifically relating to a parallel testing method and apparatus for chip electrical performance based on an improved convolutional neural network. Background Technology

[0002] Currently, integrated circuit chips are widely used in various electronic devices, and their performance and quality are crucial to the overall performance of these devices. However, with the continuous development of integrated circuit manufacturing processes, the complexity and density of chips are also rapidly increasing. Against this backdrop, chip electrical performance testing has become particularly important.

[0003] Traditional methods for testing the electrical performance of chips mainly rely on manual visual inspection or single signal analysis techniques. However, these methods suffer from low accuracy and efficiency when dealing with high-density, highly complex chips; furthermore, they may lead to missed detections and false positives because they ignore the interrelationships between different parts of the chip.

[0004] Furthermore, with the increasing intelligence and automation of electronic devices, the real-time requirements for chip electrical performance testing are becoming increasingly stringent. However, traditional chip testing methods are typically serial, requiring significant manpower and time, and cannot meet the high-volume and real-time testing demands of large-scale production.

[0005] In summary, existing chip defect detection methods suffer from low accuracy, low efficiency, and the inability to perform parallel detection. Therefore, there is an urgent need for a new, efficient, accurate, and parallel-enabled method for detecting electrical performance defects in chips to address the challenges of modern chip manufacturing. Summary of the Invention

[0006] To address the problems of low accuracy, low efficiency, and inability to perform parallel detection in existing chip defect detection methods, this invention provides a parallel detection method and apparatus for chip electrical performance based on an improved convolutional neural network. The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] In a first aspect, this invention proposes a parallel detection method for chip electrical performance based on an improved convolutional neural network, comprising:

[0008] Step 1: Acquire test signals from multiple chips under test;

[0009] Step 2: Linearly superimpose and synthesize the test signals of multiple chips under test to generate a first composite signal, and convert the first composite signal into a two-dimensional image to obtain a first time-frequency image;

[0010] Step 3: Input the first time-frequency image into the first CNN network to perform parallel fault detection of multiple chips; if no fault is found, the algorithm ends and the detection result is output; if a fault is found, proceed to step 4; wherein, the first CNN network is obtained by training a pre-built improved convolutional neural network;

[0011] Step 4: Convert the test signals of a single chip into two-dimensional images, resulting in multiple second time-frequency images;

[0012] Step 5: Input the multiple second time-frequency images into the second CNN network in sequence to perform fault detection of a single chip and output the detection results; wherein, the second CNN network is also obtained by training the pre-built improved convolutional neural network.

[0013] Secondly, this invention proposes a parallel detection device for chip electrical performance based on an improved convolutional neural network, comprising:

[0014] The signal acquisition module is used to acquire test signals from multiple chips under test.

[0015] The first signal processing module is used to linearly superimpose and synthesize the test signals of multiple chips under test to generate a first composite signal, and convert the first composite signal into a two-dimensional image to obtain a first time-frequency image;

[0016] The first detection module includes a first CNN network, which processes the first time-frequency image to achieve parallel fault detection of multiple chips, and outputs the detection result when the detection result is that no fault exists; wherein, the first CNN network is obtained by training a pre-built improved convolutional neural network;

[0017] The second signal processing module is used to convert the test signal of a single chip into a two-dimensional image when the detection result of the first detection module indicates that a fault exists, thereby obtaining multiple second time-frequency images.

[0018] The second detection module includes a second CNN network, which processes the plurality of second time-frequency images sequentially to achieve fault detection of a single chip and output the detection result; wherein, the second CNN network is also obtained by training the pre-built improved convolutional neural network.

[0019] The beneficial effects of this invention are:

[0020] The parallel chip electrical performance detection method based on an improved convolutional neural network proposed in this invention fully utilizes deep learning and image processing technologies to transform the acquired chip test signals into two-dimensional image data, thereby capturing and describing the signal features more comprehensively and accurately, thus improving the accuracy of fault detection and reducing the false alarm rate. At the same time, two CNN networks are trained to process the two-dimensional image data, first performing parallel fault detection on multiple chips, and then performing fault localization on a single chip, realizing real-time parallel detection of multiple chips, improving the accuracy and efficiency of chip defect detection, and bringing new possibilities and application prospects to the electronic equipment manufacturing industry.

[0021] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0022] Figure 1 This is a schematic flowchart of a parallel detection method for chip electrical performance based on an improved convolutional neural network provided in an embodiment of the present invention.

[0023] Figure 2 This is another flowchart illustrating the parallel detection method for chip electrical performance based on an improved convolutional neural network provided in this embodiment of the invention.

[0024] Figure 3 This is a schematic diagram of the network training process provided in an embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of the structure of the improved convolutional neural network provided in an embodiment of the present invention;

[0026] Figure 5 This is a structural block diagram of a parallel chip electrical performance detection device based on an improved convolutional neural network provided in an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] Example 1

[0029] In recent years, the rapid development of deep learning technology has brought new opportunities to the fields of image and signal processing. Deep learning models such as Convolutional Neural Networks (CNNs) have achieved significant success in image classification and feature extraction, providing new ideas for efficient and accurate chip electrical performance testing. However, applying deep learning to chip electrical performance testing still faces some challenges, such as how to effectively handle complex test signals, how to handle signals of different scales and amplitudes, and how to improve the model's generalization ability. Based on this, this invention proposes a parallel chip electrical performance testing method based on an improved convolutional neural network. Through steps such as data acquisition, preprocessing, conversion to image data, construction of a deep model, and real-time parallel detection, it effectively overcomes the shortcomings of traditional methods and improves the accuracy and efficiency of chip defect detection.

[0030] Please refer to the above. Figure 1 and Figure 2 , Figure 1 This is a flowchart illustrating a parallel detection method for chip electrical performance based on an improved convolutional neural network, provided in an embodiment of the present invention. Figure 2 This is another schematic flowchart of the parallel detection method for chip electrical performance based on an improved convolutional neural network provided in this embodiment of the invention. The parallel detection method for chip electrical performance based on an improved convolutional neural network provided in this embodiment specifically includes the following steps:

[0031] Step 1: Collect test signals from multiple chips under test.

[0032] Specifically, for multiple chips under test, electrical performance tests such as voltage, current, and frequency can be performed using hardware devices, such as probes or sensors, and the corresponding test signals can be acquired in real time.

[0033] The specific number of chips to be tested can be determined during the network training phase based on actual needs. For example, this embodiment uses 8 chips as a group for parallel testing.

[0034] Furthermore, due to noise interference, the acquired chip test signals exhibit significant amplitude differences. If the acquired test signals are directly converted into images, the feature analysis of the converted images will be extremely difficult. Therefore, after acquiring test signals from multiple chips under test, normalization preprocessing is required for the test signals from multiple chips under test.

[0035] Optionally, as one implementation method, this embodiment uses a min-max normalization method to process the acquired chip time-domain signal. The calculation method is as follows:

[0036]

[0037] In the formula, X represents the input vector, max(X) represents the maximum value of the input vector, min(X) represents the minimum value of the input vector, and x represents the magnitude to be normalized. This represents the normalized amplitude.

[0038] This embodiment uses the min-max normalization method to simply scale the amplitude of the chip test signal, compressing the amplitude range of the signal to the [0,1] interval, so that the signal amplitude values ​​of different channels are close, thereby effectively reducing the impact of noise on the results.

[0039] Step 2: Linearly superimpose and synthesize the test signals of multiple chips under test to generate a first composite signal, and convert the first composite signal into a two-dimensional image to obtain a first time-frequency image.

[0040] Specifically, the signals from multiple preprocessed chips are linearly superimposed and synthesized to generate a composite signal, referred to in this embodiment as the first composite signal. This composite signal contains comprehensive information from the test signals of multiple chips and reflects the electrical performance status of the entire chip assembly.

[0041] Specifically, the superposition calculation formula is as follows:

[0042]

[0043] In the formula, f is the first composite signal synthesized, and a i The test signal is for a single chip, where i is the chip number index, and 1 ≤ i ≤ N, where N is the total number of chips under test, which is 8 in this embodiment. i For test signal a i The corresponding weights.

[0044] Under normal circumstances, it is understandable that the same weight can be set for the test signals of each chip. In special cases, such as when the signals of some chips may be affected by noise or other interference, the weight of the test signals of those chips can be reduced to mitigate these effects; or if a signal fault is suspected in some chips, their weight can be increased. The specific allocation can be freely determined according to the actual situation.

[0045] By linearly superimposing the signals, the signal characteristics of each chip are effectively fused together to form a comprehensive signal, which is helpful for subsequent comprehensive fault detection. The first composite signal formed here will be used for overall fault detection in subsequent steps.

[0046] Furthermore, in this embodiment, the first composite signal is converted into two-dimensional image data with time and frequency domain characteristics using the continuous wavelet transform method, so that it can be processed by the subsequent convolutional neural network.

[0047] Specifically, the formula for calculating continuous wavelet transform is as follows:

[0048]

[0049] In the formula, f s This represents the input signal to be converted; here, we can substitute the first composite signal f. Let be the frequency after transformation, a be the scaling factor and a∈R, a>0, which represents frequency-related scaling, R be a real number, and τ be the translation factor and τ∈R; for The conjugate of complex numbers, For wavelet mother function, It is a wavelet basis function that depends on parameters a and τ, and is obtained by scaling and translating the wavelet.

[0050] After continuous wavelet transform, with time t as the abscissa and frequency as the ordinate... Using the vertical axis as the ordinate, we can obtain the two-dimensional image corresponding to the first composite signal, which is denoted here as the first time-frequency image.

[0051] This embodiment employs the continuous wavelet transform method to convert the one-dimensional chip test signal into a two-dimensional image. The continuous wavelet transform effectively fuses time and frequency information, providing a more comprehensive description of signal characteristics. This allows the time and frequency domain properties of the signal to be displayed in a single two-dimensional image, thereby facilitating more accurate capture and identification of specific patterns and anomalies in the signal during subsequent data processing and analysis.

[0052] Step 3: Input the first time-frequency image into the first CNN network to perform parallel fault detection of multiple chips; if no fault is found, the algorithm ends and the detection result is output; if a fault is found, proceed to step 4.

[0053] Specifically, in this embodiment, the first CNN network can also be simply referred to as the improved CNN-1. It is mainly obtained by training a pre-built improved convolutional neural network and is used to process the composite signals of multiple chips. By inputting the first time-frequency image obtained in step 2 into the improved CNN-1 network, parallel fault detection of multiple chips can be achieved.

[0054] Understandably, the improved CNN-1 network is a binary classification network designed to determine whether a composite signal is faulty. The network output indicates whether a fault exists among the multiple chips corresponding to the first composite signal. If the output shows no fault, it means that the detected chips are qualified. If the output shows a fault, further fault localization of individual chips is required, i.e., steps 4 and 5 below need to be performed.

[0055] Step 4: Convert the test signals of a single chip into two-dimensional images to obtain multiple second time-frequency images.

[0056] Specifically, the continuous wavelet transform method shown in formula (3) in step 2 can also be used here to convert the test signal of a single chip into a two-dimensional image, denoted as the second time-frequency image. Specifically, the test signal a corresponding to a single chip can be... i Substitute the input signals f to be converted into formula (3) respectively s This results in multiple second time-frequency images.

[0057] Step 5: Input multiple second time-frequency images into the second CNN network in sequence to perform fault detection on a single chip, and output the detection results.

[0058] Specifically, in this embodiment, the second CNN network can also be referred to as the improved CNN-2. It is also trained by a pre-built improved convolutional neural network. It is mainly used to further detect and locate the fault of a single chip when multiple chips are detected in parallel. Therefore, its processing object is the two-dimensional image corresponding to the test signal of a single chip, that is, the second time-frequency image.

[0059] By inputting the second time-frequency image obtained in step 4 into the improved CNN-2 network, fault detection of a single chip can be achieved.

[0060] Understandably, the improved CNN-2 network is a multi-classification network that can identify the fault category of a single chip. Its output results indicate that the chip corresponding to the input second time-frequency image has performance defects such as current, voltage, and frequency.

[0061] This embodiment can quickly and efficiently evaluate the electrical performance of the chip under test and detect any potential faults or anomalies by performing real-time parallel testing on the chip under test. Only when a fault is detected by composite signal is it necessary to perform further testing on the individual chip and output the specific fault type, which saves computing resources and improves the efficiency and accuracy of testing.

[0062] The training process of the first CNN network and the second CNN network will be described in detail below.

[0063] In this embodiment, both the first CNN network and the second CNN network are obtained by training an improved convolutional neural network. The training process mainly includes dataset construction, network model construction, and network training.

[0064] For details, please see Figure 3 , Figure 3 This is a schematic diagram of the network training process provided in an embodiment of the present invention, which can be implemented according to the following steps:

[0065] 1) Perform electrical performance tests on several chips and record different test signals for each chip; the different test signals include at least one of current, voltage, and frequency.

[0066] Specifically, each chip can be considered to have M test channels, each corresponding to a test item, such as current, voltage, or frequency. The chip's electrical performance is tested using hardware devices, such as probes or sensors. During the test, various signal characteristic data, such as voltage, current, and frequency, are collected and recorded. This data acquisition provides the foundation for subsequent processing and analysis, ensuring the accuracy and comprehensiveness of the detection. It should be noted that the data collected here is used to build a training dataset; therefore, data needs to be collected from a large number of chips with known fault types so that the trained network can measure different fault types.

[0067] Understandably, after acquiring test signals from different chips and of different types, normalization preprocessing is required. For specific processing methods, please refer to the minimum-maximum normalization method in step 1.

[0068] 2) Linearly superimpose and synthesize the same test signal according to a preset number to obtain multiple second composite signals of different test signals.

[0069] It should be noted that the preset number here refers to the number of chips that need to be processed in parallel. For example, if parallel processing of data from 8 chips is required, then the data needs to be linearly superimposed and synthesized in groups of 8. For instance, in this embodiment, current, voltage, and frequency signals from 800 chips were collected. For the current signals, linear superposition and synthesis in groups of 8 yields 100 composite signals. Similarly, 100 composite signals can be obtained for both voltage and frequency signals. These 300 composite signals are referred to as the second composite signal.

[0070] The specific linear superposition synthesis method can also adopt the calculation method shown in formula (2) in step 2, which will not be repeated here.

[0071] 3) Convert all the second composite signals into two-dimensional images and label them to obtain the first dataset.

[0072] Specifically, the continuous wavelet transform method shown in formula (3) in step 2 can be used to convert all the second composite signals into two-dimensional images, resulting in a two-dimensional image set of the composite signals, denoted as F = {F1, F2, ..., F...}. Q}; where Q represents the number of the second composite signals.

[0073] The above two-dimensional image set F is labeled to obtain the first dataset, denoted as D. F={(F1,y1),(F2,y2),…,(F Q ,y Q )}; where yi represents the label value of the second composite signal, and these label values ​​represent the fault category or other required classification information corresponding to the second composite signal.

[0074] 4) Convert the different test signals of different chips into two-dimensional images and label them to obtain the second dataset.

[0075] Specifically, the preprocessed test signals from different chips are converted into a two-dimensional image set using the continuous wavelet transform method in step 2, denoted as Z = {Z1, Z2, ..., Z...}. P}; where P represents the total number of all signals.

[0076] The above two-dimensional image set Z is labeled to obtain the second dataset, denoted as Dz={(Z1,h1),(Z2,h2),…,(Z P ,h P )};where h i The label values ​​represent individual chip signals, indicating the fault category or other required classification information corresponding to the individual chip test signal.

[0077] At this point, we have obtained two datasets.

[0078] Optionally, after obtaining the first and second datasets, the following may also be included:

[0079] Perform data augmentation operations on the first and second datasets.

[0080] Specifically, to avoid information distortion, this embodiment mainly uses rotation to augment data. Each two-dimensional image is expanded in multiples of 20 within the range of -2° to 2° to improve the generalization ability of the model and complete the expansion of the dataset. Finally, the image is adjusted to a size of 256×256.

[0081] This embodiment performs augmentation operations on the first and second datasets, which can both expand the size of the datasets and improve the generalization ability of the model.

[0082] 5) Train the pre-built convolutional neural network using the first dataset and the second dataset respectively to obtain the first CNN network and the second CNN network.

[0083] First, regarding the design of the specific structure of the convolutional neural network, this embodiment improves upon the traditional convolutional neural network to better enable the network model to learn and extract features from the input image. Specifically, because the training process of deep neural networks is very complex, although the data is normalized at the beginning, the distribution of the data inevitably changes with each layer of input and output. If this is not corrected, the differences in data distribution will further amplify with each subsequent layer, ultimately slowing down the training speed and affecting the model's accuracy. This embodiment uses batch normalization (BN) to avoid this phenomenon. Furthermore, in the training process of deep neural networks, dropout layers are typically used to avoid overfitting. Dropout layers proportionally set a portion of the neurons in the hidden layers to zero, thereby avoiding the extraction of duplicate features from too many neurons. This embodiment uses batch normalization and dropout to further improve the convergence speed and generalization ability of the model training.

[0084] For details, please see Figure 4 , Figure 4 This is a schematic diagram of the structure of the improved convolutional neural network provided in this embodiment of the invention. The improved convolutional neural network constructed in this embodiment includes five convolutional layers, five max-pooling layers, and three fully connected layers;

[0085] Five convolutional layers are connected in series, and each convolutional layer is followed by a batch normalization layer to correct the data after convolution.

[0086] The five max pooling layers are connected after the five batch normalization layers; the three fully connected layers are sequentially connected after the fifth max pooling layer. During the training phase, a certain proportion of neurons are randomly deactivated after the first two fully connected layers to avoid extracting duplicate features from too many neurons.

[0087] Furthermore, to help acquire more image feature information, an improved convolutional neural network was constructed. The first convolutional layer used 32 5×5 kernels, and the remaining four convolutional layers used 3×3 kernels, with 32, 64, 64, and 128 kernels respectively. A batch normalization layer was added after each convolution. The stride of each convolutional layer was set to 1, and zero-padding was used to ensure that the image size after each convolution was consistent with the size before convolution. To quickly reduce the input image size, the first max-pooling layer was 4×4, and the remaining four max-pooling layers were 2×2. Finally, the input 265×256 image size was transformed into a 4×4 image. After passing through three fully connected layers and two rounds of 50% random neuron deactivation, the corresponding fault category was output. The ReLU function was used as the activation function for all convolutional layers.

[0088] Batch normalization forcibly pulls the distribution of input values ​​of any neuron in each layer of the neural network back to a standard normal distribution with a mean of 0 and a variance of 1. Its calculation formula is as follows:

[0089]

[0090]

[0091]

[0092] In the formula, m is the batch size, μ B The average value of the batch processing. Let be the variance of the batch data. Then, the normalized data is scaled and translated, and its mathematical expression is: Here, γ and β are parameters. Initially, γ = 1 and β = 0, and then, through model training, these values ​​are adjusted to appropriate values.

[0093] Then, the improved convolutional neural network was trained using the first dataset and the second dataset respectively, resulting in CNN-1 network and CNN-2 network.

[0094] Furthermore, in this embodiment, during the training of the two networks, a stochastic gradient descent optimization algorithm is used to minimize the loss function; wherein, the loss function adopts the multi-class cross-entropy loss function to ensure that the model can accurately classify different fault or target categories.

[0095] Understandably, after training the first and second CNN networks, the following steps are also included:

[0096] The generalization capabilities of the first and second CNN networks were tested using multiple evaluation metrics to verify whether the model's performance met the requirements. If the performance did not meet the requirements, the hyperparameters were adjusted and training continued until the performance met the standards.

[0097] Understandably, the test set used for network testing and evaluation can come from both the first and second datasets. Generally, the first and second datasets are divided into training and test sets according to a certain ratio, with the training set used to train network parameters and the test set used to test network performance.

[0098] In this embodiment, the evaluation metrics may include classification error, accuracy of various defects, and F1 score.

[0099] The formula for calculating the classification error is as follows:

[0100]

[0101] Where N eThe number of samples that were not correctly classified is N, and the total number of samples is N.

[0102] The formulas for calculating the accuracy of various defects are as follows:

[0103]

[0104] Where N a N represents the number of samples that were correctly classified, and N represents the total number of samples.

[0105] The formula for calculating the F1 value is:

[0106]

[0107] Where P is precision and R is recall.

[0108] Once the test is passed, the trained network can be used to test the chip's electrical performance.

[0109] The parallel chip electrical performance detection method based on an improved convolutional neural network proposed in this invention fully utilizes deep learning and image processing technologies to transform the acquired chip test signals into two-dimensional image data, thereby capturing and describing the signal features more comprehensively and accurately, thus improving the accuracy of fault detection and reducing the false alarm rate. At the same time, two CNN networks are trained to process the two-dimensional image data, first performing parallel fault detection on multiple chips, and then performing fault localization on a single chip, realizing real-time parallel detection of multiple chips, improving the accuracy and efficiency of chip defect detection, and bringing new possibilities and application prospects to the electronic equipment manufacturing industry.

[0110] In addition, this method can reduce human intervention and human error, thus providing a more reliable and efficient means of quality assurance for semiconductor chip production.

[0111] Example 2

[0112] Based on Embodiment 1 above and using the same inventive concept, this embodiment provides a parallel detection device for chip electrical performance based on an improved convolutional neural network. Please refer to... Figure 5 , Figure 5 This is a structural block diagram of a parallel chip electrical performance detection device based on an improved convolutional neural network provided in an embodiment of the present invention, comprising:

[0113] The signal acquisition module is used to acquire test signals from multiple chips under test.

[0114] The first signal processing module is used to linearly superimpose and synthesize the test signals of multiple chips under test to generate a first composite signal, and convert the first composite signal into a two-dimensional image to obtain a first time-frequency image;

[0115] The first detection module includes a first CNN network for processing the first time-frequency image to achieve parallel fault detection of multiple chips, and outputs the detection result when the detection result is that no fault exists; wherein, the first CNN network is obtained by training a pre-built improved convolutional neural network;

[0116] The second signal processing module is used to convert the test signal of a single chip into a two-dimensional image when the detection result of the first detection module indicates that a fault exists, thereby obtaining multiple second time-frequency images.

[0117] The second detection module includes a second CNN network, which processes multiple second time-frequency images sequentially to achieve fault detection of a single chip and output the detection results; the second CNN network is also obtained by training a pre-built improved convolutional neural network.

[0118] The apparatus provided in this embodiment can implement the method provided in Embodiment 1 above, and the detailed process can be found in Embodiment 1 above. Therefore, this apparatus can also achieve real-time parallel detection of multiple chips, improving the accuracy and efficiency of chip defect detection, and bringing new possibilities and application prospects to the electronic equipment manufacturing industry.

[0119] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0120] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0121] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A parallel detection method for chip electrical performance based on an improved convolutional neural network, characterized in that, include: Step 1: Acquire test signals from multiple chips under test; Step 2: Linearly superimpose and synthesize the test signals of multiple chips under test to generate a first composite signal, and convert the first composite signal into a two-dimensional image to obtain a first time-frequency image; Step 3: Input the first time-frequency image into the first CNN network to perform parallel fault detection of multiple chips; if no fault is found, the algorithm ends and the detection result is output; If a fault exists, proceed to step 4; wherein the first CNN network is obtained by training a pre-built improved convolutional neural network; Step 4: Convert the test signals of a single chip into two-dimensional images, resulting in multiple second time-frequency images; Step 5: Input the multiple second time-frequency images into the second CNN network sequentially to perform fault detection on a single chip, and output the detection results; wherein, the second CNN network is also obtained by training a pre-built improved convolutional neural network; The first CNN network and the second CNN network are trained using the following method: Electrical performance tests are performed on several chips, and different test signals for each chip are recorded; wherein, the different test signals include at least one of current, voltage, and frequency; The same test signal is linearly superimposed and synthesized according to a preset number to obtain multiple second composite signals corresponding to different test signals; All the second composite signals are converted into two-dimensional images and labeled to obtain the first dataset; Different test signals from different chips are converted into two-dimensional images and labeled to obtain a second dataset; The pre-constructed improved convolutional neural network is trained using the first dataset and the second dataset respectively, resulting in the first CNN network and the second CNN network. The pre-built improved convolutional neural network includes five convolutional layers, five max pooling layers, and three fully connected layers. The five convolutional layers are connected in series, and each convolutional layer is followed by a batch normalization layer to correct the data after convolution. The five max pooling layers are connected after the five batch normalization layers; The three fully connected layers are sequentially connected after the fifth max pooling layer. During the training phase, a certain proportion of neurons are randomly deactivated after the first two fully connected layers to avoid extracting repetitive features from too many neurons.

2. The parallel detection method for chip electrical performance based on an improved convolutional neural network according to claim 1, characterized in that, In step 1, after acquiring the test signals from multiple chips under test, the following steps are also included: Normalization preprocessing is performed on the test signals of multiple chips under test.

3. The parallel detection method for chip electrical performance based on an improved convolutional neural network according to claim 1, characterized in that, In step 2, the calculation formula for linearly superimposing and synthesizing the test signals of multiple chips under test is as follows: ； In the formula, The first composite signal synthesized. For the test signal of a single chip, Indexed by the number of chips, and , This represents the total number of chips under test. For test signal The corresponding weights.

4. The parallel detection method for chip electrical performance based on an improved convolutional neural network according to claim 1, characterized in that, In step 2, the composite signal is converted into a two-dimensional image using the continuous wavelet transform method; Accordingly, in step 4, the test signals of a single chip are converted into two-dimensional images using the continuous wavelet transform method.

5. The parallel detection method for chip electrical performance based on an improved convolutional neural network according to claim 1, characterized in that, After obtaining the first and second datasets, the following is also included: Perform data augmentation operations on the first and second datasets.

6. The parallel detection method for chip electrical performance based on an improved convolutional neural network according to claim 1, characterized in that, The training process of the first CNN network and the second CNN network adopts the stochastic gradient descent optimization algorithm to minimize the loss function; wherein, the loss function adopts the multi-class cross-entropy loss function.

7. The parallel detection method for chip electrical performance based on an improved convolutional neural network according to claim 1, characterized in that, After training the first and second CNN networks, the process also includes: The generalization capabilities of the first CNN network and the second CNN network are tested based on multiple evaluation metrics, including classification error, accuracy of various defects, and F1 score.

8. A parallel detection device for chip electrical performance based on an improved convolutional neural network, characterized in that, The apparatus is used to implement the method of any one of claims 1 to 7, comprising: The signal acquisition module is used to acquire test signals from multiple chips under test. The first signal processing module is used to linearly superimpose and synthesize the test signals of multiple chips under test to generate a first composite signal, and convert the first composite signal into a two-dimensional image to obtain a first time-frequency image; The first detection module includes a first CNN network, which processes the first time-frequency image to achieve parallel fault detection of multiple chips, and outputs the detection result when the detection result is that no fault exists; wherein, the first CNN network is obtained by training a pre-built improved convolutional neural network; The second signal processing module is used to convert the test signal of a single chip into a two-dimensional image when the detection result of the first detection module indicates that a fault exists, thereby obtaining multiple second time-frequency images. The second detection module includes a second CNN network, which processes the plurality of second time-frequency images sequentially to achieve fault detection of a single chip and output the detection result; wherein, the second CNN network is also obtained by training the pre-built improved convolutional neural network.

Images