Display panel

Abstract

The application discloses a display panel, comprising a first display area and a second display area at least partially surrounding the first display area, the display panel further comprising a plurality of first pixel circuits and a plurality of second pixel circuits, the first pixel circuits being located in the first display area, and the second pixel circuits being located in the second display area, the first pixel circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor and at least two first light emitting devices; the control end of the third transistor is electrically connected with a reset signal control end, one of the source or drain of the third transistor is electrically connected with a first reset signal input end, and the other of the source or drain of the third transistor is electrically connected with a first node; the control end of the fourth transistor is electrically connected with the reset signal control end, one of the source or drain of the fourth transistor is electrically connected with the first reset signal input end, and the other of the source or drain of the fourth transistor is electrically connected with a third node.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and more specifically to a display panel. Background Technology

[0002] In full-screen display devices, in order to enable selfie and visual call functions, the camera is placed in the camera area of ​​the display panel. The existing display panel has the same pixel circuit structure in the display area and the camera area. That is, each pixel circuit in the display area controls one light-emitting device to work, and each pixel circuit in the camera area controls one light-emitting device to work.

[0003] To improve the transmittance of the camera area of ​​the display panel, each pixel circuit in the camera area controls two light-emitting devices. As the number of light-emitting devices controlled by each pixel circuit in the camera area increases, the wiring in the camera area becomes longer, resulting in an increase in the area of ​​the anode of the light-emitting devices. This reduces the transmittance of the camera area and thus affects the camera's image capture performance. Summary of the Invention

[0004] Embodiments of this application provide a display panel to improve the transmittance of the camera area of ​​the display panel.

[0005] In a first aspect, embodiments of this application provide a display panel, including a first display area and a second display area that at least partially surrounds the first display area. The display panel further includes a power supply voltage input terminal, a scan signal input terminal, a light emission control signal terminal, a data signal input terminal, a reset signal control terminal, a first reset signal input terminal, a second reset signal input terminal, a plurality of first pixel circuits, and a plurality of second pixel circuits. The first pixel circuits are located in the first display area, and the second pixel circuits are located in the second display area. The first pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and at least two first light-emitting devices.

[0006] The control terminal of the first transistor is electrically connected to the first node, one of the source or drain of the first transistor is electrically connected to the second node, the other of the source or drain of the first transistor is electrically connected to the third node, and the second node is electrically connected to the power supply voltage input terminal.

[0007] The control terminal of the second transistor is electrically connected to the scan signal input terminal, one of the source or drain of the second transistor is electrically connected to the data signal input terminal, and the other of the source or drain of the second transistor is electrically connected to the second node.

[0008] The control terminal of the third transistor is electrically connected to the reset signal control terminal, one of the source or drain of the third transistor is electrically connected to the first reset signal input terminal, and the other of the source or drain of the third transistor is electrically connected to the first node.

[0009] The control terminal of the fourth transistor is electrically connected to the reset signal control terminal, one of the source or drain of the fourth transistor is electrically connected to the first reset signal input terminal, and the other of the source or drain of the fourth transistor is electrically connected to the third node.

[0010] The anodes of the two first light-emitting devices are electrically connected to the third node.

[0011] Furthermore, the first pixel circuit also includes:

[0012] The fifth transistor has its control terminal electrically connected to the scan signal input terminal, one of its source or drain terminal electrically connected to the first node, and the other of its source or drain terminal electrically connected to the third node.

[0013] Furthermore, the first pixel circuit also includes:

[0014] The sixth transistor has its control terminal electrically connected to the light-emitting control signal terminal, one of the source or drain of the sixth transistor is electrically connected to the power supply voltage input terminal, and the other of the source or drain of the sixth transistor is electrically connected to the second node.

[0015] The seventh transistor has its control terminal electrically connected to the light-emitting control signal terminal, one of its source or drain terminals being electrically connected to the third node, and the other of its source or drain terminal being electrically connected to the anode of the first light-emitting device.

[0016] Furthermore, the first pixel circuit also includes a first capacitor, one end of which is electrically connected to the power supply voltage input terminal, and the other end of which is electrically connected to the first node.

[0017] Furthermore, the second pixel circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a second light-emitting device;

[0018] The control terminal of the eighth transistor is electrically connected to the fourth node, one of the source or drain of the eighth transistor is electrically connected to the fifth node, the other of the source or drain of the eighth transistor is electrically connected to the sixth node, and the fourth node is electrically connected to the power supply voltage input terminal.

[0019] The control terminal of the ninth transistor is electrically connected to the scan signal input terminal, one of the source or drain of the ninth transistor is electrically connected to the data signal input terminal, and the other of the source or drain of the ninth transistor is electrically connected to the fifth node.

[0020] The control terminal of the tenth transistor is electrically connected to the reset signal control terminal, one of the source or drain of the tenth transistor is electrically connected to the first reset signal input terminal, and the other of the source or drain of the tenth transistor is electrically connected to the fourth node.

[0021] The control terminal of the eleventh transistor is electrically connected to the reset signal control terminal, one of the source or drain of the eleventh transistor is electrically connected to the second reset signal input terminal, and the other of the source or drain of the eleventh transistor is electrically connected to the sixth node.

[0022] The anodes of the two second light-emitting devices are electrically connected to the sixth node;

[0023] The voltage signal at the first reset signal input terminal is different from the voltage signal at the second reset signal input terminal.

[0024] Furthermore, the second pixel circuit also includes:

[0025] The twelfth transistor has its control terminal electrically connected to the scan signal input terminal, one of its source or drain terminals electrically connected to the fourth node, and the other of its source or drain terminal electrically connected to the sixth node.

[0026] Furthermore, the first pixel circuit also includes:

[0027] The thirteenth transistor has its control terminal electrically connected to the light-emitting control signal terminal, one of the source or drain of the thirteenth transistor is electrically connected to the power supply voltage input terminal, and the other of the source or drain of the thirteenth transistor is electrically connected to the fifth node.

[0028] The fourteenth transistor has its control terminal electrically connected to the light-emitting control signal terminal, one of its source or drain terminals electrically connected to the sixth node, and the other of its source or drain terminal electrically connected to the anode of the second light-emitting device.

[0029] Furthermore, the first pixel circuit also includes a second capacitor, one end of which is electrically connected to the power supply voltage input terminal, and the other end of which is electrically connected to the fourth node.

[0030] Furthermore, the voltage at the first reset signal input terminal is greater than the voltage at the second reset signal input terminal.

[0031] Furthermore, both the third transistor and the tenth transistor are dual-gate transistors.

[0032] The beneficial effects of this application are:

[0033] This application provides a display panel, including a first display area and a second display area at least partially surrounding the first display area. The display panel further includes a power supply voltage input terminal, a scan signal input terminal, a light emission control signal terminal, a data signal input terminal, a reset signal control terminal, a first reset signal input terminal, a second reset signal input terminal, a plurality of first pixel circuits, and a plurality of second pixel circuits. The first pixel circuits are located in the first display area, and the second pixel circuits are located in the second display area. Each first pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and at least two first light-emitting devices. The control terminal of the first transistor is electrically connected to a first node, one of the source or drain of the first transistor is electrically connected to a second node, and the other of the source or drain of the first transistor is electrically connected to a third node. The second node is connected to the control terminal of the first pixel circuit. The source voltage input terminal is electrically connected; the control terminal of the second transistor is electrically connected to the scan signal input terminal, one of the source or drain of the second transistor is electrically connected to the data signal input terminal, and the other of the source or drain of the second transistor is electrically connected to the second node; the control terminal of the third transistor is electrically connected to the reset signal control terminal, one of the source or drain of the third transistor is electrically connected to the first reset signal input terminal, and the other of the source or drain of the third transistor is electrically connected to the first node; the control terminal of the fourth transistor is electrically connected to the reset signal control terminal, one of the source or drain of the fourth transistor is electrically connected to the first reset signal input terminal, and the other of the source or drain of the fourth transistor is electrically connected to the third node; the anodes of the two first light-emitting devices are electrically connected to the third node. By electrically connecting the control terminal of the third transistor to the reset signal control terminal, electrically connecting one of the source or drain of the third transistor to the first reset signal input terminal, and electrically connecting the other of the source or drain of the third transistor to the first node, electrically connecting the control terminal of the fourth transistor to the reset signal control terminal, electrically connecting one of the source or drain of the fourth transistor to the first reset signal input terminal, and electrically connecting the other of the source or drain of the fourth transistor to the third node, the first reset signal input terminal can simultaneously input signals to the third transistor and the fourth transistor, thereby reducing a set of signal traces located in the camera area of ​​the display panel, freeing up trace space in the camera area, increasing the light-transmitting area of ​​the camera area, and improving the transmittance of the camera area. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the display panel in this application;

[0035] Figure 2This is a schematic diagram showing the connection relationship between the first pixel circuit and the first light-emitting device in the first display area of ​​the display panel in this application;

[0036] Figure 3 This is a schematic diagram showing the connection relationship between the second pixel circuit and the second light-emitting device in the second display area of ​​the display panel in this application;

[0037] Figure 4 This is a schematic diagram of the first pixel circuit in this application;

[0038] Figure 5 This is a schematic diagram of the second pixel circuit in this application;

[0039] Figure 6 This is a timing diagram of the first pixel circuit or the second pixel circuit in this application. Detailed Implementation

[0040] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The technical solutions described below are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0041] Furthermore, the terms "first," "second," and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms "multiple" and similar words indicate two or more unless otherwise expressly specified.

[0042] To improve the transmittance of the camera area of ​​the display panel, each pixel circuit in the camera area controls two light-emitting devices. As the number of light-emitting devices controlled by each pixel circuit in the camera area increases, the wiring in the camera area becomes longer, resulting in an increase in the area of ​​the anode of the light-emitting devices. This reduces the transmittance of the camera area and thus affects the camera's image capture performance.

[0043] Embodiments of this application provide a display panel, see reference. Figures 1-4 The display panel includes a first display area A and a second display area B that at least partially surrounds the first display area A. The display panel also includes a power supply voltage input terminal VDD, a scan signal input terminal SCAN, a light emission control signal terminal EM, a data signal input terminal DATA, a reset signal control terminal RST, a first reset signal input terminal VI_GATE, a second reset signal input terminal VI_ANO, a plurality of first pixel circuits, and a plurality of second pixel circuits. The first pixel circuits are located in the first display area A, and the second pixel circuits are located in the second display area B. The first pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and at least two first light-emitting devices D1.

[0044] Specifically, the control terminal of the first transistor T1 is electrically connected to the first node Q1; one of the source or drain of the first transistor T1 is electrically connected to the second node Q2; the other of the source or drain of the first transistor T1 is electrically connected to the third node Q3; and the second node Q2 is electrically connected to the power supply voltage input terminal VDD. The control terminal of the second transistor T2 is electrically connected to the scan signal input terminal SCAN; one of the source or drain of the second transistor T2 is electrically connected to the data signal input terminal DATA; and the other of the source or drain of the second transistor T2 is electrically connected to the second node Q2. The third transistor T3... The control terminal is electrically connected to the reset signal control terminal RST. One of the sources or drains of the third transistor T3 is electrically connected to the first reset signal input terminal VI_GATE, and the other of the sources or drains of the third transistor T3 is electrically connected to the first node Q1. The control terminal of the fourth transistor T4 is electrically connected to the reset signal control terminal RST. One of the sources or drains of the fourth transistor T4 is electrically connected to the first reset signal input terminal VI_GATE, and the other of the sources or drains of the fourth transistor T4 is electrically connected to the third node Q3. The anodes of the two first light-emitting devices D1 are electrically connected to the third node Q3.

[0045] In this embodiment, the first transistor T1 is used to provide driving current to the first light-emitting device D1 under the control of the signals of the first node Q1 and the second node Q2. The second transistor T2 is used to write the signal of the data signal input terminal DATA to the second node Q2 under the control of the signal of the scan signal input terminal SCAN. The third transistor T3 is used to reset the control terminal of the first transistor T1 under the control of the signal of the reset signal control terminal RST. The fourth transistor T4 is used to reset the anode of the first light-emitting device D1 under the control of the signal of the reset signal control terminal RST.

[0046] By electrically connecting the control terminal of the third transistor T3 to the reset signal control terminal RST, and electrically connecting one of the sources or drains of the third transistor T3 to the first reset signal input terminal VI_GATE, and the other of the sources or drains of the third transistor T3 to the first node Q1, and electrically connecting the control terminal of the fourth transistor T4 to the reset signal control terminal RST, and electrically connecting one of the sources or drains of the fourth transistor T4 to the first reset signal input terminal VI_GATE, and the other of the sources or drains of the fourth transistor T4 to the third node Q3, a set of signal traces in the camera area is reduced, thereby freeing up trace space in the camera area, increasing the light-transmitting area of ​​the camera area, and improving the transmittance of the camera area of ​​the display panel.

[0047] In this embodiment, the first display area A is the camera area, and the second display area B is the area on the display panel other than the camera area.

[0048] In this embodiment, the first pixel circuit further includes a fifth transistor T5. The control terminal of the fifth transistor T5 is electrically connected to the scan signal input terminal SCAN. One of the source or drain of the fifth transistor T5 is electrically connected to the first node Q1, and the other of the source or drain of the fifth transistor T5 is electrically connected to the third node Q3. The fifth transistor T5 is used to compensate the threshold voltage of the first transistor T1 under the control of the signal at the scan signal input terminal SCAN.

[0049] In this embodiment, the first pixel circuit further includes a sixth transistor T6 and a seventh transistor T7. The control terminal of the sixth transistor T6 is electrically connected to the light emission control signal terminal EM. One of the sources or drains of the sixth transistor T6 is electrically connected to the power supply voltage input terminal VDD, and the other of the sources or drains of the sixth transistor T6 is electrically connected to the second node Q2. The control terminal of the seventh transistor T7 is electrically connected to the light emission control signal terminal EM. One of the sources or drains of the seventh transistor T7 is electrically connected to the third node Q3, and the other of the sources or drains of the seventh transistor T7 is electrically connected to the anode of the first light-emitting device D1.

[0050] In this embodiment, the sixth transistor T6 is used to form a path between the power supply voltage input terminal VDD and the second node Q2 under the control of the light emission control signal terminal EM; the seventh transistor T7 is used to form a path between the third node Q3 and the anode of the first light-emitting device D1 under the control of the light emission control signal terminal EM.

[0051] In this embodiment, the first pixel circuit further includes a first capacitor C1, one end of which is electrically connected to the power supply voltage input terminal VDD, and the other end of which is electrically connected to the first node Q1; wherein, the first capacitor C1 is configured to increase the voltage of the first node Q1 through coupling to ensure the potential stability of the first node Q1.

[0052] In this embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all P-type transistors.

[0053] In this embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all N-type transistors.

[0054] refer to Figure 4 and Figure 6During the initialization phase t1, the signals at the scan signal input terminal SCAN and the light emission control signal terminal EM are both high-level signals, while the signal at the reset signal control terminal RST is low-level. The third transistor T3 is turned on, thereby initializing the first capacitor C1 and clearing the original data voltage of the first capacitor C1. The first transistor T1 is turned off, and at the same time, the fourth transistor T4 is turned on, so that the initial voltage of the first reset signal input terminal VI_GATE is provided to the anode of the first light-emitting device D1, initializing the anode of the first light-emitting device D1, clearing the pre-stored voltage inside the first light-emitting device D1, and completing the initialization.

[0055] During the data writing phase t2, the signal at the scan signal input terminal SCAN is a low-level signal, while the signals at the light emission control signal terminal EM and the reset signal control terminal RST are both high-level signals. The data signal input terminal DATA outputs a data voltage. At this time, since the signal at the connection point between the first capacitor C1 and the first node Q1 is a low-level signal, the voltage signal at the first node Q1 is also a low-level signal. The first transistor T1 is turned on, and the low-level signal at the scan signal input terminal SCAN causes the second transistor T2 and the fifth transistor T5 to be turned on. The turning on of the first transistor T1 and the second transistor T2 allows the data voltage at the data signal input terminal DATA to be supplied to the first node Q1 through the second node Q2, the first transistor T1, the third node Q3, and the turned-on fifth transistor T5. The sum of the data voltage V1 output by the data signal input terminal DATA and the threshold voltage Vth of the first transistor T1 is charged into the first capacitor C1. The voltage of the first node Q1 is V1 + Vth, where V1 is the data voltage output by the data signal input terminal DATA, and Vth is the threshold voltage of the first transistor T1. The gate-source voltage difference of the first transistor T1 is Vgs = V1 + Vth - Vdd, where Vdd is the power supply voltage output from the power supply voltage input terminal VDD.

[0056] During the holding phase t3, the signals at the scan signal input terminal SCAN, the reset signal control terminal RST, and the light emission control signal terminal EM are all high-level signals. The second transistor T2, the third transistor T3, and the fourth transistor T4 are disconnected. The voltage of the first node Q1 remains unchanged at V1+Vth. The voltage of the anode of the first light-emitting device D1 remains unchanged, and the first light-emitting device D1 does not emit light.

[0057] During the light-emitting stage t4, the signal at the light-emitting control signal terminal EM is a low-level signal, while the signals at the scan signal input terminal SCAN and the reset signal control terminal RST are both high-level signals. The low-level signal at the light-emitting control signal terminal EM turns on the sixth transistor T6 and the seventh transistor T7. The power supply voltage output from the power supply voltage input terminal VDD provides a driving voltage to the anode of the first light-emitting device D1 through the turned-on sixth transistor T6, first transistor T1, and seventh transistor T7. The first light-emitting device D1 emits light as a driving current flows through it.

[0058] In this embodiment, the second pixel circuit includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a second light-emitting device D2; the control terminal of the eighth transistor T8 is electrically connected to the fourth node Q4, one of the source or drain of the eighth transistor T8 is electrically connected to the fifth node Q5, the other of the source or drain of the eighth transistor T8 is electrically connected to the sixth node Q6, and the fourth node Q4 is electrically connected to the power supply voltage input terminal VDD; the control terminal of the ninth transistor T9 is electrically connected to the scan signal input terminal SCAN, one of the source or drain of the ninth transistor T9 is electrically connected to the data signal input terminal DATA, and the other of the source or drain of the ninth transistor T9 is electrically connected to the fifth node Q5; the tenth transistor T10... The control terminal is electrically connected to the reset signal control terminal RST. One of the sources or drains of the tenth transistor T10 is electrically connected to the first reset signal input terminal VI_GATE, and the other of the sources or drains of the tenth transistor T10 is electrically connected to the fourth node Q4. The control terminal of the eleventh transistor T11 is electrically connected to the reset signal control terminal RST. One of the sources or drains of the eleventh transistor T11 is electrically connected to the second reset signal input terminal VI_ANO, and the other of the sources or drains of the eleventh transistor T11 is electrically connected to the sixth node Q6. The anodes of the two second light-emitting devices D2 are electrically connected to the sixth node Q6. The voltage signal of the first reset signal input terminal VI_GATE is different from the voltage signal of the second reset signal input terminal VI_ANO.

[0059] In this embodiment, the eighth transistor T8 is used to provide driving current to the second light-emitting device D2 under the control of the signals of the fourth node Q4 and the fifth node Q5. The ninth transistor T9 is used to write the signal of the data signal input terminal DATA to the fifth node Q5 under the control of the signal of the scan signal input terminal SCAN. The tenth transistor T10 is used to reset the control terminal of the eighth transistor T8 under the control of the signal of the reset signal control terminal RST. The eleventh transistor T11 is used to reset the anode of the second light-emitting device D2 under the control of the signal of the reset signal control terminal RST.

[0060] In this embodiment, the second pixel circuit further includes a twelfth transistor T12. The control terminal of the twelfth transistor T12 is electrically connected to the scan signal input terminal SCAN. One of the source or drain of the twelfth transistor T12 is electrically connected to the fourth node Q4, and the other of the source or drain of the twelfth transistor T12 is electrically connected to the sixth node Q6. The twelfth transistor T12 is used to compensate the threshold voltage of the eighth transistor T8 under the control of the signal at the scan signal input terminal SCAN.

[0061] In this embodiment, the first pixel circuit further includes a thirteenth transistor T13 and a fourteenth transistor T14. The control terminal of the thirteenth transistor T13 is electrically connected to the light emission control signal terminal EM. One of the sources or drains of the thirteenth transistor T13 is electrically connected to the power supply voltage input terminal VDD, and the other of the sources or drains of the thirteenth transistor T13 is electrically connected to the fifth node Q5. The control terminal of the fourteenth transistor T14 is electrically connected to the light emission control signal terminal EM. One of the sources or drains of the fourteenth transistor T14 is electrically connected to the sixth node Q6, and the other of the sources or drains of the fourteenth transistor T14 is electrically connected to the anode of the second light-emitting device D2. The thirteenth transistor T13 is used to form a path between the power supply voltage input terminal VDD and the fifth node Q5 under the control of the signal from the light emission control signal terminal EM. The fourteenth transistor T14 is used to form a path between the sixth node Q6 and the anode of the second light-emitting device D2 under the control of the signal from the light emission control signal terminal EM.

[0062] In this embodiment, the first pixel circuit further includes a second capacitor C2. One end of the second capacitor C2 is electrically connected to the power supply voltage input terminal VDD, and the other end of the second capacitor C2 is electrically connected to the fourth node Q4. The second capacitor C2 is configured to increase the voltage of the first node Q1 through coupling to ensure the potential stability of the first node Q1.

[0063] In this embodiment, the voltage of the first reset signal input terminal VI_GATE is greater than the voltage of the second reset signal input terminal VI_ANO. By setting the voltage of the first reset signal input terminal VI_GATE to be greater than the voltage of the second reset signal input terminal VI_ANO, the first light-emitting device D1 in the camera area can light up faster, thereby improving the problem of uneven brightness at low gray levels in the camera area.

[0064] In this embodiment, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are all P-type transistors.

[0065] In this embodiment, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are all N-type transistors.

[0066] In this embodiment, the third transistor T3 is a dual-gate transistor. By setting the third transistor T3 to a dual-gate transistor, leakage current in the first node Q1 can be prevented.

[0067] Specifically, the first and second control terminals of the third transistor T3 are both electrically connected to the reset signal control terminal RST.

[0068] In this embodiment, the fifth transistor T5 is a dual-gate transistor. By setting the fifth transistor T5 to a dual-gate transistor, leakage current in the first node Q1 can be prevented.

[0069] Specifically, the first and second control terminals of the fifth transistor T5 are both electrically connected to the scan signal input terminal SCAN.

[0070] In this embodiment, the tenth transistor T10 is a dual-gate transistor. By setting the tenth transistor T10 to a dual-gate transistor, leakage current at the fourth node Q4 can be prevented.

[0071] Specifically, the first and second control terminals of the tenth transistor T10 are both electrically connected to the reset signal control terminal RST.

[0072] In this embodiment, the twelfth transistor T12 is a dual-gate transistor. By setting the twelfth transistor T12 to a dual-gate transistor, leakage current at the fourth node Q4 can be prevented.

[0073] Specifically, the first and second control terminals of the twelfth transistor T12 are both electrically connected to the scan signal input terminal SCAN.

[0074] refer to Figure 5 and Figure 6 During the initialization phase t1, the signals at the scan signal input terminal SCAN and the light emission control signal terminal EM are both high-level signals, while the signal at the reset signal control terminal RST is low-level. The tenth transistor T10 is turned on, thereby initializing the second capacitor C2 and clearing the original data voltage of the second capacitor C2. The eighth transistor T8 is turned off, and at the same time, the eleventh transistor T11 is turned on, so that the initial voltage of the first reset signal input terminal VI_GATE is provided to the anode of the second light-emitting device D2, initializing the anode of the second light-emitting device D2, clearing the pre-stored voltage inside the second light-emitting device D2, and completing the initialization.

[0075] During the data writing phase t2, the signal at the scan signal input terminal SCAN is low, while the signals at the light emission control signal terminal EM and the reset signal control terminal RST are both high. The data signal input terminal DATA outputs a data voltage. At this time, since the signal at the connection point between the second capacitor C2 and the fourth node Q4 is low, the voltage signal at the fourth node Q4 is also low. The eighth transistor T8 is turned on. The low signal at the scan signal input terminal SCAN turns on the ninth transistor T9 and the twelfth transistor T12. The turn-on of the eighth transistor T8 and the ninth transistor T9 allows the data voltage at the data signal input terminal DATA to be supplied to the fourth node Q4 through the fifth node Q5, the eighth transistor T8, the sixth node Q6, and the turned-on twelfth transistor T12. The sum of the data voltage V1 output by the data signal input terminal DATA and the threshold voltage Vth of the eighth transistor T8 is charged into the second capacitor C2. The voltage at the fourth node Q4 is V1 + Vth, where V1 is the data voltage output by the data signal input terminal DATA and Vth is the threshold voltage of the eighth transistor T8. The gate-source voltage difference of the eighth transistor T8 is Vgs = V1 + Vth - Vdd, where Vdd is the power supply voltage output from the power supply voltage input terminal VDD.

[0076] During the holding phase t3, the signals at the scan signal input terminal SCAN, the reset signal control terminal RST, and the light emission control signal terminal EM are all high-level signals. The ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are disconnected. The voltage of the fourth node Q4 remains unchanged at V1+Vth. The voltage of the anode of the second light-emitting device D2 remains unchanged, and the second light-emitting device D2 does not emit light.

[0077] During the light-emitting stage t4, the signal at the light-emitting control signal terminal EM is a low-level signal, while the signals at the scan signal input terminal SCAN and the reset signal control terminal RST are both high-level signals. The low-level signal at the light-emitting control signal terminal EM turns on the thirteenth transistor T13 and the fourteenth transistor T14. The power supply voltage output from the power supply voltage input terminal VDD provides a driving voltage to the anode of the second light-emitting device D2 through the turned-on thirteenth transistor T13, eighth transistor T8, and fourteenth transistor T14. The second light-emitting device D2 emits light as a driving current flows through it.

[0078] The specific embodiments of this application have been described in detail above. The embodiments disclosed above are merely preferred embodiments of this application. Those skilled in the art can make many modifications and improvements without departing from the concept of this application. All such modifications and improvements fall within the scope of protection defined by the claims of this application.

Claims

1. A display panel, characterized in that, The display panel includes a first display area and a second display area that at least partially surrounds the first display area. The display panel also includes a power supply voltage input terminal, a scan signal input terminal, a light emission control signal terminal, a data signal input terminal, a reset signal control terminal, a first reset signal input terminal, a second reset signal input terminal, a plurality of first pixel circuits, and a plurality of second pixel circuits. The first pixel circuits are located in the first display area, and the second pixel circuits are located in the second display area. The first pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and at least two first light-emitting devices. The control terminal of the first transistor is electrically connected to the first node, one of the source or drain of the first transistor is electrically connected to the second node, the other of the source or drain of the first transistor is electrically connected to the third node, and the second node is electrically connected to the power supply voltage input terminal. The control terminal of the second transistor is electrically connected to the scan signal input terminal, one of the source or drain of the second transistor is electrically connected to the data signal input terminal, and the other of the source or drain of the second transistor is electrically connected to the second node. The control terminal of the third transistor is electrically connected to the reset signal control terminal, one of the source or drain of the third transistor is electrically connected to the first reset signal input terminal, and the other of the source or drain of the third transistor is electrically connected to the first node. The control terminal of the fourth transistor is electrically connected to the reset signal control terminal, one of the source or drain of the fourth transistor is electrically connected to the first reset signal input terminal, and the other of the source or drain of the fourth transistor is electrically connected to the third node. The anodes of the two first light-emitting devices are electrically connected to the third node; The second pixel circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a second light-emitting device. The control terminal of the tenth transistor is electrically connected to the reset signal control terminal. One of the source or drain of the tenth transistor is electrically connected to the first reset signal input terminal. The control terminal of the eleventh transistor is electrically connected to the reset signal control terminal. One of the source or drain of the eleventh transistor is electrically connected to the second reset signal input terminal. The voltage signal at the first reset signal input terminal is different from the voltage signal at the second reset signal input terminal. Both the third transistor and the tenth transistor are dual-gate transistors.

2. The display panel according to claim 1, characterized in that, The first pixel circuit also includes: The fifth transistor has its control terminal electrically connected to the scan signal input terminal, one of its source or drain terminal electrically connected to the first node, and the other of its source or drain terminal electrically connected to the third node.

3. The display panel according to claim 2, characterized in that, The first pixel circuit also includes: The sixth transistor has its control terminal electrically connected to the light-emitting control signal terminal, one of the source or drain of the sixth transistor is electrically connected to the power supply voltage input terminal, and the other of the source or drain of the sixth transistor is electrically connected to the second node. The seventh transistor has its control terminal electrically connected to the light-emitting control signal terminal, one of its source or drain terminals being electrically connected to the third node, and the other of its source or drain terminal being electrically connected to the anode of the first light-emitting device.

4. The display panel according to claim 2, characterized in that, The first pixel circuit also includes a first capacitor, one end of which is electrically connected to the power supply voltage input terminal, and the other end of which is electrically connected to the first node.

5. The display panel according to any one of claims 1-4, characterized in that, The control terminal of the eighth transistor is electrically connected to the fourth node, one of the source or drain of the eighth transistor is electrically connected to the fifth node, the other of the source or drain of the eighth transistor is electrically connected to the sixth node, and the fourth node is electrically connected to the power supply voltage input terminal. The control terminal of the ninth transistor is electrically connected to the scan signal input terminal, one of the source or drain of the ninth transistor is electrically connected to the data signal input terminal, and the other of the source or drain of the ninth transistor is electrically connected to the fifth node. The other of the source or drain of the tenth transistor is electrically connected to the fourth node; The other of the source or drain of the eleventh transistor is electrically connected to the sixth node; The anodes of the two second light-emitting devices are electrically connected to the sixth node.

6. The display panel according to claim 5, characterized in that, The second pixel circuit also includes: The twelfth transistor has its control terminal electrically connected to the scan signal input terminal, one of its source or drain terminals electrically connected to the fourth node, and the other of its source or drain terminal electrically connected to the sixth node.

7. The display panel according to claim 6, characterized in that, The first pixel circuit also includes: The thirteenth transistor has its control terminal electrically connected to the light-emitting control signal terminal, one of the source or drain of the thirteenth transistor is electrically connected to the power supply voltage input terminal, and the other of the source or drain of the thirteenth transistor is electrically connected to the fifth node. The fourteenth transistor has its control terminal electrically connected to the light-emitting control signal terminal, one of its source or drain terminals electrically connected to the sixth node, and the other of its source or drain terminal electrically connected to the anode of the second light-emitting device.

8. The display panel according to claim 6, characterized in that, The first pixel circuit also includes a second capacitor, one end of which is electrically connected to the power supply voltage input terminal, and the other end of which is electrically connected to the fourth node.

9. The display panel according to claim 5, characterized in that, The voltage at the first reset signal input terminal is greater than the voltage at the second reset signal input terminal.

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