Single bit line SRAM pixel and method of driving the same

Abstract

A novel bit storage circuit includes a first voltage supply line, a second voltage supply line, a bit line, a latch, a first switch transistor, and a blocking transistor. The latch includes an input and an output. The first switch transistor includes a first terminal, a second terminal, and a control terminal. The first switch transistor is operable to provide a conductive path and a non-conductive path between the bit line and the input of the latch in response to a first control signal asserted on the control terminal of the first switch transistor. The blocking transistor includes a control terminal and is operable to selectively provide a conductive path and a non-conductive path between the input of the latch and the second voltage supply line in response to a second control signal. The blocking transistor facilitates use of a single bit line.

Description

Technical Field

[0001] This invention relates generally to digital displays, and more specifically to pixel circuits of digital displays. Background Technology

[0002] As digital displays (e.g., liquid crystal displays on silicon, miniature light-emitting diode displays, etc.) are incorporated into more and more devices, there is a constant need to improve their performance. A typical digital display includes a driver circuit that is electrically connected to an m×n pixel array arranged in m columns and n rows. Each row of pixels is electrically connected to a corresponding row select line, and each column of pixels is electrically connected to a corresponding set of data lines. Each set of data lines typically includes a bit line and an inverted bit line. When writing a data bit to a single pixel circuit, the bit value is asserted on the bit line, and its reciprocal is asserted on the inverted bit line. In other words, writing a single data bit to a pixel circuit requires asserting two different bit values ​​on two corresponding different signal lines.

[0003] Driving the array of pixel circuits consumes a significant amount of power by driving the bit lines. This high power consumption significantly degrades the overall performance of a digital display. For example, the high power consumption of a display device rapidly depletes the host device's battery, thus limiting the types of host devices the display can be integrated into. High power consumption also leads to heat dissipation issues, imposing substantial design constraints on display devices.

[0004] Attempts have been made to mitigate the power consumption challenges in pixel array circuitry by designing more complex pixel circuits. However, these more complex designs are extremely difficult to implement, and often impossible, due to the very small size constraints of individual pixels. Summary of the Invention

[0005] This invention overcomes the problems associated with the prior art by providing a seven-transistor circuit mounted in an array with a pitch of no more than 3 μm. Four of the transistors are used as latches. One of the transistors facilitates selective access or retention of a single transistor in a given enable sequence. Another transistor uses only a single bit line to block current to facilitate transitions between digital values ​​in the latch.

[0006] An example bit storage circuit includes a first voltage supply line, a second voltage supply line, a bit line, a latch, a first switching transistor, and a blocking transistor. The latch has an input and an output. The first switching transistor has a first terminal, a second terminal, and a control terminal. In response to a first control signal asserted on the control terminal of the first switching transistor, the first switching transistor is operable to selectively provide a conductive path and a non-conductive path between the bit line and the input of the latch. The blocking transistor includes a control terminal and is operable to selectively provide a conductive path and a non-conductive path between the input of the latch and the second voltage supply line in response to a second control signal.

[0007] The example bit storage circuit may additionally include a second switching transistor having a first terminal, a second terminal, and a control terminal. In response to a third control signal asserted on the control terminal of the second switching transistor, the second switching transistor can selectively provide a conductive path and a non-conductive path between the bit line and the input of the latch. The first and second switching transistors may be coupled in series between the bit line and the input of the latch.

[0008] In an example bit storage circuit, a latch may include a first p-channel transistor, a first n-channel transistor, a second p-channel transistor, and a second n-channel transistor. The first p-channel transistor has a source terminal coupled to a first voltage supply line, a drain terminal coupled to the output of the latch, and a gate terminal coupled to the input of the latch. The first n-channel transistor has a source terminal coupled to a second voltage supply line, a drain terminal coupled to the output of the latch, and a gate terminal coupled to the input of the latch. The second p-channel transistor has a source terminal coupled to the first voltage supply line, a drain terminal coupled to the input of the latch, and a gate terminal coupled to the output of the latch. The second n-channel transistor has a source terminal coupled to the second voltage supply line, a drain terminal selectively coupled to the input of the latch via a blocking transistor, and a gate terminal coupled to the output of the latch. Alternatively, the second n-channel transistor may have its source terminal selectively coupled to the second voltage supply line via a blocking transistor, its drain terminal coupled to the input of the latch, and its gate terminal coupled to the output of the latch.

[0009] Example bit storage circuitry can be used in display devices. For instance, the bit storage circuitry may additionally include pixel electrodes coupled to the output of a latch. The pixel electrodes may be reflective pixel mirrors in a liquid crystal on silicon (LCoS) device.

[0010] The example bit storage circuit may include no more than seven transistors. Additionally, in the example system, the bit storage circuit may operate with a single bit line and be connected to no more than one bit line.

[0011] The example bit storage circuit may additionally include a pulse generator having an output coupled to a control terminal of a blocking transistor. The pulse generator may be included, for example, in a row address decoder, and the generated pulse may be coordinated with a row enable signal generated by the row address decoder. Alternatively, the control terminal of the blocking transistor may be coupled to a third voltage supply line having a constant voltage between the voltage of the first voltage supply line and the voltage of the second voltage supply line. In this case, the second control signal may be a constant voltage, and the blocking transistor may thus remain in a partially conductive state.

[0012] Example methods are also disclosed. One method for writing data bits to a pixel of a display includes asserting the data bit on a bit line of an input to a latch of the pixel, and asserting a first control signal on the gate of a first transistor of the pixel. In response to the first control signal, the first transistor at least partially disables a second transistor of the pixel to prevent it from affecting the voltage on the input of the latch. The example method further includes asserting an enable signal on a third transistor of the pixel to selectively couple the input of the latch to the bit line, and then changing the first control signal to re-enable the second transistor of the pixel to affect the voltage on the input of the latch. This example method further includes asserting a disable signal on the third transistor to selectively decouple the bit line from the input of the latch.

[0013] The example method may additionally include asserting a second enable signal on a fourth transistor of the pixel, and asserting a second disable signal on the fourth transistor of the pixel. Asserting the enable signal on the third transistor and asserting the second enable signal on the fourth transistor causes the third and fourth transistors to electrically couple the bit line to the input of the latch. Asserting the enable signal on the third transistor and the second disable signal on the fourth transistor isolates the bit line from the input of the latch. Asserting the disable signal on the third transistor and the second enable signal on the fourth transistor isolates the bit line from the input of the latch.

[0014] An example display includes a first voltage supply line, a second voltage supply line, an array of pixel electrodes arranged in columns and rows, a plurality of power lines, a plurality of blocking signal lines, a plurality of bit lines, and an array of pixel circuits arranged in columns and rows. Each pixel circuit may include a latch, a first switching transistor, and a blocking transistor. The latch has an input coupled to one of the bit lines and an output coupled to one of the pixel electrodes. The first switching transistor has a control terminal coupled to one of the power lines. The first switching transistor is operable to provide a conductive path and a non-conductive path between the bit line and the input of the latch in response to an assertion of a first control signal on the power line. The blocking transistor includes a control terminal coupled to one of the blocking signal lines and is operable to selectively provide a conductive path and a non-conductive path between the input of the latch and the second voltage supply line in response to a second control signal asserted on the coupled blocking signal line.

[0015] The example display may additionally include multiple column enable lines. Each pixel includes a second switching transistor having a control terminal coupled to one of the column enable lines. The second switching transistor is operable to selectively provide a conductive and non-conductive path between the bit line and the input of the latch in response to an assertion of a third control signal on the coupled column enable line. The first and second switching transistors are coupled in series between the bit line and the input of the latch.

[0016] In the example display, each of the latches includes a first p-channel transistor, a first n-channel transistor, a second p-channel transistor, and a second n-channel transistor. The first p-channel transistor has a source terminal coupled to a first voltage supply line, a drain terminal coupled to the output of the latch, and a gate terminal coupled to the input of the latch. The first n-channel transistor has a source terminal coupled to a second voltage supply line, a drain terminal coupled to the output of the latch, and a gate terminal coupled to the input of the latch. The second p-channel transistor has a source terminal coupled to the first voltage supply line, a drain terminal coupled to the input of the latch, and a gate terminal coupled to the output of the latch. The second n-channel transistor has a source terminal coupled to a second voltage supply line, a drain terminal selectively coupled to the input of the latch via a blocking transistor, and a gate terminal coupled to the output of the latch. Alternatively, the second n-channel transistor may have a source terminal selectively coupled to a second voltage supply line via a blocking transistor, a drain terminal coupled to the input of the latch, and a gate terminal coupled to the output of the latch.

[0017] In the example display, each pixel circuit includes no more than seven transistors. In a particular embodiment, the example pixel circuit includes exactly seven transistors. In the example display, each pixel circuit is coupled to no more than one bit line in the bit lines. More specifically, each pixel circuit is coupled to exactly one bit line in the bit lines.

[0018] An example array of bit memory circuits formed in and on a p-type semiconductor substrate is also disclosed. Each bit memory circuit includes at least one n-well formed in the p-type substrate, a first p-type doped region formed in the at least one n-well, a second p-type doped region formed in the at least one n-well, and a third p-type doped region formed in the at least one n-well. Each bit memory circuit further includes a first n-type doped region formed in the p-type substrate, a second n-type doped region formed in the p-type substrate, a third n-type doped region formed in the p-type substrate, a fourth n-type doped region formed in the p-type substrate, a fifth n-type doped region formed in the p-type substrate, a sixth n-type doped region formed in the p-type substrate, and a seventh n-type doped region formed in the p-type substrate.

[0019] Each bit memory circuit further includes a first polysilicon gate, a second polysilicon gate, a third polysilicon gate, a fourth polysilicon gate, a fifth polysilicon gate, a sixth polysilicon gate, and a seventh polysilicon gate. The first polysilicon gate is formed above a first region of a p-type substrate disposed between a first n-type doped region and a second n-type doped region. The second polysilicon gate is formed above a second region of a p-type substrate disposed between a second n-type doped region and a third n-type doped region. The third polysilicon gate is formed above a third region of a p-type substrate disposed between a third n-type doped region and a fourth n-type doped region. The fourth polysilicon gate is formed above a fourth region of a p-type substrate disposed between a fourth n-type doped region and a fifth n-type doped region. The fifth polysilicon gate is formed above a first region of at least one n-well disposed between a first p-type doped region and a second p-type doped region. The sixth polysilicon gate is formed above a second region of at least one n-well disposed between a second p-type doped region and a third p-type doped region. The seventh polysilicon gate is formed above a fifth region of a p-type substrate disposed between a sixth n-type doped region and a seventh n-type doped region.

[0020] An example array of bit memory cells further includes one or more conductive layers formed over a substrate and a polysilicon gate. The one or more conductive layers include multiple conductive paths providing interconnections between components of the bit memory cells. A first conductive path electrically couples a first n-type doped region to a bit line of the array. A second conductive path electrically couples a first polysilicon gate to a first control line of the array. A third conductive path electrically couples a second polysilicon gate to a second control line of the array. A fourth conductive path electrically couples a third polysilicon gate to a third control line of the array. A fifth conductive path electrically couples a third n-type doped region, a first p-type doped region, a sixth polysilicon gate, and a seventh polysilicon gate. A sixth conductive path electrically couples a fourth polysilicon gate, a fifth polysilicon gate, a first p-type doped region, and a sixth n-type doped region. A seventh conductive path electrically couples a second p-type doped region to a first voltage supply line of the array. An eighth conductive path electrically couples a fifth n-type doped region and a seventh n-type doped region to a second voltage supply line of the array. The second voltage supply line provides a lower voltage than the first voltage supply line. The array has a spacing of no more than 3 μm.

[0021] In an example array of bit-based storage circuitry, the first control line of the array can be an enable line. The second control line of the array can be a column enable line, and a sixth conductive path is electrically coupled to a pixel mirror.

[0022] In a specific example array of in-bit storage circuits, the region of each of the first n-type doped region, the second n-type doped region, and the third n-type doped region is larger than the region of the largest of the fourth n-type doped region, the fifth n-type doped region, the sixth n-type doped region, and the seventh n-type doped region. Attached Figure Description

[0023] The invention is described with reference to the following figures, wherein the same reference numerals denote substantially similar elements:

[0024] Figure 1 It is a perspective view of a pair of glasses, including a digital display system;

[0025] Figure 2 It is shown Figure 1 A block diagram of the components of a digital display system;

[0026] Figure 3 yes Figure 2 A cross-sectional side view of a digital display;

[0027] Figure 4 It is shown Figure 2 A diagram showing additional details of the pixel array;

[0028] Figure 5 yes Figure 4 Amplifier circuit diagram of a single bit line regulator circuit;

[0029] Figure 6 yes Figure 4 A circuit diagram of an example pixel in a pixel array;

[0030] Figure 7 It is shown Figure 6 Example timing diagram of the pixel driver;

[0031] Figure 8 It is shown Figure 6 Another example timing diagram of the pixel drive;

[0032] Figure 9A It shows Figure 6 The physical layout of the n-type and p-type doped regions of the pixels on a p-type silicon substrate;

[0033] Figure 9B It shows Figure 6 The physical layout of the polysilicon gate regions of the pixels; and

[0034] Figure 9C It shows Figure 6 Conductive interconnections between different areas of the pixel. Detailed Implementation

[0035] This invention overcomes the problems associated with the prior art by providing a pixel mirror driving circuit that can be driven by a single bit line, facilitating the reading and writing of individual pixels, and / or retaining data with or without a valid word line signal. In the following description, numerous specific details (e.g., transistor types, specific voltages, specific display types, etc.) are set forth in order to provide a thorough understanding of the invention. However, those skilled in the art will recognize that the invention can be practiced separately from these specific details. In other instances, details of well-known digital display manufacturing practices and components have been omitted so as not to unnecessarily obscure the invention.

[0036] Figure 1A digital display system 100 integrated into a hosting device is shown, depicted by way of non-limiting example as a pair of glasses 102. More specifically, the display system 100 is incorporated into a projector system fixed inside the arm 104 of the glasses 102 to project images directly onto the lens 106 of the glasses 102. In this example, the display system 100 is a liquid crystal on silicon (LCOS) display. Although the display system 100 is depicted as an LCOS display, the invention can also be used in conjunction with other types of digital displays, such as miniature light-emitting diode (μLED) displays. In fact, aspects of this pixel circuitry can be advantageously incorporated into memory circuitry independent of the pixels driving the display. Furthermore, the glasses 102 are intended to illustrate an example environment. However, the display and pixel circuitry disclosed herein can be used in any display environment.

[0037] Figure 2 This is a block diagram showing example components of a digital display system 100 in more detail. The display system 100 includes a controller 200, a timing generator 202, a first frame buffer 204, a second frame buffer 206, a data buffer 208, a bit line adjuster 210, a row decoder 212, a column decoder 214, and a pixel array 216.

[0038] Controller 200 is coupled to receive timing signals from timing generator 202 and is configured to use these timing signals to coordinate the transmission of video data to frame buffers 204 and 206, and is configured to drive the pixels of pixel array 216 to display an image corresponding to the video data. For example, the controller can “set” (e.g., turn on) and “reset” (e.g., turn off) each pixel of the display such that each pixel is turned on for a portion of a predefined frame time. The specific amount of on-time is based on the value of the corresponding multi-bit intensity value stored in frame buffer 204 or 206.

[0039] The first frame buffer 204 and the second frame buffer 206 are each configured to receive entire frames of video data and are used alternately by the controller 200. When a frame of video data from the first frame buffer 204 is used to determine the signal asserted on the pixel array 216, subsequent frames of video data are loaded into the second frame buffer 206. Then, when the controller 200 uses video data frames from the second frame buffer 206 to determine the signal asserted on the pixel array 216, the next video data frame is loaded into the first frame buffer 204, and so on.

[0040] Pixel array 216 is an (m) x (n) array of individual pixels, where (m) is the number of columns and (n) is the number of rows. Pixel array 216 displays video (e.g., a series of fast images) by turning on individual pixels within predetermined portions of a frame time corresponding to a specific desired intensity. Individual pixels are turned on and off by data bits latched onto bit line 218 by bit line modulator 210. Pixels are enabled to latch onto the data bits latched onto bit line 218 by a row enable signal from row decoder 212 and a column enable signal from column decoder 214. (See reference...) Figure 3-7 A more detailed description of the pixel array 216.

[0041] Data buffer 208 is configured to receive lines of data bits, in this example, with the data bit lines turned on and off for individual pixels of pixel array 216. Bit line adjuster 210 is configured to receive data bits from data buffer 208 in a low-power electrical state via data line 219 and assert a stronger signal onto bit line 218 of pixel array 216 based on the value of the original data bit. Reference will be made below. Figure 4 and Figure 5 The internal circuitry and operation of the bit line modulator 210 and the pixel array 216 will be discussed in more detail.

[0042] Row decoder 212 and column decoder 214, in response to address and control signals from controller 200, enable pixels in pixel array 216 to latch data bits asserted on bit lines by data buffer 208 and bit line adjuster 210. For a particular pixel to be enabled, it must be enabled by both column decoder 214 and row decoder 212.

[0043] The line decoder 212 is coupled between the controller 200 and the pixel array 216 and is configured to selectively assert enable signals onto word lines 220 connected to the respective pixel rows of the pixel array 216. The enable signal enables each pixel in the enabled row to load data bits asserted by the data buffer 208 on the corresponding bit line 218. More specifically, the line decoder 212 receives a series of row addresses from the controller 200 and sequentially asserts enable signals on the corresponding word lines for each received row address.

[0044] Column decoder 214 is coupled between controller 200 and pixel array 216 and is configured to selectively assert column enable signals onto individual pixel column lines 222 of pixel array 216 in response to control signals from controller 200. While row decoder 212 typically asserts enable signals on one word line 220 at a time, column decoder 214 can assert enable signals on some, all, or none of the column enable lines 222 simultaneously. Not asserting a column enable signal on a particular pixel column line 222 allows the associated pixels of the enabled row to retain their previous data, even though the enable signal is asserted on its word line 220.

[0045] Figure 3 A cross-sectional side view of a portion of a display system 100 is shown. The display system 100 includes a silicon substrate (e.g., an integrated circuit chip) 300 having circuitry and a pixel array 216 formed thereon. The pixel array 216 includes a plurality of pixels arranged in a plurality of columns and a plurality of rows. Figure 4 (As shown in the diagram). Because the display system 100 is reflective, those skilled in the art will recognize that the pixels of the pixel array 216 include reflective pixel mirrors (such as...) that reflect incident light. Figure 6 (As shown).

[0046] The display system also includes a lower liquid crystal alignment layer 302, a liquid crystal material layer 304, an upper liquid crystal alignment layer 306, a transparent electrode 308, a transparent (e.g., glass) substrate 310, and spacers 312 that hold the liquid crystal layer 304 between the lower alignment layer 302 and the upper alignment layer 306. The transparent electrode 308 is formed on the bottom surface of the transparent substrate 310 by, for example, an indium tin oxide (ITO) layer, and serves as a common electrode for the display system 100. Alignment layers 302 and 306 are formed on the pixel array 216 and the transparent electrode 308, respectively, and promote the alignment of the liquid crystal in the liquid crystal layer 304 in the desired direction.

[0047] During operation of the display system 100, incident light 312 is polarized by polarizer 314 to a first predetermined polarization state, enters through the top surface of transparent substrate 310, passes through layers 308, 306, 304, and 302, and is reflected from the pixel mirrors of pixel array 216, then passes through layers 302, 304, 306, 308, and 310 again before leaving the display system 100. The polarization of the light is altered by liquid crystal layer 304 depending on the electric field applied to the liquid crystal. When transparent electrode 308 is held at a specific voltage, the electric field on liquid crystal layer 304 is controlled by voltages applied to individual pixel mirrors (not shown) of pixel array 216. Therefore, the polarization of the incident light is spatially modulated according to the image asserted on pixel array 216, and the light is output as a modulated beam 316. The modulated beam 316 is then analyzed by analyzer 318 with a predetermined polarization orientation to produce a displayable image. Therefore, the intensity of light displayed by each pixel depends on the change in polarization imparted by the liquid crystal under the influence of the electric field between the pixel's reflector and the common electrode 308.

[0048] Figure 4 This diagram illustrates additional details of a pixel array 216 comprising a plurality of pixels 400 arranged in an array of (m) columns and (n) rows. Each column of pixels 400 is electrically connected to a corresponding bit line 218 and a corresponding column control line 222. The bit line 218 is electrically connected to a data buffer 208 via a bit line adjuster 210, and the control line 222 is electrically connected to a column decoder 214. Each row of pixels 400 is electrically connected to a corresponding word line 220 and a blocking signal line 408. The row decoder 212 asserts an enable signal and a blocking signal (described below) on the word line 220 and the blocking signal line 408, respectively, to latch the data asserted on the bit line 218 into the pixels 400 of a particular row.

[0049] Each bit line 218 is coupled to a corresponding column of pixel 400 and is driven by a corresponding bit line adjustment circuit 410 of the bit line adjuster 210. Each bit line adjustment circuit 410 is coupled to the data buffer 208 via a corresponding data line 219. In response to the data buffer asserting a specific data bit onto one of the data lines 219, the corresponding bit adjustment circuit 410 asserts a stronger inverted version of the data bit on the corresponding bit line 218. (See below for reference...) Figure 5 A more detailed description of an example of the regulator circuit 410 is provided below.

[0050] Column control lines 222 and word lines 220 work together to actuate specific individual pixels 400. To actuate a specific pixel 400, column decoder 214 asserts an enable signal (e.g., a high digital value) on the control line 222 associated with the specific column of the pixel. Simultaneously, row decoder 212 asserts an enable signal (e.g., a high digital value) on the word line 220 associated with the row of the specific pixel. In response to simultaneously asserting enable signals on the associated word line 220 and the associated column line 222, the specific pixel 400 latches / loads any data values ​​asserted on the bit line 218 associated with the pixel 400.

[0051] The line decoder 212 also asserts the signal on the blocking signal line 408. The signal asserted on the blocking signal line 408 helps latch specific position values ​​into the pixels of the relevant row, thus enabling the use of a single bit line for each column of pixels, unlike the two bit lines required in the prior art. The use of a single bit line and the use of the blocking signal advantageously provides a significant reduction in power consumption and allows for the reference... Figure 5 and Figure 6 To describe in more detail.

[0052] Figure 5 A circuit diagram of an exemplary bit line adjustment circuit in a bit line adjustment circuit 410 is shown, which includes a digital high-voltage power supply 500 (Vdd), a digital low-voltage power supply 502, a transistor 504, and a complementary transistor 506. In this example, transistor 504 is a PMOS transistor, and complementary transistor 506 is an NMOS transistor. Transistor 504 includes a gate 508, a first conductive terminal 510, and a second conductive terminal 512. Gate 508 is electrically connected to data buffer 208 via data line 219. First conductive terminal 510 is connected to Vdd node 500, and second conductive terminal 512 is connected to bit line 218, which extends into a corresponding pixel column of pixel array 216. Complementary transistor 506 includes a gate 514, a first conductive terminal 516, and a second conductive terminal 518. Gate 514 is also electrically connected to gate 508, and therefore electrically connected to data line 219. First conductive terminal 516 is electrically connected to low-voltage node 502. The first conductive terminal 516 is connected to the second conductive terminal 512 of the transistor 504, and thus to the bit line 218.

[0053] Bit adjustment circuit 410 operates as follows: When a digital high signal from buffer 208 is asserted on data line 219 and gates 508 and 514, it causes transistor 506 to operate in a conducting state, thereby pulling bit line 218 low. Simultaneously, the same digital high signal asserted on gate 508 of complementary transistor 504 causes complementary transistor 504 to operate in a non-conducting state, thereby preventing high-voltage source 500 from pulling bit line 218 high. When a digital low signal from data buffer 208 is asserted on gates 508 and 514, it causes transistor 506 to operate in a non-conducting state, thereby preventing low-voltage node 502 from pulling bit line 218 low. Simultaneously, this digital low signal on gate 508 causes complementary transistor 504 to operate in a conducting state, thereby pulling bit line 218 high. Therefore, bit line adjustment circuit 504, in response to the digital value asserted on data line 219, can operate to assert an inverted digital value on data line 218.

[0054] Figure 6 A circuit diagram of a pixel 400 connected to a pixel array 302 with bit line 218, column control line 222, word line 220, and blocking signal line 408 is shown. Pixel 400 includes a digital high-voltage source 600, a digital low-voltage source 602, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a pixel mirror 604. The high-voltage source 600 is configured to provide a relatively constant voltage, for example, 5 volts, to the circuitry of pixel 400. The low-voltage source 602 provides a common low voltage (e.g., ground or 0 volts) to the circuitry of pixel 400.

[0055] Transistor M1 is an NMOS transistor and is electrically connected to provide a selective conductive path between bit line 218 and transistor M2. The gate of transistor M1 is electrically connected to word line 220, and when a digital high signal is asserted on word line 220, transistor M1 provides a conductive path between bit line 218 and transistor M2. On the other hand, a digital low signal asserted on word line 220 and therefore on the gate of transistor M1 will put transistor M1 into a non-conductive state, thereby isolating bit line 218 from transistor M2.

[0056] Transistor M2 is an NMOS transistor and is electrically connected to provide a selective conductive path between transistor M1 and node A of pixel 400. The gate of transistor M2 is electrically connected to column control line 222, and when a digital high signal is asserted on control line 222, transistor M2 provides a conductive path between transistor M1 and node A. A digital low signal asserted on control line 222, and therefore a digital low signal asserted on the gate of transistor M2, will put transistor M2 into a non-conductive state, thereby isolating transistor M1 from node A. Therefore, when a digital high signal is asserted on both word line 220 and control line 222, both transistors M1 and M2 will be in a conductive state, providing a conductive path between bit line 218 and node A. However, if a low signal is asserted on either or both of word line 220 and control line 222, one or both of transistors M1 and M2 will be in a non-conductive state, thereby isolating bit line 218 from node A.

[0057] Transistor M3 is an NMOS transistor that is electrically connected to provide a selective conductive path between node A and transistor M4. The gate of transistor M3 is electrically connected to blocking signal line 408, and when a digital high signal is asserted on blocking signal line 408, transistor M3 provides a conductive path between node A and transistor M4. However, when a digital low signal is asserted on blocking signal line 408, transistor M3 is placed in a non-conductive state and blocks current flow between node A and transistor M4. The function and advantages of blocking transistor M3 will be described in more detail below.

[0058] Transistor M4 is an NMOS transistor, electrically connected to provide a selective conductive path between transistor M3 and ground source 602. The gate of transistor M4 is electrically connected to node B of pixel 400, and when node B is in a digital high state, transistor M4 forms a conductive path between transistor M3 and ground node 602. Conversely, when node B is in a digital low state, transistor M4 is in a non-conductive state, isolating transistor M3 from ground source 602.

[0059] Transistor M5 is a PMOS transistor that is electrically connected to provide a selective conductive path between node A and the high-voltage source 600. The gate of transistor M5 is electrically connected to node B, and when node B is in a digital low state, transistor M5 forms a conductive path between node A and the high-voltage source 600. When node B is in a digital high state, transistor M5 will be in a non-conductive state, thereby isolating node A from the high-voltage node 600.

[0060] Transistor M6 is also a PMOS transistor electrically connected between node B and the high-voltage source 600. The gate of transistor M6 is electrically connected to node A, and when node A is in a digital low state, transistor M6 forms a conductive path between node B and the high-voltage source 600. Conversely, when node A is in a digital high state, transistor M6 is placed in a non-conductive state, thereby isolating node B from the high-voltage source 600.

[0061] Transistor M7 is an NMOS transistor that is electrically connected to provide a selective conductive path between node B and ground supply 602. The gate of transistor M7 is electrically connected to node A, and when node A is in a digital high state, transistor M7 forms a conductive path between node B and ground supply 602. Conversely, when node A is in a digital low state, transistor M7 will be in a non-conductive state, thereby isolating node B from ground node 602.

[0062] Pixel mirror 604 is electrically connected to node B. Pixel mirror 604 and transparent electrode 310 ( Figure 3 The orientation of the liquid crystal material between (as shown) nodes B and the transparent electrode 310 depends on the voltage difference between them. Therefore, by latching a digital high voltage or a digital low voltage onto node B, the intensity of the light output by the associated pixel 400 can be attenuated (e.g., turned on and off).

[0063] It should be recognized that transistors M4-M7 operate together to latch data from bit line 218 into pixel 400. That is, a high digital value asserted at node A latches a low digital value to node B, and a low digital value asserted at node A latches a high digital value to node B. Transistor M3 provides a significant advantage by facilitating efficient data latching using only a single bit line, as opposed to existing designs that require both bit lines and inverted bit lines. Specifically, by asserting a low signal on control line 222, transistor M3 is placed in a non-conductive state, preventing current from flowing from node A through transistor M4 to ground power supply 602. Transistor M4 will conduct when initiating a low-to-high transition of node A. Without transistor M3, bit line 218 will attempt to pull node A high, while transistor M4 attempts to keep node A low. Furthermore, bit line adjustment circuit 210 (which attempts to pull node A high)... Figure 4 Transistor 508 is a PMOS transistor, which is much weaker than NMOS transistor M4, which attempts to keep node A low. Transistor M3 isolates node A from transistor M4 and ground power supply 602, thereby mitigating this conflict and providing significant power savings.

[0064] In the aforementioned example embodiment, transistor M3 is controlled by a signal on blocking signal line 408. In an alternative example embodiment, the gate of transistor M3 may be connected to a constant source of intermediate voltage between high-voltage power supply 600 and ground power supply 602. A specific constant voltage will be selected to limit, but not completely block, the current through transistor M3, and thus limit the current through transistor M4. This "throttling" of transistor M4 provides transistor 508 of bit line conditioning circuit 210 with the ability to pull node A high and node B low, which will turn off transistor M4 and mitigate interference.

[0065] Reference Figure 7 Example timing diagram 700 describes the operation of pixel 400, where the example pixel is cut off, remains in the cut-off state, and is turned on and remains in the on state. Recall that controller 200 ( Figure 2 The image data in frame buffers 204 and 206 is used to determine the 400 ( ) of each pixel. Figure 4 The point(s) during the frame time during which the latch bits are turned on and off. The ability to maintain latch bits (e.g., not writing a 1 on an existing 1, or writing a 0 on an existing 0) results in significant power savings.

[0066] Cutoff pixel (node ​​A changes from 0 to 1 and node B changes from 1 to 0):

[0067] At time t = 0, node B is in a high state and node A is in a low state. A high signal is asserted on bit line 218 and a low signal is asserted on blocking signal line 408. The low state on blocking signal line 408 puts transistor M3 into a non-conductive state, thereby isolating node A from transistor M4.

[0068] Shortly after bit line 218 reaches a high state and blocking signal line 408 reaches a low state, a high signal is asserted on word line 220 and a high signal is asserted on control line 222. The high states on word line 220 and control line 222 respectively enable transistors M1 and M2 to operate in a conductive state, thereby providing a conductive path between bit line 218 and node A. Because transistor M3 prevents transistor M4 from pulling node A low, bit line 218 can easily pull node A high.

[0069] The high state at node A turns off transistor M6, thus isolating node B from the high power supply 600. The high state at node A also turns on transistor M7, thus connecting node B to ground node 602 and pulling node B and pixel mirror 604 low (pixel cutoff).

[0070] A low state at node B turns on transistor M5, thus connecting node A to the high voltage source 600. A low state at node B also turns off transistor M4, thus isolating node A from the ground source 602. With both transistors M3 and M4 "off," the pixel is latched into a stable state where node A is high.

[0071] After the circuit is latched into a stable state, the blocking signal line 408 is restored to a high state, which allows transistor M3 to provide a conductive path between node A and transistor M4. However, at this point in time, transistor M4 is turned off, so node A remains high and node B remains low, without consuming power from bit line 218.

[0072] Shortly after the blocking signal line 408 returns to a high state, both word line 220 and control line 222 return to a low state, thus isolating node A from bit line 218. Although node A is disconnected from bit line 218 at this point, node A remains high because it is now connected to the high voltage source 600 via the conducting transistor M5. The bit line can then be switched up and down as needed to latch data into pixels in other rows.

[0073] Keep pixel cutoff (node ​​A remains high (1) and node B remains low (0)):

[0074] Just before time t=1, the pixel remains in the aforementioned stable state, with node B in a low state and node A in a high state. At time t=1, bit line 218 will be either high or low, but the state of bit line 218 will be irrelevant because the previous state of the pixel is being maintained. A low signal will be asserted on blocking signal line 408 because other pixels in the row may be cut off, as described in the previous section. The low state on blocking signal line 408 causes transistor M3 to be cut off, but this has little effect because transistor M4 is also cut off.

[0075] When bit line 218 is high or low and blocking signal line 408 is low, a high signal is asserted on word line 220, causing transistor M1 to conduct. However, because column control line 222 remains low, transistor M2 remains off, and bit line 218 remains isolated from node A. Therefore, even if the row in which the pixel resides is enabled by a high signal on word line 220, the pixel remains latched in its previous stable state (node ​​A high and node B low). Thus, by asserting a low signal on the selected control line 222, previously latched data can be held in the selected pixel of the row even when other pixels in the same row are loaded with new data. In other words, by using word line 220 in conjunction with column control line 222, each pixel of array 216 can be accessed individually.

[0076] Finally, a high signal is re-established on blocking signal line 408, and a low signal is established on word line 220. These signals keep the pixel in its disabled stable state until it is accessed again.

[0077] Keep pixels off (node ​​A remains high (1), and node B remains low (0)):

[0078] Just before time t=2, node B is in a low state and node A is in a high state. Then, at time t=2, a low signal is asserted on bit line 218 and a low signal is asserted on blocking signal line 408. The low state on blocking signal line 408 puts transistor M3 into a non-conductive state, thereby isolating node A from transistor M4.

[0079] Shortly after bit line 218 reaches a low state and blocking signal line 408 reaches a low state, a high signal is asserted on word line 220 and a high signal is asserted on column control line 222. The high states on word line 220 and control line 222 respectively enable transistors M1 and M2 to operate in a conductive state, thereby connecting bit line 218 to node A.

[0080] Bit line 218 pulls node A low, temporarily overpowering PMOS transistor M5. The low state on node A turns on transistor M6, thereby connecting node B to the high voltage source 600. The low state of node A also causes transistor M7 to isolate node B from ground source 602, thus putting node B and pixel mirror 408 high (on).

[0081] The high state of node B causes transistor M5 to isolate node A from the high voltage source 600, thereby ending the temporary over-supply of PMOS transistor M5 to bit line 218. The high state of node B also causes transistor M4 to connect transistor M3 to ground node 602. With both transistors M3 and M4 on, node A is connected to ground source 602 and therefore remains in a low state.

[0082] Shortly after node A reaches a low state and node B reaches a high state, the blocking signal line 408 is restored to a high state, which turns transistor M3 back on, thereby reconnecting node A to transistor M4. At this point, nodes A and B are latched into a stable state.

[0083] Shortly after the blocking signal line 408 returns to a high state, both word line 220 and control line 222 return to a low state, thus disconnecting node A from bit line 218. Therefore, the pixel remains in its disabled stable state until the next time it is accessed.

[0084] Keep the pixel on (node ​​A remains low (0) and node B remains high (1)):

[0085] Just before time t=3, the pixel remains in the aforementioned stable state, with node B in a high state and node A in a low state. At time t=3, bit line 218 will be high or low, but the state of bit line 218 will be irrelevant because the pixel's previous state is being maintained. A low signal will be asserted on blocking signal line 408 because other pixels in the row may be being cut off, as described above. The low state on blocking signal line 408 cuts off transistor M3, but this does not affect the stable state of the pixel.

[0086] When bit line 218 is high or low and blocking signal line 408 is low, a high signal is asserted on word line 220, causing transistor M1 to conduct. However, because column control line 222 remains low, transistor M2 remains off, and bit line 218 remains isolated from node A. Therefore, even if the row in which the pixel resides is enabled by a high signal on word line 220, the pixel remains latched in its previous stable state (node ​​A low and node B high). Thus, by asserting a low signal on the selected control line 222, previously latched data is maintained in the selected pixel of the row, even when other pixels in the same row are loaded with new data. In other words, by using word line 220 in conjunction with column control line 222, each pixel of array 216 can be accessed individually.

[0087] Finally, a high signal is re-established on blocking signal line 408, and a low signal is established on word line 220. These signals keep the pixel in its disabled stable state until it is accessed again.

[0088] As described above, transistor M3 enables pixel 400 to operate with a single bit line instead of two bit lines. By halving the number of bit lines, pixel array 216 consumes less power than conventional pixel arrays that require two bit lines per pixel column. By consuming significantly less power, pixel array 216 also operates at much lower temperatures and therefore avoids many of the challenges associated with high heat dissipation, such as, for example, stringent design constraints, premature pixel failure, and short battery life.

[0089] In this example embodiment, the signals on word line 220 and blocking signal line 408 are correlated and can be generated by the line decoder 212. For example, in response to receiving a line address, the line decoder 212 can pull the corresponding blocking signal line 408 low. Then, the line decoder 212 can invert and slightly delay the low signal on the blocking signal line 408 to generate a slightly delayed high signal on word line 220.

[0090] Although transistor M3 transitions between a fully "on" state and a fully "off" state, in Figure 6In the example, transistor M3 can be controlled in other ways. For instance, transistor M3 can be kept in a constant state somewhere between "on" and "off" and operate like a resistor or other current limiter, thereby allowing only a small amount of current to flow. The current flowing from node A to transistor M4 will be throttled just enough to give transistors M4 and M5 sufficient time to transition to the new stable operating state, while preventing node A from being pulled to ground.

[0091] Figure 8 An example timing diagram 800 of pixel 400 is shown when driven with an alternative driving scheme. More specifically, the driving scheme of timing diagram 800 is substantially similar to that of timing diagram 700, except that the blocking signal line 408 is maintained at a constant intermediate voltage, causing transistor M3 to operate constantly in a partially conducted state, where a small amount of current is constantly allowed to flow through transistor M3. The constant intermediate voltage asserted on the gate of transistor M3 via the blocking signal line 408 is chosen to throttle the current flowing through transistor M3. This mitigates the conflict between transistor M4, which attempts to pull node A to ground, and PMOS transistor 508, which attempts to pull node A high, when node A transitions from a digital low state to a digital high state.

[0092] Figures 9A-9C An example physical layout of various elements of pixel 400 formed in and on a p-type substrate is shown. The spacing (defined as the distance between identical points in two adjacent pixels) is 3 μm or less. All seven transistors M1 to M7 are included in each pixel. Figure 1 Transistors M1-M7 shown Figures 9A to 9C The transistor corresponds to Figure 6 The same transistors M1 to M7 are shown in the circuit diagram.

[0093] Figure 9A The p-type substrate 300 is shown (see Figure 3 It is a part of a circuit that forms representative pixels 400 thereon. More specifically, Figure 9AThe semiconductor doped regions of pixel 400 are shown, including multiple n-type doped regions 900, 902, 904, 906, 908, 910, 912 and an n-well 914, and multiple p-type doped regions 916, 918 and 920 formed in the n-well 914. N-type region 900 (n1) forms the source of transistor M1. N-type region 902 (n2) forms the drain of transistor M1 and the source of transistor M2. N-type region 904 (n3) forms the drain of transistor M2 and the source of transistor M3. N-type region 906 (n4) forms the drain of transistor M3 and the source of transistor M4. N-type region 908 (n5) forms the drain of transistor M4. N-type region 910 (n6) forms the source of transistor M7, and N-type region 912 (n7) forms the drain of transistor M7.

[0094] N-type region 914 is an N-well. P-type region 916 (p3) is formed in n-well 914 and is the source of transistor M5. P-type region 918 (p2) is also formed in n-well 914 and is the drain of transistor M5 and the drain of transistor M6. P-type region 920 (p1) is also formed in n-well 914 and is the source of transistor M6.

[0095] Figure 9B The physical layout of the polysilicon regions (with an invisible underlying insulating layer) forming the gates of the corresponding transistors of pixel 400 is shown. Polysilicon region 924 forms the gate g1 of transistor M1, polysilicon region 926 forms the gate g2 of transistor M2, polysilicon region 928 forms the gate g3 of transistor M3, polysilicon region 930 forms the gate g4 of transistor M4 and the gate g5 of transistor M5, polysilicon region 932 forms the gate g6 of transistor M6, and polysilicon region 934 forms the gate g7 of transistor M7.

[0096] Figure 9C The interconnections between components of pixel 400 are shown, the components being formed in one or more interconnect metal layers formed above substrate 300. Figure 9C The components forming various transistors M1-M7 are also outlined. The first conductive node 940 electrically connects the n-type region (n1) (the source of transistor M1) to bit line 218. Figure 6The second conductive node 942 electrically connects the polysilicon region (g1) (the gate of transistor M1) to word line 220. The third conductive node 944 electrically connects the polysilicon region (g2) (the gate of transistor M2) to column control line 222. The fourth conductive node 946 electrically connects the polysilicon region (g3) (the gate of transistor M3) to blocking signal line 408. The fifth conductive node 948 provides electrical connections between the n-type region (n3) (the drain of transistor M2), the p-type region (p1) (the source of transistor M5), the polysilicon region (g6) (the gate of transistor M6), and the polysilicon region (g7) (the gate of transistor M7). The sixth conductive node 950 provides electrical connections between the n-type region (n6) (the source of transistor M7), the p-type region (p3) (the source of transistor M6), and the polysilicon regions (g4) and (g5) (the gates of transistors M4 and M5). The seventh conductive node 952 electrically connects the p-type region (p2) (the drain of transistors M5 and M6) to the first voltage source (Vdd). The eighth conductive node 954 electrically connects the n-type regions (n5) (the source of transistor M4) and (n7) (the source of transistor M7) to the second voltage source (Vss). The second voltage source (Vss) is maintained at a lower voltage than the first voltage source (Vdd).

[0097] The description of specific embodiments of the invention is now complete. Many of the described features may be substituted, altered, or omitted without departing from the scope of the invention. For example, the described memory circuitry can be used in other types of display devices. As another example, one or more additional blocking transistors may be used at other points in the described circuitry to facilitate transitions between high and low values ​​of the latch. These and other deviations from the specific embodiments shown will be apparent to those skilled in the art, especially in light of the foregoing disclosure.

Claims

1. A bit storage circuit, comprising: First voltage supply line; Second voltage supply line; Bit line; A latch having inputs and outputs; A first switching transistor having a first terminal, a second terminal, and a control terminal, the first switching transistor being operable to selectively provide a conductive path and a non-conductive path between the bit line and the input of the latch in response to a first control signal asserted on the control terminal of the first switching transistor. A blocking transistor, the blocking transistor including a control terminal and operable to selectively provide a conductive path and a non-conductive path between the input of the latch and the second voltage supply line in response to a second control signal; as well as A second switching transistor having a first terminal, a second terminal, and a control terminal, the second switching transistor being operable to selectively provide a conductive path and a non-conductive path between the bit line and the input of the latch in response to a third control signal asserted on the control terminal of the second switching transistor; and wherein The first switching transistor and the second switching transistor are coupled in series between the bit line and the input of the latch; and The bit storage circuit is connected to no more than one bit line.

2. The bit storage circuit according to claim 1, wherein, The latch includes: A first p-channel transistor has a source terminal coupled to the first voltage supply line, a drain terminal coupled to the output of the latch, and a gate terminal coupled to the input of the latch; A first n-channel transistor has a source terminal coupled to the second voltage supply line, a drain terminal coupled to the output of the latch, and a gate terminal coupled to the input of the latch; A second p-channel transistor has a source terminal coupled to the first voltage supply line, a drain terminal coupled to the input of the latch, and a gate terminal coupled to the output of the latch; and The second n-channel transistor has a source terminal coupled to the second voltage supply line, a drain terminal selectively coupled to the input of the latch via the blocking transistor, and a gate terminal coupled to the output of the latch.

3. The bit storage circuit according to claim 1, wherein, The latch includes: A first p-channel transistor has a source terminal coupled to the first voltage supply line, a drain terminal coupled to the output of the latch, and a gate terminal coupled to the input of the latch; A first n-channel transistor has a source terminal coupled to the second voltage supply line, a drain terminal coupled to the output of the latch, and a gate terminal coupled to the input of the latch; A second p-channel transistor has a source terminal coupled to the first voltage supply line, a drain terminal coupled to the input of the latch, and a gate terminal coupled to the output of the latch; and The second n-channel transistor has a source terminal selectively coupled to the second voltage supply line via the blocking transistor, a drain terminal coupled to the input of the latch, and a gate terminal coupled to the output of the latch.

4. The bit storage circuit according to claim 1, further comprising a pixel electrode coupled to the output of the latch.

5. The bit storage circuit according to claim 1, wherein, The bit storage circuit includes no more than seven transistors.

6. The bit storage circuit of claim 1 further includes a pulse generator having an output coupled to the control terminal of the blocking transistor.

7. The bit storage circuit according to claim 1, wherein, The control terminal of the blocking transistor is coupled to a third voltage supply line having a constant voltage between the voltage of the first voltage supply line and the voltage of the second voltage supply line, whereby the second control signal is the constant voltage and the blocking transistor remains in a partially conductive state.

8. A display comprising: First voltage supply line; Second voltage supply line; An array of pixel electrodes arranged in columns and rows; Multiple driving lines; Multiple signal lines blocked; Multiple bit lines; as well as An array of pixel circuits arranged in columns and rows; and each of the pixel circuits includes a latch having an input coupled to one of the bit lines and an output coupled to one of the pixel electrodes; A first switching transistor having a control terminal coupled to one of the power lines, the first switching transistor being operable to provide a conductive and non-conductive path between the bit line and the input of the latch in response to a first control signal asserted on the power line. A blocking transistor includes a control terminal coupled to one of the blocking signal lines and is operable to selectively provide a conductive path and a non-conductive path between the input of the latch and the second voltage supply line in response to a second control signal asserted on one of the blocking signal lines; as well as Multiple column enable lines; and in Each pixel includes a second switching transistor having a control terminal coupled to one of the column enable lines. The second switching transistor is operable to selectively provide a conductive path and a non-conductive path between the bit line and the input of the latch in response to a third control signal asserted on one of the column enable lines. The first switching transistor and the second switching transistor are coupled in series between the bit line and the input of the latch; and Each pixel circuit is coupled to no more than one bit line in the bit lines.

9. The display according to claim 8, wherein, Each of the latches includes: A first p-channel transistor has a source terminal coupled to the first voltage supply line, a drain terminal coupled to the output of the latch, and a gate terminal coupled to the input of the latch; A first n-channel transistor has a source terminal coupled to the second voltage supply line, a drain terminal coupled to the output of the latch, and a gate terminal coupled to the input of the latch; A second p-channel transistor has a source terminal coupled to the first voltage supply line, a drain terminal coupled to the input of the latch, and a gate terminal coupled to the output of the latch; and The second n-channel transistor has a source terminal coupled to the second voltage supply line, a drain terminal selectively coupled to the input of the latch via the blocking transistor, and a gate terminal coupled to the output of the latch.

10. The display according to claim 8, wherein, Each of the latches includes: A first p-channel transistor has a source terminal coupled to the first voltage supply line, a drain terminal coupled to the output of the latch, and a gate terminal coupled to the input of the latch; A first n-channel transistor has a source terminal coupled to the second voltage supply line, a drain terminal coupled to the output of the latch, and a gate terminal coupled to the input of the latch; A second p-channel transistor has a source terminal coupled to the first voltage supply line, a drain terminal coupled to the input of the latch, and a gate terminal coupled to the output of the latch; and The second n-channel transistor has a source terminal selectively coupled to the second voltage supply line via the blocking transistor, a drain terminal coupled to the input of the latch, and a gate terminal coupled to the output of the latch.

11. The display according to claim 8, wherein, Each pixel circuit includes no more than seven transistors.

12. A bit storage circuit combined with a plurality of additional bit storage circuits, said bit storage circuits and said additional bit storage circuits being arranged in an array of bit storage circuits formed in and on a p-type semiconductor substrate, said bit storage circuit comprising: First voltage supply line; Second voltage supply line; Bit line; A latch having inputs and outputs; A first switching transistor having a first terminal, a second terminal, and a control terminal, the first switching transistor being operable to selectively provide a conductive path and a non-conductive path between the bit line and the input of the latch in response to a first control signal asserted on the control terminal of the first switching transistor. as well as A blocking transistor, the blocking transistor including a control terminal and operable to selectively provide a conductive path and a non-conductive path between the input of the latch and the second voltage supply line in response to a second control signal; Furthermore, each additional bit storage circuit of the array includes: At least one n-well is formed in the p-type substrate; A first p-type doped region is formed in the at least one n-well; A second p-type doped region is formed in the at least one n-well; A third p-type doped region is formed in the at least one n-well; A first n-type doped region is formed in the p-type substrate; A second n-type doped region is formed in the p-type substrate; A third n-type doped region is formed in the p-type substrate; A fourth n-type doped region is formed in the p-type substrate; A fifth n-type doped region is formed in the p-type substrate; A sixth n-type doped region is formed in the p-type substrate; A seventh n-type doped region is formed in the p-type substrate; A first polysilicon gate is formed above a first region of the p-type substrate disposed between the first n-type doped region and the second n-type doped region; The second polysilicon gate is formed above a second region of the p-type substrate disposed between the second n-type doped region and the third n-type doped region; A third polysilicon gate is formed above a third region of the p-type substrate disposed between the third n-type doped region and the fourth n-type doped region; A fourth polysilicon gate is formed above a fourth region of the p-type substrate disposed between the fourth n-type doped region and the fifth n-type doped region; A fifth polysilicon gate is formed over a first region of the at least one n-well disposed between the first p-type doped region and the second p-type doped region; A sixth polysilicon gate is formed over a second region of the at least one n-well disposed between the second p-type doped region and the third p-type doped region; A seventh polysilicon gate, the seventh polysilicon gate being formed above a fifth region of the p-type substrate disposed between the sixth n-type doped region and the seventh n-type doped region; and One or more conductive layers are formed on the substrate and the polysilicon gate, the one or more conductive layers comprising: A first conductive path electrically couples the first n-type doped region to the bit line of the array. A second conductive path electrically couples the first polysilicon gate to a first control line of the array. A third conductive path electrically couples the second polysilicon gate to a second control line of the array. A fourth conductive path electrically couples the third polysilicon gate to the third control line of the array. The fifth conductive path electrically couples the third n-type doped region, the first p-type doped region, the sixth polysilicon gate, and the seventh polysilicon gate. The sixth conductive path electrically couples the fourth polysilicon gate, the fifth polysilicon gate, the third p-type doped region, and the sixth n-type doped region. A seventh conductive path, wherein the seventh conductive path electrically couples the second p-type doped region to the first voltage supply line of the array, and The eighth conductive path electrically couples the fifth n-type doped region and the seventh n-type doped region to the second voltage supply line of the array, the second voltage supply line providing a lower voltage than the first voltage supply line.

13. The array of bit storage circuits according to claim 12, wherein, The array has a spacing of no more than 3 μm.

14. The array of bit storage circuits according to claim 12, wherein: The first control line of the array is a power line; The second control line of the array is a column enable line; and The sixth conductive path is electrically coupled to the pixel mirror.

15. The array of bit storage circuits according to claim 12, wherein the region of each of the first n-type doped region, the second n-type doped region, and the third n-type doped region is larger than the region of the largest of the fourth n-type doped region, the fifth n-type doped region, the sixth n-type doped region, and the seventh n-type doped region.

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