A switching circuit and method, and a DCDC

Abstract

The present application provides a switching circuit, a method, and a DCDC. The switching circuit includes: a first delay module, a first counting module, and a latching module connected in sequence. The first delay module is configured to obtain a periodic signal of a switching transistor of the DCDC, and generate a first delay signal according to the periodic signal and a first time value. The first counting module calculates the number of times the first delay signal is continuously generated, and outputs a first counting signal to the latching module when the number of times is greater than or equal to a first value, so that the latching module outputs a first indication signal to indicate that the DCDC switches from a normal mode to a low-power mode. In this circuit, entering the low-power mode only when the number of switching cycles greater than the first time value continuously calculated is greater than the first value can reduce the situation of accidentally entering the low-power mode due to the load transient changing from heavy load to light load, and improve the accuracy of the DCDC entering the low-power mode.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic power technology, and in particular to a switching circuit and method, and a DCDC. Background Art

[0002] Under the condition of increasingly tense energy, more portable devices hope to reduce the standby power consumption of the electrical appliance itself when the load is small, so as to extend the standby time. For example, in wearable products, watches and bracelets, etc., when communication and wake-up are not required, their standby power consumption is reduced, so as to increase the standby time, reduce the charging times, extend the internal battery life and enhance the user experience.

[0003] As the lower-level power supply in such products, the control of the standby power consumption of the DCDC is particularly important. For example, when it is detected that the load current is small, the DCDC first enters the Discontinuous Conduction Mode (DCM). As the load current continues to decrease, the switching period will continue to increase. At this time, the DCDC needs to switch to the low-power mode to work. In the low-power mode, most of the power-consuming modules in the DCDC will be turned off, and the power consumption can be as low as below 1 μA. However, currently, when the DCDC switches the working mode, in the case of load transient conditions, such as from heavy load to light load quickly, it will erroneously enter the low-power mode. Summary of the Invention

[0004] The embodiments of the present application provide a switching circuit and method, and a DCDC, which can improve the accuracy of the DCDC entering the low-power mode.

[0005] In a first aspect, the embodiments of the present application provide a switching circuit applied to a DCDC. The switching circuit includes: a first delay module, configured to obtain a periodic signal of a switching tube of the DCDC, and generate a first delay signal according to the periodic signal and a first time value; a first counting module, an input end of the first counting module is connected to an output end of the first delay module, and the first counting module is configured to calculate a first number of times that the first delay signal is continuously generated, and output a first counting signal when the first number of times is greater than or equal to a first value; a latching module, a first input end of the latching module is connected to an output end of the first counting module, and the latching module outputs a first indication signal through a first output end of the latching module based on the first counting signal, and the first indication signal is used to indicate that the DCDC switches from a normal mode to a low-power mode.

[0006] In some embodiments, the switching transistor of the DCDC includes a rectifying transistor and a synchronous transistor, and the first delay module includes a NAND gate and a first delay unit; the first input terminal of the NAND gate is configured to receive the control signal of the rectifying transistor, the second input terminal of the NAND gate is configured to receive the control signal of the synchronous transistor, the output terminal of the NAND gate is connected to the input terminal of the first delay unit, and the output terminal of the first delay unit is connected to the input terminal of the first counting module; wherein, the NAND gate outputs a logic signal to the first delay unit based on the control signal of the rectifying transistor and the control signal of the synchronous transistor; the first delay unit is configured to generate the first delay signal to the first counting module based on the logic signal and the first time value.

[0007] In some embodiments, the first counting module includes N first DFFs; the clock input terminal of the first first DFF is connected to the output terminal of the first delay module, the inverted data output terminal of the nth first DFF is respectively connected to the data input terminal of the nth first DFF and the clock input terminal of the (n + 1)th first DFF, the data output terminal of the Nth first DFF is connected to the first input terminal of the latching module, and the set terminals of all the first DFFs are connected to the second output terminal of the latching module; wherein, the latching module outputs a clear signal to all the first DFFs through the second output terminal of the latching module based on the first counting signal, so as to clear all the first DFFs; N and the first value M1 have the following relationship:

[0008] M1 = 2 N-1 ;

[0009] N is an integer greater than or equal to 1, and 1 ≤ n < N.

[0010] In some embodiments, the switching circuit further includes a second delay module; the first output terminal of the second delay module is connected to the second input terminal of the latching module; wherein, the second delay module is configured to obtain the periodic signal and generate a second delay signal to the latching module according to the periodic signal and the second time value; the latching module outputs a second indication signal through the first output terminal of the latching module based on the second delay signal, and the second indication signal is used to indicate that the DCDC switches from the low-power mode to the normal mode.

[0011] In some embodiments, the switching circuit further includes a second counting module; a first output end of the second delay module is connected to an input end of the second counting module, and an output end of the second counting module is connected to a second input end of the latching module; wherein, the second delay module is configured to generate a second delay signal to the second counting module according to the periodic signal and the second time value; the second counting module is configured to calculate a second number of times generated by the second delay signal, and output a second counting signal to the latching module when the second number of times is greater than or equal to a second value; and the latching module outputs the second indication signal through a first output end of the latching module based on the second counting signal.

[0012] In some embodiments, the DCDC includes a synchronous transistor, and the second delay module includes a second delay unit and a logic unit; an input end of the second delay unit and a first input end of the logic unit are configured to receive a control signal of the synchronous transistor, an output end of the second delay unit is connected to a second input end of the logic unit, and a third input end of the logic unit is connected to a third output end of the latching module;

[0013] wherein, the second delay unit generates a third delay signal to the logic unit based on the control signal of the synchronous transistor and the second time value; the logic unit is configured to output the second delay signal to the second counting module according to the control signal of the synchronous transistor, the third delay signal, and an output signal of the third output end of the latching module, and the output signal of the third output end of the latching module and the output signal of the second output end of the latching module have opposite levels.

[0014] In some embodiments, the second delay unit includes: a rising-edge delay sub-unit, a first falling-edge delay sub-unit, a NOT gate, and a NOR gate; an input end of the rising-edge delay sub-unit is configured to receive the control signal of the synchronous transistor, an output end of the rising-edge delay sub-unit is respectively connected to an input end of the first falling-edge delay sub-unit and a first input end of the NOR gate, an output end of the first falling-edge delay sub-unit is connected to an input end of the NOT gate, an output end of the NOT gate is connected to a second input end of the NOR gate, and an output end of the NOR gate is connected to a second input end of the logic unit.

[0015] In some embodiments, the logic unit includes an AND gate; a first input end of the AND gate is configured to receive the control signal of the synchronous transistor, a second input end of the AND gate is connected to an output end of the second delay unit, a third input end of the AND gate is connected to the third output end of the latching module, and an output end of the AND gate is connected to an input end of the second counting module.

[0016] In some embodiments, the second counting module includes K second DFFs; the clock input terminal of the first second DFF is connected to the first output terminal of the second delay module, the inverted data output terminal of the k-th second DFF is respectively connected to the data input terminal of the k-th second DFF and the clock input terminal of the (k + 1)-th second DFF, the data output terminal of the K-th second DFF is connected to the second input terminal of the latch module, and the set terminals of the second DFFs are all connected to the second output terminal of the second delay module; wherein, K and the second value M2 have the following relationship:

[0017] M2 = 2 K-1 ;

[0018] K is an integer greater than or equal to 1, and 1 ≤ k < K.

[0019] In some embodiments, the switching circuit further includes a first comparison module and a voltage adjustment module; the input terminal of the voltage adjustment module is connected to the output terminal of the DCDC, the output terminal of the voltage adjustment module is connected to the first input terminal of the first comparison module, the second input terminal of the first comparison module is used to connect to a reference voltage source, and the output terminal of the first comparison module is connected to the third input terminal of the latch module; wherein, the voltage adjustment module outputs an adjusted voltage to the first comparison module based on the output voltage of the DCDC; the first comparison module outputs a comparison signal to the latch module based on the adjusted voltage and the reference voltage output by the reference voltage source; the latch module outputs a third indication signal through the first output terminal of the latch module based on the comparison signal, and the third indication signal is used to indicate that the DCDC switches from the low power consumption mode to the normal mode.

[0020] In some embodiments, the switching circuit further includes a second comparison module; the first input terminal of the second comparison module is connected to the output terminal of the DCDC, and the second input terminal of the second comparison module is used to connect to a reference voltage source; wherein, the second comparison module outputs a control signal for the synchronous tube based on the output voltage of the DCDC and the reference voltage.

[0021] In a second aspect, an embodiment of the present application provides a switching method applied to a DCDC. The switching method includes: obtaining the switching period of the switching tube of the DCDC and a first time value; determining the first number of times that the switching period is continuously greater than the first time value; if the first number is greater than or equal to a first value, controlling the DCDC to switch from the normal mode to the low power consumption mode.

[0022] In some embodiments, the method further includes: obtaining a second time value; if the switching period is less than the second time value, controlling the DCDC to switch from the low power consumption mode to the normal mode.

[0023] In some embodiments, when the switching period is less than the second time value, controlling the DCDC to switch from the low-power mode to the normal mode includes: determining a second number of times that the switching period is less than the second time value; if the second number of times is greater than or equal to a second value, controlling the DCDC to switch from the low-power mode to the normal mode.

[0024] In some embodiments, the method further includes: obtaining the output voltage, the dropout voltage, and the reference voltage of the DCDC; obtaining an adjustment voltage according to the output voltage and the dropout voltage; and controlling the DCDC to switch from the normal mode to the low-power mode according to the adjustment voltage and the reference voltage.

[0025] In some embodiments, the method further includes: outputting a control signal to a synchronous transistor according to the output voltage and the reference voltage.

[0026] In a third aspect, an embodiment of the present application provides a control device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute the method according to any one of the second aspect.

[0027] In a fourth aspect, an embodiment of the present application provides a DCDC, which includes the switching circuit according to any one of the first aspect, or includes the control device according to the third aspect.

[0028] In a fifth aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer-executable instructions for causing a computer to execute the method according to any one of the second aspect above.

[0029] In a sixth aspect, an embodiment of the present invention further provides a computer program product, which includes a computer program stored on a computer-readable storage medium, and the computer program includes program instructions, and when the program instructions are executed by a computer, the computer is caused to execute the method according to any one of the second aspect above.

[0030] Compared with the prior art, the beneficial effects of the present application are as follows: Different from the prior art, the embodiments of the present application provide a switching circuit, a method, and a DCDC. The switching circuit includes: a first delay module, a first counting module, and a latching module connected in sequence. The first delay module is configured to obtain a periodic signal of a switching transistor of the DCDC, and generate a first delay signal according to the periodic signal and a first time value. The first counting module calculates the number of times the first delay signal is continuously generated, and outputs a first counting signal to the latching module when the number of times is greater than or equal to a first value, so that the latching module outputs a first indication signal to indicate that the DCDC switches from a normal mode to a low power consumption mode. In this circuit, by continuously calculating that the number of switching cycles greater than the first time value is greater than the first value before entering the low power consumption mode, the situation of mistakenly entering the low power consumption mode due to the load transient changing from heavy load to light load can be reduced, and the accuracy of the DCDC entering the low power consumption mode can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In one or more embodiments, exemplary illustrations are provided through the pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements / modules and steps with the same reference numerals in the drawings represent similar elements / modules and steps, unless otherwise stated, the drawings in the figures do not constitute a proportional limitation.

[0032] Figure 1 is a structural block diagram of a switching circuit provided by an embodiment of the present application;

[0033] Figure 2 is a circuit diagram of a switching circuit provided by an embodiment of the present application;

[0034] Figure 3 is a schematic diagram of a curve showing the change of output inductor current over time provided by an embodiment of the present application;

[0035] Figure 4 is a structural block diagram of another switching circuit provided by an embodiment of the present application;

[0036] Figure 5 is a structural block diagram of yet another switching circuit provided by an embodiment of the present application;

[0037] Figure 6 is a partial circuit diagram of a switching circuit provided by an embodiment of the present application;

[0038] Figure 7 is a structural block diagram of a control device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0039] The present application will be described in detail below with reference to specific embodiments. The following embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any form. It should be noted that those of ordinary skill in the art can make several modifications and improvements without departing from the concept of the present application. These all fall within the protection scope of the present application.

[0040] To facilitate the understanding of the present application, the present application will be described in more detail below with reference to the accompanying drawings and specific embodiments. Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not used to limit the present application. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items.

[0041] It should be noted that if there is no conflict, the various features in the embodiments of the present application can be combined with each other, and all are within the protection scope of the present application. In addition, although the functional modules are divided in the device schematic diagram, in some cases, it can be different from the module division in the device. In addition, the terms "first", "second", etc. used herein do not limit the data and execution order, but only distinguish the same items or similar items with basically the same functions and roles.

[0042] In the lower-level power supply of wearable products, the control of the standby power consumption of DCDC is particularly important. When the load current is detected to be small, DCDC first enters DCM. Then, as the load current continues to decrease, the switching period will continue to increase. At this time, it is necessary to switch to the ultra-low power consumption mode to work. In this mode, most of the power-consuming modules in DCDC will be turned off, so as to enter the ultra-low power consumption operation, and the power consumption can be as low as below 1 μA. When the load current increases to the set value, it is necessary to jump out of the low-power mode. Since the increase speed of the load current is unknown, it may change slowly or there may be a rapid heavy load. Therefore, how to achieve a smooth switch between the ultra-low power consumption mode and the normal mode, ensure the stability of the output power supply, that is, the output fluctuation is small, and there will be no repeated mode switching at a certain load, becomes the key.

[0043] To solve the above technical problems, the embodiments of the present application provide a switching circuit and method, and DCDC, which can switch from the normal mode to the low-power mode when the load becomes lighter, and can also switch from the low-power mode to the normal mode when the load slowly becomes heavier, realizing a smooth switch, ensuring stable output, reducing the output ripple, thereby providing a stable power supply for the subsequent circuit. In addition, when the load quickly becomes heavier, it can also ensure that the output drop meets the requirements of the subsequent circuit.

[0044] In a first aspect, the embodiments of the present application provide a switching circuit, which is applied to DCDC. Please refer toFigure 1 , the switching circuit includes: a first delay module 10, a first counting module 20, and a latching module 30.

[0045] The input end of the first counting module 20 is connected to the output end of the first delay module 10, and the first input end of the latching module 30 is connected to the output end of the first counting module 20. The first delay module 10 is configured to obtain a periodic signal of a switching tube of the DCDC, and generate a first delay signal according to the periodic signal and a first time value T1. The first counting module 20 is configured to calculate a first number of times that the first delay signal is continuously generated, and output a first counting signal when the first number of times is greater than or equal to a first value. The latching module 30 outputs a first indication signal through a first output end of the latching module 30 based on the first counting signal, and the first indication signal is used to indicate that the DCDC switches from a normal mode to a low power consumption mode.

[0046] The DCDC, that is, a DC converter, can convert electrical energy of one voltage value into electrical energy of another voltage value. In the normal mode, all the internal current source, reference source, etc. for controlling the comparator and loop of the circuit work normally and consume current. In the low power consumption mode, all the internal current source, reference source, etc. for controlling the comparator and loop of the circuit are in the sleep mode, do not consume current, and only leave the circuits that must work in the low power consumption mode.

[0047] It can be understood that in the DCDC, if the load becomes lighter (the load impedance becomes larger), the DCDC first enters the DCM. Then, if the load continues to become lighter, the switching period of the DCDC will gradually increase. Under the condition that the input voltage vin, the output voltage vout, and the inductance value L of the inductor are fixed, the switching period T of the DCDC 非 is only related to the load current Io and the peak current Ipeak of the inductor, and the relationship is as follows:

[0048]

[0049]

[0050] T = ton + toff;

[0051]

[0052] where, ton is the conduction time of the synchronous tube of the DCDC, toff is the turn-off time of the synchronous tube of the DCDC, and T 非 is the switching period of the synchronous tube of the DCDC.

[0053] Since in the buck DCDC in the constant conduction time control mode, the conduction time ton of the synchronous tube of the DCDC is a constant value, the peak current Ipeak of the inductor is constant. Then, at this time, in the DCM, the switching period T of the DCDC非 It is only related to the load current Io. Additionally, in a buck DCDC with peak current mode control, the minimum peak current of the DCDC can be limited. In this way, when the DCDC enters the DCM mode, the peak current Ipeak of the inductor is also constant. Then, the switching period T of the DCDC 非 is also only related to the load current Io. Similarly, in a boost DCDC with constant on-time control mode and a boost DCDC with peak current mode control, the switching period T of the DCDC 非 is also only related to the load current Io, and the relationship is as follows:

[0054]

[0055]

[0056]

[0057] In summary, under DCM, there is a certain relationship between the external load current Io and the switching period T 非 That is, the switching period can be used to characterize the magnitude of the external load current. Specifically, the larger the switching period, the smaller the load current entering the timing period count, and the lighter the load. The smaller the switching period, the larger the load current entering the timing period count, and the heavier the load. Therefore, by timing the switching period, it can be determined whether the DCDC switches from the normal mode to the low-power mode, or whether to switch from the low-power mode to the normal mode.

[0058] In this embodiment, the first delay module 10 can be used to obtain the periodic signal of the switching tube of the DCDC, and determine the switching period of the DCDC based on the periodic signal, that is, the period when the synchronous tube of the DCDC is turned on, which is also the working period of the DCDC, and is also the time corresponding to the working frequency of the DCDC. Specifically, the first delay module 10 can simultaneously obtain the control signal Ison of the rectifier tube and the control signal hson of the synchronous tube, and compare the switching period with the first time value in the following manner: within one period, start timing from 0 at the moment when both the rectifier tube and the synchronous tube are turned off, that is, start timing from 0 when the control signal Ison of the rectifier tube and the control signal hson of the synchronous tube are both at low level. If the current load current decreases, and after reaching the first time value T1, the control signal Ison of the rectifier tube and the control signal hson of the synchronous tube are still at low level, then the first delay module 10 outputs a first delay signal to the first counting module 20, and the first counting module 20 will increment the first count by one. Then, calculate the signals in the next period in the above manner until the first count calculated by the first counting module 20 is greater than or equal to the first value. At this time, the first counting module 20 will output a first counting signal, which indicates that in the first value of consecutive periods, the switching period of the DCDC is greater than the first time value T1, and also indicates that the load is relatively light in the first value of consecutive periods. Then, the latch module 30 will output a first indication signal upon receiving this first counting signal to indicate that the DCDC switches from the normal mode to the low power consumption mode.

[0059] It can be understood that if the first delay module 10 does not continuously generate the first delay signal, the first counting module 20 will set the first count to 0. In practical applications, the first time value T1 and the first value can be set according to actual needs. For example, the first value can be any value from 2 to 9999.

[0060] In this embodiment, by calculating whether the switching period is greater than the first time value T1 according to the periodic signal to determine the current load condition, and by continuously calculating that the number of times the switching period is greater than the first time value T1 is greater than the first value before entering the low power consumption mode, the situation of mistakenly entering the low power consumption mode due to the load transient changing from heavy load to light load can be reduced, the accuracy of the DCDC entering the low power consumption mode can be improved, and the smooth switching between the ultra-low power consumption mode and the normal mode can be achieved, with relatively small output fluctuations, thereby improving the stability of the DCDC output power supply.

[0061] In some of these embodiments, after entering the ultra-low power consumption mode, it is necessary to ensure that the energy provided by each DCDC switch is slightly greater than or equal to that in the DCM in the normal mode. As Figure 3 shown, the energy provided to the output by each switching operation needs to meet the following conditions:

[0062] Ipeak1≥Ipeak0;

[0063] Among them, Ipeak1 is the peak current brought by each switch in the ultra-low power consumption mode; Ipeak0 is the peak current brought by each switch when the DCDC is normally in the DCM mode. That is, for the COT DCDC, it is necessary to ensure that the conduction time of the synchronous tube of the DCDC remains unchanged or increases when entering the low power consumption mode. For the DCDC in the peak current mode, it is necessary to ensure that the peak current remains unchanged or increases in the low power consumption mode, so as to realize the smooth switching between the ultra-low power consumption mode and the normal mode, improve the stability of the output power supply, and reduce the output fluctuation.

[0064] In some of these embodiments, refer to Figure 2 , the latch module 30 includes a latch U3, a NOT gate U4, and a NOT gate U5. Among them, the first input terminal of the latch U3 is connected to the output terminal of the first counting module 20, the output terminal of the latch U3 is connected to the input terminal of the NOT gate U4, and the output terminal of the NOT gate U4 is respectively connected to the input terminal of the NOT gate U5 and the first counting module 20.

[0065] The specific circuit structures of the latch U3, the NOT gate U4, and the NOT gate U5 can refer to the prior art and will not be limited here. In this latch module 30, when the first input terminal of the latch U3 receives a high level, it outputs a high level to the NOT gate U4. The NOT gate U4 will output a low level to the NOT gate U5, and the NOT gate U5 outputs a high level (the first indication signal). In practical applications, the specific structure of the latch module 30 can be set according to actual needs and there is no need to be restricted by the limitations in this embodiment.

[0066] In this embodiment, the latch U3 can maintain the previous state when the input signal does not change, reducing the situation where the DCDC frequently switches working modes. In addition, the NOT gate U4 and the NOT gate U5 can improve the anti-interference ability of the output signal and the driving ability for the subsequent stage.

[0067] In some of these embodiments, refer to Figure 2 , the switching tube of the DCDC includes a rectifier tube and a synchronous tube. The first delay module 10 includes a NAND gate U1 and a first delay unit. The first input terminal of the NAND gate U1 is used to receive the control signal Ison of the rectifier tube, the second input terminal of the NAND gate U1 is used to receive the control signal hson of the synchronous tube, the output terminal of the NAND gate U1 is connected to the input terminal of the first delay unit, and the output terminal of the first delay unit is connected to the input terminal of the first counting module 20.

[0068] Among them, the NAND gate U1 outputs a logic signal to the first delay unit based on the control signal Ison of the rectifier tube and the control signal hson of the synchronous tube. The first delay unit is used to generate a first delay signal to the first counting module 20 based on the logic signal and the first time value T1.

[0069] Specifically, the first delay unit includes a second falling-edge delay subunit 11 and a NOT gate U2. The input end of the second falling-edge delay subunit 11 is connected to the output end of the NAND gate U1, and the output end of the second falling-edge delay subunit 11 is connected to the input end of the NOT gate U2.

[0070] In the first delay module 10, the NAND gate U1 receives the control signal Ison of the rectifier diode and the control signal hson of the synchronous tube simultaneously, and outputs a high level to the second falling-edge delay subunit 11 when at least one of the control signal Ison of the rectifier diode and the control signal hson of the synchronous tube is at a low level, and outputs a low level to the second falling-edge delay subunit 11 when both the control signal Ison of the rectifier diode and the control signal hson of the synchronous tube are at a high level.

[0071] The second falling-edge delay subunit 11 is used to delay the falling edge of the signal output by the NAND gate U1 and output the delayed signal to the NOT gate U2. For example, when the falling edge of the signal output by the NAND gate U1 arrives, due to the delay of the second falling-edge delay subunit 11, the output signal of the second falling-edge delay subunit 11 will not immediately become low level, but will undergo a level conversion after a period of time (the first time value T1), so that the signal with a low level duration less than the first time value T1 output by the NAND gate U1 cannot pass through the second falling-edge delay subunit 11. The NOT gate U2 is used to output a low level when the output signal of the second falling-edge delay subunit 11 is at a high level, and output a high level when the output signal of the second falling-edge delay subunit 11 is at a low level.

[0072] In this embodiment, through the above circuit, when the control signal Ison of the rectifier diode and the control signal hson of the synchronous tube are both at a low level, the first delay module 10 can start timing from 0. If the timing reaches the first time value T1, that is, when the control signal Ison of the rectifier diode and the control signal hson of the synchronous tube are still at a low level, a high level is output to the first counting module 20, so that the first counting module 20 completes a count.

[0073] In some of these embodiments, please refer to Figure 2 , the first counting module 20 includes N first DFFs. The clock input end Clk of the first first DFF 21 is connected to the output end of the first delay module 10, and the inverted data output end of the nth first DFF Connect the data input terminal D of the nth first DFF and the clock input terminal Clk of the (n + 1)th first DFF respectively. The data output terminal Q of the Nth first DFF 2N is connected to the first input terminal of the latch module 30. The set terminals Set of all the first DFFs are connected to the second output terminal of the latch module 30. Among them, the latch module 30 outputs a clear signal to each first DFF through the second output terminal of the latch module 30 based on the first counting signal, so as to clear each first DFF. N and the first value M1 have the following relationship:

[0074] M1 = 2 N-1 ;

[0075] N is an integer greater than or equal to 1, and 1 ≤ n < N.

[0076] Specifically, the data output terminal of the Nth first DFF is connected to the first input terminal of the latch U3, and the set terminals of all the first DFFs are connected to the output terminal of the NOT gate U4.

[0077] In this embodiment, when the first counting module 20 receives the first delay signal output by the first delay module 10, it will complete a count. When the first value M1 is accumulated for the specified number of times, the Nth first DFF 2N will output a high-level signal to the latch module 30, so that the NOT gate U5 will output a high-level signal (the first indication signal). It can be seen that the first counting module 20 can compare the number of consecutive times that the switching period is greater than the first time value T1 with the first value, and output a high-level signal when it is greater than the first value; at the same time, the NOT gate U4 will output a low-level signal (clear signal) to each first DFF to set each first DFF to 0 to ensure the normal operation of the next count. For the specific structure of the first DFF, reference can be made to the prior art and will not be limited here.

[0078] In some of these embodiments, please refer to Figure 4 , the switching circuit further includes a second delay module 40. The first output terminal of the second delay module 40 is connected to the second input terminal of the latch module 30. Among them, the second delay module 40 is used to obtain a periodic signal and generate a second delay signal to the latch module 30 according to the periodic signal and the second time value. The latch module 30 outputs a second indication signal through the first output terminal of the latch module 30 based on the second delay signal, and the second indication signal is used to indicate that the DCDC switches from the low-power mode to the normal mode.

[0079] In this embodiment, the second delay module 40 can be used to obtain the control signal hson of the synchronous tube and determine the switching period of the DCDC based on the control signal hson of the synchronous tube. Moreover, the second delay module 40 compares the switching period with the second time value T2 in the following manner: within one cycle, the timing starts from 0 at the moment when the synchronous tube is turned off, that is, the timing starts from 0 when the control signal hson of the synchronous tube is at a low level. If the current load current increases, that is, the load becomes heavier, then the time when the control signal hson of the synchronous tube is at a low level is less than the second time value T2. Then, the second delay module 40 outputs a second delay signal to the latch module 30. Subsequently, the latch module 30 receives this second delay signal and outputs a second indication signal to indicate that the DCDC switches from the low-power mode to the normal mode. In practical applications, the second time value T2 can be set according to actual needs.

[0080] It can be understood that when the load current output by the DCDC slowly and gradually increases, the switching period of the DCDC will gradually decrease. Therefore, in this embodiment, by timing and comparing the switching period, when the switching period is less than the second time value T2, a second indication signal will be output to indicate that the DCDC exits the low-power mode.

[0081] In addition, the current I when entering the low-power mode loadin is:

[0082]

[0083] The current I when exiting the low-power mode loadout is:

[0084]

[0085] Among them, Ipeak0 is the peak current when entering the low-power mode, T is the conduction time of the synchronous tube of the DCDC, and Ipeak1 is the peak current when exiting the low-power mode. At this time, the second time value T2 can be made less than the first time value T1, so that the current when entering the low-power mode is less than the current when exiting the low-power mode, thereby realizing the load current hysteresis for entering and exiting the low-power mode, ensuring that the circuit will not repeatedly enter and exit the low-power mode under a certain load, and improving the stability of the circuit.

[0086] In some of these embodiments, please refer to Figure 5, the switching circuit further includes a second counting module 50. The first output terminal of the second delay module 40 is connected to the input terminal of the second counting module 50, and the output terminal of the second counting module 50 is connected to the second input terminal of the latching module 30. Among them, the second delay module 40 is used to generate a second delay signal to the second counting module 50 according to the periodic signal and the second time value. The second counting module 50 is used to calculate the second number of times generated by the second delay signal, and output a second counting signal to the latching module 30 when the second number of times is greater than or equal to the second value. The latching module 30 outputs a second indication signal through the first output terminal of the latching module 30 based on the second counting signal.

[0087] In this embodiment, the second delay module 40 can be used to obtain the periodic signal of the switching tube of the DCDC, and judge whether it is less than the second time value based on the periodic signal of the switching tube of the DCDC. If so, the second delay module 40 outputs a second delay signal to the second counting module 50, so that the second counting module 50 completes one count.

[0088] Specifically, the second delay module 40 can obtain the control signal hson of the synchronous tube and time as follows: within one cycle, when the control signal hson of the synchronous tube is at a low level, it starts timing from 0. If after reaching the second time value T2, the control signal hson of the synchronous tube is at a high level, the second delay module 40 outputs a second delay signal to the second counting module 50, and the second counting module 50 will increment the second number of times by one. Then, calculate the signal in the next cycle in the above manner until the second number of times calculated by the second counting module 50 is greater than or equal to the second value, and then output a second counting signal, which indicates that in the second value of cycles, the periodic signal of the switching tube is less than the second time value T0, and also indicates that the current load is heavier. Then, when the latching module 30 receives the second counting signal, it will output a second indication signal to indicate that the DCDC switches from the low power consumption mode to the normal mode.

[0089] It can be understood that if the second delay module 40 does not continuously generate the second delay signal, the second counting module 50 may not reset the second number of times to 0. In practical applications, the second value can be set according to actual needs. For example, the second value can be any value from 2 to 9999. Among them, the second time value T2 can be equal to the first time value T1.

[0090] In this embodiment, by calculating that the number of switching cycles less than the second time value T2 based on the periodic signal is greater than the second value before entering the normal mode, it is avoided that in the low power consumption mode, due to insufficient energy transfer in each switching cycle, multiple switches are required, resulting in premature exit from the low power consumption mode and a decrease in efficiency. The accuracy of the DCDC entering the normal mode is improved, and the smooth switching between the ultra-low power consumption mode and the normal mode can be realized, with less output fluctuation and improved stability of the DCDC output power.

[0091] In some of these embodiments, the DCDC includes a synchronous tube, and the second delay module 40 includes a second delay unit and a logic unit. The input end of the second delay unit and the first input end of the logic unit are used to receive the control signal hson of the synchronous tube. The output end of the second delay unit is connected to the second input end of the logic unit, and the third input end of the logic unit is connected to the third output end of the latch module 30. Among them, the second delay unit generates a third delay signal to the logic unit based on the control signal of the synchronous tube and the second time value. The logic unit is used to output a second delay signal to the second counting module 50 according to the control signal of the synchronous tube, the third delay signal, and the output signal of the third output end of the latch module 30. The output signal of the third output end of the latch module 30 and the output signal of the second output end of the latch module 30 have opposite levels.

[0092] Specifically, please refer to Figure 2 , the second delay unit includes: a rising-edge delay sub-unit 41, a first falling-edge delay sub-unit 42, a NOT gate U6, and a NOR gate U7. The input end of the rising-edge delay sub-unit 41 is used to receive the control signal hson of the synchronous tube. The output end of the rising-edge delay sub-unit 41 is respectively connected to the input end of the first falling-edge delay sub-unit 42 and the first input end of the NOR gate U7. The output end of the first falling-edge delay sub-unit 42 is respectively connected to the input end of the NOT gate U6 and the set end of the second counting module 50. The output end of the NOT gate U6 is connected to the second input end of the NOR gate U7. The output end of the NOR gate U7 is connected to the second input end of the logic unit.

[0093] The rising-edge delay sub-unit 41 is used to output a rising edge after delaying the third time value T3 after receiving the rising edge. The third time value T3 is relatively small and is mainly used to generate the pulse high level for counting. The first falling-edge delay sub-unit 42 is used to delay the falling edge of the signal output by the rising-edge delay sub-unit 41 and output the delayed signal to the NOT gate U6. For example, when the falling edge of the signal output by the rising-edge delay sub-unit 41 comes, due to the delay of the first falling-edge delay sub-unit 42, the output signal of the first falling-edge delay sub-unit 42 will not immediately become low level, but will undergo a level conversion after a period of time (the second time value T2), so that the signal with a low-level duration less than the second time value T2 output by the rising-edge delay sub-unit 41 cannot pass through the first falling-edge delay sub-unit 42. The NOT gate U6 is used to output a low level when the delayed signal output by the rising-edge delay sub-unit 41 is high level, and output a high level when the delayed signal output by the rising-edge delay sub-unit 41 is low level. The NOR gate U7 is used to output a high level when both input signals are low level, and output a low level when any one of the input signals is high level.

[0094] The logic unit includes an AND gate U8. The first input terminal of the AND gate U8 is used to receive the control signal hson of the synchronous tube. The second input terminal of the AND gate U8 is connected to the output terminal of the second delay unit. The third input terminal of the AND gate U8 is connected to the third output terminal of the latch module 30. The output terminal of the AND gate U8 is connected to the input terminal of the second counting module 50. That is, the second input terminal of the AND gate U8 is connected to the output terminal of the NOR gate U7, and the third input terminal of the AND gate U8 is connected to the output terminal of the latch U3. The AND gate U8 outputs a high level when all input signals are high levels, otherwise it outputs a low level.

[0095] In this circuit, first, the rising-edge delay sub-unit 41 delays the rising edge of the control signal hson of the synchronous tube. Then, it is delayed by the first falling-edge delay sub-unit 42. If the low-level duration of the control signal hson of the synchronous tube is less than the second time value T2, the rising-edge delay sub-unit outputs a low level to the first falling-edge delay sub-unit 42 and the NOR gate U7. The first falling-edge delay sub-unit 42 will output a high level to the NOT gate U6. Then, the NOT gate U6 will output a low level to the NOR gate U7, and the NOR gate U7 will output a high level to the AND gate U8, and the control signal hson of the synchronous tube is a high level. At the same time, the AND gate U8 also receives the output signal of the latch U3. From the foregoing analysis, it can be seen that the output terminal of the latch U3 is at a high level after the DCDC enters the low-power mode. Then, the three input terminals of the AND gate U8 are all at high levels. At this time, the AND gate U8 will output a high level (the second delay signal) to the second counting module 50.

[0096] It can be seen that in this embodiment, through the above circuit, when the control signal hson of the synchronous tube is at a low level, the second delay module can start timing from 0. If the control signal hson of the synchronous tube is at a high level after reaching the second time value T2, the second delay module outputs the second delay signal to the second counting module 50. At the same time, the second counting module 50 will cumulatively calculate the second number of times the second delay signal appears. Only when the number of times the switching period is less than the second time value T2 is greater than the second value can it enter the normal mode, avoiding the need for multiple switches due to insufficient energy transfer in each switching period in the low-power mode, resulting in premature exit from the low-power mode and a decrease in efficiency, improving the accuracy of the DCDC entering the normal mode, and enabling smooth switching between the ultra-low-power mode and the normal mode, with less output fluctuation and improving the stability of the DCDC output power.

[0097] In addition, in this circuit, the AND gate U8 determines whether to output the second delay signal based on the level of the control signal hson of the synchronous tube, the level output by the NOR gate U7, and the level output by the latch module 30, improving the accuracy of outputting the second delay signal and ultimately improving the accuracy of outputting the second indication signal.

[0098] In some of these embodiments, please refer toFigure 2 The second counting module 50 includes K second DFFs. The clock input terminal Clk of the first second DFF 51 is connected to the first output terminal of the second delay module 40, and the inverted data output terminal of the k-th second DFF is respectively connected to the data input terminal D of the k-th second DFF and the clock input terminal Clk of the (k + 1)-th second DFF. The data output terminal Q of the K-th second DFF 52K is connected to the second input terminal of the latch module 30, and the set terminals Set of the respective second DFFs are all connected to the second output terminal of the second delay module 40. Among them, K and the second value M2 have the following relationship:

[0099] M2 = 2 K-1 ;

[0100] K is an integer greater than or equal to 1, and 1 ≤ k < K.

[0101] Specifically, the output terminals of the first falling-edge delay sub-unit 42 are respectively connected to the set terminals Set of the respective second DFFs. In this second counting module 50, when receiving the high-level pulse output by the AND gate U8, a count is completed. Since the set signals of the respective second DFFs all adopt the output signals of the first falling-edge delay sub-unit 42, then only when K consecutive switching cycles are all less than the second time value T2, the last DFF 52K in the logic can output a high level to the latch U3, causing the NOT gate U5 to output a low level to indicate that the DCDC switches from the low-power mode to the normal mode, thereby ensuring that when the current changes slowly, the situation of output voltage drop is reduced. The specific structure of the second DFF can refer to the prior art and is not limited herein.

[0102] In some of the embodiments, please refer to Figure 6 and Figure 2 , the switching circuit further includes a first comparison module U9 and a voltage adjustment module 60. The input terminal of the voltage adjustment module 60 is connected to the output terminal VOUT of the DCDC, the output terminal of the voltage adjustment module 60 is connected to the first input terminal of the first comparison module U9, the second input terminal of the first comparison module U9 is used to connect to the reference voltage source VREF, and the output terminal of the first comparison module U9 is connected to the third input terminal of the latch module 30. Among them, the voltage adjustment module 60 outputs an adjustment voltage to the first comparison module U9 based on the output voltage of the DCDC. The first comparison module U9 outputs a comparison signal to the latch module 30 based on the adjustment voltage and the reference voltage output by the reference voltage source VREF. The latch module 30 outputs a third indication signal through the first output terminal of the latch module 30 based on the comparison signal, and the third indication signal is used to indicate that the DCDC switches from the low-power mode to the normal mode.

[0103] Specifically, the first comparison module U9 is a comparator. The first input terminal of the first comparison module U9 is the negative input terminal of the comparator, and the second input terminal of the first comparison module U9 is the positive input terminal of the comparator. The voltage adjustment module 60 includes a resistor R0 and a current source I0. Among them, the current source I0 is respectively connected to the first end of the resistor R0 and the first input terminal of the first comparison module U9. The second input terminal of the first comparison module U9 is connected to the reference voltage source VREF, and the output terminal of the first comparison module U9 is connected to the third input terminal of the latch U3.

[0104] It can be understood that when the load increases rapidly, since in the ultra-low power consumption mode, the energy transferred in each switching cycle is limited, when using Figure 4 or Figure 5 the method shown in the embodiment shown to exit the low power consumption mode, taking counting twice as an example: If the counting method is used, there will be a time of the second time value T2 when the output cannot be supplied with energy, which will cause a large drop in the output, resulting in a large output drop. The output drop voltage is Vdrop = Idrop * T2, where Idrop is the drop current and T2 is the second time value.

[0105] To solve the problem of excessive drop, in this embodiment, by setting the first comparison module U9, the voltage adjustment module 60 and the reference voltage source VREF, when the difference between the output voltage Vout and the drop voltage Vo is less than the reference voltage Vref, the comparison signal is directly output to the latch module 30, so that the latch module 30 outputs a third indication signal to indicate that the DCDC quickly switches from the low power consumption mode to the normal mode, reducing the output drop. Among them, the drop voltage Vo = Ro * Io, where Ro is the resistance value of the resistor R0 and Io is the current of the current source I0.

[0106] In addition, after the DCDC switches from the low power consumption mode to the normal mode, the synchronous tube can be controlled to turn on and the conduction time can be extended to increase the peak current in the first cycle after the switch (this peak current must be greater than the maximum load current of the chip) to quickly supplement energy to the output, thereby reducing the output drop and improving the output stability.

[0107] In some of these embodiments, please refer to Figure 6 , the switching circuit further includes a second comparison module U10. The first input terminal of the second comparison module U10 is connected to the output terminal of the DCDC, and the second input terminal of the second comparison module U10 is used to connect to the reference voltage source VREF. Among them, the second comparison module U10 outputs a control signal for the synchronous tube based on the output voltage and the reference voltage of the DCDC.

[0108] Specifically, the second comparison module U10 can be a second comparator. The first input terminal of the second comparison module U10 is the negative input terminal of the second comparator, and the second input terminal of the second comparison module U10 is the positive input terminal of the second comparator.

[0109] In this switching circuit, if the reference voltage source VREF is greater than the output voltage of the DCDC, a high level is output. This high level will indicate that the DCDC turns on the synchronous tube, that is, the control signal of the synchronous tube is at a high level. If the reference voltage source VREF is less than the output voltage of the DCDC, a low level is output. This low level will indicate that the DCDC turns off the synchronous tube, that is, the control signal of the synchronous tube is at a low level. In this way, when the output voltage drops to the set value, the power switch can be quickly turned on to provide energy for the output, thereby maintaining the output stability.

[0110] In a second aspect, an embodiment of the present application further provides a switching method applied to a DCDC. The execution subject of the switching method is the control device provided in the embodiment of the present application. The switching method includes:

[0111] Step S100: Obtain the switching period of the switching tube of the DCDC and a first time value.

[0112] The switching period of the switching tube of the DCDC, that is, the period when the synchronous tube of the DCDC is turned on, that is, the working period of the DCDC, is also the time corresponding to the working frequency of the DCDC. The control device can calculate the switching period of the switching tube of the DCDC by obtaining the control signal Ison of the rectifier tube and the control signal hson of the synchronous tube and based on the two.

[0113] The first time value T1 can be pre-stored in the control device. In this way, the control device can call the memory to obtain the first time value T1, or it can be manually input into the control device so that the control device obtains the first time value T1.

[0114] Step S200: Determine the first number of times that the switching period is continuously greater than the first time value.

[0115] Next, when the control device obtains the switching period within one cycle, it will compare it with the first time value T0. If the switching period is greater than the first time value T1, the first number is incremented by one, and the magnitudes of the switching period within each cycle and the first time value T0 are continuously calculated in the above manner. If the switching period is less than the first time value T1, the first number is set to 0.

[0116] Step S300: If the first number is greater than or equal to the first value, control the DCDC to switch from the normal mode to the low power consumption mode.

[0117] After calculating the first number, the control device also compares the first number with the first value. When the first number is greater than or equal to the first value, it controls the DCDC to switch from the normal mode to the low power consumption mode. When the first number is less than the first value, steps S100 - S200 are repeatedly executed.

[0118] In this embodiment, by determining whether the calculated switching period is greater than the first time value T1 to determine the current load condition, and entering the low power consumption mode only when the number of times the switching period is greater than the first time value T1 is greater than the first value, the situation of mistakenly entering the low power consumption mode due to the load transient changing from heavy load to light load can be reduced, the accuracy of the DCDC entering the low power consumption mode can be improved, and the smooth switching between the ultra - low power consumption mode and the normal mode can be achieved, with less output fluctuation and improved stability of the DCDC output power.

[0119] In some embodiments, the method further includes:

[0120] Step S400: Obtain a second time value.

[0121] The second time value T2 can be pre - stored in the control device. In this way, the control device can call the memory to obtain the second time value T2, or it can be manually input into the control device so that the control device obtains the second time value T2.

[0122] Step S500: If the switching period is less than the second time value, control the DCDC to switch from the low power consumption mode to the normal mode.

[0123] Next, when the control device obtains the switching period within a period, it compares it with the second time value T2. If the switching period is less than the second time value T2, it controls the DCDC to switch from the low power consumption mode to the normal mode.

[0124] In this embodiment, by comparing the timing of the switching period, when the switching period is less than the second time value T2, the DCDC can be controlled to exit the low power consumption mode.

[0125] In addition, in some embodiments, the second time value T2 can be less than the first time value T1, which can make the current when entering the low power consumption mode less than the current when exiting the low power consumption mode, so as to achieve a load current hysteresis for entering and exiting the low power consumption mode, ensure that the circuit will not repeatedly enter and exit the low power consumption mode under a certain load, and improve the stability of the circuit.

[0126] In some embodiments, step S500 includes:

[0127] Step S510: Determine the second number of times that the switching period is less than the second time value.

[0128] Specifically, when the control device obtains the switching period within one cycle, it will compare it with the second time value T2. If the switching period is greater than the second time value T2, the second count is incremented by one, and the magnitudes of the switching period within each cycle and the second time value T2 are continuously calculated in the above manner.

[0129] Step S520: If the second count is greater than or equal to the second value, the DCDC is switched from the low-power mode to the normal mode.

[0130] After calculating the second count, the control device will also compare the second count with the second value. When the second count is greater than or equal to the second value, the control device will switch the DCDC from the low-power mode to the normal mode. When the second count is less than the second value, steps S400 - S510 are repeatedly executed.

[0131] In this embodiment, the second time value T2 can be equal to the first time value T1 or less than the first time value T1. By calculating that the number of times the switching period is less than the second time value T2 is greater than the second value before entering the normal mode, it is avoided that in the low-power mode, due to insufficient energy transfer in each switching period, multiple switchings are required, resulting in premature exit from the low-power mode and a decrease in efficiency. The accuracy of the DCDC entering the normal mode is improved, and smooth switching between the ultra-low-power mode and the normal mode can be achieved, with less output fluctuation, improving the stability of the DCDC output power supply.

[0132] In some of these embodiments, the method further includes:

[0133] Step S600: Obtain the output voltage, dropout voltage, and reference voltage of the DCDC.

[0134] Specifically, the control device can obtain the output voltage by performing voltage sampling on the output terminal of the DCDC. The dropout voltage is the preset maximum voltage value that the DCDC allows the output to drop when the load rapidly increases after the DCDC enters the low-power mode. The dropout voltage and the reference voltage can be pre-stored or manually input so that the control device can obtain them.

[0135] Step S700: Obtain the adjustment voltage based on the output voltage and the dropout voltage.

[0136] Next, the control device will calculate the difference between the output voltage and the dropout voltage, and this difference is the adjustment voltage.

[0137] Step S800: Control the DCDC to switch from the normal mode to the low-power mode based on the adjustment voltage and the reference voltage.

[0138] Finally, the control device will compare the adjustment voltage and the reference voltage. If the adjustment voltage is less than the reference voltage, the control device will control the DCDC to switch from the normal mode to the low-power mode.

[0139] In this embodiment, the control device can control the DCDC to exit the low-power mode in the above manner, enabling the DCDC to quickly switch from the low-power mode to the normal mode and reducing the output drop.

[0140] In some embodiments, the method further includes:

[0141] Step S900: Output a control signal to the synchronous tube according to the output voltage and the reference voltage.

[0142] Specifically, the control device compares the magnitudes of the output voltage and the reference voltage, and controls the synchronous tube to turn off when the output voltage is greater than the reference voltage, and controls the synchronous tube to turn on when the output voltage is less than the reference voltage. In this way, when the output voltage drops to the set value, the power switch can be quickly turned on to provide energy for the output, thereby maintaining the output stability.

[0143] In a third aspect, an embodiment of the present application further provides a control device 100. Please refer to Figure 7 , which shows the hardware structure of the control device 100 capable of executing the switching method provided by the present application.

[0144] The control device 100 includes: at least one processor 110; and a memory 120 communicatively connected to the at least one processor 110. Figure 7 Taking one processor 110 as an example. The memory 120 stores instructions executable by the at least one processor 110. The instructions are executed by the at least one processor 110 so that the at least one processor 110 can execute the switching method of any one of the following embodiments. The processor 110 and the memory 120 can be connected through a bus or other means. Figure 7 Taking the connection through the bus as an example.

[0145] As a non-volatile computer-readable storage medium, the memory 120 can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions / modules corresponding to the switching method described in any one of the embodiments of the present application. By running the non-volatile software programs, instructions, and modules stored in the memory 120, the processor 110 executes various functional applications and data processing of the server, that is, implements the switching method of any one of the following embodiments.

[0146] The memory 120 may include a program storage area and a data storage area. The program storage area may store an operating system and application programs required for at least one function. The data storage area may store data created according to the use of the server and the like. In addition, the memory 120 may include a high-speed random access memory and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some of these embodiments, the memory 120 may optionally include a memory remotely provided with respect to the processor 110, and these remote memories may be connected to the server through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0147] One or more modules are stored in the memory 120 and, when executed by one or more processors 110, execute the switching method according to any one of the embodiments in the second aspect above.

[0148] The above product can execute the method provided by the embodiments of the present application and has corresponding functional modules and beneficial effects for executing the method. For technical details not described in detail in this embodiment, reference may be made to the method provided by the embodiments of the present application.

[0149] In a fourth aspect, the embodiments of the present application further provide a DCDC, which includes a switching circuit according to any one of the first aspect, or includes a control device as described in the third aspect. In this embodiment, the switching circuit has the same structure and function as the switching circuit according to any one of the first aspect, and the control device has the same structure and function as the control device according to any one of the third aspect, and will not be described in detail here.

[0150] In a fifth aspect, the embodiments of the present application further provide a non-volatile computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are executed by one or more processors. For example, the switching method according to any one of the embodiments in the second aspect described above is executed.

[0151] In a sixth aspect, the embodiments of the present application further provide a computer program product, including a computing program stored on a non-volatile computer-readable storage medium. The computer program includes program instructions, and when the program instructions are executed by a computer, the computer is caused to execute the switching method according to any one of the embodiments in the second aspect described above.

[0152] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0153] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them. Under the idea of the present application, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order. There are many other variations in different aspects of the present application as described above, and for the sake of brevity, they are not provided in detail. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or equivalently replace some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A switching circuit, characterized in that, Applied to a DCDC, the switching tubes of the DCDC include a synchronous tube and a rectifying tube, and the switching circuit includes: A first delay module, configured to obtain the control signal of the synchronous tube and the control signal of the rectifying tube, and start timing from zero when both the control signal of the rectifying tube and the control signal of the synchronous tube are at low level. If, when the timing reaches a first time value, the control signal of the rectifying tube and the control signal of the synchronous tube are still at low level, a first delay signal is generated; A first counting module, the input end of the first counting module is connected to the output end of the first delay module, and the first counting module is configured to calculate the first number of times that the first delay signal is continuously generated, and output a first counting signal when the first number is greater than or equal to a first value; A latching module, the first input end of the latching module is connected to the output end of the first counting module, and the latching module outputs a first indication signal through the first output end of the latching module based on the first counting signal, and the first indication signal is used to indicate that the DCDC switches from the normal mode to the low power consumption mode; A second comparison module, the first input end of the second comparison module is connected to the output end of the DCDC, and the second input end of the second comparison module is used to connect to a reference voltage source; wherein, the second comparison module outputs the control signal of the synchronous tube based on the output voltage of the DCDC and the reference voltage output by the reference voltage source; A second delay module and a second counting module, the first output end of the second delay module is connected to the input end of the second counting module, the output end of the second counting module is connected to the second input end of the latching module, the second delay module is configured to generate the second delay signal to the second counting module according to the control signal of the synchronous tube and a second time value, the second counting module is configured to calculate the second number of times that the second delay signal is generated, and output a second counting signal to the latching module when the second number is greater than or equal to a second value, and the latching module outputs a second indication signal through the first output end of the latching module based on the second counting signal, and the second indication signal is used to indicate that the DCDC switches from the low power consumption mode to the normal mode; Among them, the second delay module includes a second delay unit and a logic unit. The second delay unit includes a rising-edge delay subunit, a first falling-edge delay subunit, a NOT gate, and a NOR gate. The input end of the rising-edge delay subunit and the first input end of the logic unit are used to receive the control signal of the synchronous tube. The output end of the rising-edge delay subunit is respectively connected to the input end of the first falling-edge delay subunit and the first input end of the NOR gate. The output end of the first falling-edge delay subunit is connected to the input end of the NOT gate. The output end of the NOT gate is connected to the second input end of the NOR gate. The output end of the NOR gate is connected to the second input end of the logic unit. The third input end of the logic unit is connected to the third output end of the latch module. The second delay unit generates a third delay signal to the logic unit based on the control signal of the synchronous tube and the second time value. The logic unit is used to output the second delay signal to the second counting module according to the control signal of the synchronous tube, the third delay signal, and the output signal of the third output end of the latch module. The output signal of the third output end of the latch module and the output signal of the second output end of the latch module have opposite levels.

2. The switching circuit according to claim 1, wherein The switching circuit further includes a first comparison module and a voltage adjustment module; The input end of the voltage adjustment module is connected to the output end of the DCDC. The output end of the voltage adjustment module is connected to the first input end of the first comparison module. The second input end of the first comparison module is used to connect to a reference voltage source. The output end of the first comparison module is connected to the third input end of the latch module; Among them, the voltage adjustment module outputs an adjusted voltage to the first comparison module based on the output voltage of the DCDC; The first comparison module outputs a comparison signal to the latch module based on the adjusted voltage and the reference voltage output by the reference voltage source; The latch module outputs a third indication signal through the first output end of the latch module based on the comparison signal. The third indication signal is used to indicate that the DCDC quickly switches from the low-power mode to the normal mode.

3. The switching circuit according to claim 1, characterized in that The first delay module includes a NAND gate and a first delay unit; The first input end of the NAND gate is used to receive the control signal of the rectifying tube. The second input end of the NAND gate is used to receive the control signal of the synchronous tube. The output end of the NAND gate is connected to the input end of the first delay unit. The output end of the first delay unit is connected to the input end of the first counting module; Among them, the NAND gate outputs a logic signal to the first delay unit based on the control signal of the rectifying tube and the control signal of the synchronous tube; The first delay unit is used to generate the first delay signal to the first counting module based on the logic signal and the first time value.

4. The switching circuit according to claim 1, characterized in that, The first counting module includes N first DFFs; The clock input terminal of the first first DFF is connected to the output terminal of the first delay module. The inverted data output terminal of the nth first DFF is respectively connected to the data input terminal of the nth first DFF and the clock input terminal of the (n + 1)th first DFF. The data output terminal of the Nth first DFF is connected to the first input terminal of the latch module. The set terminals of all the first DFFs are connected to the second output terminal of the latch module; Wherein, the latch module outputs a clear signal to each of the first DFFs through the second output terminal of the latch module based on the first count signal, so as to clear each of the first DFFs; N and the first value M1 have the following relationship: M1＝2 N-1 ； N is an integer greater than or equal to 1, and 1 ≤ n < N.

5. The switching circuit according to claim 1, characterized in that, The logic unit includes an AND gate; The first input terminal of the AND gate is used to receive the control signal of the synchronous tube. The second input terminal of the AND gate is connected to the output terminal of the second delay unit. The third input terminal of the AND gate is connected to the third output terminal of the latch module. The output terminal of the AND gate is connected to the input terminal of the second counting module.

6. The switching circuit according to claim 5, wherein The second counting module includes K second DFFs; The clock input terminal of the first second DFF is connected to the first output terminal of the second delay module. The inverted data output terminal of the kth second DFF is respectively connected to the data input terminal of the kth second DFF and the clock input terminal of the (k + 1)th second DFF. The data output terminal of the Kth second DFF is connected to the second input terminal of the latch module. The set terminals of all the second DFFs are connected to the second output terminal of the second delay module; Wherein, the first output terminal of the second delay module is the output terminal of the logic unit, and the second output terminal of the second delay module is the output terminal of the first falling-edge delay sub-unit. K and the second value M2 have the following relationship: M2＝2 K-1 ； K is an integer greater than or equal to 1, and 1 ≤ k < K.

7. A switching method, characterized in that, Applied to DCDC, the DCDC includes a switching circuit, a synchronous tube, and a rectifying tube as described in any one of claims 1-6. The switching method includes: Obtain a switching period and a first time value determined based on the control signal of the synchronous tube and the control signal of the rectifying tube; Determine the first number of times that the switching period determined based on the control signal of the synchronous tube and the control signal of the rectifying tube is continuously greater than the first time value; If the first number is greater than or equal to the first value, control the DCDC to switch from the normal mode to the low-power mode; Obtain the output voltage and the reference voltage of the DCDC; According to the output voltage and the reference voltage, output a control signal to the synchronous tube; Obtain a drop voltage; According to the output voltage and the drop voltage, obtain an adjusted voltage; According to the adjusted voltage and the reference voltage, control the DCDC to switch from the normal mode to the low-power mode.

8. The switching method according to claim 7, wherein The method further includes: Obtain a second time value; If the switching period determined based on the control signal of the synchronous tube is less than the second time value, control the DCDC to switch from the low-power mode to the normal mode.

9. The switching method according to claim 8, wherein If the switching period determined based on the control signal of the synchronous tube is less than the second time value, controlling the DCDC to switch from the low power consumption mode to the normal mode includes: Determining a second number of times that the switching period determined based on the control signal of the synchronous tube is less than the second time value; If the second number of times is greater than or equal to a second value, controlling the DCDC to switch from the low power consumption mode to the normal mode.

10. A control device, characterized in that, Including: At least one processor; And, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method according to any one of claims 7-9.

11. A DCDC, characterized in that, Including the switching circuit according to any one of claims 1-6, or including the control device according to claim 10.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to execute the method according to any one of claims 7-9.

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